include/linux/mfd/asic3.h

   1 /*
   2  * include/linux/mfd/asic3.h
   3  *
   4  * Compaq ASIC3 headers.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Copyright 2001 Compaq Computer Corporation.
  11  * Copyright 2007 OpendHand.
  12  */
  13
  14 #ifndef __ASIC3_H__
  15 #define __ASIC3_H__
  16
  17 #include <linux/types.h>
  18
  19 struct asic3_platform_data {
  20         struct {
  21                 u32 dir;
  22                 u32 init;
  23                 u32 sleep_mask;
  24                 u32 sleep_out;
  25                 u32 batt_fault_out;
  26                 u32 sleep_conf;
  27                 u32 alt_function;
  28         } gpio_a, gpio_b, gpio_c, gpio_d;
  29
  30         unsigned int bus_shift;
  31
  32         unsigned int irq_base;
  33
  34         unsigned int gpio_base;
  35
  36         struct platform_device **children;
  37         unsigned int n_children;
  38 };
  39
  40 #define ASIC3_NUM_GPIO_BANKS    4
  41 #define ASIC3_GPIOS_PER_BANK    16
  42 #define ASIC3_NUM_GPIOS         64
  43 #define ASIC3_NR_IRQS           ASIC3_NUM_GPIOS + 6
  44
  45 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
  46
  47 #define ASIC3_GPIO_BANK_A       0
  48 #define ASIC3_GPIO_BANK_B       1
  49 #define ASIC3_GPIO_BANK_C       2
  50 #define ASIC3_GPIO_BANK_D       3
  51
  52 #define ASIC3_GPIO(bank, gpio) \
  53         ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
  54 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
  55 /* All offsets below are specified with this address bus shift */
  56 #define ASIC3_DEFAULT_ADDR_SHIFT 2
  57
  58 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
  59 #define ASIC3_GPIO_OFFSET(base, reg) \
  60         (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
  61
  62 #define ASIC3_GPIO_A_Base      0x0000
  63 #define ASIC3_GPIO_B_Base      0x0100
  64 #define ASIC3_GPIO_C_Base      0x0200
  65 #define ASIC3_GPIO_D_Base      0x0300
  66
  67 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
  68 #define ASIC3_GPIO_TO_BIT(gpio)  ((gpio) - \
  69                                   (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
  70 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
  71 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_Base + (((gpio) >> 4) * 0x0100))
  72 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_Base + ((bank) * 0x100))
  73
  74 #define ASIC3_GPIO_Mask          0x00    /* R/W 0:don't mask */
  75 #define ASIC3_GPIO_Direction     0x04    /* R/W 0:input */
  76 #define ASIC3_GPIO_Out           0x08    /* R/W 0:output low */
  77 #define ASIC3_GPIO_TriggerType   0x0c    /* R/W 0:level */
  78 #define ASIC3_GPIO_EdgeTrigger   0x10    /* R/W 0:falling */
  79 #define ASIC3_GPIO_LevelTrigger  0x14    /* R/W 0:low level detect */
  80 #define ASIC3_GPIO_SleepMask     0x18    /* R/W 0:don't mask in sleep mode */
  81 #define ASIC3_GPIO_SleepOut      0x1c    /* R/W level 0:low in sleep mode */
  82 #define ASIC3_GPIO_BattFaultOut  0x20    /* R/W level 0:low in batt_fault */
  83 #define ASIC3_GPIO_IntStatus     0x24    /* R/W 0:none, 1:detect */
  84 #define ASIC3_GPIO_AltFunction   0x28    /* R/W 1:LED register control */
  85 #define ASIC3_GPIO_SleepConf     0x2c    /*
  86                                           * R/W bit 1: autosleep
  87                                           * 0: disable gposlpout in normal mode,
  88                                           * enable gposlpout in sleep mode.
  89                                           */
  90 #define ASIC3_GPIO_Status        0x30    /* R   Pin status */
  91
  92 #define ASIC3_SPI_Base                0x0400
  93 #define ASIC3_SPI_Control               0x0000
  94 #define ASIC3_SPI_TxData                0x0004
  95 #define ASIC3_SPI_RxData                0x0008
  96 #define ASIC3_SPI_Int                   0x000c
  97 #define ASIC3_SPI_Status                0x0010
  98
  99 #define SPI_CONTROL_SPR(clk)      ((clk) & 0x0f)  /* Clock rate */
 100
 101 #define ASIC3_PWM_0_Base                0x0500
 102 #define ASIC3_PWM_1_Base                0x0600
 103 #define ASIC3_PWM_TimeBase              0x0000
 104 #define ASIC3_PWM_PeriodTime            0x0004
 105 #define ASIC3_PWM_DutyTime              0x0008
 106
 107 #define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
 108 #define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
 109
 110 #define ASIC3_LED_0_Base                0x0700
 111 #define ASIC3_LED_1_Base                0x0800
 112 #define ASIC3_LED_2_Base                      0x0900
 113 #define ASIC3_LED_TimeBase              0x0000    /* R/W  7 bits */
 114 #define ASIC3_LED_PeriodTime            0x0004    /* R/W 12 bits */
 115 #define ASIC3_LED_DutyTime              0x0008    /* R/W 12 bits */
 116 #define ASIC3_LED_AutoStopCount         0x000c    /* R/W 16 bits */
 117
 118 /* LED TimeBase bits - match ASIC2 */
 119 #define LED_TBS         0x0f /* Low 4 bits sets time base, max = 13 */
 120                              /* Note: max = 5 on hx4700 */
 121                              /* 0: maximum time base */
 122                              /* 1: maximum time base / 2 */
 123                              /* n: maximum time base / 2^n */
 124
 125 #define LED_EN          (1 << 4) /* LED ON/OFF 0:off, 1:on */
 126 #define LED_AUTOSTOP    (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
 127 #define LED_ALWAYS      (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
 128
 129 #define ASIC3_CLOCK_Base                0x0A00
 130 #define ASIC3_CLOCK_CDEX           0x00
 131 #define ASIC3_CLOCK_SEL            0x04
 132
 133 #define CLOCK_CDEX_SOURCE       (1 << 0)  /* 2 bits */
 134 #define CLOCK_CDEX_SOURCE0      (1 << 0)
 135 #define CLOCK_CDEX_SOURCE1      (1 << 1)
 136 #define CLOCK_CDEX_SPI          (1 << 2)
 137 #define CLOCK_CDEX_OWM          (1 << 3)
 138 #define CLOCK_CDEX_PWM0         (1 << 4)
 139 #define CLOCK_CDEX_PWM1         (1 << 5)
 140 #define CLOCK_CDEX_LED0         (1 << 6)
 141 #define CLOCK_CDEX_LED1         (1 << 7)
 142 #define CLOCK_CDEX_LED2         (1 << 8)
 143
 144 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
 145 #define CLOCK_CDEX_SD_HOST      (1 << 9)   /* R/W: SD host clock source */
 146 #define CLOCK_CDEX_SD_BUS       (1 << 10)  /* R/W: SD bus clock source ctrl */
 147 #define CLOCK_CDEX_SMBUS        (1 << 11)
 148 #define CLOCK_CDEX_CONTROL_CX   (1 << 12)
 149
 150 #define CLOCK_CDEX_EX0          (1 << 13)  /* R/W: 32.768 kHz crystal */
 151 #define CLOCK_CDEX_EX1          (1 << 14)  /* R/W: 24.576 MHz crystal */
 152
 153 #define CLOCK_SEL_SD_HCLK_SEL   (1 << 0)   /* R/W: SDIO host clock select */
 154 #define CLOCK_SEL_SD_BCLK_SEL   (1 << 1)   /* R/W: SDIO bus clock select */
 155
 156 /* R/W: INT clock source control (32.768 kHz) */
 157 #define CLOCK_SEL_CX            (1 << 2)
 158
 159
 160 #define ASIC3_INTR_Base         0x0B00
 161
 162 #define ASIC3_INTR_IntMask       0x00  /* Interrupt mask control */
 163 #define ASIC3_INTR_PIntStat      0x04  /* Peripheral interrupt status */
 164 #define ASIC3_INTR_IntCPS        0x08  /* Interrupt timer clock pre-scale */
 165 #define ASIC3_INTR_IntTBS        0x0c  /* Interrupt timer set */
 166
 167 #define ASIC3_INTMASK_GINTMASK    (1 << 0)  /* Global INTs mask 1:enable */
 168 #define ASIC3_INTMASK_GINTEL      (1 << 1)  /* 1: rising edge, 0: hi level */
 169 #define ASIC3_INTMASK_MASK0       (1 << 2)
 170 #define ASIC3_INTMASK_MASK1       (1 << 3)
 171 #define ASIC3_INTMASK_MASK2       (1 << 4)
 172 #define ASIC3_INTMASK_MASK3       (1 << 5)
 173 #define ASIC3_INTMASK_MASK4       (1 << 6)
 174 #define ASIC3_INTMASK_MASK5       (1 << 7)
 175
 176 #define ASIC3_INTR_PERIPHERAL_A   (1 << 0)
 177 #define ASIC3_INTR_PERIPHERAL_B   (1 << 1)
 178 #define ASIC3_INTR_PERIPHERAL_C   (1 << 2)
 179 #define ASIC3_INTR_PERIPHERAL_D   (1 << 3)
 180 #define ASIC3_INTR_LED0           (1 << 4)
 181 #define ASIC3_INTR_LED1           (1 << 5)
 182 #define ASIC3_INTR_LED2           (1 << 6)
 183 #define ASIC3_INTR_SPI            (1 << 7)
 184 #define ASIC3_INTR_SMBUS          (1 << 8)
 185 #define ASIC3_INTR_OWM            (1 << 9)
 186
 187 #define ASIC3_INTR_CPS(x)         ((x)&0x0f)    /* 4 bits, max 14 */
 188 #define ASIC3_INTR_CPS_SET        (1 << 4)    /* Time base enable */
 189
 190
 191 /* Basic control of the SD ASIC */
 192 #define ASIC3_SDHWCTRL_Base     0x0E00
 193 #define ASIC3_SDHWCTRL_SDConf    0x00
 194
 195 #define ASIC3_SDHWCTRL_SUSPEND    (1 << 0)  /* 1=suspend all SD operations */
 196 #define ASIC3_SDHWCTRL_CLKSEL     (1 << 1)  /* 1=SDICK, 0=HCLK */
 197 #define ASIC3_SDHWCTRL_PCLR       (1 << 2)  /* All registers of SDIO cleared */
 198 #define ASIC3_SDHWCTRL_LEVCD      (1 << 3)  /* SD card detection: 0:low */
 199
 200 /* SD card write protection: 0=high */
 201 #define ASIC3_SDHWCTRL_LEVWP      (1 << 4)
 202 #define ASIC3_SDHWCTRL_SDLED      (1 << 5)  /* SD card LED signal 0=disable */
 203
 204 /* SD card power supply ctrl 1=enable */
 205 #define ASIC3_SDHWCTRL_SDPWR      (1 << 6)
 206
 207 #define ASIC3_EXTCF_Base                0x1100
 208
 209 #define ASIC3_EXTCF_Select         0x00
 210 #define ASIC3_EXTCF_Reset          0x04
 211
 212 #define ASIC3_EXTCF_SMOD0                (1 << 0)  /* slot number of mode 0 */
 213 #define ASIC3_EXTCF_SMOD1                (1 << 1)  /* slot number of mode 1 */
 214 #define ASIC3_EXTCF_SMOD2                (1 << 2)  /* slot number of mode 2 */
 215 #define ASIC3_EXTCF_OWM_EN               (1 << 4)  /* enable onewire module */
 216 #define ASIC3_EXTCF_OWM_SMB              (1 << 5)  /* OWM bus selection */
 217 #define ASIC3_EXTCF_OWM_RESET            (1 << 6)  /* ?? used by OWM and CF */
 218 #define ASIC3_EXTCF_CF0_SLEEP_MODE       (1 << 7)  /* CF0 sleep state */
 219 #define ASIC3_EXTCF_CF1_SLEEP_MODE       (1 << 8)  /* CF1 sleep state */
 220 #define ASIC3_EXTCF_CF0_PWAIT_EN         (1 << 10) /* CF0 PWAIT_n control */
 221 #define ASIC3_EXTCF_CF1_PWAIT_EN         (1 << 11) /* CF1 PWAIT_n control */
 222 #define ASIC3_EXTCF_CF0_BUF_EN           (1 << 12) /* CF0 buffer control */
 223 #define ASIC3_EXTCF_CF1_BUF_EN           (1 << 13) /* CF1 buffer control */
 224 #define ASIC3_EXTCF_SD_MEM_ENABLE        (1 << 14)
 225 #define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
 226
 227 /*********************************************
 228  *  The Onewire interface registers
 229  *
 230  *  OWM_CMD
 231  *  OWM_DAT
 232  *  OWM_INTR
 233  *  OWM_INTEN
 234  *  OWM_CLKDIV
 235  *
 236  *********************************************/
 237
 238 #define ASIC3_OWM_Base          0xC00
 239
 240 #define ASIC3_OWM_CMD         0x00
 241 #define ASIC3_OWM_DAT         0x04
 242 #define ASIC3_OWM_INTR        0x08
 243 #define ASIC3_OWM_INTEN       0x0C
 244 #define ASIC3_OWM_CLKDIV      0x10
 245
 246 #define ASIC3_OWM_CMD_ONEWR         (1 << 0)
 247 #define ASIC3_OWM_CMD_SRA           (1 << 1)
 248 #define ASIC3_OWM_CMD_DQO           (1 << 2)
 249 #define ASIC3_OWM_CMD_DQI           (1 << 3)
 250
 251 #define ASIC3_OWM_INTR_PD          (1 << 0)
 252 #define ASIC3_OWM_INTR_PDR         (1 << 1)
 253 #define ASIC3_OWM_INTR_TBE         (1 << 2)
 254 #define ASIC3_OWM_INTR_TEMP        (1 << 3)
 255 #define ASIC3_OWM_INTR_RBF         (1 << 4)
 256
 257 #define ASIC3_OWM_INTEN_EPD        (1 << 0)
 258 #define ASIC3_OWM_INTEN_IAS        (1 << 1)
 259 #define ASIC3_OWM_INTEN_ETBE       (1 << 2)
 260 #define ASIC3_OWM_INTEN_ETMT       (1 << 3)
 261 #define ASIC3_OWM_INTEN_ERBF       (1 << 4)
 262
 263 #define ASIC3_OWM_CLKDIV_PRE       (3 << 0) /* two bits wide at bit 0 */
 264 #define ASIC3_OWM_CLKDIV_DIV       (7 << 2) /* 3 bits wide at bit 2 */
 265
 266
 267 /*****************************************************************************
 268  *  The SD configuration registers are at a completely different location
 269  *  in memory.  They are divided into three sets of registers:
 270  *
 271  *  SD_CONFIG         Core configuration register
 272  *  SD_CTRL           Control registers for SD operations
 273  *  SDIO_CTRL         Control registers for SDIO operations
 274  *
 275  *****************************************************************************/
 276 #define ASIC3_SD_CONFIG_Base            0x0400 /* Assumes 32 bit addressing */
 277
 278 #define ASIC3_SD_CONFIG_Command           0x08   /* R/W: Command */
 279
 280 /* [0:8] SD Control Register Base Address */
 281 #define ASIC3_SD_CONFIG_Addr0             0x20
 282
 283 /* [9:31] SD Control Register Base Address */
 284 #define ASIC3_SD_CONFIG_Addr1             0x24
 285
 286 /* R/O: interrupt assigned to pin */
 287 #define ASIC3_SD_CONFIG_IntPin            0x78
 288
 289 /*
 290  * Set to 0x1f to clock SD controller, 0 otherwise.
 291  * At 0x82 - Gated Clock Ctrl
 292  */
 293 #define ASIC3_SD_CONFIG_ClkStop           0x80
 294
 295 /* Control clock of SD controller */
 296 #define ASIC3_SD_CONFIG_ClockMode         0x84
 297 #define ASIC3_SD_CONFIG_SDHC_PinStatus    0x88   /* R/0: SD pins status */
 298 #define ASIC3_SD_CONFIG_SDHC_Power1       0x90   /* Power1 - manual pwr ctrl */
 299
 300 /* auto power up after card inserted */
 301 #define ASIC3_SD_CONFIG_SDHC_Power2       0x92
 302
 303 /* auto power down when card removed */
 304 #define ASIC3_SD_CONFIG_SDHC_Power3       0x94
 305 #define ASIC3_SD_CONFIG_SDHC_CardDetect   0x98
 306 #define ASIC3_SD_CONFIG_SDHC_Slot         0xA0   /* R/O: support slot number */
 307 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1  0x1E0  /* Not used */
 308 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2  0x1E2  /* Not used*/
 309
 310 /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
 311 #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable  0x1E8
 312 #define ASIC3_SD_CONFIG_SDHC_GPIO_Status  0x1EC  /* GPIO Status Reg. */
 313
 314 /* Bit 1: double buffer/single buffer */
 315 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3  0x1F0
 316
 317 /* Memory access enable (set to 1 to access SD Controller) */
 318 #define SD_CONFIG_COMMAND_MAE                (1<<1)
 319
 320 #define SD_CONFIG_CLK_ENABLE_ALL             0x1f
 321
 322 #define SD_CONFIG_POWER1_PC_33V              0x0200    /* Set for 3.3 volts */
 323 #define SD_CONFIG_POWER1_PC_OFF              0x0000    /* Turn off power */
 324
 325  /* two bits - number of cycles for card detection */
 326 #define SD_CONFIG_CARDDETECTMODE_CLK           ((x) & 0x3)
 327
 328
 329 #define ASIC3_SD_CTRL_Base            0x1000
 330
 331 #define ASIC3_SD_CTRL_Cmd                  0x00
 332 #define ASIC3_SD_CTRL_Arg0                 0x08
 333 #define ASIC3_SD_CTRL_Arg1                 0x0C
 334 #define ASIC3_SD_CTRL_StopInternal         0x10
 335 #define ASIC3_SD_CTRL_TransferSectorCount  0x14
 336 #define ASIC3_SD_CTRL_Response0            0x18
 337 #define ASIC3_SD_CTRL_Response1            0x1C
 338 #define ASIC3_SD_CTRL_Response2            0x20
 339 #define ASIC3_SD_CTRL_Response3            0x24
 340 #define ASIC3_SD_CTRL_Response4            0x28
 341 #define ASIC3_SD_CTRL_Response5            0x2C
 342 #define ASIC3_SD_CTRL_Response6            0x30
 343 #define ASIC3_SD_CTRL_Response7            0x34
 344 #define ASIC3_SD_CTRL_CardStatus           0x38
 345 #define ASIC3_SD_CTRL_BufferCtrl           0x3C
 346 #define ASIC3_SD_CTRL_IntMaskCard          0x40
 347 #define ASIC3_SD_CTRL_IntMaskBuffer        0x44
 348 #define ASIC3_SD_CTRL_CardClockCtrl        0x48
 349 #define ASIC3_SD_CTRL_MemCardXferDataLen   0x4C
 350 #define ASIC3_SD_CTRL_MemCardOptionSetup   0x50
 351 #define ASIC3_SD_CTRL_ErrorStatus0         0x58
 352 #define ASIC3_SD_CTRL_ErrorStatus1         0x5C
 353 #define ASIC3_SD_CTRL_DataPort             0x60
 354 #define ASIC3_SD_CTRL_TransactionCtrl      0x68
 355 #define ASIC3_SD_CTRL_SoftwareReset        0x1C0
 356
 357 #define SD_CTRL_SOFTWARE_RESET_CLEAR            (1<<0)
 358
 359 #define SD_CTRL_TRANSACTIONCONTROL_SET          (1<<8)
 360
 361 #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD    (1<<15)
 362 #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK   (1<<8)
 363 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512    (1<<7)
 364 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256    (1<<6)
 365 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128    (1<<5)
 366 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64     (1<<4)
 367 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32     (1<<3)
 368 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16     (1<<2)
 369 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8      (1<<1)
 370 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4      (1<<0)
 371 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2      (0<<0)
 372
 373 #define MEM_CARD_OPTION_REQUIRED                   0x000e
 374 #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x)   (((x) & 0x0f) << 4)
 375 #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT      (1<<14)
 376 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1           (1<<15)
 377 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4           0
 378
 379 #define SD_CTRL_COMMAND_INDEX(x)                   ((x) & 0x3f)
 380 #define SD_CTRL_COMMAND_TYPE_CMD                   (0 << 6)
 381 #define SD_CTRL_COMMAND_TYPE_ACMD                  (1 << 6)
 382 #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION        (2 << 6)
 383 #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL       (0 << 8)
 384 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1       (4 << 8)
 385 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B      (5 << 8)
 386 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2       (6 << 8)
 387 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3       (7 << 8)
 388 #define SD_CTRL_COMMAND_DATA_PRESENT               (1 << 11)
 389 #define SD_CTRL_COMMAND_TRANSFER_READ              (1 << 12)
 390 #define SD_CTRL_COMMAND_TRANSFER_WRITE             (0 << 12)
 391 #define SD_CTRL_COMMAND_MULTI_BLOCK                (1 << 13)
 392 #define SD_CTRL_COMMAND_SECURITY_CMD               (1 << 14)
 393
 394 #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12         (1 << 0)
 395 #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12     (1 << 8)
 396
 397 #define SD_CTRL_CARDSTATUS_RESPONSE_END            (1 << 0)
 398 #define SD_CTRL_CARDSTATUS_RW_END                  (1 << 2)
 399 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0          (1 << 3)
 400 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0         (1 << 4)
 401 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0  (1 << 5)
 402 #define SD_CTRL_CARDSTATUS_WRITE_PROTECT           (1 << 7)
 403 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3          (1 << 8)
 404 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3         (1 << 9)
 405 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3  (1 << 10)
 406
 407 #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR       (1 << 0)
 408 #define SD_CTRL_BUFFERSTATUS_CRC_ERROR             (1 << 1)
 409 #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR    (1 << 2)
 410 #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT          (1 << 3)
 411 #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW       (1 << 4)
 412 #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW      (1 << 5)
 413 #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT           (1 << 6)
 414 #define SD_CTRL_BUFFERSTATUS_UNK7                  (1 << 7)
 415 #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE    (1 << 8)
 416 #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE   (1 << 9)
 417 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION      (1 << 13)
 418 #define SD_CTRL_BUFFERSTATUS_CMD_BUSY              (1 << 14)
 419 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS        (1 << 15)
 420
 421 #define SD_CTRL_INTMASKCARD_RESPONSE_END           (1 << 0)
 422 #define SD_CTRL_INTMASKCARD_RW_END                 (1 << 2)
 423 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0         (1 << 3)
 424 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0        (1 << 4)
 425 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
 426 #define SD_CTRL_INTMASKCARD_UNK6                   (1 << 6)
 427 #define SD_CTRL_INTMASKCARD_WRITE_PROTECT          (1 << 7)
 428 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3         (1 << 8)
 429 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3        (1 << 9)
 430 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
 431
 432 #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR      (1 << 0)
 433 #define SD_CTRL_INTMASKBUFFER_CRC_ERROR            (1 << 1)
 434 #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR   (1 << 2)
 435 #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT         (1 << 3)
 436 #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW      (1 << 4)
 437 #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW     (1 << 5)
 438 #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT          (1 << 6)
 439 #define SD_CTRL_INTMASKBUFFER_UNK7                 (1 << 7)
 440 #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE   (1 << 8)
 441 #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE  (1 << 9)
 442 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION     (1 << 13)
 443 #define SD_CTRL_INTMASKBUFFER_CMD_BUSY             (1 << 14)
 444 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS       (1 << 15)
 445
 446 #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR                   (1 << 0)
 447 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
 448 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12     (1 << 3)
 449 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA          (1 << 4)
 450 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS   (1 << 5)
 451 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12     (1 << 8)
 452 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12         (1 << 9)
 453 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA              (1 << 10)
 454 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD              (1 << 11)
 455
 456 #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE                      (1 << 0)
 457 #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA                    (1 << 4)
 458 #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS                   (1 << 5)
 459 #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY                     (1 << 6)
 460
 461 #define ASIC3_SDIO_CTRL_Base          0x1200
 462
 463 #define ASIC3_SDIO_CTRL_Cmd                  0x00
 464 #define ASIC3_SDIO_CTRL_CardPortSel          0x04
 465 #define ASIC3_SDIO_CTRL_Arg0                 0x08
 466 #define ASIC3_SDIO_CTRL_Arg1                 0x0C
 467 #define ASIC3_SDIO_CTRL_TransferBlockCount   0x14
 468 #define ASIC3_SDIO_CTRL_Response0            0x18
 469 #define ASIC3_SDIO_CTRL_Response1            0x1C
 470 #define ASIC3_SDIO_CTRL_Response2            0x20
 471 #define ASIC3_SDIO_CTRL_Response3            0x24
 472 #define ASIC3_SDIO_CTRL_Response4            0x28
 473 #define ASIC3_SDIO_CTRL_Response5            0x2C
 474 #define ASIC3_SDIO_CTRL_Response6            0x30
 475 #define ASIC3_SDIO_CTRL_Response7            0x34
 476 #define ASIC3_SDIO_CTRL_CardStatus           0x38
 477 #define ASIC3_SDIO_CTRL_BufferCtrl           0x3C
 478 #define ASIC3_SDIO_CTRL_IntMaskCard          0x40
 479 #define ASIC3_SDIO_CTRL_IntMaskBuffer        0x44
 480 #define ASIC3_SDIO_CTRL_CardXferDataLen      0x4C
 481 #define ASIC3_SDIO_CTRL_CardOptionSetup      0x50
 482 #define ASIC3_SDIO_CTRL_ErrorStatus0         0x54
 483 #define ASIC3_SDIO_CTRL_ErrorStatus1         0x58
 484 #define ASIC3_SDIO_CTRL_DataPort             0x60
 485 #define ASIC3_SDIO_CTRL_TransactionCtrl      0x68
 486 #define ASIC3_SDIO_CTRL_CardIntCtrl          0x6C
 487 #define ASIC3_SDIO_CTRL_ClocknWaitCtrl       0x70
 488 #define ASIC3_SDIO_CTRL_HostInformation      0x74
 489 #define ASIC3_SDIO_CTRL_ErrorCtrl            0x78
 490 #define ASIC3_SDIO_CTRL_LEDCtrl              0x7C
 491 #define ASIC3_SDIO_CTRL_SoftwareReset        0x1C0
 492
 493 #define ASIC3_MAP_SIZE                       0x2000
 494
 495 #endif /* __ASIC3_H__ */