drivers/pcmcia/m8xx_pcmcia.c

   1 /*
   2  * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
   3  *
   4  * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
   5  * (C) 2001-2002 Montavista Software, Inc.
   6  *     <mlocke@mvista.com>
   7  *
   8  * Support for two slots by Cyclades Corporation
   9  *     <oliver.kurth@cyclades.de>
  10  * Further fixes, v2.6 kernel port
  11  *     <marcelo.tosatti@cyclades.com>
  12  *
  13  * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
  14  *     <vbordug@ru.mvista.com>
  15  *
  16  * "The ExCA standard specifies that socket controllers should provide
  17  * two IO and five memory windows per socket, which can be independently
  18  * configured and positioned in the host address space and mapped to
  19  * arbitrary segments of card address space. " - David A Hinds. 1999
  20  *
  21  * This controller does _not_ meet the ExCA standard.
  22  *
  23  * m8xx pcmcia controller brief info:
  24  * + 8 windows (attrib, mem, i/o)
  25  * + up to two slots (SLOT_A and SLOT_B)
  26  * + inputpins, outputpins, event and mask registers.
  27  * - no offset register. sigh.
  28  *
  29  * Because of the lacking offset register we must map the whole card.
  30  * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
  31  * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
  32  * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
  33  * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
  34  * They are maximum 64KByte each...
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/types.h>
  40 #include <linux/fcntl.h>
  41 #include <linux/string.h>
  42
  43 #include <linux/kernel.h>
  44 #include <linux/errno.h>
  45 #include <linux/slab.h>
  46 #include <linux/timer.h>
  47 #include <linux/ioport.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/fsl_devices.h>
  51
  52 #include <asm/io.h>
  53 #include <asm/bitops.h>
  54 #include <asm/system.h>
  55 #include <asm/time.h>
  56 #include <asm/mpc8xx.h>
  57 #include <asm/8xx_immap.h>
  58 #include <asm/irq.h>
  59 #include <asm/fs_pd.h>
  60 #include <asm/of_device.h>
  61 #include <asm/of_platform.h>
  62
  63 #include <pcmcia/version.h>
  64 #include <pcmcia/cs_types.h>
  65 #include <pcmcia/cs.h>
  66 #include <pcmcia/ss.h>
  67
  68 #ifdef PCMCIA_DEBUG
  69 static int pc_debug = PCMCIA_DEBUG;
  70 module_param(pc_debug, int, 0);
  71 #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
  72 #else
  73 #define dprintk(args...)
  74 #endif
  75
  76 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
  77 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
  78
  79 static const char *version = "Version 0.06, Aug 2005";
  80 MODULE_LICENSE("Dual MPL/GPL");
  81
  82 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  83
  84 /* The RPX series use SLOT_B */
  85 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
  86 #define CONFIG_PCMCIA_SLOT_B
  87 #define CONFIG_BD_IS_MHZ
  88 #endif
  89
  90 /* The ADS board use SLOT_A */
  91 #ifdef CONFIG_ADS
  92 #define CONFIG_PCMCIA_SLOT_A
  93 #define CONFIG_BD_IS_MHZ
  94 #endif
  95
  96 /* The FADS series are a mess */
  97 #ifdef CONFIG_FADS
  98 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
  99 #define CONFIG_PCMCIA_SLOT_A
 100 #else
 101 #define CONFIG_PCMCIA_SLOT_B
 102 #endif
 103 #endif
 104
 105 #if defined(CONFIG_MPC885ADS)
 106 #define CONFIG_PCMCIA_SLOT_A
 107 #define PCMCIA_GLITCHY_CD
 108 #endif
 109
 110 /* Cyclades ACS uses both slots */
 111 #ifdef CONFIG_PRxK
 112 #define CONFIG_PCMCIA_SLOT_A
 113 #define CONFIG_PCMCIA_SLOT_B
 114 #endif
 115
 116 #endif                          /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
 117
 118 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
 119
 120 #define PCMCIA_SOCKETS_NO 2
 121 /* We have only 8 windows, dualsocket support will be limited. */
 122 #define PCMCIA_MEM_WIN_NO 2
 123 #define PCMCIA_IO_WIN_NO  2
 124 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
 125
 126 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
 127
 128 #define PCMCIA_SOCKETS_NO 1
 129 /* full support for one slot */
 130 #define PCMCIA_MEM_WIN_NO 5
 131 #define PCMCIA_IO_WIN_NO  2
 132
 133 /* define _slot_ to be able to optimize macros */
 134
 135 #ifdef CONFIG_PCMCIA_SLOT_A
 136 #define _slot_ 0
 137 #define PCMCIA_SLOT_MSG "SLOT_A"
 138 #else
 139 #define _slot_ 1
 140 #define PCMCIA_SLOT_MSG "SLOT_B"
 141 #endif
 142
 143 #else
 144 #error m8xx_pcmcia: Bad configuration!
 145 #endif
 146
 147 /* ------------------------------------------------------------------------- */
 148
 149 #define PCMCIA_MEM_WIN_BASE 0xe0000000  /* base address for memory window 0   */
 150 #define PCMCIA_MEM_WIN_SIZE 0x04000000  /* each memory window is 64 MByte     */
 151 #define PCMCIA_IO_WIN_BASE  _IO_BASE    /* base address for io window 0       */
 152 /* ------------------------------------------------------------------------- */
 153
 154 static int pcmcia_schlvl;
 155
 156 static DEFINE_SPINLOCK(events_lock);
 157
 158 #define PCMCIA_SOCKET_KEY_5V 1
 159 #define PCMCIA_SOCKET_KEY_LV 2
 160
 161 /* look up table for pgcrx registers */
 162 static u32 *m8xx_pgcrx[2];
 163
 164 /*
 165  * This structure is used to address each window in the PCMCIA controller.
 166  *
 167  * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
 168  * after pcmcia_win[n]...
 169  */
 170
 171 struct pcmcia_win {
 172         u32 br;
 173         u32 or;
 174 };
 175
 176 /*
 177  * For some reason the hardware guys decided to make both slots share
 178  * some registers.
 179  *
 180  * Could someone invent object oriented hardware ?
 181  *
 182  * The macros are used to get the right bit from the registers.
 183  * SLOT_A : slot = 0
 184  * SLOT_B : slot = 1
 185  */
 186
 187 #define M8XX_PCMCIA_VS1(slot)      (0x80000000 >> (slot << 4))
 188 #define M8XX_PCMCIA_VS2(slot)      (0x40000000 >> (slot << 4))
 189 #define M8XX_PCMCIA_VS_MASK(slot)  (0xc0000000 >> (slot << 4))
 190 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
 191
 192 #define M8XX_PCMCIA_WP(slot)       (0x20000000 >> (slot << 4))
 193 #define M8XX_PCMCIA_CD2(slot)      (0x10000000 >> (slot << 4))
 194 #define M8XX_PCMCIA_CD1(slot)      (0x08000000 >> (slot << 4))
 195 #define M8XX_PCMCIA_BVD2(slot)     (0x04000000 >> (slot << 4))
 196 #define M8XX_PCMCIA_BVD1(slot)     (0x02000000 >> (slot << 4))
 197 #define M8XX_PCMCIA_RDY(slot)      (0x01000000 >> (slot << 4))
 198 #define M8XX_PCMCIA_RDY_L(slot)    (0x00800000 >> (slot << 4))
 199 #define M8XX_PCMCIA_RDY_H(slot)    (0x00400000 >> (slot << 4))
 200 #define M8XX_PCMCIA_RDY_R(slot)    (0x00200000 >> (slot << 4))
 201 #define M8XX_PCMCIA_RDY_F(slot)    (0x00100000 >> (slot << 4))
 202 #define M8XX_PCMCIA_MASK(slot)     (0xFFFF0000 >> (slot << 4))
 203
 204 #define M8XX_PCMCIA_POR_VALID    0x00000001
 205 #define M8XX_PCMCIA_POR_WRPROT   0x00000002
 206 #define M8XX_PCMCIA_POR_ATTRMEM  0x00000010
 207 #define M8XX_PCMCIA_POR_IO       0x00000018
 208 #define M8XX_PCMCIA_POR_16BIT    0x00000040
 209
 210 #define M8XX_PGCRX(slot)  m8xx_pgcrx[slot]
 211
 212 #define M8XX_PGCRX_CXOE    0x00000080
 213 #define M8XX_PGCRX_CXRESET 0x00000040
 214
 215 /* we keep one lookup table per socket to check flags */
 216
 217 #define PCMCIA_EVENTS_MAX 5     /* 4 max at a time + termination */
 218
 219 struct event_table {
 220         u32 regbit;
 221         u32 eventbit;
 222 };
 223
 224 static const char driver_name[] = "m8xx-pcmcia";
 225
 226 struct socket_info {
 227         void (*handler) (void *info, u32 events);
 228         void *info;
 229
 230         u32 slot;
 231         pcmconf8xx_t *pcmcia;
 232         u32 bus_freq;
 233         int hwirq;
 234
 235         socket_state_t state;
 236         struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
 237         struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
 238         struct event_table events[PCMCIA_EVENTS_MAX];
 239         struct pcmcia_socket socket;
 240 };
 241
 242 static struct socket_info socket[PCMCIA_SOCKETS_NO];
 243
 244 /*
 245  * Search this table to see if the windowsize is
 246  * supported...
 247  */
 248
 249 #define M8XX_SIZES_NO 32
 250
 251 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
 252         0x00000001, 0x00000002, 0x00000008, 0x00000004,
 253         0x00000080, 0x00000040, 0x00000010, 0x00000020,
 254         0x00008000, 0x00004000, 0x00001000, 0x00002000,
 255         0x00000100, 0x00000200, 0x00000800, 0x00000400,
 256
 257         0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 258         0x01000000, 0x02000000, 0xffffffff, 0x04000000,
 259         0x00010000, 0x00020000, 0x00080000, 0x00040000,
 260         0x00800000, 0x00400000, 0x00100000, 0x00200000
 261 };
 262
 263 /* ------------------------------------------------------------------------- */
 264
 265 static irqreturn_t m8xx_interrupt(int irq, void *dev);
 266
 267 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
 268
 269 /* ------------------------------------------------------------------------- */
 270 /* board specific stuff:                                                     */
 271 /* voltage_set(), hardware_enable() and hardware_disable()                   */
 272 /* ------------------------------------------------------------------------- */
 273 /* RPX Boards from Embedded Planet                                           */
 274
 275 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
 276
 277 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
 278  * SYPCR is write once only, therefore must the slowest memory be faster
 279  * than the bus monitor or we will get a machine check due to the bus timeout.
 280  */
 281
 282 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
 283
 284 #undef PCMCIA_BMT_LIMIT
 285 #define PCMCIA_BMT_LIMIT (6*8)
 286
 287 static int voltage_set(int slot, int vcc, int vpp)
 288 {
 289         u32 reg = 0;
 290
 291         switch (vcc) {
 292         case 0:
 293                 break;
 294         case 33:
 295                 reg |= BCSR1_PCVCTL4;
 296                 break;
 297         case 50:
 298                 reg |= BCSR1_PCVCTL5;
 299                 break;
 300         default:
 301                 return 1;
 302         }
 303
 304         switch (vpp) {
 305         case 0:
 306                 break;
 307         case 33:
 308         case 50:
 309                 if (vcc == vpp)
 310                         reg |= BCSR1_PCVCTL6;
 311                 else
 312                         return 1;
 313                 break;
 314         case 120:
 315                 reg |= BCSR1_PCVCTL7;
 316         default:
 317                 return 1;
 318         }
 319
 320         if (!((vcc == 50) || (vcc == 0)))
 321                 return 1;
 322
 323         /* first, turn off all power */
 324
 325         out_be32(((u32 *) RPX_CSR_ADDR),
 326                  in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
 327                                                      BCSR1_PCVCTL5 |
 328                                                      BCSR1_PCVCTL6 |
 329                                                      BCSR1_PCVCTL7));
 330
 331         /* enable new powersettings */
 332
 333         out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
 334
 335         return 0;
 336 }
 337
 338 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 339 #define hardware_enable(_slot_) /* No hardware to enable */
 340 #define hardware_disable(_slot_)        /* No hardware to disable */
 341
 342 #endif                          /* CONFIG_RPXCLASSIC */
 343
 344 /* FADS Boards from Motorola                                               */
 345
 346 #if defined(CONFIG_FADS)
 347
 348 #define PCMCIA_BOARD_MSG "FADS"
 349
 350 static int voltage_set(int slot, int vcc, int vpp)
 351 {
 352         u32 reg = 0;
 353
 354         switch (vcc) {
 355         case 0:
 356                 break;
 357         case 33:
 358                 reg |= BCSR1_PCCVCC0;
 359                 break;
 360         case 50:
 361                 reg |= BCSR1_PCCVCC1;
 362                 break;
 363         default:
 364                 return 1;
 365         }
 366
 367         switch (vpp) {
 368         case 0:
 369                 break;
 370         case 33:
 371         case 50:
 372                 if (vcc == vpp)
 373                         reg |= BCSR1_PCCVPP1;
 374                 else
 375                         return 1;
 376                 break;
 377         case 120:
 378                 if ((vcc == 33) || (vcc == 50))
 379                         reg |= BCSR1_PCCVPP0;
 380                 else
 381                         return 1;
 382         default:
 383                 return 1;
 384         }
 385
 386         /* first, turn off all power */
 387         out_be32((u32 *) BCSR1,
 388                  in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
 389                                             BCSR1_PCCVPP_MASK));
 390
 391         /* enable new powersettings */
 392         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
 393
 394         return 0;
 395 }
 396
 397 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 398
 399 static void hardware_enable(int slot)
 400 {
 401         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
 402 }
 403
 404 static void hardware_disable(int slot)
 405 {
 406         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
 407 }
 408
 409 #endif
 410
 411 /* MPC885ADS Boards */
 412
 413 #if defined(CONFIG_MPC885ADS)
 414
 415 #define PCMCIA_BOARD_MSG "MPC885ADS"
 416 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 417
 418 static inline void hardware_enable(int slot)
 419 {
 420         m8xx_pcmcia_ops.hw_ctrl(slot, 1);
 421 }
 422
 423 static inline void hardware_disable(int slot)
 424 {
 425         m8xx_pcmcia_ops.hw_ctrl(slot, 0);
 426 }
 427
 428 static inline int voltage_set(int slot, int vcc, int vpp)
 429 {
 430         return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
 431 }
 432
 433 #endif
 434
 435 /* ------------------------------------------------------------------------- */
 436 /* Motorola MBX860                                                           */
 437
 438 #if defined(CONFIG_MBX)
 439
 440 #define PCMCIA_BOARD_MSG "MBX"
 441
 442 static int voltage_set(int slot, int vcc, int vpp)
 443 {
 444         u8 reg = 0;
 445
 446         switch (vcc) {
 447         case 0:
 448                 break;
 449         case 33:
 450                 reg |= CSR2_VCC_33;
 451                 break;
 452         case 50:
 453                 reg |= CSR2_VCC_50;
 454                 break;
 455         default:
 456                 return 1;
 457         }
 458
 459         switch (vpp) {
 460         case 0:
 461                 break;
 462         case 33:
 463         case 50:
 464                 if (vcc == vpp)
 465                         reg |= CSR2_VPP_VCC;
 466                 else
 467                         return 1;
 468                 break;
 469         case 120:
 470                 if ((vcc == 33) || (vcc == 50))
 471                         reg |= CSR2_VPP_12;
 472                 else
 473                         return 1;
 474         default:
 475                 return 1;
 476         }
 477
 478         /* first, turn off all power */
 479         out_8((u8 *) MBX_CSR2_ADDR,
 480               in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
 481
 482         /* enable new powersettings */
 483         out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
 484
 485         return 0;
 486 }
 487
 488 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 489 #define hardware_enable(_slot_) /* No hardware to enable */
 490 #define hardware_disable(_slot_)        /* No hardware to disable */
 491
 492 #endif                          /* CONFIG_MBX */
 493
 494 #if defined(CONFIG_PRxK)
 495 #include <asm/cpld.h>
 496 extern volatile fpga_pc_regs *fpga_pc;
 497
 498 #define PCMCIA_BOARD_MSG "MPC855T"
 499
 500 static int voltage_set(int slot, int vcc, int vpp)
 501 {
 502         u8 reg = 0;
 503         u8 regread;
 504         cpld_regs *ccpld = get_cpld();
 505
 506         switch (vcc) {
 507         case 0:
 508                 break;
 509         case 33:
 510                 reg |= PCMCIA_VCC_33;
 511                 break;
 512         case 50:
 513                 reg |= PCMCIA_VCC_50;
 514                 break;
 515         default:
 516                 return 1;
 517         }
 518
 519         switch (vpp) {
 520         case 0:
 521                 break;
 522         case 33:
 523         case 50:
 524                 if (vcc == vpp)
 525                         reg |= PCMCIA_VPP_VCC;
 526                 else
 527                         return 1;
 528                 break;
 529         case 120:
 530                 if ((vcc == 33) || (vcc == 50))
 531                         reg |= PCMCIA_VPP_12;
 532                 else
 533                         return 1;
 534         default:
 535                 return 1;
 536         }
 537
 538         reg = reg >> (slot << 2);
 539         regread = in_8(&ccpld->fpga_pc_ctl);
 540         if (reg !=
 541             (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
 542                 /* enable new powersettings */
 543                 regread =
 544                     regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
 545                                 (slot << 2));
 546                 out_8(&ccpld->fpga_pc_ctl, reg | regread);
 547                 msleep(100);
 548         }
 549
 550         return 0;
 551 }
 552
 553 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
 554 #define hardware_enable(_slot_) /* No hardware to enable */
 555 #define hardware_disable(_slot_)        /* No hardware to disable */
 556
 557 #endif                          /* CONFIG_PRxK */
 558
 559 static u32 pending_events[PCMCIA_SOCKETS_NO];
 560 static DEFINE_SPINLOCK(pending_event_lock);
 561
 562 static irqreturn_t m8xx_interrupt(int irq, void *dev)
 563 {
 564         struct socket_info *s;
 565         struct event_table *e;
 566         unsigned int i, events, pscr, pipr, per;
 567         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 568
 569         dprintk("Interrupt!\n");
 570         /* get interrupt sources */
 571
 572         pscr = in_be32(&pcmcia->pcmc_pscr);
 573         pipr = in_be32(&pcmcia->pcmc_pipr);
 574         per = in_be32(&pcmcia->pcmc_per);
 575
 576         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
 577                 s = &socket[i];
 578                 e = &s->events[0];
 579                 events = 0;
 580
 581                 while (e->regbit) {
 582                         if (pscr & e->regbit)
 583                                 events |= e->eventbit;
 584
 585                         e++;
 586                 }
 587
 588                 /*
 589                  * report only if both card detect signals are the same
 590                  * not too nice done,
 591                  * we depend on that CD2 is the bit to the left of CD1...
 592                  */
 593                 if (events & SS_DETECT)
 594                         if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
 595                             (pipr & M8XX_PCMCIA_CD1(i))) {
 596                                 events &= ~SS_DETECT;
 597                         }
 598 #ifdef PCMCIA_GLITCHY_CD
 599                 /*
 600                  * I've experienced CD problems with my ADS board.
 601                  * We make an extra check to see if there was a
 602                  * real change of Card detection.
 603                  */
 604
 605                 if ((events & SS_DETECT) &&
 606                     ((pipr &
 607                       (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
 608                     (s->state.Vcc | s->state.Vpp)) {
 609                         events &= ~SS_DETECT;
 610                         /*printk( "CD glitch workaround - CD = 0x%08x!\n",
 611                            (pipr & (M8XX_PCMCIA_CD2(i)
 612                            | M8XX_PCMCIA_CD1(i)))); */
 613                 }
 614 #endif
 615
 616                 /* call the handler */
 617
 618                 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
 619                         "pipr = 0x%08x\n", i, events, pscr, pipr);
 620
 621                 if (events) {
 622                         spin_lock(&pending_event_lock);
 623                         pending_events[i] |= events;
 624                         spin_unlock(&pending_event_lock);
 625                         /*
 626                          * Turn off RDY_L bits in the PER mask on
 627                          * CD interrupt receival.
 628                          *
 629                          * They can generate bad interrupts on the
 630                          * ACS4,8,16,32.   - marcelo
 631                          */
 632                         per &= ~M8XX_PCMCIA_RDY_L(0);
 633                         per &= ~M8XX_PCMCIA_RDY_L(1);
 634
 635                         out_be32(&pcmcia->pcmc_per, per);
 636
 637                         if (events)
 638                                 pcmcia_parse_events(&socket[i].socket, events);
 639                 }
 640         }
 641
 642         /* clear the interrupt sources */
 643         out_be32(&pcmcia->pcmc_pscr, pscr);
 644
 645         dprintk("Interrupt done.\n");
 646
 647         return IRQ_HANDLED;
 648 }
 649
 650 static u32 m8xx_get_graycode(u32 size)
 651 {
 652         u32 k;
 653
 654         for (k = 0; k < M8XX_SIZES_NO; k++)
 655                 if (m8xx_size_to_gray[k] == size)
 656                         break;
 657
 658         if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
 659                 k = -1;
 660
 661         return k;
 662 }
 663
 664 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
 665 {
 666         u32 reg, clocks, psst, psl, psht;
 667
 668         if (!ns) {
 669
 670                 /*
 671                  * We get called with IO maps setup to 0ns
 672                  * if not specified by the user.
 673                  * They should be 255ns.
 674                  */
 675
 676                 if (is_io)
 677                         ns = 255;
 678                 else
 679                         ns = 100;       /* fast memory if 0 */
 680         }
 681
 682         /*
 683          * In PSST, PSL, PSHT fields we tell the controller
 684          * timing parameters in CLKOUT clock cycles.
 685          * CLKOUT is the same as GCLK2_50.
 686          */
 687
 688 /* how we want to adjust the timing - in percent */
 689
 690 #define ADJ 180                 /* 80 % longer accesstime - to be sure */
 691
 692         clocks = ((bus_freq / 1000) * ns) / 1000;
 693         clocks = (clocks * ADJ) / (100 * 1000);
 694         if (clocks >= PCMCIA_BMT_LIMIT) {
 695                 printk("Max access time limit reached\n");
 696                 clocks = PCMCIA_BMT_LIMIT - 1;
 697         }
 698
 699         psst = clocks / 7;      /* setup time */
 700         psht = clocks / 7;      /* hold time */
 701         psl = (clocks * 5) / 7; /* strobe length */
 702
 703         psst += clocks - (psst + psht + psl);
 704
 705         reg = psst << 12;
 706         reg |= psl << 7;
 707         reg |= psht << 16;
 708
 709         return reg;
 710 }
 711
 712 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
 713 {
 714         int lsock = container_of(sock, struct socket_info, socket)->slot;
 715         struct socket_info *s = &socket[lsock];
 716         unsigned int pipr, reg;
 717         pcmconf8xx_t *pcmcia = s->pcmcia;
 718
 719         pipr = in_be32(&pcmcia->pcmc_pipr);
 720
 721         *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
 722                            | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
 723         *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
 724
 725         if (s->state.flags & SS_IOCARD)
 726                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
 727         else {
 728                 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
 729                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
 730                 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
 731         }
 732
 733         if (s->state.Vcc | s->state.Vpp)
 734                 *value |= SS_POWERON;
 735
 736         /*
 737          * Voltage detection:
 738          * This driver only supports 16-Bit pc-cards.
 739          * Cardbus is not handled here.
 740          *
 741          * To determine what voltage to use we must read the VS1 and VS2 pin.
 742          * Depending on what socket type is present,
 743          * different combinations mean different things.
 744          *
 745          * Card Key  Socket Key   VS1   VS2   Card         Vcc for CIS parse
 746          *
 747          * 5V        5V, LV*      NC    NC    5V only       5V (if available)
 748          *
 749          * 5V        5V, LV*      GND   NC    5 or 3.3V     as low as possible
 750          *
 751          * 5V        5V, LV*      GND   GND   5, 3.3, x.xV  as low as possible
 752          *
 753          * LV*       5V            -     -    shall not fit into socket
 754          *
 755          * LV*       LV*          GND   NC    3.3V only     3.3V
 756          *
 757          * LV*       LV*          NC    GND   x.xV          x.xV (if avail.)
 758          *
 759          * LV*       LV*          GND   GND   3.3 or x.xV   as low as possible
 760          *
 761          * *LV means Low Voltage
 762          *
 763          *
 764          * That gives us the following table:
 765          *
 766          * Socket    VS1  VS2   Voltage
 767          *
 768          * 5V        NC   NC    5V
 769          * 5V        NC   GND   none (should not be possible)
 770          * 5V        GND  NC    >= 3.3V
 771          * 5V        GND  GND   >= x.xV
 772          *
 773          * LV        NC   NC    5V   (if available)
 774          * LV        NC   GND   x.xV (if available)
 775          * LV        GND  NC    3.3V
 776          * LV        GND  GND   >= x.xV
 777          *
 778          * So, how do I determine if I have a 5V or a LV
 779          * socket on my board?  Look at the socket!
 780          *
 781          *
 782          * Socket with 5V key:
 783          * ++--------------------------------------------+
 784          * ||                                            |
 785          * ||                                           ||
 786          * ||                                           ||
 787          * |                                             |
 788          * +---------------------------------------------+
 789          *
 790          * Socket with LV key:
 791          * ++--------------------------------------------+
 792          * ||                                            |
 793          * |                                            ||
 794          * |                                            ||
 795          * |                                             |
 796          * +---------------------------------------------+
 797          *
 798          *
 799          * With other words - LV only cards does not fit
 800          * into the 5V socket!
 801          */
 802
 803         /* read out VS1 and VS2 */
 804
 805         reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
 806             >> M8XX_PCMCIA_VS_SHIFT(lsock);
 807
 808         if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
 809                 switch (reg) {
 810                 case 1:
 811                         *value |= SS_3VCARD;
 812                         break;  /* GND, NC - 3.3V only */
 813                 case 2:
 814                         *value |= SS_XVCARD;
 815                         break;  /* NC. GND - x.xV only */
 816                 };
 817         }
 818
 819         dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
 820         return 0;
 821 }
 822
 823 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
 824 {
 825         int lsock = container_of(sock, struct socket_info, socket)->slot;
 826         struct socket_info *s = &socket[lsock];
 827         struct event_table *e;
 828         unsigned int reg;
 829         unsigned long flags;
 830         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 831
 832         dprintk("SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 833                 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
 834                 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 835
 836         /* First, set voltage - bail out if invalid */
 837         if (voltage_set(lsock, state->Vcc, state->Vpp))
 838                 return -EINVAL;
 839
 840         /* Take care of reset... */
 841         if (state->flags & SS_RESET)
 842                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET);   /* active high */
 843         else
 844                 out_be32(M8XX_PGCRX(lsock),
 845                          in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
 846
 847         /* ... and output enable. */
 848
 849         /* The CxOE signal is connected to a 74541 on the ADS.
 850            I guess most other boards used the ADS as a reference.
 851            I tried to control the CxOE signal with SS_OUTPUT_ENA,
 852            but the reset signal seems connected via the 541.
 853            If the CxOE is left high are some signals tristated and
 854            no pullups are present -> the cards act wierd.
 855            So right now the buffers are enabled if the power is on. */
 856
 857         if (state->Vcc || state->Vpp)
 858                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE);     /* active low */
 859         else
 860                 out_be32(M8XX_PGCRX(lsock),
 861                          in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
 862
 863         /*
 864          * We'd better turn off interrupts before
 865          * we mess with the events-table..
 866          */
 867
 868         spin_lock_irqsave(&events_lock, flags);
 869
 870         /*
 871          * Play around with the interrupt mask to be able to
 872          * give the events the generic pcmcia driver wants us to.
 873          */
 874
 875         e = &s->events[0];
 876         reg = 0;
 877
 878         if (state->csc_mask & SS_DETECT) {
 879                 e->eventbit = SS_DETECT;
 880                 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
 881                                     | M8XX_PCMCIA_CD1(lsock));
 882                 e++;
 883         }
 884         if (state->flags & SS_IOCARD) {
 885                 /*
 886                  * I/O card
 887                  */
 888                 if (state->csc_mask & SS_STSCHG) {
 889                         e->eventbit = SS_STSCHG;
 890                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 891                         e++;
 892                 }
 893                 /*
 894                  * If io_irq is non-zero we should enable irq.
 895                  */
 896                 if (state->io_irq) {
 897                         out_be32(M8XX_PGCRX(lsock),
 898                                  in_be32(M8XX_PGCRX(lsock)) |
 899                                  mk_int_int_mask(s->hwirq) << 24);
 900                         /*
 901                          * Strange thing here:
 902                          * The manual does not tell us which interrupt
 903                          * the sources generate.
 904                          * Anyhow, I found out that RDY_L generates IREQLVL.
 905                          *
 906                          * We use level triggerd interrupts, and they don't
 907                          * have to be cleared in PSCR in the interrupt handler.
 908                          */
 909                         reg |= M8XX_PCMCIA_RDY_L(lsock);
 910                 } else
 911                         out_be32(M8XX_PGCRX(lsock),
 912                                  in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
 913         } else {
 914                 /*
 915                  * Memory card
 916                  */
 917                 if (state->csc_mask & SS_BATDEAD) {
 918                         e->eventbit = SS_BATDEAD;
 919                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 920                         e++;
 921                 }
 922                 if (state->csc_mask & SS_BATWARN) {
 923                         e->eventbit = SS_BATWARN;
 924                         reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
 925                         e++;
 926                 }
 927                 /* What should I trigger on - low/high,raise,fall? */
 928                 if (state->csc_mask & SS_READY) {
 929                         e->eventbit = SS_READY;
 930                         reg |= e->regbit = 0;   //??
 931                         e++;
 932                 }
 933         }
 934
 935         e->regbit = 0;          /* terminate list */
 936
 937         /*
 938          * Clear the status changed .
 939          * Port A and Port B share the same port.
 940          * Writing ones will clear the bits.
 941          */
 942
 943         out_be32(&pcmcia->pcmc_pscr, reg);
 944
 945         /*
 946          * Write the mask.
 947          * Port A and Port B share the same port.
 948          * Need for read-modify-write.
 949          * Ones will enable the interrupt.
 950          */
 951
 952         reg |=
 953             in_be32(&pcmcia->
 954                     pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
 955         out_be32(&pcmcia->pcmc_per, reg);
 956
 957         spin_unlock_irqrestore(&events_lock, flags);
 958
 959         /* copy the struct and modify the copy */
 960
 961         s->state = *state;
 962
 963         return 0;
 964 }
 965
 966 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
 967 {
 968         int lsock = container_of(sock, struct socket_info, socket)->slot;
 969
 970         struct socket_info *s = &socket[lsock];
 971         struct pcmcia_win *w;
 972         unsigned int reg, winnr;
 973         pcmconf8xx_t *pcmcia = s->pcmcia;
 974
 975 #define M8XX_SIZE (io->stop - io->start + 1)
 976 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
 977
 978         dprintk("SetIOMap(%d, %d, %#2.2x, %d ns, "
 979                 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
 980                 io->speed, io->start, io->stop);
 981
 982         if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
 983             || (io->stop > 0xffff) || (io->stop < io->start))
 984                 return -EINVAL;
 985
 986         if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
 987                 return -EINVAL;
 988
 989         if (io->flags & MAP_ACTIVE) {
 990
 991                 dprintk("io->flags & MAP_ACTIVE\n");
 992
 993                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
 994                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
 995
 996                 /* setup registers */
 997
 998                 w = (void *)&pcmcia->pcmc_pbr0;
 999                 w += winnr;
1000
1001                 out_be32(&w->or, 0);    /* turn off window first */
1002                 out_be32(&w->br, M8XX_BASE);
1003
1004                 reg <<= 27;
1005                 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
1006
1007                 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
1008
1009                 if (io->flags & MAP_WRPROT)
1010                         reg |= M8XX_PCMCIA_POR_WRPROT;
1011
1012                 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1013                 if (io->flags & MAP_16BIT)
1014                         reg |= M8XX_PCMCIA_POR_16BIT;
1015
1016                 if (io->flags & MAP_ACTIVE)
1017                         reg |= M8XX_PCMCIA_POR_VALID;
1018
1019                 out_be32(&w->or, reg);
1020
1021                 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1022                         "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1023         } else {
1024                 /* shutdown IO window */
1025                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1026                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1027
1028                 /* setup registers */
1029
1030                 w = (void *)&pcmcia->pcmc_pbr0;
1031                 w += winnr;
1032
1033                 out_be32(&w->or, 0);    /* turn off window */
1034                 out_be32(&w->br, 0);    /* turn off base address */
1035
1036                 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1037                         "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1038         }
1039
1040         /* copy the struct and modify the copy */
1041         s->io_win[io->map] = *io;
1042         s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1043         dprintk("SetIOMap exit\n");
1044
1045         return 0;
1046 }
1047
1048 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1049                             struct pccard_mem_map *mem)
1050 {
1051         int lsock = container_of(sock, struct socket_info, socket)->slot;
1052         struct socket_info *s = &socket[lsock];
1053         struct pcmcia_win *w;
1054         struct pccard_mem_map *old;
1055         unsigned int reg, winnr;
1056         pcmconf8xx_t *pcmcia = s->pcmcia;
1057
1058         dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1059                 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1060                 mem->speed, mem->static_start, mem->card_start);
1061
1062         if ((mem->map >= PCMCIA_MEM_WIN_NO)
1063 //          || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1064             || (mem->card_start >= 0x04000000)
1065             || (mem->static_start & 0xfff)      /* 4KByte resolution */
1066             ||(mem->card_start & 0xfff))
1067                 return -EINVAL;
1068
1069         if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1070                 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1071                 return -EINVAL;
1072         }
1073         reg <<= 27;
1074
1075         winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1076
1077         /* Setup the window in the pcmcia controller */
1078
1079         w = (void *)&pcmcia->pcmc_pbr0;
1080         w += winnr;
1081
1082         reg |= lsock << 2;
1083
1084         reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1085
1086         if (mem->flags & MAP_ATTRIB)
1087                 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1088
1089         if (mem->flags & MAP_WRPROT)
1090                 reg |= M8XX_PCMCIA_POR_WRPROT;
1091
1092         if (mem->flags & MAP_16BIT)
1093                 reg |= M8XX_PCMCIA_POR_16BIT;
1094
1095         if (mem->flags & MAP_ACTIVE)
1096                 reg |= M8XX_PCMCIA_POR_VALID;
1097
1098         out_be32(&w->or, reg);
1099
1100         dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1101                 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1102
1103         if (mem->flags & MAP_ACTIVE) {
1104                 /* get the new base address */
1105                 mem->static_start = PCMCIA_MEM_WIN_BASE +
1106                     (PCMCIA_MEM_WIN_SIZE * winnr)
1107                     + mem->card_start;
1108         }
1109
1110         dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1111                 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1112                 mem->speed, mem->static_start, mem->card_start);
1113
1114         /* copy the struct and modify the copy */
1115
1116         old = &s->mem_win[mem->map];
1117
1118         *old = *mem;
1119         old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1120
1121         return 0;
1122 }
1123
1124 static int m8xx_sock_init(struct pcmcia_socket *sock)
1125 {
1126         int i;
1127         pccard_io_map io = { 0, 0, 0, 0, 1 };
1128         pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1129
1130         dprintk("sock_init(%d)\n", s);
1131
1132         m8xx_set_socket(sock, &dead_socket);
1133         for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1134                 io.map = i;
1135                 m8xx_set_io_map(sock, &io);
1136         }
1137         for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1138                 mem.map = i;
1139                 m8xx_set_mem_map(sock, &mem);
1140         }
1141
1142         return 0;
1143
1144 }
1145
1146 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1147 {
1148         return m8xx_set_socket(sock, &dead_socket);
1149 }
1150
1151 static struct pccard_operations m8xx_services = {
1152         .init = m8xx_sock_init,
1153         .suspend = m8xx_sock_suspend,
1154         .get_status = m8xx_get_status,
1155         .set_socket = m8xx_set_socket,
1156         .set_io_map = m8xx_set_io_map,
1157         .set_mem_map = m8xx_set_mem_map,
1158 };
1159
1160 static int __init m8xx_probe(struct of_device *ofdev,
1161                              const struct of_device_id *match)
1162 {
1163         struct pcmcia_win *w;
1164         unsigned int i, m, hwirq;
1165         pcmconf8xx_t *pcmcia;
1166         int status;
1167         struct device_node *np = ofdev->node;
1168
1169         pcmcia_info("%s\n", version);
1170
1171         pcmcia = of_iomap(np, 0);
1172         if (pcmcia == NULL)
1173                 return -EINVAL;
1174
1175         pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1176         hwirq = irq_map[pcmcia_schlvl].hwirq;
1177         if (pcmcia_schlvl < 0)
1178                 return -EINVAL;
1179
1180         m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1181         m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1182
1183         pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1184                     " with IRQ %u  (%d). \n", pcmcia_schlvl, hwirq);
1185
1186         /* Configure Status change interrupt */
1187
1188         if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1189                         driver_name, socket)) {
1190                 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1191                              pcmcia_schlvl);
1192                 return -1;
1193         }
1194
1195         w = (void *)&pcmcia->pcmc_pbr0;
1196
1197         out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1198         clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1199
1200         /* connect interrupt and disable CxOE */
1201
1202         out_be32(M8XX_PGCRX(0),
1203                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1204         out_be32(M8XX_PGCRX(1),
1205                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1206
1207         /* intialize the fixed memory windows */
1208
1209         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1210                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1211                         out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1212                                  (PCMCIA_MEM_WIN_SIZE
1213                                   * (m + i * PCMCIA_MEM_WIN_NO)));
1214
1215                         out_be32(&w->or, 0);    /* set to not valid */
1216
1217                         w++;
1218                 }
1219         }
1220
1221         /* turn off voltage */
1222         voltage_set(0, 0, 0);
1223         voltage_set(1, 0, 0);
1224
1225         /* Enable external hardware */
1226         hardware_enable(0);
1227         hardware_enable(1);
1228
1229         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1230                 socket[i].slot = i;
1231                 socket[i].socket.owner = THIS_MODULE;
1232                 socket[i].socket.features =
1233                     SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1234                 socket[i].socket.irq_mask = 0x000;
1235                 socket[i].socket.map_size = 0x1000;
1236                 socket[i].socket.io_offset = 0;
1237                 socket[i].socket.pci_irq = pcmcia_schlvl;
1238                 socket[i].socket.ops = &m8xx_services;
1239                 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
1240                 socket[i].socket.cb_dev = NULL;
1241                 socket[i].socket.dev.parent = &ofdev->dev;
1242                 socket[i].pcmcia = pcmcia;
1243                 socket[i].bus_freq = ppc_proc_freq;
1244                 socket[i].hwirq = hwirq;
1245
1246         }
1247
1248         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1249                 status = pcmcia_register_socket(&socket[i].socket);
1250                 if (status < 0)
1251                         pcmcia_error("Socket register failed\n");
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int m8xx_remove(struct of_device *ofdev)
1258 {
1259         u32 m, i;
1260         struct pcmcia_win *w;
1261         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1262
1263         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1264                 w = (void *)&pcmcia->pcmc_pbr0;
1265
1266                 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1267                 out_be32(&pcmcia->pcmc_per,
1268                          in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1269
1270                 /* turn off interrupt and disable CxOE */
1271                 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1272
1273                 /* turn off memory windows */
1274                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1275                         out_be32(&w->or, 0);    /* set to not valid */
1276                         w++;
1277                 }
1278
1279                 /* turn off voltage */
1280                 voltage_set(i, 0, 0);
1281
1282                 /* disable external hardware */
1283                 hardware_disable(i);
1284         }
1285         for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1286                 pcmcia_unregister_socket(&socket[i].socket);
1287
1288         free_irq(pcmcia_schlvl, NULL);
1289
1290         return 0;
1291 }
1292
1293 #ifdef CONFIG_PM
1294 static int m8xx_suspend(struct platform_device *pdev, pm_message_t state)
1295 {
1296         return pcmcia_socket_dev_suspend(&pdev->dev, state);
1297 }
1298
1299 static int m8xx_resume(struct platform_device *pdev)
1300 {
1301         return pcmcia_socket_dev_resume(&pdev->dev);
1302 }
1303 #else
1304 #define m8xx_suspend NULL
1305 #define m8xx_resume NULL
1306 #endif
1307
1308 static struct of_device_id m8xx_pcmcia_match[] = {
1309         {
1310          .type = "pcmcia",
1311          .compatible = "fsl,pq-pcmcia",
1312          },
1313         {},
1314 };
1315
1316 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1317
1318 static struct of_platform_driver m8xx_pcmcia_driver = {
1319         .name = driver_name,
1320         .match_table = m8xx_pcmcia_match,
1321         .probe = m8xx_probe,
1322         .remove = m8xx_remove,
1323         .suspend = m8xx_suspend,
1324         .resume = m8xx_resume,
1325 };
1326
1327 static int __init m8xx_init(void)
1328 {
1329         return of_register_platform_driver(&m8xx_pcmcia_driver);
1330 }
1331
1332 static void __exit m8xx_exit(void)
1333 {
1334         of_unregister_platform_driver(&m8xx_pcmcia_driver);
1335 }
1336
1337 module_init(m8xx_init);
1338 module_exit(m8xx_exit);