2 * linux/arch/arm/mm/proc-sa1100.S
4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * MMU functions for SA110
13 * These are the low level assembler for performing cache and TLB
14 * functions on the StrongARM-1100 and StrongARM-1110.
16 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
19 * Flush the read buffer at context switches
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <mach/hardware.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/pgtable.h>
30 #include "proc-macros.S"
33 * the cache line size of the I and D cache
35 #define DCACHELINESIZE 32
40 * cpu_sa1100_proc_init()
42 ENTRY(cpu_sa1100_proc_init)
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
51 * cpu_sa1100_proc_fin()
53 * Prepare the CPU for reset:
54 * - Disable interrupts
55 * - Clean and turn off caches.
57 ENTRY(cpu_sa1100_proc_fin)
58 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
59 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
60 bic r0, r0, #0x1000 @ ...i............
61 bic r0, r0, #0x000e @ ............wca.
62 mcr p15, 0, r0, c1, c0, 0 @ disable caches
66 * cpu_sa1100_reset(loc)
68 * Perform a soft reset of the system. Put the CPU into the
69 * same state as it would be if it had been reset, and branch
70 * to what would be the reset vector.
72 * loc: location to jump to for soft reset
75 ENTRY(cpu_sa1100_reset)
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
82 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
83 bic ip, ip, #0x000f @ ............wcam
84 bic ip, ip, #0x1100 @ ...i...s........
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
89 * cpu_sa1100_do_idle(type)
91 * Cause the processor to idle
96 * 2 = switch to slow processor clock
97 * 3 = switch to fast processor clock
100 ENTRY(cpu_sa1100_do_idle)
101 mov r0, r0 @ 4 nop padding
104 mov r0, r0 @ 4 nop padding
108 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
109 @ --- aligned to a cache line
110 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
111 ldr r1, [r1, #0] @ force switch to MCLK
112 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
114 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
117 /* ================================= CACHE ================================ */
120 * cpu_sa1100_dcache_clean_area(addr,sz)
122 * Clean the specified entry of any caches such that the MMU
123 * translation fetches will obtain correct data.
125 * addr: cache-unaligned virtual address
128 ENTRY(cpu_sa1100_dcache_clean_area)
129 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
130 add r0, r0, #DCACHELINESIZE
131 subs r1, r1, #DCACHELINESIZE
135 /* =============================== PageTable ============================== */
138 * cpu_sa1100_switch_mm(pgd)
140 * Set the translation base pointer to be as described by pgd.
142 * pgd: new page tables
145 ENTRY(cpu_sa1100_switch_mm)
148 bl v4wb_flush_kern_cache_all @ clears IP
149 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
150 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
151 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
158 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
160 * Set a PTE and flush it out
163 ENTRY(cpu_sa1100_set_pte_ext)
165 armv3_set_pte_ext wc_disable=0
167 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
168 mcr p15, 0, r0, c7, c10, 4 @ drain WB
174 .type __sa1100_setup, #function
177 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
178 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
180 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
184 mrc p15, 0, r0, c1, c0 @ get control register v4
188 .size __sa1100_setup, . - __sa1100_setup
192 * .RVI ZFRS BLDP WCAM
193 * ..11 0001 ..11 1101
196 .type sa1100_crval, #object
198 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
203 * Purpose : Function pointers used to access above functions - all calls
208 * SA1100 and SA1110 share the same function calls
210 .type sa1100_processor_functions, #object
211 ENTRY(sa1100_processor_functions)
214 .word cpu_sa1100_proc_init
215 .word cpu_sa1100_proc_fin
216 .word cpu_sa1100_reset
217 .word cpu_sa1100_do_idle
218 .word cpu_sa1100_dcache_clean_area
219 .word cpu_sa1100_switch_mm
220 .word cpu_sa1100_set_pte_ext
221 .size sa1100_processor_functions, . - sa1100_processor_functions
225 .type cpu_arch_name, #object
228 .size cpu_arch_name, . - cpu_arch_name
230 .type cpu_elf_name, #object
233 .size cpu_elf_name, . - cpu_elf_name
235 .type cpu_sa1100_name, #object
237 .asciz "StrongARM-1100"
238 .size cpu_sa1100_name, . - cpu_sa1100_name
240 .type cpu_sa1110_name, #object
242 .asciz "StrongARM-1110"
243 .size cpu_sa1110_name, . - cpu_sa1110_name
247 .section ".proc.info.init", #alloc, #execinstr
249 .type __sa1100_proc_info,#object
253 .long PMD_TYPE_SECT | \
254 PMD_SECT_BUFFERABLE | \
255 PMD_SECT_CACHEABLE | \
256 PMD_SECT_AP_WRITE | \
258 .long PMD_TYPE_SECT | \
259 PMD_SECT_AP_WRITE | \
264 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
265 .long cpu_sa1100_name
266 .long sa1100_processor_functions
270 .size __sa1100_proc_info, . - __sa1100_proc_info
272 .type __sa1110_proc_info,#object
276 .long PMD_TYPE_SECT | \
277 PMD_SECT_BUFFERABLE | \
278 PMD_SECT_CACHEABLE | \
279 PMD_SECT_AP_WRITE | \
281 .long PMD_TYPE_SECT | \
282 PMD_SECT_AP_WRITE | \
287 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
288 .long cpu_sa1110_name
289 .long sa1100_processor_functions
293 .size __sa1110_proc_info, . - __sa1110_proc_info