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x86/oprofile: Whitespaces changes only
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / oprofile / op_model_amd.c
blobf676f8825a3f54b096e5dd773944a4d04d2361d5
1 /*
2 * @file op_model_amd.c
3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
4 *
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author John Levon
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf
13 */
14
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
18
19 #include <asm/ptrace.h>
20 #include <asm/msr.h>
21 #include <asm/nmi.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
28 #define OP_EVENT_MASK 0x0FFF
29 #define OP_CTR_OVERFLOW (1ULL<<31)
30
31 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
32
33 static unsigned long reset_value[NUM_COUNTERS];
34
35 #ifdef CONFIG_OPROFILE_IBS
36
37 /* IbsFetchCtl bits/masks */
38 #define IBS_FETCH_RAND_EN (1ULL<<57)
39 #define IBS_FETCH_VAL (1ULL<<49)
40 #define IBS_FETCH_ENABLE (1ULL<<48)
41 #define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
42
43 /*IbsOpCtl bits */
44 #define IBS_OP_CNT_CTL (1ULL<<19)
45 #define IBS_OP_VAL (1ULL<<18)
46 #define IBS_OP_ENABLE (1ULL<<17)
47
48 #define IBS_FETCH_SIZE 6
49 #define IBS_OP_SIZE 12
50
51 static int has_ibs; /* AMD Family10h and later */
52
53 struct op_ibs_config {
54 unsigned long op_enabled;
55 unsigned long fetch_enabled;
56 unsigned long max_cnt_fetch;
57 unsigned long max_cnt_op;
58 unsigned long rand_en;
59 unsigned long dispatched_ops;
60 };
61
62 static struct op_ibs_config ibs_config;
63
64 #endif
65
66 /* functions for op_amd_spec */
67
68 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
69 {
70 int i;
71
72 for (i = 0; i < NUM_COUNTERS; i++) {
73 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
74 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
75 else
76 msrs->counters[i].addr = 0;
77 }
78
79 for (i = 0; i < NUM_CONTROLS; i++) {
80 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
81 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
82 else
83 msrs->controls[i].addr = 0;
84 }
85 }
86
87 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
88 struct op_msrs const * const msrs)
89 {
90 u64 val;
91 int i;
92
93 /* clear all counters */
94 for (i = 0; i < NUM_CONTROLS; ++i) {
95 if (unlikely(!msrs->controls[i].addr))
96 continue;
97 rdmsrl(msrs->controls[i].addr, val);
98 val &= model->reserved;
99 wrmsrl(msrs->controls[i].addr, val);
100 }
101
102 /* avoid a false detection of ctr overflows in NMI handler */
103 for (i = 0; i < NUM_COUNTERS; ++i) {
104 if (unlikely(!msrs->counters[i].addr))
105 continue;
106 wrmsrl(msrs->counters[i].addr, -1LL);
107 }
108
109 /* enable active counters */
110 for (i = 0; i < NUM_COUNTERS; ++i) {
111 if (counter_config[i].enabled && msrs->counters[i].addr) {
112 reset_value[i] = counter_config[i].count;
113 wrmsrl(msrs->counters[i].addr,
114 -(u64)counter_config[i].count);
115 rdmsrl(msrs->controls[i].addr, val);
116 val &= model->reserved;
117 val |= op_x86_get_ctrl(model, &counter_config[i]);
118 wrmsrl(msrs->controls[i].addr, val);
119 } else {
120 reset_value[i] = 0;
121 }
122 }
123 }
124
125 #ifdef CONFIG_OPROFILE_IBS
126
127 static inline int
128 op_amd_handle_ibs(struct pt_regs * const regs,
129 struct op_msrs const * const msrs)
130 {
131 u64 val, ctl;
132 struct op_entry entry;
133
134 if (!has_ibs)
135 return 0;
136
137 if (ibs_config.fetch_enabled) {
138 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
139 if (ctl & IBS_FETCH_VAL) {
140 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
141 oprofile_write_reserve(&entry, regs, val,
142 IBS_FETCH_CODE, IBS_FETCH_SIZE);
143 oprofile_add_data64(&entry, val);
144 oprofile_add_data64(&entry, ctl);
145 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
146 oprofile_add_data64(&entry, val);
147 oprofile_write_commit(&entry);
148
149 /* reenable the IRQ */
150 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
151 ctl |= IBS_FETCH_ENABLE;
152 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
153 }
154 }
155
156 if (ibs_config.op_enabled) {
157 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
158 if (ctl & IBS_OP_VAL) {
159 rdmsrl(MSR_AMD64_IBSOPRIP, val);
160 oprofile_write_reserve(&entry, regs, val,
161 IBS_OP_CODE, IBS_OP_SIZE);
162 oprofile_add_data64(&entry, val);
163 rdmsrl(MSR_AMD64_IBSOPDATA, val);
164 oprofile_add_data64(&entry, val);
165 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
166 oprofile_add_data64(&entry, val);
167 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
168 oprofile_add_data64(&entry, val);
169 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
170 oprofile_add_data64(&entry, val);
171 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
172 oprofile_add_data64(&entry, val);
173 oprofile_write_commit(&entry);
174
175 /* reenable the IRQ */
176 ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
177 ctl |= IBS_OP_ENABLE;
178 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
179 }
180 }
181
182 return 1;
183 }
184
185 static inline void op_amd_start_ibs(void)
186 {
187 u64 val;
188 if (has_ibs && ibs_config.fetch_enabled) {
189 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
190 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
191 val |= IBS_FETCH_ENABLE;
192 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
193 }
194
195 if (has_ibs && ibs_config.op_enabled) {
196 val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
197 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
198 val |= IBS_OP_ENABLE;
199 wrmsrl(MSR_AMD64_IBSOPCTL, val);
200 }
201 }
202
203 static void op_amd_stop_ibs(void)
204 {
205 if (has_ibs && ibs_config.fetch_enabled)
206 /* clear max count and enable */
207 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
208
209 if (has_ibs && ibs_config.op_enabled)
210 /* clear max count and enable */
211 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
212 }
213
214 #else
215
216 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
217 struct op_msrs const * const msrs)
218 {
219 return 0;
220 }
221 static inline void op_amd_start_ibs(void) { }
222 static inline void op_amd_stop_ibs(void) { }
223
224 #endif
225
226 static int op_amd_check_ctrs(struct pt_regs * const regs,
227 struct op_msrs const * const msrs)
228 {
229 u64 val;
230 int i;
231
232 for (i = 0; i < NUM_COUNTERS; ++i) {
233 if (!reset_value[i])
234 continue;
235 rdmsrl(msrs->counters[i].addr, val);
236 /* bit is clear if overflowed: */
237 if (val & OP_CTR_OVERFLOW)
238 continue;
239 oprofile_add_sample(regs, i);
240 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[i]);
241 }
242
243 op_amd_handle_ibs(regs, msrs);
244
245 /* See op_model_ppro.c */
246 return 1;
247 }
248
249 static void op_amd_start(struct op_msrs const * const msrs)
250 {
251 u64 val;
252 int i;
253 for (i = 0; i < NUM_COUNTERS; ++i) {
254 if (reset_value[i]) {
255 rdmsrl(msrs->controls[i].addr, val);
256 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
257 wrmsrl(msrs->controls[i].addr, val);
258 }
259 }
260
261 op_amd_start_ibs();
262 }
263
264 static void op_amd_stop(struct op_msrs const * const msrs)
265 {
266 u64 val;
267 int i;
268
269 /*
270 * Subtle: stop on all counters to avoid race with setting our
271 * pm callback
272 */
273 for (i = 0; i < NUM_COUNTERS; ++i) {
274 if (!reset_value[i])
275 continue;
276 rdmsrl(msrs->controls[i].addr, val);
277 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
278 wrmsrl(msrs->controls[i].addr, val);
279 }
280
281 op_amd_stop_ibs();
282 }
283
284 static void op_amd_shutdown(struct op_msrs const * const msrs)
285 {
286 int i;
287
288 for (i = 0; i < NUM_COUNTERS; ++i) {
289 if (msrs->counters[i].addr)
290 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
291 }
292 for (i = 0; i < NUM_CONTROLS; ++i) {
293 if (msrs->controls[i].addr)
294 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
295 }
296 }
297
298 #ifdef CONFIG_OPROFILE_IBS
299
300 static u8 ibs_eilvt_off;
301
302 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
303 {
304 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
305 }
306
307 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
308 {
309 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
310 }
311
312 static int init_ibs_nmi(void)
313 {
314 #define IBSCTL_LVTOFFSETVAL (1 << 8)
315 #define IBSCTL 0x1cc
316 struct pci_dev *cpu_cfg;
317 int nodes;
318 u32 value = 0;
319
320 /* per CPU setup */
321 on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
322
323 nodes = 0;
324 cpu_cfg = NULL;
325 do {
326 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
327 PCI_DEVICE_ID_AMD_10H_NB_MISC,
328 cpu_cfg);
329 if (!cpu_cfg)
330 break;
331 ++nodes;
332 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
333 | IBSCTL_LVTOFFSETVAL);
334 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
335 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
336 pci_dev_put(cpu_cfg);
337 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
338 "IBSCTL = 0x%08x", value);
339 return 1;
340 }
341 } while (1);
342
343 if (!nodes) {
344 printk(KERN_DEBUG "No CPU node configured for IBS");
345 return 1;
346 }
347
348 #ifdef CONFIG_NUMA
349 /* Sanity check */
350 /* Works only for 64bit with proper numa implementation. */
351 if (nodes != num_possible_nodes()) {
352 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
353 "found: %d, expected %d",
354 nodes, num_possible_nodes());
355 return 1;
356 }
357 #endif
358 return 0;
359 }
360
361 /* uninitialize the APIC for the IBS interrupts if needed */
362 static void clear_ibs_nmi(void)
363 {
364 if (has_ibs)
365 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
366 }
367
368 /* initialize the APIC for the IBS interrupts if available */
369 static void ibs_init(void)
370 {
371 has_ibs = boot_cpu_has(X86_FEATURE_IBS);
372
373 if (!has_ibs)
374 return;
375
376 if (init_ibs_nmi()) {
377 has_ibs = 0;
378 return;
379 }
380
381 printk(KERN_INFO "oprofile: AMD IBS detected\n");
382 }
383
384 static void ibs_exit(void)
385 {
386 if (!has_ibs)
387 return;
388
389 clear_ibs_nmi();
390 }
391
392 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
393
394 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
395 {
396 struct dentry *dir;
397 int ret = 0;
398
399 /* architecture specific files */
400 if (create_arch_files)
401 ret = create_arch_files(sb, root);
402
403 if (ret)
404 return ret;
405
406 if (!has_ibs)
407 return ret;
408
409 /* model specific files */
410
411 /* setup some reasonable defaults */
412 ibs_config.max_cnt_fetch = 250000;
413 ibs_config.fetch_enabled = 0;
414 ibs_config.max_cnt_op = 250000;
415 ibs_config.op_enabled = 0;
416 ibs_config.dispatched_ops = 1;
417
418 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
419 oprofilefs_create_ulong(sb, dir, "enable",
420 &ibs_config.fetch_enabled);
421 oprofilefs_create_ulong(sb, dir, "max_count",
422 &ibs_config.max_cnt_fetch);
423 oprofilefs_create_ulong(sb, dir, "rand_enable",
424 &ibs_config.rand_en);
425
426 dir = oprofilefs_mkdir(sb, root, "ibs_op");
427 oprofilefs_create_ulong(sb, dir, "enable",
428 &ibs_config.op_enabled);
429 oprofilefs_create_ulong(sb, dir, "max_count",
430 &ibs_config.max_cnt_op);
431 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
432 &ibs_config.dispatched_ops);
433
434 return 0;
435 }
436
437 static int op_amd_init(struct oprofile_operations *ops)
438 {
439 ibs_init();
440 create_arch_files = ops->create_files;
441 ops->create_files = setup_ibs_files;
442 return 0;
443 }
444
445 static void op_amd_exit(void)
446 {
447 ibs_exit();
448 }
449
450 #else
451
452 /* no IBS support */
453
454 static int op_amd_init(struct oprofile_operations *ops)
455 {
456 return 0;
457 }
458
459 static void op_amd_exit(void) {}
460
461 #endif /* CONFIG_OPROFILE_IBS */
462
463 struct op_x86_model_spec const op_amd_spec = {
464 .num_counters = NUM_COUNTERS,
465 .num_controls = NUM_CONTROLS,
466 .reserved = MSR_AMD_EVENTSEL_RESERVED,
467 .event_mask = OP_EVENT_MASK,
468 .init = op_amd_init,
469 .exit = op_amd_exit,
470 .fill_in_addresses = &op_amd_fill_in_addresses,
471 .setup_ctrs = &op_amd_setup_ctrs,
472 .check_ctrs = &op_amd_check_ctrs,
473 .start = &op_amd_start,
474 .stop = &op_amd_stop,
475 .shutdown = &op_amd_shutdown,
476 };
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