arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2008 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/notifier.h>
  13 #include <linux/smp.h>
  14 #include <linux/oprofile.h>
  15 #include <linux/sysdev.h>
  16 #include <linux/slab.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/cpu.h>
  20 #include <asm/nmi.h>
  21 #include <asm/msr.h>
  22 #include <asm/apic.h>
  23
  24 #include "op_counter.h"
  25 #include "op_x86_model.h"
  26
  27 static struct op_x86_model_spec const *model;
  28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  30
  31 /* 0 == registered but off, 1 == registered and on */
  32 static int nmi_enabled = 0;
  33
  34 /* common functions */
  35
  36 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  37                     struct op_counter_config *counter_config)
  38 {
  39         u64 val = 0;
  40         u16 event = (u16)counter_config->event;
  41
  42         val |= ARCH_PERFMON_EVENTSEL_INT;
  43         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  44         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  45         val |= (counter_config->unit_mask & 0xFF) << 8;
  46         event &= model->event_mask ? model->event_mask : 0xFF;
  47         val |= event & 0xFF;
  48         val |= (event & 0x0F00) << 24;
  49
  50         return val;
  51 }
  52
  53
  54 static int profile_exceptions_notify(struct notifier_block *self,
  55                                      unsigned long val, void *data)
  56 {
  57         struct die_args *args = (struct die_args *)data;
  58         int ret = NOTIFY_DONE;
  59         int cpu = smp_processor_id();
  60
  61         switch (val) {
  62         case DIE_NMI:
  63         case DIE_NMI_IPI:
  64                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  65                 ret = NOTIFY_STOP;
  66                 break;
  67         default:
  68                 break;
  69         }
  70         return ret;
  71 }
  72
  73 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  74 {
  75         struct op_msr *counters = msrs->counters;
  76         struct op_msr *controls = msrs->controls;
  77         unsigned int i;
  78
  79         for (i = 0; i < model->num_counters; ++i) {
  80                 if (counters[i].addr)
  81                         rdmsrl(counters[i].addr, counters[i].saved);
  82         }
  83
  84         for (i = 0; i < model->num_controls; ++i) {
  85                 if (controls[i].addr)
  86                         rdmsrl(controls[i].addr, controls[i].saved);
  87         }
  88 }
  89
  90 static void free_msrs(void)
  91 {
  92         int i;
  93         for_each_possible_cpu(i) {
  94                 kfree(per_cpu(cpu_msrs, i).counters);
  95                 per_cpu(cpu_msrs, i).counters = NULL;
  96                 kfree(per_cpu(cpu_msrs, i).controls);
  97                 per_cpu(cpu_msrs, i).controls = NULL;
  98         }
  99 }
 100
 101 static int allocate_msrs(void)
 102 {
 103         int success = 1;
 104         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 105         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 106
 107         int i;
 108         for_each_possible_cpu(i) {
 109                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 110                                                                 GFP_KERNEL);
 111                 if (!per_cpu(cpu_msrs, i).counters) {
 112                         success = 0;
 113                         break;
 114                 }
 115                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 116                                                                 GFP_KERNEL);
 117                 if (!per_cpu(cpu_msrs, i).controls) {
 118                         success = 0;
 119                         break;
 120                 }
 121         }
 122
 123         if (!success)
 124                 free_msrs();
 125
 126         return success;
 127 }
 128
 129 static void nmi_cpu_setup(void *dummy)
 130 {
 131         int cpu = smp_processor_id();
 132         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 133         nmi_cpu_save_registers(msrs);
 134         spin_lock(&oprofilefs_lock);
 135         model->setup_ctrs(model, msrs);
 136         spin_unlock(&oprofilefs_lock);
 137         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 138         apic_write(APIC_LVTPC, APIC_DM_NMI);
 139 }
 140
 141 static struct notifier_block profile_exceptions_nb = {
 142         .notifier_call = profile_exceptions_notify,
 143         .next = NULL,
 144         .priority = 2
 145 };
 146
 147 static int nmi_setup(void)
 148 {
 149         int err = 0;
 150         int cpu;
 151
 152         if (!allocate_msrs())
 153                 return -ENOMEM;
 154
 155         err = register_die_notifier(&profile_exceptions_nb);
 156         if (err) {
 157                 free_msrs();
 158                 return err;
 159         }
 160
 161         /* We need to serialize save and setup for HT because the subset
 162          * of msrs are distinct for save and setup operations
 163          */
 164
 165         /* Assume saved/restored counters are the same on all CPUs */
 166         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 167         for_each_possible_cpu(cpu) {
 168                 if (cpu != 0) {
 169                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 170                                 per_cpu(cpu_msrs, 0).counters,
 171                                 sizeof(struct op_msr) * model->num_counters);
 172
 173                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 174                                 per_cpu(cpu_msrs, 0).controls,
 175                                 sizeof(struct op_msr) * model->num_controls);
 176                 }
 177
 178         }
 179         on_each_cpu(nmi_cpu_setup, NULL, 1);
 180         nmi_enabled = 1;
 181         return 0;
 182 }
 183
 184 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 185 {
 186         struct op_msr *counters = msrs->counters;
 187         struct op_msr *controls = msrs->controls;
 188         unsigned int i;
 189
 190         for (i = 0; i < model->num_controls; ++i) {
 191                 if (controls[i].addr)
 192                         wrmsrl(controls[i].addr, controls[i].saved);
 193         }
 194
 195         for (i = 0; i < model->num_counters; ++i) {
 196                 if (counters[i].addr)
 197                         wrmsrl(counters[i].addr, counters[i].saved);
 198         }
 199 }
 200
 201 static void nmi_cpu_shutdown(void *dummy)
 202 {
 203         unsigned int v;
 204         int cpu = smp_processor_id();
 205         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 206
 207         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 208          * mode and vector nr combination can be illegal. That's by design: on
 209          * power on apic lvt contain a zero vector nr which are legal only for
 210          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 211          */
 212         v = apic_read(APIC_LVTERR);
 213         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 214         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 215         apic_write(APIC_LVTERR, v);
 216         nmi_cpu_restore_registers(msrs);
 217 }
 218
 219 static void nmi_shutdown(void)
 220 {
 221         struct op_msrs *msrs;
 222
 223         nmi_enabled = 0;
 224         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 225         unregister_die_notifier(&profile_exceptions_nb);
 226         msrs = &get_cpu_var(cpu_msrs);
 227         model->shutdown(msrs);
 228         free_msrs();
 229         put_cpu_var(cpu_msrs);
 230 }
 231
 232 static void nmi_cpu_start(void *dummy)
 233 {
 234         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 235         model->start(msrs);
 236 }
 237
 238 static int nmi_start(void)
 239 {
 240         on_each_cpu(nmi_cpu_start, NULL, 1);
 241         return 0;
 242 }
 243
 244 static void nmi_cpu_stop(void *dummy)
 245 {
 246         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 247         model->stop(msrs);
 248 }
 249
 250 static void nmi_stop(void)
 251 {
 252         on_each_cpu(nmi_cpu_stop, NULL, 1);
 253 }
 254
 255 struct op_counter_config counter_config[OP_MAX_COUNTER];
 256
 257 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 258 {
 259         unsigned int i;
 260
 261         for (i = 0; i < model->num_counters; ++i) {
 262                 struct dentry *dir;
 263                 char buf[4];
 264
 265                 /* quick little hack to _not_ expose a counter if it is not
 266                  * available for use.  This should protect userspace app.
 267                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 268                  *        sequentially in their struct assignment).
 269                  */
 270                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 271                         continue;
 272
 273                 snprintf(buf,  sizeof(buf), "%d", i);
 274                 dir = oprofilefs_mkdir(sb, root, buf);
 275                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 276                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 277                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 278                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 279                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 280                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 281         }
 282
 283         return 0;
 284 }
 285
 286 #ifdef CONFIG_SMP
 287 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 288                                  void *data)
 289 {
 290         int cpu = (unsigned long)data;
 291         switch (action) {
 292         case CPU_DOWN_FAILED:
 293         case CPU_ONLINE:
 294                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 295                 break;
 296         case CPU_DOWN_PREPARE:
 297                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 298                 break;
 299         }
 300         return NOTIFY_DONE;
 301 }
 302
 303 static struct notifier_block oprofile_cpu_nb = {
 304         .notifier_call = oprofile_cpu_notifier
 305 };
 306 #endif
 307
 308 #ifdef CONFIG_PM
 309
 310 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 311 {
 312         /* Only one CPU left, just stop that one */
 313         if (nmi_enabled == 1)
 314                 nmi_cpu_stop(NULL);
 315         return 0;
 316 }
 317
 318 static int nmi_resume(struct sys_device *dev)
 319 {
 320         if (nmi_enabled == 1)
 321                 nmi_cpu_start(NULL);
 322         return 0;
 323 }
 324
 325 static struct sysdev_class oprofile_sysclass = {
 326         .name           = "oprofile",
 327         .resume         = nmi_resume,
 328         .suspend        = nmi_suspend,
 329 };
 330
 331 static struct sys_device device_oprofile = {
 332         .id     = 0,
 333         .cls    = &oprofile_sysclass,
 334 };
 335
 336 static int __init init_sysfs(void)
 337 {
 338         int error;
 339
 340         error = sysdev_class_register(&oprofile_sysclass);
 341         if (!error)
 342                 error = sysdev_register(&device_oprofile);
 343         return error;
 344 }
 345
 346 static void exit_sysfs(void)
 347 {
 348         sysdev_unregister(&device_oprofile);
 349         sysdev_class_unregister(&oprofile_sysclass);
 350 }
 351
 352 #else
 353 #define init_sysfs() do { } while (0)
 354 #define exit_sysfs() do { } while (0)
 355 #endif /* CONFIG_PM */
 356
 357 static int __init p4_init(char **cpu_type)
 358 {
 359         __u8 cpu_model = boot_cpu_data.x86_model;
 360
 361         if (cpu_model > 6 || cpu_model == 5)
 362                 return 0;
 363
 364 #ifndef CONFIG_SMP
 365         *cpu_type = "i386/p4";
 366         model = &op_p4_spec;
 367         return 1;
 368 #else
 369         switch (smp_num_siblings) {
 370         case 1:
 371                 *cpu_type = "i386/p4";
 372                 model = &op_p4_spec;
 373                 return 1;
 374
 375         case 2:
 376                 *cpu_type = "i386/p4-ht";
 377                 model = &op_p4_ht2_spec;
 378                 return 1;
 379         }
 380 #endif
 381
 382         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 383         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 384         return 0;
 385 }
 386
 387 static int force_arch_perfmon;
 388 static int force_cpu_type(const char *str, struct kernel_param *kp)
 389 {
 390         if (!strcmp(str, "arch_perfmon")) {
 391                 force_arch_perfmon = 1;
 392                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 393         }
 394
 395         return 0;
 396 }
 397 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 398
 399 static int __init ppro_init(char **cpu_type)
 400 {
 401         __u8 cpu_model = boot_cpu_data.x86_model;
 402         struct op_x86_model_spec const *spec = &op_ppro_spec;   /* default */
 403
 404         if (force_arch_perfmon && cpu_has_arch_perfmon)
 405                 return 0;
 406
 407         switch (cpu_model) {
 408         case 0 ... 2:
 409                 *cpu_type = "i386/ppro";
 410                 break;
 411         case 3 ... 5:
 412                 *cpu_type = "i386/pii";
 413                 break;
 414         case 6 ... 8:
 415         case 10 ... 11:
 416                 *cpu_type = "i386/piii";
 417                 break;
 418         case 9:
 419         case 13:
 420                 *cpu_type = "i386/p6_mobile";
 421                 break;
 422         case 14:
 423                 *cpu_type = "i386/core";
 424                 break;
 425         case 15: case 23:
 426                 *cpu_type = "i386/core_2";
 427                 break;
 428         case 26:
 429                 spec = &op_arch_perfmon_spec;
 430                 *cpu_type = "i386/core_i7";
 431                 break;
 432         case 28:
 433                 *cpu_type = "i386/atom";
 434                 break;
 435         default:
 436                 /* Unknown */
 437                 return 0;
 438         }
 439
 440         model = spec;
 441         return 1;
 442 }
 443
 444 /* in order to get sysfs right */
 445 static int using_nmi;
 446
 447 int __init op_nmi_init(struct oprofile_operations *ops)
 448 {
 449         __u8 vendor = boot_cpu_data.x86_vendor;
 450         __u8 family = boot_cpu_data.x86;
 451         char *cpu_type = NULL;
 452         int ret = 0;
 453
 454         if (!cpu_has_apic)
 455                 return -ENODEV;
 456
 457         switch (vendor) {
 458         case X86_VENDOR_AMD:
 459                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 460
 461                 switch (family) {
 462                 case 6:
 463                         cpu_type = "i386/athlon";
 464                         break;
 465                 case 0xf:
 466                         /*
 467                          * Actually it could be i386/hammer too, but
 468                          * give user space an consistent name.
 469                          */
 470                         cpu_type = "x86-64/hammer";
 471                         break;
 472                 case 0x10:
 473                         cpu_type = "x86-64/family10";
 474                         break;
 475                 case 0x11:
 476                         cpu_type = "x86-64/family11h";
 477                         break;
 478                 default:
 479                         return -ENODEV;
 480                 }
 481                 model = &op_amd_spec;
 482                 break;
 483
 484         case X86_VENDOR_INTEL:
 485                 switch (family) {
 486                         /* Pentium IV */
 487                 case 0xf:
 488                         p4_init(&cpu_type);
 489                         break;
 490
 491                         /* A P6-class processor */
 492                 case 6:
 493                         ppro_init(&cpu_type);
 494                         break;
 495
 496                 default:
 497                         break;
 498                 }
 499
 500                 if (cpu_type)
 501                         break;
 502
 503                 if (!cpu_has_arch_perfmon)
 504                         return -ENODEV;
 505
 506                 /* use arch perfmon as fallback */
 507                 cpu_type = "i386/arch_perfmon";
 508                 model = &op_arch_perfmon_spec;
 509                 break;
 510
 511         default:
 512                 return -ENODEV;
 513         }
 514
 515 #ifdef CONFIG_SMP
 516         register_cpu_notifier(&oprofile_cpu_nb);
 517 #endif
 518         /* default values, can be overwritten by model */
 519         ops->create_files       = nmi_create_files;
 520         ops->setup              = nmi_setup;
 521         ops->shutdown           = nmi_shutdown;
 522         ops->start              = nmi_start;
 523         ops->stop               = nmi_stop;
 524         ops->cpu_type           = cpu_type;
 525
 526         if (model->init)
 527                 ret = model->init(ops);
 528         if (ret)
 529                 return ret;
 530
 531         init_sysfs();
 532         using_nmi = 1;
 533         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 534         return 0;
 535 }
 536
 537 void op_nmi_exit(void)
 538 {
 539         if (using_nmi) {
 540                 exit_sysfs();
 541 #ifdef CONFIG_SMP
 542                 unregister_cpu_notifier(&oprofile_cpu_nb);
 543 #endif
 544         }
 545         if (model->exit)
 546                 model->exit();
 547 }