2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
26 #include <video/sh_mobile_hdmi.h>
27 #include <video/sh_mobile_lcdc.h>
29 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
30 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
31 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
32 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
33 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
34 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
35 bits 19..16 of Internal CTS */
36 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
37 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
38 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
39 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
40 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
41 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
42 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
43 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
44 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
45 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
46 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
47 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
48 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
49 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
50 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
51 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
52 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
53 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
54 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
56 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
57 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
59 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
60 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
61 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
62 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
63 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
64 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
65 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
66 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
67 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
68 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
69 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
70 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
71 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
72 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
73 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
74 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
75 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
76 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
77 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
78 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
79 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
80 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
81 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
82 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
83 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
84 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
85 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
93 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
94 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
95 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
97 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
98 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
125 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
126 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
127 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
128 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
129 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
130 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
131 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
132 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
133 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
134 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
135 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
136 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
137 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
138 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
139 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
140 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
141 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
142 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
143 #define HDMI_SHA0 0xB9 /* sha0 */
144 #define HDMI_SHA1 0xBA /* sha1 */
145 #define HDMI_SHA2 0xBB /* sha2 */
146 #define HDMI_SHA3 0xBC /* sha3 */
147 #define HDMI_SHA4 0xBD /* sha4 */
148 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
149 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
150 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
151 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
152 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
153 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
154 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
155 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
156 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
157 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
158 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
159 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
160 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
161 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
162 #define HDMI_AN_SEED 0xCC /* An seed */
163 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
164 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
165 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
166 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
167 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
168 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
169 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
170 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
171 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
172 #define HDMI_PJ 0xD7 /* Pj */
173 #define HDMI_SHA_RD 0xD8 /* sha_rd */
174 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
175 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
176 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
177 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
178 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
179 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
180 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
181 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
182 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
183 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
184 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
185 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
186 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
187 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
188 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
189 #define HDMI_AN_23_16 0xEA /* An [23:16] */
190 #define HDMI_AN_31_24 0xEB /* An [31:24] */
191 #define HDMI_AN_39_32 0xEC /* An [39:32] */
192 #define HDMI_AN_47_40 0xED /* An [47:40] */
193 #define HDMI_AN_55_48 0xEE /* An [55:48] */
194 #define HDMI_AN_63_56 0xEF /* An [63:56] */
195 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
196 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
197 #define HDMI_TEST_MODE 0xFE /* Test mode */
200 HDMI_HOTPLUG_DISCONNECTED
,
201 HDMI_HOTPLUG_CONNECTED
,
202 HDMI_HOTPLUG_EDID_DONE
,
207 enum hotplug_state hp_state
;
208 struct clk
*hdmi_clk
;
210 struct fb_info
*info
;
211 struct delayed_work edid_work
;
212 struct fb_var_screeninfo var
;
215 static void hdmi_write(struct sh_hdmi
*hdmi
, u8 data
, u8 reg
)
217 iowrite8(data
, hdmi
->base
+ reg
);
220 static u8
hdmi_read(struct sh_hdmi
*hdmi
, u8 reg
)
222 return ioread8(hdmi
->base
+ reg
);
225 /* External video parameter settings */
226 static void hdmi_external_video_param(struct sh_hdmi
*hdmi
)
228 struct fb_var_screeninfo
*var
= &hdmi
->var
;
229 u16 htotal
, hblank
, hdelay
, vtotal
, vblank
, vdelay
, voffset
;
232 htotal
= var
->xres
+ var
->right_margin
+ var
->left_margin
+ var
->hsync_len
;
234 hdelay
= var
->hsync_len
+ var
->left_margin
;
235 hblank
= var
->right_margin
+ hdelay
;
238 * Vertical timing looks a bit different in Figure 18,
239 * but let's try the same first by setting offset = 0
241 vtotal
= var
->yres
+ var
->upper_margin
+ var
->lower_margin
+ var
->vsync_len
;
243 vdelay
= var
->vsync_len
+ var
->upper_margin
;
244 vblank
= var
->lower_margin
+ vdelay
;
245 voffset
= min(var
->upper_margin
/ 2, 6U);
248 * [3]: VSYNC polarity: Positive
249 * [2]: HSYNC polarity: Positive
250 * [1]: Interlace/Progressive: Progressive
251 * [0]: External video settings enable: used.
253 if (var
->sync
& FB_SYNC_HOR_HIGH_ACT
)
255 if (var
->sync
& FB_SYNC_VERT_HIGH_ACT
)
258 pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
259 htotal
, hblank
, hdelay
, var
->hsync_len
,
260 vtotal
, vblank
, vdelay
, var
->vsync_len
, sync
);
262 hdmi_write(hdmi
, sync
| (voffset
<< 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS
);
264 hdmi_write(hdmi
, htotal
, HDMI_EXTERNAL_H_TOTAL_7_0
);
265 hdmi_write(hdmi
, htotal
>> 8, HDMI_EXTERNAL_H_TOTAL_11_8
);
267 hdmi_write(hdmi
, hblank
, HDMI_EXTERNAL_H_BLANK_7_0
);
268 hdmi_write(hdmi
, hblank
>> 8, HDMI_EXTERNAL_H_BLANK_9_8
);
270 hdmi_write(hdmi
, hdelay
, HDMI_EXTERNAL_H_DELAY_7_0
);
271 hdmi_write(hdmi
, hdelay
>> 8, HDMI_EXTERNAL_H_DELAY_9_8
);
273 hdmi_write(hdmi
, var
->hsync_len
, HDMI_EXTERNAL_H_DURATION_7_0
);
274 hdmi_write(hdmi
, var
->hsync_len
>> 8, HDMI_EXTERNAL_H_DURATION_9_8
);
276 hdmi_write(hdmi
, vtotal
, HDMI_EXTERNAL_V_TOTAL_7_0
);
277 hdmi_write(hdmi
, vtotal
>> 8, HDMI_EXTERNAL_V_TOTAL_9_8
);
279 hdmi_write(hdmi
, vblank
, HDMI_EXTERNAL_V_BLANK
);
281 hdmi_write(hdmi
, vdelay
, HDMI_EXTERNAL_V_DELAY
);
283 hdmi_write(hdmi
, var
->vsync_len
, HDMI_EXTERNAL_V_DURATION
);
285 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
289 * sh_hdmi_video_config()
291 static void sh_hdmi_video_config(struct sh_hdmi
*hdmi
)
294 * [7:4]: Audio sampling frequency: 48kHz
295 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
296 * [0]: Internal/External DE select: internal
298 hdmi_write(hdmi
, 0x20, HDMI_AUDIO_VIDEO_SETTING_1
);
301 * [7:6]: Video output format: RGB 4:4:4
302 * [5:4]: Input video data width: 8 bit
303 * [3:1]: EAV/SAV location: channel 1
304 * [0]: Video input color space: RGB
306 hdmi_write(hdmi
, 0x34, HDMI_VIDEO_SETTING_1
);
309 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
310 * left at 0 by default, this configures 24bpp and sets the Color Depth
311 * (CD) field in the General Control Packet
313 hdmi_write(hdmi
, 0x20, HDMI_DEEP_COLOR_MODES
);
317 * sh_hdmi_audio_config()
319 static void sh_hdmi_audio_config(struct sh_hdmi
*hdmi
)
322 * [7:4] L/R data swap control
323 * [3:0] appropriate N[19:16]
325 hdmi_write(hdmi
, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT
);
326 /* appropriate N[15:8] */
327 hdmi_write(hdmi
, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8
);
328 /* appropriate N[7:0] */
329 hdmi_write(hdmi
, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0
);
331 /* [7:4] 48 kHz SPDIF not used */
332 hdmi_write(hdmi
, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS
);
335 * [6:5] set required down sampling rate if required
336 * [4:3] set required audio source
338 hdmi_write(hdmi
, 0x00, HDMI_AUDIO_SETTING_1
);
340 /* [3:0] set sending channel number for channel status */
341 hdmi_write(hdmi
, 0x40, HDMI_AUDIO_SETTING_2
);
344 * [5:2] set valid I2S source input pin
345 * [1:0] set input I2S source mode
347 hdmi_write(hdmi
, 0x04, HDMI_I2S_AUDIO_SET
);
349 /* [7:4] set valid DSD source input pin */
350 hdmi_write(hdmi
, 0x00, HDMI_DSD_AUDIO_SET
);
352 /* [7:0] set appropriate I2S input pin swap settings if required */
353 hdmi_write(hdmi
, 0x00, HDMI_I2S_INPUT_PIN_SWAP
);
356 * [7] set validity bit for channel status
357 * [3:0] set original sample frequency for channel status
359 hdmi_write(hdmi
, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1
);
362 * [7] set value for channel status
363 * [6] set value for channel status
364 * [5] set copyright bit for channel status
365 * [4:2] set additional information for channel status
366 * [1:0] set clock accuracy for channel status
368 hdmi_write(hdmi
, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2
);
370 /* [7:0] set category code for channel status */
371 hdmi_write(hdmi
, 0x00, HDMI_CATEGORY_CODE
);
374 * [7:4] set source number for channel status
375 * [3:0] set word length for channel status
377 hdmi_write(hdmi
, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN
);
379 /* [7:4] set sample frequency for channel status */
380 hdmi_write(hdmi
, 0x20, HDMI_AUDIO_VIDEO_SETTING_1
);
384 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
386 static void sh_hdmi_phy_config(struct sh_hdmi
*hdmi
)
388 if (hdmi
->var
.yres
> 480) {
389 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
397 hdmi_write(hdmi
, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1
);
398 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
399 hdmi_write(hdmi
, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2
);
404 hdmi_write(hdmi
, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3
);
405 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
406 hdmi_write(hdmi
, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5
);
408 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
409 * LPF capacitance, LPF resistance[1]
411 hdmi_write(hdmi
, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6
);
412 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
413 hdmi_write(hdmi
, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7
);
415 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
416 * LPF capacitance, LPF resistance[1]
418 hdmi_write(hdmi
, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8
);
419 /* DRV_CONFIG, PE_CONFIG */
420 hdmi_write(hdmi
, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9
);
422 * [2:0] AMON_SEL (4 == LPF voltage)
423 * [4] PLLA_CONFIG[16]
424 * [5] PLLB_CONFIG[16]
426 hdmi_write(hdmi
, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10
);
428 /* for 480p8bit 27MHz */
429 hdmi_write(hdmi
, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1
);
430 hdmi_write(hdmi
, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2
);
431 hdmi_write(hdmi
, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3
);
432 hdmi_write(hdmi
, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5
);
433 hdmi_write(hdmi
, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6
);
434 hdmi_write(hdmi
, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7
);
435 hdmi_write(hdmi
, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8
);
436 hdmi_write(hdmi
, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9
);
437 hdmi_write(hdmi
, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10
);
442 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
444 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi
*hdmi
)
449 hdmi_write(hdmi
, 0x06, HDMI_CTRL_PKT_BUF_INDEX
);
451 /* Packet Type = 0x82 */
452 hdmi_write(hdmi
, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0
);
455 hdmi_write(hdmi
, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1
);
457 /* Length = 13 (0x0D) */
458 hdmi_write(hdmi
, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2
);
461 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0
);
466 * B = Bar Data not valid
469 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1
);
473 * M = 16:9 Picture Aspect Ratio
474 * R = Same as picture aspect ratio
476 hdmi_write(hdmi
, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2
);
481 * Q = Default (depends on video format)
482 * SC = No Known non_uniform Scaling
484 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3
);
487 * VIC = 1280 x 720p: ignored if external config is used
488 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
490 if (hdmi
->var
.yres
== 1080 && hdmi
->var
.xres
== 1920)
492 else if (hdmi
->var
.yres
== 480 && hdmi
->var
.xres
== 720)
496 hdmi_write(hdmi
, vic
, HDMI_CTRL_PKT_BUF_ACCESS_PB4
);
498 /* PR = No Repetition */
499 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5
);
501 /* Line Number of End of Top Bar (lower 8 bits) */
502 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6
);
504 /* Line Number of End of Top Bar (upper 8 bits) */
505 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7
);
507 /* Line Number of Start of Bottom Bar (lower 8 bits) */
508 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8
);
510 /* Line Number of Start of Bottom Bar (upper 8 bits) */
511 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9
);
513 /* Pixel Number of End of Left Bar (lower 8 bits) */
514 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10
);
516 /* Pixel Number of End of Left Bar (upper 8 bits) */
517 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11
);
519 /* Pixel Number of Start of Right Bar (lower 8 bits) */
520 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12
);
522 /* Pixel Number of Start of Right Bar (upper 8 bits) */
523 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13
);
527 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
529 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi
*hdmi
)
531 /* Audio InfoFrame */
532 hdmi_write(hdmi
, 0x08, HDMI_CTRL_PKT_BUF_INDEX
);
534 /* Packet Type = 0x84 */
535 hdmi_write(hdmi
, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0
);
537 /* Version Number = 0x01 */
538 hdmi_write(hdmi
, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1
);
540 /* 0 Length = 10 (0x0A) */
541 hdmi_write(hdmi
, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2
);
544 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0
);
546 /* Audio Channel Count = Refer to Stream Header */
547 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1
);
549 /* Refer to Stream Header */
550 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2
);
552 /* Format depends on coding type (i.e. CT0...CT3) */
553 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3
);
555 /* Speaker Channel Allocation = Front Right + Front Left */
556 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4
);
558 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
559 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5
);
562 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6
);
563 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7
);
564 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8
);
565 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9
);
566 hdmi_write(hdmi
, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10
);
570 * sh_hdmi_configure() - Initialise HDMI for output
572 static void sh_hdmi_configure(struct sh_hdmi
*hdmi
)
574 /* Configure video format */
575 sh_hdmi_video_config(hdmi
);
577 /* Configure audio format */
578 sh_hdmi_audio_config(hdmi
);
581 sh_hdmi_phy_config(hdmi
);
583 /* Auxiliary Video Information (AVI) InfoFrame */
584 sh_hdmi_avi_infoframe_setup(hdmi
);
586 /* Audio InfoFrame */
587 sh_hdmi_audio_infoframe_setup(hdmi
);
590 * Control packet auto send with VSYNC control: auto send
591 * General control, Gamut metadata, ISRC, and ACP packets
593 hdmi_write(hdmi
, 0x8E, HDMI_CTRL_PKT_AUTO_SEND
);
598 /* PS mode b->d, reset PLLA and PLLB */
599 hdmi_write(hdmi
, 0x4C, HDMI_SYSTEM_CTRL
);
603 hdmi_write(hdmi
, 0x40, HDMI_SYSTEM_CTRL
);
606 static void sh_hdmi_read_edid(struct sh_hdmi
*hdmi
)
608 struct fb_var_screeninfo tmpvar
;
609 /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */
610 struct fb_var_screeninfo
*var
= &tmpvar
;
615 pr_debug("Read back EDID code:");
616 for (i
= 0; i
< 128; i
++) {
617 edid
[i
] = hdmi_read(hdmi
, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW
);
620 printk(KERN_CONT
"\n");
621 printk(KERN_DEBUG
"%02X | %02X", i
, edid
[i
]);
623 printk(KERN_CONT
" %02X", edid
[i
]);
628 printk(KERN_CONT
"\n");
630 fb_parse_edid(edid
, var
);
631 pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
632 var
->left_margin
, var
->xres
, var
->right_margin
, var
->hsync_len
,
633 var
->upper_margin
, var
->yres
, var
->lower_margin
, var
->vsync_len
,
634 PICOS2KHZ(var
->pixclock
));
636 hdmi_external_video_param(hdmi
);
639 static irqreturn_t
sh_hdmi_hotplug(int irq
, void *dev_id
)
641 struct sh_hdmi
*hdmi
= dev_id
;
642 u8 status1
, status2
, mask1
, mask2
;
644 /* mode_b and PLLA and PLLB reset */
645 hdmi_write(hdmi
, 0x2C, HDMI_SYSTEM_CTRL
);
647 /* How long shall reset be held? */
650 /* mode_b and PLLA and PLLB reset release */
651 hdmi_write(hdmi
, 0x20, HDMI_SYSTEM_CTRL
);
653 status1
= hdmi_read(hdmi
, HDMI_INTERRUPT_STATUS_1
);
654 status2
= hdmi_read(hdmi
, HDMI_INTERRUPT_STATUS_2
);
656 mask1
= hdmi_read(hdmi
, HDMI_INTERRUPT_MASK_1
);
657 mask2
= hdmi_read(hdmi
, HDMI_INTERRUPT_MASK_2
);
659 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
660 hdmi_write(hdmi
, 0xFF, HDMI_INTERRUPT_STATUS_1
);
661 hdmi_write(hdmi
, 0xFF, HDMI_INTERRUPT_STATUS_2
);
663 if (printk_ratelimit())
664 pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
665 irq
, status1
, mask1
, status2
, mask2
);
667 if (!((status1
& mask1
) | (status2
& mask2
))) {
669 } else if (status1
& 0xc0) {
672 /* Datasheet specifies 10ms... */
675 msens
= hdmi_read(hdmi
, HDMI_HOT_PLUG_MSENS_STATUS
);
676 pr_debug("MSENS 0x%x\n", msens
);
677 /* Check, if hot plug & MSENS pin status are both high */
678 if ((msens
& 0xC0) == 0xC0) {
679 /* Display plug in */
680 hdmi
->hp_state
= HDMI_HOTPLUG_CONNECTED
;
682 /* Set EDID word address */
683 hdmi_write(hdmi
, 0x00, HDMI_EDID_WORD_ADDRESS
);
684 /* Set EDID segment pointer */
685 hdmi_write(hdmi
, 0x00, HDMI_EDID_SEGMENT_POINTER
);
686 /* Enable EDID interrupt */
687 hdmi_write(hdmi
, 0xC6, HDMI_INTERRUPT_MASK_1
);
688 } else if (!(status1
& 0x80)) {
689 /* Display unplug, beware multiple interrupts */
690 if (hdmi
->hp_state
!= HDMI_HOTPLUG_DISCONNECTED
)
691 schedule_delayed_work(&hdmi
->edid_work
, 0);
693 hdmi
->hp_state
= HDMI_HOTPLUG_DISCONNECTED
;
694 /* display_off will switch back to mode_a */
696 } else if (status1
& 2) {
697 /* EDID error interrupt: retry */
698 /* Set EDID word address */
699 hdmi_write(hdmi
, 0x00, HDMI_EDID_WORD_ADDRESS
);
700 /* Set EDID segment pointer */
701 hdmi_write(hdmi
, 0x00, HDMI_EDID_SEGMENT_POINTER
);
702 } else if (status1
& 4) {
703 /* Disable EDID interrupt */
704 hdmi_write(hdmi
, 0xC0, HDMI_INTERRUPT_MASK_1
);
705 hdmi
->hp_state
= HDMI_HOTPLUG_EDID_DONE
;
706 schedule_delayed_work(&hdmi
->edid_work
, msecs_to_jiffies(10));
712 static void hdmi_display_on(void *arg
, struct fb_info
*info
)
714 struct sh_hdmi
*hdmi
= arg
;
715 struct sh_mobile_hdmi_info
*pdata
= hdmi
->dev
->platform_data
;
717 pr_debug("%s(%p): state %x\n", __func__
, pdata
->lcd_dev
, info
->state
);
719 * FIXME: not a good place to store fb_info. And we cannot nullify it
720 * even on monitor disconnect. What should the lifecycle be?
723 switch (hdmi
->hp_state
) {
724 case HDMI_HOTPLUG_EDID_DONE
:
725 /* PS mode d->e. All functions are active */
726 hdmi_write(hdmi
, 0x80, HDMI_SYSTEM_CTRL
);
727 pr_debug("HDMI running\n");
729 case HDMI_HOTPLUG_DISCONNECTED
:
730 info
->state
= FBINFO_STATE_SUSPENDED
;
732 hdmi
->var
= info
->var
;
736 static void hdmi_display_off(void *arg
)
738 struct sh_hdmi
*hdmi
= arg
;
739 struct sh_mobile_hdmi_info
*pdata
= hdmi
->dev
->platform_data
;
741 pr_debug("%s(%p)\n", __func__
, pdata
->lcd_dev
);
743 hdmi_write(hdmi
, 0x10, HDMI_SYSTEM_CTRL
);
746 /* Hotplug interrupt occurred, read EDID */
747 static void edid_work_fn(struct work_struct
*work
)
749 struct sh_hdmi
*hdmi
= container_of(work
, struct sh_hdmi
, edid_work
.work
);
750 struct sh_mobile_hdmi_info
*pdata
= hdmi
->dev
->platform_data
;
752 pr_debug("%s(%p): begin, hotplug status %d\n", __func__
,
753 pdata
->lcd_dev
, hdmi
->hp_state
);
758 if (hdmi
->hp_state
== HDMI_HOTPLUG_EDID_DONE
) {
759 pm_runtime_get_sync(hdmi
->dev
);
760 /* A device has been plugged in */
761 sh_hdmi_read_edid(hdmi
);
763 sh_hdmi_configure(hdmi
);
764 /* Switched to another (d) power-save mode */
770 acquire_console_sem();
773 hdmi
->info
->var
= hdmi
->var
;
774 if (hdmi
->info
->state
!= FBINFO_STATE_RUNNING
)
775 fb_set_suspend(hdmi
->info
, 0);
777 hdmi_display_on(hdmi
, hdmi
->info
);
779 release_console_sem();
784 acquire_console_sem();
786 /* HDMI disconnect */
787 fb_set_suspend(hdmi
->info
, 1);
789 release_console_sem();
790 pm_runtime_put(hdmi
->dev
);
793 pr_debug("%s(%p): end\n", __func__
, pdata
->lcd_dev
);
796 static int __init
sh_hdmi_probe(struct platform_device
*pdev
)
798 struct sh_mobile_hdmi_info
*pdata
= pdev
->dev
.platform_data
;
799 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
800 int irq
= platform_get_irq(pdev
, 0), ret
;
801 struct sh_hdmi
*hdmi
;
804 if (!res
|| !pdata
|| irq
< 0)
807 hdmi
= kzalloc(sizeof(*hdmi
), GFP_KERNEL
);
809 dev_err(&pdev
->dev
, "Cannot allocate device data\n");
813 hdmi
->dev
= &pdev
->dev
;
815 hdmi
->hdmi_clk
= clk_get(&pdev
->dev
, "ick");
816 if (IS_ERR(hdmi
->hdmi_clk
)) {
817 ret
= PTR_ERR(hdmi
->hdmi_clk
);
818 dev_err(&pdev
->dev
, "Unable to get clock: %d\n", ret
);
822 /* TODO: reconfigure the clock on monitor plug in */
823 rate
= PICOS2KHZ(pdata
->lcd_chan
->lcd_cfg
[0].pixclock
) * 1000;
825 rate
= clk_round_rate(hdmi
->hdmi_clk
, rate
);
828 dev_err(&pdev
->dev
, "Cannot get suitable rate: %ld\n", rate
);
832 ret
= clk_set_rate(hdmi
->hdmi_clk
, rate
);
834 dev_err(&pdev
->dev
, "Cannot set rate %ld: %d\n", rate
, ret
);
838 pr_debug("HDMI set frequency %lu\n", rate
);
840 ret
= clk_enable(hdmi
->hdmi_clk
);
842 dev_err(&pdev
->dev
, "Cannot enable clock: %d\n", ret
);
846 dev_info(&pdev
->dev
, "Enabled HDMI clock at %luHz\n", rate
);
848 if (!request_mem_region(res
->start
, resource_size(res
), dev_name(&pdev
->dev
))) {
849 dev_err(&pdev
->dev
, "HDMI register region already claimed\n");
854 hdmi
->base
= ioremap(res
->start
, resource_size(res
));
856 dev_err(&pdev
->dev
, "HDMI register region already claimed\n");
861 platform_set_drvdata(pdev
, hdmi
);
864 /* Product and revision IDs are 0 in sh-mobile version */
865 dev_info(&pdev
->dev
, "Detected HDMI controller 0x%x:0x%x\n",
866 hdmi_read(hdmi
, HDMI_PRODUCT_ID
), hdmi_read(hdmi
, HDMI_REVISION_ID
));
869 /* Set up LCDC callbacks */
870 pdata
->lcd_chan
->board_cfg
.board_data
= hdmi
;
871 pdata
->lcd_chan
->board_cfg
.display_on
= hdmi_display_on
;
872 pdata
->lcd_chan
->board_cfg
.display_off
= hdmi_display_off
;
874 INIT_DELAYED_WORK(&hdmi
->edid_work
, edid_work_fn
);
876 pm_runtime_enable(&pdev
->dev
);
877 pm_runtime_resume(&pdev
->dev
);
879 ret
= request_irq(irq
, sh_hdmi_hotplug
, 0,
880 dev_name(&pdev
->dev
), hdmi
);
882 dev_err(&pdev
->dev
, "Unable to request irq: %d\n", ret
);
889 pm_runtime_disable(&pdev
->dev
);
892 release_mem_region(res
->start
, resource_size(res
));
894 clk_disable(hdmi
->hdmi_clk
);
897 clk_put(hdmi
->hdmi_clk
);
904 static int __exit
sh_hdmi_remove(struct platform_device
*pdev
)
906 struct sh_mobile_hdmi_info
*pdata
= pdev
->dev
.platform_data
;
907 struct sh_hdmi
*hdmi
= platform_get_drvdata(pdev
);
908 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
909 int irq
= platform_get_irq(pdev
, 0);
911 pdata
->lcd_chan
->board_cfg
.display_on
= NULL
;
912 pdata
->lcd_chan
->board_cfg
.display_off
= NULL
;
913 pdata
->lcd_chan
->board_cfg
.board_data
= NULL
;
916 pm_runtime_disable(&pdev
->dev
);
917 cancel_delayed_work_sync(&hdmi
->edid_work
);
918 clk_disable(hdmi
->hdmi_clk
);
919 clk_put(hdmi
->hdmi_clk
);
921 release_mem_region(res
->start
, resource_size(res
));
927 static struct platform_driver sh_hdmi_driver
= {
928 .remove
= __exit_p(sh_hdmi_remove
),
930 .name
= "sh-mobile-hdmi",
934 static int __init
sh_hdmi_init(void)
936 return platform_driver_probe(&sh_hdmi_driver
, sh_hdmi_probe
);
938 module_init(sh_hdmi_init
);
940 static void __exit
sh_hdmi_exit(void)
942 platform_driver_unregister(&sh_hdmi_driver
);
944 module_exit(sh_hdmi_exit
);
946 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
947 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
948 MODULE_LICENSE("GPL v2");