drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24 #include <linux/module.h>
  25
  26 #include "../iio.h"
  27 #include "../sysfs.h"
  28 #include "../buffer_generic.h"
  29
  30 #include "lis3l02dq.h"
  31
  32 /* At the moment the spi framework doesn't allow global setting of cs_change.
  33  * It's in the likely to be added comment at the top of spi.h.
  34  * This means that use cannot be made of spi_write etc.
  35  */
  36 /* direct copy of the irq_default_primary_handler */
  37 #ifndef CONFIG_IIO_BUFFER
  38 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  39 {
  40         return IRQ_WAKE_THREAD;
  41 }
  42 #endif
  43
  44 /**
  45  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  46  * @indio_dev: iio_dev for this actual device
  47  * @reg_address: the address of the register to be read
  48  * @val: pass back the resulting value
  49  **/
  50 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  51                              u8 reg_address, u8 *val)
  52 {
  53         struct lis3l02dq_state *st = iio_priv(indio_dev);
  54         struct spi_message msg;
  55         int ret;
  56         struct spi_transfer xfer = {
  57                 .tx_buf = st->tx,
  58                 .rx_buf = st->rx,
  59                 .bits_per_word = 8,
  60                 .len = 2,
  61         };
  62
  63         mutex_lock(&st->buf_lock);
  64         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  65         st->tx[1] = 0;
  66
  67         spi_message_init(&msg);
  68         spi_message_add_tail(&xfer, &msg);
  69         ret = spi_sync(st->us, &msg);
  70         *val = st->rx[1];
  71         mutex_unlock(&st->buf_lock);
  72
  73         return ret;
  74 }
  75
  76 /**
  77  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  78  * @indio_dev: iio_dev for this device
  79  * @reg_address: the address of the register to be written
  80  * @val: the value to write
  81  **/
  82 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  83                               u8 reg_address,
  84                               u8 val)
  85 {
  86         int ret;
  87         struct lis3l02dq_state *st = iio_priv(indio_dev);
  88
  89         mutex_lock(&st->buf_lock);
  90         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  91         st->tx[1] = val;
  92         ret = spi_write(st->us, st->tx, 2);
  93         mutex_unlock(&st->buf_lock);
  94
  95         return ret;
  96 }
  97
  98 /**
  99  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 100  * @indio_dev: iio_dev for this device
 101  * @lower_reg_address: the address of the lower of the two registers.
 102  *               Second register is assumed to have address one greater.
 103  * @value: value to be written
 104  **/
 105 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 106                                        u8 lower_reg_address,
 107                                        s16 value)
 108 {
 109         int ret;
 110         struct spi_message msg;
 111         struct lis3l02dq_state *st = iio_priv(indio_dev);
 112         struct spi_transfer xfers[] = { {
 113                         .tx_buf = st->tx,
 114                         .bits_per_word = 8,
 115                         .len = 2,
 116                         .cs_change = 1,
 117                 }, {
 118                         .tx_buf = st->tx + 2,
 119                         .bits_per_word = 8,
 120                         .len = 2,
 121                 },
 122         };
 123
 124         mutex_lock(&st->buf_lock);
 125         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 126         st->tx[1] = value & 0xFF;
 127         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 128         st->tx[3] = (value >> 8) & 0xFF;
 129
 130         spi_message_init(&msg);
 131         spi_message_add_tail(&xfers[0], &msg);
 132         spi_message_add_tail(&xfers[1], &msg);
 133         ret = spi_sync(st->us, &msg);
 134         mutex_unlock(&st->buf_lock);
 135
 136         return ret;
 137 }
 138
 139 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 140                                   u8 lower_reg_address,
 141                                   int *val)
 142 {
 143         struct lis3l02dq_state *st = iio_priv(indio_dev);
 144
 145         struct spi_message msg;
 146         int ret;
 147         s16 tempval;
 148         struct spi_transfer xfers[] = { {
 149                         .tx_buf = st->tx,
 150                         .rx_buf = st->rx,
 151                         .bits_per_word = 8,
 152                         .len = 2,
 153                         .cs_change = 1,
 154                 }, {
 155                         .tx_buf = st->tx + 2,
 156                         .rx_buf = st->rx + 2,
 157                         .bits_per_word = 8,
 158                         .len = 2,
 159                 },
 160         };
 161
 162         mutex_lock(&st->buf_lock);
 163         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 164         st->tx[1] = 0;
 165         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 166         st->tx[3] = 0;
 167
 168         spi_message_init(&msg);
 169         spi_message_add_tail(&xfers[0], &msg);
 170         spi_message_add_tail(&xfers[1], &msg);
 171         ret = spi_sync(st->us, &msg);
 172         if (ret) {
 173                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 174                 goto error_ret;
 175         }
 176         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 177
 178         *val = tempval;
 179 error_ret:
 180         mutex_unlock(&st->buf_lock);
 181         return ret;
 182 }
 183
 184 enum lis3l02dq_rm_ind {
 185         LIS3L02DQ_ACCEL,
 186         LIS3L02DQ_GAIN,
 187         LIS3L02DQ_BIAS,
 188 };
 189
 190 static u8 lis3l02dq_axis_map[3][3] = {
 191         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 192                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 193                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 194         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 195                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 196                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 197         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 198                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 199                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 200 };
 201
 202 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 203                                  u64 e,
 204                                  int *val)
 205 {
 206         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 207 }
 208
 209 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 210                                   u64 event_code,
 211                                   int val)
 212 {
 213         u16 value = val;
 214         return lis3l02dq_spi_write_reg_s16(indio_dev,
 215                                            LIS3L02DQ_REG_THS_L_ADDR,
 216                                            value);
 217 }
 218
 219 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 220                                struct iio_chan_spec const *chan,
 221                                int val,
 222                                int val2,
 223                                long mask)
 224 {
 225         int ret = -EINVAL, reg;
 226         u8 uval;
 227         s8 sval;
 228         switch (mask) {
 229         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 230                 if (val > 255 || val < -256)
 231                         return -EINVAL;
 232                 sval = val;
 233                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 234                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 235                 break;
 236         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 237                 if (val & ~0xFF)
 238                         return -EINVAL;
 239                 uval = val;
 240                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 241                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 242                 break;
 243         }
 244         return ret;
 245 }
 246
 247 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 248                               struct iio_chan_spec const *chan,
 249                               int *val,
 250                               int *val2,
 251                               long mask)
 252 {
 253         u8 utemp;
 254         s8 stemp;
 255         ssize_t ret = 0;
 256         u8 reg;
 257
 258         switch (mask) {
 259         case 0:
 260                 /* Take the iio_dev status lock */
 261                 mutex_lock(&indio_dev->mlock);
 262                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
 263                         ret = lis3l02dq_read_accel_from_buffer(indio_dev->
 264                                                                buffer,
 265                                                                chan->scan_index,
 266                                                                val);
 267                 else {
 268                         reg = lis3l02dq_axis_map
 269                                 [LIS3L02DQ_ACCEL][chan->address];
 270                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 271                 }
 272                 mutex_unlock(&indio_dev->mlock);
 273                 return IIO_VAL_INT;
 274         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 275                 *val = 0;
 276                 *val2 = 9580;
 277                 return IIO_VAL_INT_PLUS_MICRO;
 278         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 279                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 280                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 281                 if (ret)
 282                         goto error_ret;
 283                 /* to match with what previous code does */
 284                 *val = utemp;
 285                 return IIO_VAL_INT;
 286
 287         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 288                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 289                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 290                 /* to match with what previous code does */
 291                 *val = stemp;
 292                 return IIO_VAL_INT;
 293         }
 294 error_ret:
 295         return ret;
 296 }
 297
 298 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 299                                         struct device_attribute *attr,
 300                                         char *buf)
 301 {
 302         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 303         int ret, len = 0;
 304         s8 t;
 305         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 306                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 307                                        (u8 *)&t);
 308         if (ret)
 309                 return ret;
 310         t &= LIS3L02DQ_DEC_MASK;
 311         switch (t) {
 312         case LIS3L02DQ_REG_CTRL_1_DF_128:
 313                 len = sprintf(buf, "280\n");
 314                 break;
 315         case LIS3L02DQ_REG_CTRL_1_DF_64:
 316                 len = sprintf(buf, "560\n");
 317                 break;
 318         case LIS3L02DQ_REG_CTRL_1_DF_32:
 319                 len = sprintf(buf, "1120\n");
 320                 break;
 321         case LIS3L02DQ_REG_CTRL_1_DF_8:
 322                 len = sprintf(buf, "4480\n");
 323                 break;
 324         }
 325         return len;
 326 }
 327
 328 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 329                                          struct device_attribute *attr,
 330                                          const char *buf,
 331                                          size_t len)
 332 {
 333         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 334         long val;
 335         int ret;
 336         u8 t;
 337
 338         ret = strict_strtol(buf, 10, &val);
 339         if (ret)
 340                 return ret;
 341
 342         mutex_lock(&indio_dev->mlock);
 343         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 344                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 345                                        &t);
 346         if (ret)
 347                 goto error_ret_mutex;
 348         /* Wipe the bits clean */
 349         t &= ~LIS3L02DQ_DEC_MASK;
 350         switch (val) {
 351         case 280:
 352                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 353                 break;
 354         case 560:
 355                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 356                 break;
 357         case 1120:
 358                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 359                 break;
 360         case 4480:
 361                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 362                 break;
 363         default:
 364                 ret = -EINVAL;
 365                 goto error_ret_mutex;
 366         }
 367
 368         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 369                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 370                                         t);
 371
 372 error_ret_mutex:
 373         mutex_unlock(&indio_dev->mlock);
 374
 375         return ret ? ret : len;
 376 }
 377
 378 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 379 {
 380         struct lis3l02dq_state *st = iio_priv(indio_dev);
 381         int ret;
 382         u8 val, valtest;
 383
 384         st->us->mode = SPI_MODE_3;
 385
 386         spi_setup(st->us);
 387
 388         val = LIS3L02DQ_DEFAULT_CTRL1;
 389         /* Write suitable defaults to ctrl1 */
 390         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 391                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 392                                         val);
 393         if (ret) {
 394                 dev_err(&st->us->dev, "problem with setup control register 1");
 395                 goto err_ret;
 396         }
 397         /* Repeat as sometimes doesn't work first time?*/
 398         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 399                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 400                                         val);
 401         if (ret) {
 402                 dev_err(&st->us->dev, "problem with setup control register 1");
 403                 goto err_ret;
 404         }
 405
 406         /* Read back to check this has worked acts as loose test of correct
 407          * chip */
 408         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 409                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 410                                        &valtest);
 411         if (ret || (valtest != val)) {
 412                 dev_err(&indio_dev->dev,
 413                         "device not playing ball %d %d\n", valtest, val);
 414                 ret = -EINVAL;
 415                 goto err_ret;
 416         }
 417
 418         val = LIS3L02DQ_DEFAULT_CTRL2;
 419         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 420                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 421                                         val);
 422         if (ret) {
 423                 dev_err(&st->us->dev, "problem with setup control register 2");
 424                 goto err_ret;
 425         }
 426
 427         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 428         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 429                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 430                                         val);
 431         if (ret)
 432                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 433 err_ret:
 434
 435         return ret;
 436 }
 437
 438 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 439                               lis3l02dq_read_frequency,
 440                               lis3l02dq_write_frequency);
 441
 442 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 443
 444 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 445 {
 446         struct iio_dev *indio_dev = private;
 447         u8 t;
 448
 449         s64 timestamp = iio_get_time_ns();
 450
 451         lis3l02dq_spi_read_reg_8(indio_dev,
 452                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 453                                  &t);
 454
 455         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 456                 iio_push_event(indio_dev,
 457                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 458                                                   0,
 459                                                   IIO_MOD_Z,
 460                                                   IIO_EV_TYPE_THRESH,
 461                                                   IIO_EV_DIR_RISING),
 462                                timestamp);
 463
 464         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 465                 iio_push_event(indio_dev,
 466                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 467                                                   0,
 468                                                   IIO_MOD_Z,
 469                                                   IIO_EV_TYPE_THRESH,
 470                                                   IIO_EV_DIR_FALLING),
 471                                timestamp);
 472
 473         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 474                 iio_push_event(indio_dev,
 475                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 476                                                   0,
 477                                                   IIO_MOD_Y,
 478                                                   IIO_EV_TYPE_THRESH,
 479                                                   IIO_EV_DIR_RISING),
 480                                timestamp);
 481
 482         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 483                 iio_push_event(indio_dev,
 484                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 485                                                   0,
 486                                                   IIO_MOD_Y,
 487                                                   IIO_EV_TYPE_THRESH,
 488                                                   IIO_EV_DIR_FALLING),
 489                                timestamp);
 490
 491         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 492                 iio_push_event(indio_dev,
 493                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 494                                                   0,
 495                                                   IIO_MOD_X,
 496                                                   IIO_EV_TYPE_THRESH,
 497                                                   IIO_EV_DIR_RISING),
 498                                timestamp);
 499
 500         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 501                 iio_push_event(indio_dev,
 502                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 503                                                   0,
 504                                                   IIO_MOD_X,
 505                                                   IIO_EV_TYPE_THRESH,
 506                                                   IIO_EV_DIR_FALLING),
 507                                timestamp);
 508
 509         /* Ack and allow for new interrupts */
 510         lis3l02dq_spi_read_reg_8(indio_dev,
 511                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 512                                  &t);
 513
 514         return IRQ_HANDLED;
 515 }
 516
 517 #define LIS3L02DQ_INFO_MASK                             \
 518         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 519          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 520          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 521
 522 #define LIS3L02DQ_EVENT_MASK                                    \
 523         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 524          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 525
 526 static struct iio_chan_spec lis3l02dq_channels[] = {
 527         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 528                  0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 529         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 530                  1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 531         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 532                  2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 533         IIO_CHAN_SOFT_TIMESTAMP(3)
 534 };
 535
 536
 537 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 538                                            u64 event_code)
 539 {
 540
 541         u8 val;
 542         int ret;
 543         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 544                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 545                           IIO_EV_DIR_RISING)));
 546         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 547                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 548                                        &val);
 549         if (ret < 0)
 550                 return ret;
 551
 552         return !!(val & mask);
 553 }
 554
 555 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 556 {
 557         int ret;
 558         u8 control, val;
 559
 560         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 561                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 562                                        &control);
 563
 564         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 565         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 566                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 567                                         control);
 568         if (ret)
 569                 goto error_ret;
 570         /* Also for consistency clear the mask */
 571         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 572                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 573                                        &val);
 574         if (ret)
 575                 goto error_ret;
 576         val &= ~0x3f;
 577
 578         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 579                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 580                                         val);
 581         if (ret)
 582                 goto error_ret;
 583
 584         ret = control;
 585 error_ret:
 586         return ret;
 587 }
 588
 589 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 590                                         u64 event_code,
 591                                         int state)
 592 {
 593         int ret = 0;
 594         u8 val, control;
 595         u8 currentlyset;
 596         bool changed = false;
 597         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 598                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 599                           IIO_EV_DIR_RISING)));
 600
 601         mutex_lock(&indio_dev->mlock);
 602         /* read current control */
 603         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 604                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 605                                        &control);
 606         if (ret)
 607                 goto error_ret;
 608         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 609                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 610                                        &val);
 611         if (ret < 0)
 612                 goto error_ret;
 613         currentlyset = val & mask;
 614
 615         if (!currentlyset && state) {
 616                 changed = true;
 617                 val |= mask;
 618         } else if (currentlyset && !state) {
 619                 changed = true;
 620                 val &= ~mask;
 621         }
 622
 623         if (changed) {
 624                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 625                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 626                                                 val);
 627                 if (ret)
 628                         goto error_ret;
 629                 control = val & 0x3f ?
 630                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 631                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 632                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 633                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 634                                                control);
 635                 if (ret)
 636                         goto error_ret;
 637         }
 638
 639 error_ret:
 640         mutex_unlock(&indio_dev->mlock);
 641         return ret;
 642 }
 643
 644 static struct attribute *lis3l02dq_attributes[] = {
 645         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 646         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 647         NULL
 648 };
 649
 650 static const struct attribute_group lis3l02dq_attribute_group = {
 651         .attrs = lis3l02dq_attributes,
 652 };
 653
 654 static const struct iio_info lis3l02dq_info = {
 655         .read_raw = &lis3l02dq_read_raw,
 656         .write_raw = &lis3l02dq_write_raw,
 657         .read_event_value = &lis3l02dq_read_thresh,
 658         .write_event_value = &lis3l02dq_write_thresh,
 659         .write_event_config = &lis3l02dq_write_event_config,
 660         .read_event_config = &lis3l02dq_read_event_config,
 661         .driver_module = THIS_MODULE,
 662         .attrs = &lis3l02dq_attribute_group,
 663 };
 664
 665 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 666 {
 667         int ret;
 668         struct lis3l02dq_state *st;
 669         struct iio_dev *indio_dev;
 670
 671         indio_dev = iio_allocate_device(sizeof *st);
 672         if (indio_dev == NULL) {
 673                 ret = -ENOMEM;
 674                 goto error_ret;
 675         }
 676         st = iio_priv(indio_dev);
 677         /* this is only used tor removal purposes */
 678         spi_set_drvdata(spi, indio_dev);
 679
 680         st->us = spi;
 681         mutex_init(&st->buf_lock);
 682         indio_dev->name = spi->dev.driver->name;
 683         indio_dev->dev.parent = &spi->dev;
 684         indio_dev->info = &lis3l02dq_info;
 685         indio_dev->channels = lis3l02dq_channels;
 686         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 687
 688         indio_dev->modes = INDIO_DIRECT_MODE;
 689
 690         ret = lis3l02dq_configure_buffer(indio_dev);
 691         if (ret)
 692                 goto error_free_dev;
 693
 694         ret = iio_buffer_register(indio_dev,
 695                                   lis3l02dq_channels,
 696                                   ARRAY_SIZE(lis3l02dq_channels));
 697         if (ret) {
 698                 printk(KERN_ERR "failed to initialize the buffer\n");
 699                 goto error_unreg_buffer_funcs;
 700         }
 701
 702         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 703                 ret = request_threaded_irq(st->us->irq,
 704                                            &lis3l02dq_th,
 705                                            &lis3l02dq_event_handler,
 706                                            IRQF_TRIGGER_RISING,
 707                                            "lis3l02dq",
 708                                            indio_dev);
 709                 if (ret)
 710                         goto error_uninitialize_buffer;
 711
 712                 ret = lis3l02dq_probe_trigger(indio_dev);
 713                 if (ret)
 714                         goto error_free_interrupt;
 715         }
 716
 717         /* Get the device into a sane initial state */
 718         ret = lis3l02dq_initial_setup(indio_dev);
 719         if (ret)
 720                 goto error_remove_trigger;
 721
 722         ret = iio_device_register(indio_dev);
 723         if (ret)
 724                 goto error_remove_trigger;
 725
 726         return 0;
 727
 728 error_remove_trigger:
 729         if (indio_dev->modes & INDIO_BUFFER_TRIGGERED)
 730                 lis3l02dq_remove_trigger(indio_dev);
 731 error_free_interrupt:
 732         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 733                 free_irq(st->us->irq, indio_dev);
 734 error_uninitialize_buffer:
 735         iio_buffer_unregister(indio_dev);
 736 error_unreg_buffer_funcs:
 737         lis3l02dq_unconfigure_buffer(indio_dev);
 738 error_free_dev:
 739                 iio_free_device(indio_dev);
 740 error_ret:
 741         return ret;
 742 }
 743
 744 /* Power down the device */
 745 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 746 {
 747         int ret;
 748         struct lis3l02dq_state *st = iio_priv(indio_dev);
 749         u8 val = 0;
 750
 751         mutex_lock(&indio_dev->mlock);
 752         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 753                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 754                                         val);
 755         if (ret) {
 756                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 757                 goto err_ret;
 758         }
 759
 760         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 761                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 762                                         val);
 763         if (ret)
 764                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 765 err_ret:
 766         mutex_unlock(&indio_dev->mlock);
 767         return ret;
 768 }
 769
 770 /* fixme, confirm ordering in this function */
 771 static int lis3l02dq_remove(struct spi_device *spi)
 772 {
 773         int ret;
 774         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 775         struct lis3l02dq_state *st = iio_priv(indio_dev);
 776
 777         ret = lis3l02dq_disable_all_events(indio_dev);
 778         if (ret)
 779                 goto err_ret;
 780
 781         ret = lis3l02dq_stop_device(indio_dev);
 782         if (ret)
 783                 goto err_ret;
 784
 785         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 786                 free_irq(st->us->irq, indio_dev);
 787
 788         lis3l02dq_remove_trigger(indio_dev);
 789         iio_buffer_unregister(indio_dev);
 790         lis3l02dq_unconfigure_buffer(indio_dev);
 791
 792         iio_device_unregister(indio_dev);
 793
 794 err_ret:
 795         return ret;
 796 }
 797
 798 static struct spi_driver lis3l02dq_driver = {
 799         .driver = {
 800                 .name = "lis3l02dq",
 801                 .owner = THIS_MODULE,
 802         },
 803         .probe = lis3l02dq_probe,
 804         .remove = __devexit_p(lis3l02dq_remove),
 805 };
 806
 807 static __init int lis3l02dq_init(void)
 808 {
 809         return spi_register_driver(&lis3l02dq_driver);
 810 }
 811 module_init(lis3l02dq_init);
 812
 813 static __exit void lis3l02dq_exit(void)
 814 {
 815         spi_unregister_driver(&lis3l02dq_driver);
 816 }
 817 module_exit(lis3l02dq_exit);
 818
 819 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 820 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 821 MODULE_LICENSE("GPL v2");