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Merge branch 'topic/asoc' into for-linus
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / sh_mobile_hdmi.c
blob47635fd145578b81b5494f893f074c3628457767
1 /*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28
29 #include <video/sh_mobile_hdmi.h>
30 #include <video/sh_mobile_lcdc.h>
31
32 #include "sh_mobile_lcdcfb.h"
33
34 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
36 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
40 bits 19..16 of Internal CTS */
41 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
42 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
43 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
44 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
45 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
46 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
47 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
48 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
49 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
50 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
51 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
52 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
55 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
57 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
58 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
59 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
60
61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
63
64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
65 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
66 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
67 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
68 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
69 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
70 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
71 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
72 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
73 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
74 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
75 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
76 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
77 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
78 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
80 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
81 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
82 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
83 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
84 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
98 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
133 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
134 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
135 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
136 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
137 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
138 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
139 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
140 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
141 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
142 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
144 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
145 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
146 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
147 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
148 #define HDMI_SHA0 0xB9 /* sha0 */
149 #define HDMI_SHA1 0xBA /* sha1 */
150 #define HDMI_SHA2 0xBB /* sha2 */
151 #define HDMI_SHA3 0xBC /* sha3 */
152 #define HDMI_SHA4 0xBD /* sha4 */
153 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
154 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
155 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
156 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
157 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
158 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
159 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
160 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
161 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
162 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
163 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
164 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
165 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
166 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
167 #define HDMI_AN_SEED 0xCC /* An seed */
168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
171 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
172 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
174 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
175 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
176 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
177 #define HDMI_PJ 0xD7 /* Pj */
178 #define HDMI_SHA_RD 0xD8 /* sha_rd */
179 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
180 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
181 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
182 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
183 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
184 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
185 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
186 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
187 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
188 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
189 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
190 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
191 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
192 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
193 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
194 #define HDMI_AN_23_16 0xEA /* An [23:16] */
195 #define HDMI_AN_31_24 0xEB /* An [31:24] */
196 #define HDMI_AN_39_32 0xEC /* An [39:32] */
197 #define HDMI_AN_47_40 0xED /* An [47:40] */
198 #define HDMI_AN_55_48 0xEE /* An [55:48] */
199 #define HDMI_AN_63_56 0xEF /* An [63:56] */
200 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
201 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
202 #define HDMI_TEST_MODE 0xFE /* Test mode */
203
204 enum hotplug_state {
205 HDMI_HOTPLUG_DISCONNECTED,
206 HDMI_HOTPLUG_CONNECTED,
207 HDMI_HOTPLUG_EDID_DONE,
208 };
209
210 struct sh_hdmi {
211 void __iomem *base;
212 enum hotplug_state hp_state; /* hot-plug status */
213 bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
214 struct clk *hdmi_clk;
215 struct device *dev;
216 struct fb_info *info;
217 struct mutex mutex; /* Protect the info pointer */
218 struct delayed_work edid_work;
219 struct fb_var_screeninfo var;
220 struct fb_monspecs monspec;
221 };
222
223 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
224 {
225 iowrite8(data, hdmi->base + reg);
226 }
227
228 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
229 {
230 return ioread8(hdmi->base + reg);
231 }
232
233 /*
234 * HDMI sound
235 */
236 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
237 unsigned int reg)
238 {
239 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
240
241 return hdmi_read(hdmi, reg);
242 }
243
244 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
245 unsigned int reg,
246 unsigned int value)
247 {
248 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
249
250 hdmi_write(hdmi, value, reg);
251 return 0;
252 }
253
254 static struct snd_soc_dai_driver sh_hdmi_dai = {
255 .name = "sh_mobile_hdmi-hifi",
256 .playback = {
257 .stream_name = "Playback",
258 .channels_min = 2,
259 .channels_max = 8,
260 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
261 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
262 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
263 SNDRV_PCM_RATE_192000,
264 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
265 },
266 };
267
268 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
269 {
270 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
271
272 return 0;
273 }
274
275 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
276 .probe = sh_hdmi_snd_probe,
277 .read = sh_hdmi_snd_read,
278 .write = sh_hdmi_snd_write,
279 };
280
281 /*
282 * HDMI video
283 */
284
285 /* External video parameter settings */
286 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
287 {
288 struct fb_var_screeninfo *var = &hdmi->var;
289 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
290 u8 sync = 0;
291
292 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
293
294 hdelay = var->hsync_len + var->left_margin;
295 hblank = var->right_margin + hdelay;
296
297 /*
298 * Vertical timing looks a bit different in Figure 18,
299 * but let's try the same first by setting offset = 0
300 */
301 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
302
303 vdelay = var->vsync_len + var->upper_margin;
304 vblank = var->lower_margin + vdelay;
305 voffset = min(var->upper_margin / 2, 6U);
306
307 /*
308 * [3]: VSYNC polarity: Positive
309 * [2]: HSYNC polarity: Positive
310 * [1]: Interlace/Progressive: Progressive
311 * [0]: External video settings enable: used.
312 */
313 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
314 sync |= 4;
315 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
316 sync |= 8;
317
318 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
319 htotal, hblank, hdelay, var->hsync_len,
320 vtotal, vblank, vdelay, var->vsync_len, sync);
321
322 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
323
324 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
325 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
326
327 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
328 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
329
330 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
331 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
332
333 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
334 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
335
336 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
337 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
338
339 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
340
341 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
342
343 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
344
345 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
346 if (!hdmi->preprogrammed_mode)
347 hdmi_write(hdmi, sync | 1 | (voffset << 4),
348 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
349 }
350
351 /**
352 * sh_hdmi_video_config()
353 */
354 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
355 {
356 /*
357 * [7:4]: Audio sampling frequency: 48kHz
358 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
359 * [0]: Internal/External DE select: internal
360 */
361 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
362
363 /*
364 * [7:6]: Video output format: RGB 4:4:4
365 * [5:4]: Input video data width: 8 bit
366 * [3:1]: EAV/SAV location: channel 1
367 * [0]: Video input color space: RGB
368 */
369 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
370
371 /*
372 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
373 * left at 0 by default, this configures 24bpp and sets the Color Depth
374 * (CD) field in the General Control Packet
375 */
376 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
377 }
378
379 /**
380 * sh_hdmi_audio_config()
381 */
382 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
383 {
384 u8 data;
385 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
386
387 /*
388 * [7:4] L/R data swap control
389 * [3:0] appropriate N[19:16]
390 */
391 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
392 /* appropriate N[15:8] */
393 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
394 /* appropriate N[7:0] */
395 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
396
397 /* [7:4] 48 kHz SPDIF not used */
398 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
399
400 /*
401 * [6:5] set required down sampling rate if required
402 * [4:3] set required audio source
403 */
404 switch (pdata->flags & HDMI_SND_SRC_MASK) {
405 default:
406 /* fall through */
407 case HDMI_SND_SRC_I2S:
408 data = 0x0 << 3;
409 break;
410 case HDMI_SND_SRC_SPDIF:
411 data = 0x1 << 3;
412 break;
413 case HDMI_SND_SRC_DSD:
414 data = 0x2 << 3;
415 break;
416 case HDMI_SND_SRC_HBR:
417 data = 0x3 << 3;
418 break;
419 }
420 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
421
422 /* [3:0] set sending channel number for channel status */
423 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
424
425 /*
426 * [5:2] set valid I2S source input pin
427 * [1:0] set input I2S source mode
428 */
429 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
430
431 /* [7:4] set valid DSD source input pin */
432 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
433
434 /* [7:0] set appropriate I2S input pin swap settings if required */
435 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
436
437 /*
438 * [7] set validity bit for channel status
439 * [3:0] set original sample frequency for channel status
440 */
441 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
442
443 /*
444 * [7] set value for channel status
445 * [6] set value for channel status
446 * [5] set copyright bit for channel status
447 * [4:2] set additional information for channel status
448 * [1:0] set clock accuracy for channel status
449 */
450 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
451
452 /* [7:0] set category code for channel status */
453 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
454
455 /*
456 * [7:4] set source number for channel status
457 * [3:0] set word length for channel status
458 */
459 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
460
461 /* [7:4] set sample frequency for channel status */
462 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
463 }
464
465 /**
466 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
467 */
468 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
469 {
470 if (hdmi->var.yres > 480) {
471 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
472 /*
473 * [1:0] Speed_A
474 * [3:2] Speed_B
475 * [4] PLLA_Bypass
476 * [6] DRV_TEST_EN
477 * [7] DRV_TEST_IN
478 */
479 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
480 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
481 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
482 /*
483 * [2:0] BGR_I_OFFSET
484 * [6:4] BGR_V_OFFSET
485 */
486 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
487 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
488 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
489 /*
490 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
491 * LPF capacitance, LPF resistance[1]
492 */
493 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
494 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
495 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
496 /*
497 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
498 * LPF capacitance, LPF resistance[1]
499 */
500 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
501 /* DRV_CONFIG, PE_CONFIG */
502 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
503 /*
504 * [2:0] AMON_SEL (4 == LPF voltage)
505 * [4] PLLA_CONFIG[16]
506 * [5] PLLB_CONFIG[16]
507 */
508 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
509 } else {
510 /* for 480p8bit 27MHz */
511 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
512 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
513 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
514 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
515 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
516 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
517 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
518 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
519 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
520 }
521 }
522
523 /**
524 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
525 */
526 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
527 {
528 u8 vic;
529
530 /* AVI InfoFrame */
531 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
532
533 /* Packet Type = 0x82 */
534 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
535
536 /* Version = 0x02 */
537 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
538
539 /* Length = 13 (0x0D) */
540 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
541
542 /* N. A. Checksum */
543 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
544
545 /*
546 * Y = RGB
547 * A0 = No Data
548 * B = Bar Data not valid
549 * S = No Data
550 */
551 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
552
553 /*
554 * [7:6] C = Colorimetry: no data
555 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
556 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
557 */
558 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
559
560 /*
561 * ITC = No Data
562 * EC = xvYCC601
563 * Q = Default (depends on video format)
564 * SC = No Known non_uniform Scaling
565 */
566 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
567
568 /*
569 * VIC = 1280 x 720p: ignored if external config is used
570 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
571 */
572 if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
573 vic = 16;
574 else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
575 vic = 2;
576 else
577 vic = 4;
578 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
579
580 /* PR = No Repetition */
581 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
582
583 /* Line Number of End of Top Bar (lower 8 bits) */
584 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
585
586 /* Line Number of End of Top Bar (upper 8 bits) */
587 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
588
589 /* Line Number of Start of Bottom Bar (lower 8 bits) */
590 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
591
592 /* Line Number of Start of Bottom Bar (upper 8 bits) */
593 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
594
595 /* Pixel Number of End of Left Bar (lower 8 bits) */
596 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
597
598 /* Pixel Number of End of Left Bar (upper 8 bits) */
599 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
600
601 /* Pixel Number of Start of Right Bar (lower 8 bits) */
602 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
603
604 /* Pixel Number of Start of Right Bar (upper 8 bits) */
605 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
606 }
607
608 /**
609 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
610 */
611 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
612 {
613 /* Audio InfoFrame */
614 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
615
616 /* Packet Type = 0x84 */
617 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
618
619 /* Version Number = 0x01 */
620 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
621
622 /* 0 Length = 10 (0x0A) */
623 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
624
625 /* n. a. Checksum */
626 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
627
628 /* Audio Channel Count = Refer to Stream Header */
629 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
630
631 /* Refer to Stream Header */
632 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
633
634 /* Format depends on coding type (i.e. CT0...CT3) */
635 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
636
637 /* Speaker Channel Allocation = Front Right + Front Left */
638 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
639
640 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
641 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
642
643 /* Reserved (0) */
644 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
645 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
646 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
647 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
648 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
649 }
650
651 /**
652 * sh_hdmi_configure() - Initialise HDMI for output
653 */
654 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
655 {
656 /* Configure video format */
657 sh_hdmi_video_config(hdmi);
658
659 /* Configure audio format */
660 sh_hdmi_audio_config(hdmi);
661
662 /* Configure PHY */
663 sh_hdmi_phy_config(hdmi);
664
665 /* Auxiliary Video Information (AVI) InfoFrame */
666 sh_hdmi_avi_infoframe_setup(hdmi);
667
668 /* Audio InfoFrame */
669 sh_hdmi_audio_infoframe_setup(hdmi);
670
671 /*
672 * Control packet auto send with VSYNC control: auto send
673 * General control, Gamut metadata, ISRC, and ACP packets
674 */
675 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
676
677 /* FIXME */
678 msleep(10);
679
680 /* PS mode b->d, reset PLLA and PLLB */
681 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
682
683 udelay(10);
684
685 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
686 }
687
688 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
689 const struct fb_videomode *mode)
690 {
691 long target = PICOS2KHZ(mode->pixclock) * 1000,
692 rate = clk_round_rate(hdmi->hdmi_clk, target);
693 unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
694
695 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
696 mode->left_margin, mode->xres,
697 mode->right_margin, mode->hsync_len,
698 mode->upper_margin, mode->yres,
699 mode->lower_margin, mode->vsync_len);
700
701 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
702 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
703 mode->refresh);
704
705 return rate_error;
706 }
707
708 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
709 {
710 struct fb_var_screeninfo tmpvar;
711 struct fb_var_screeninfo *var = &tmpvar;
712 const struct fb_videomode *mode, *found = NULL;
713 struct fb_info *info = hdmi->info;
714 struct fb_modelist *modelist = NULL;
715 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
716 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
717 bool exact_match = false;
718 u8 edid[128];
719 char *forced;
720 int i;
721
722 /* Read EDID */
723 dev_dbg(hdmi->dev, "Read back EDID code:");
724 for (i = 0; i < 128; i++) {
725 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
726 #ifdef DEBUG
727 if ((i % 16) == 0) {
728 printk(KERN_CONT "\n");
729 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
730 } else {
731 printk(KERN_CONT " %02X", edid[i]);
732 }
733 #endif
734 }
735 #ifdef DEBUG
736 printk(KERN_CONT "\n");
737 #endif
738
739 fb_edid_to_monspecs(edid, &hdmi->monspec);
740
741 fb_get_options("sh_mobile_lcdc", &forced);
742 if (forced && *forced) {
743 /* Only primitive parsing so far */
744 i = sscanf(forced, "%ux%u@%u",
745 &f_width, &f_height, &f_refresh);
746 if (i < 2) {
747 f_width = 0;
748 f_height = 0;
749 }
750 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
751 f_width, f_height, f_refresh);
752 }
753
754 /* Walk monitor modes to find the best or the exact match */
755 for (i = 0, mode = hdmi->monspec.modedb;
756 f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
757 i++, mode++) {
758 unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
759
760 /* No interest in unmatching modes */
761 if (f_width != mode->xres || f_height != mode->yres)
762 continue;
763 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
764 /*
765 * Exact match if either the refresh rate matches or it
766 * hasn't been specified and we've found a mode, for
767 * which we can configure the clock precisely
768 */
769 exact_match = true;
770 else if (found && found_rate_error <= rate_error)
771 /*
772 * We otherwise search for the closest matching clock
773 * rate - either if no refresh rate has been specified
774 * or we cannot find an exactly matching one
775 */
776 continue;
777
778 /* Check if supported: sufficient fb memory, supported clock-rate */
779 fb_videomode_to_var(var, mode);
780
781 if (info && info->fbops->fb_check_var &&
782 info->fbops->fb_check_var(var, info)) {
783 exact_match = false;
784 continue;
785 }
786
787 found = mode;
788 found_rate_error = rate_error;
789 }
790
791 hdmi->var.width = hdmi->monspec.max_x * 10;
792 hdmi->var.height = hdmi->monspec.max_y * 10;
793
794 /*
795 * TODO 1: if no ->info is present, postpone running the config until
796 * after ->info first gets registered.
797 * TODO 2: consider registering the HDMI platform device from the LCDC
798 * driver, and passing ->info with HDMI platform data.
799 */
800 if (info && !found) {
801 modelist = hdmi->info->modelist.next &&
802 !list_empty(&hdmi->info->modelist) ?
803 list_entry(hdmi->info->modelist.next,
804 struct fb_modelist, list) :
805 NULL;
806
807 if (modelist) {
808 found = &modelist->mode;
809 found_rate_error = sh_hdmi_rate_error(hdmi, found);
810 }
811 }
812
813 /* No cookie today */
814 if (!found)
815 return -ENXIO;
816
817 dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
818 modelist ? "default" : "EDID", found->xres, found->yres,
819 found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
820
821 if ((found->xres == 720 && found->yres == 480) ||
822 (found->xres == 1280 && found->yres == 720) ||
823 (found->xres == 1920 && found->yres == 1080))
824 hdmi->preprogrammed_mode = true;
825 else
826 hdmi->preprogrammed_mode = false;
827
828 fb_videomode_to_var(&hdmi->var, found);
829 sh_hdmi_external_video_param(hdmi);
830
831 return 0;
832 }
833
834 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
835 {
836 struct sh_hdmi *hdmi = dev_id;
837 u8 status1, status2, mask1, mask2;
838
839 /* mode_b and PLLA and PLLB reset */
840 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
841
842 /* How long shall reset be held? */
843 udelay(10);
844
845 /* mode_b and PLLA and PLLB reset release */
846 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
847
848 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
849 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
850
851 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
852 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
853
854 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
855 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
856 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
857
858 if (printk_ratelimit())
859 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
860 irq, status1, mask1, status2, mask2);
861
862 if (!((status1 & mask1) | (status2 & mask2))) {
863 return IRQ_NONE;
864 } else if (status1 & 0xc0) {
865 u8 msens;
866
867 /* Datasheet specifies 10ms... */
868 udelay(500);
869
870 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
871 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
872 /* Check, if hot plug & MSENS pin status are both high */
873 if ((msens & 0xC0) == 0xC0) {
874 /* Display plug in */
875 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
876
877 /* Set EDID word address */
878 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
879 /* Set EDID segment pointer */
880 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
881 /* Enable EDID interrupt */
882 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
883 } else if (!(status1 & 0x80)) {
884 /* Display unplug, beware multiple interrupts */
885 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
886 schedule_delayed_work(&hdmi->edid_work, 0);
887
888 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
889 /* display_off will switch back to mode_a */
890 }
891 } else if (status1 & 2) {
892 /* EDID error interrupt: retry */
893 /* Set EDID word address */
894 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
895 /* Set EDID segment pointer */
896 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
897 } else if (status1 & 4) {
898 /* Disable EDID interrupt */
899 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
900 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
901 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
902 }
903
904 return IRQ_HANDLED;
905 }
906
907 /* locking: called with info->lock held, or before register_framebuffer() */
908 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
909 {
910 /*
911 * info is guaranteed to be valid, when we are called, because our
912 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
913 */
914 struct sh_hdmi *hdmi = arg;
915 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
916 struct sh_mobile_lcdc_chan *ch = info->par;
917
918 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
919 pdata->lcd_dev, info->state);
920
921 /* No need to lock */
922 hdmi->info = info;
923
924 /*
925 * hp_state can be set to
926 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
927 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
928 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
929 */
930 switch (hdmi->hp_state) {
931 case HDMI_HOTPLUG_EDID_DONE:
932 /* PS mode d->e. All functions are active */
933 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
934 dev_dbg(hdmi->dev, "HDMI running\n");
935 break;
936 case HDMI_HOTPLUG_DISCONNECTED:
937 info->state = FBINFO_STATE_SUSPENDED;
938 default:
939 hdmi->var = ch->display_var;
940 }
941 }
942
943 /* locking: called with info->lock held */
944 static void sh_hdmi_display_off(void *arg)
945 {
946 struct sh_hdmi *hdmi = arg;
947 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
948
949 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
950 /* PS mode e->a */
951 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
952 }
953
954 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
955 {
956 struct fb_info *info = hdmi->info;
957 struct sh_mobile_lcdc_chan *ch = info->par;
958 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
959 struct fb_videomode mode1, mode2;
960
961 fb_var_to_videomode(&mode1, old_var);
962 fb_var_to_videomode(&mode2, new_var);
963
964 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
965 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
966
967 if (fb_mode_is_equal(&mode1, &mode2)) {
968 /* It can be a different monitor with an equal video-mode */
969 old_var->width = new_var->width;
970 old_var->height = new_var->height;
971 return false;
972 }
973
974 dev_dbg(info->dev, "Switching %u -> %u lines\n",
975 mode1.yres, mode2.yres);
976 *old_var = *new_var;
977
978 return true;
979 }
980
981 /**
982 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
983 * @hdmi: driver context
984 * @pixclock: pixel clock period in picoseconds
985 * return: configured positive rate if successful
986 * 0 if couldn't set the rate, but managed to enable the clock
987 * negative error, if couldn't enable the clock
988 */
989 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
990 {
991 long rate;
992 int ret;
993
994 rate = PICOS2KHZ(pixclock) * 1000;
995 rate = clk_round_rate(hdmi->hdmi_clk, rate);
996 if (rate > 0) {
997 ret = clk_set_rate(hdmi->hdmi_clk, rate);
998 if (ret < 0) {
999 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
1000 rate = 0;
1001 } else {
1002 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
1003 }
1004 } else {
1005 rate = 0;
1006 dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
1007 }
1008
1009 ret = clk_enable(hdmi->hdmi_clk);
1010 if (ret < 0) {
1011 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1012 return ret;
1013 }
1014
1015 return rate;
1016 }
1017
1018 /* Hotplug interrupt occurred, read EDID */
1019 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1020 {
1021 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1022 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1023 struct sh_mobile_lcdc_chan *ch;
1024 int ret;
1025
1026 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1027 pdata->lcd_dev, hdmi->hp_state);
1028
1029 if (!pdata->lcd_dev)
1030 return;
1031
1032 mutex_lock(&hdmi->mutex);
1033
1034 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1035 /* A device has been plugged in */
1036 pm_runtime_get_sync(hdmi->dev);
1037
1038 ret = sh_hdmi_read_edid(hdmi);
1039 if (ret < 0)
1040 goto out;
1041
1042 /* Reconfigure the clock */
1043 clk_disable(hdmi->hdmi_clk);
1044 ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
1045 if (ret < 0)
1046 goto out;
1047
1048 msleep(10);
1049 sh_hdmi_configure(hdmi);
1050 /* Switched to another (d) power-save mode */
1051 msleep(10);
1052
1053 if (!hdmi->info)
1054 goto out;
1055
1056 ch = hdmi->info->par;
1057
1058 acquire_console_sem();
1059
1060 /* HDMI plug in */
1061 if (!sh_hdmi_must_reconfigure(hdmi) &&
1062 hdmi->info->state == FBINFO_STATE_RUNNING) {
1063 /*
1064 * First activation with the default monitor - just turn
1065 * on, if we run a resume here, the logo disappears
1066 */
1067 if (lock_fb_info(hdmi->info)) {
1068 struct fb_info *info = hdmi->info;
1069 info->var.width = hdmi->var.width;
1070 info->var.height = hdmi->var.height;
1071 sh_hdmi_display_on(hdmi, info);
1072 unlock_fb_info(info);
1073 }
1074 } else {
1075 /* New monitor or have to wake up */
1076 fb_set_suspend(hdmi->info, 0);
1077 }
1078
1079 release_console_sem();
1080 } else {
1081 ret = 0;
1082 if (!hdmi->info)
1083 goto out;
1084
1085 hdmi->monspec.modedb_len = 0;
1086 fb_destroy_modedb(hdmi->monspec.modedb);
1087 hdmi->monspec.modedb = NULL;
1088
1089 acquire_console_sem();
1090
1091 /* HDMI disconnect */
1092 fb_set_suspend(hdmi->info, 1);
1093
1094 release_console_sem();
1095 pm_runtime_put(hdmi->dev);
1096 }
1097
1098 out:
1099 if (ret < 0)
1100 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1101 mutex_unlock(&hdmi->mutex);
1102
1103 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1104 }
1105
1106 static int sh_hdmi_notify(struct notifier_block *nb,
1107 unsigned long action, void *data);
1108
1109 static struct notifier_block sh_hdmi_notifier = {
1110 .notifier_call = sh_hdmi_notify,
1111 };
1112
1113 static int sh_hdmi_notify(struct notifier_block *nb,
1114 unsigned long action, void *data)
1115 {
1116 struct fb_event *event = data;
1117 struct fb_info *info = event->info;
1118 struct sh_mobile_lcdc_chan *ch = info->par;
1119 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1120 struct sh_hdmi *hdmi = board_cfg->board_data;
1121
1122 if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1123 return NOTIFY_DONE;
1124
1125 switch(action) {
1126 case FB_EVENT_FB_REGISTERED:
1127 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1128 break;
1129 case FB_EVENT_FB_UNREGISTERED:
1130 /*
1131 * We are called from unregister_framebuffer() with the
1132 * info->lock held. This is bad for us, because we can race with
1133 * the scheduled work, which has to call fb_set_suspend(), which
1134 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1135 * cannot take and hold info->lock for the whole function
1136 * duration. Using an additional lock creates a classical AB-BA
1137 * lock up. Therefore, we have to release the info->lock
1138 * temporarily, synchronise with the work queue and re-acquire
1139 * the info->lock.
1140 */
1141 unlock_fb_info(hdmi->info);
1142 mutex_lock(&hdmi->mutex);
1143 hdmi->info = NULL;
1144 mutex_unlock(&hdmi->mutex);
1145 lock_fb_info(hdmi->info);
1146 return NOTIFY_OK;
1147 }
1148 return NOTIFY_DONE;
1149 }
1150
1151 static int __init sh_hdmi_probe(struct platform_device *pdev)
1152 {
1153 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1154 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1155 struct sh_mobile_lcdc_board_cfg *board_cfg;
1156 int irq = platform_get_irq(pdev, 0), ret;
1157 struct sh_hdmi *hdmi;
1158 long rate;
1159
1160 if (!res || !pdata || irq < 0)
1161 return -ENODEV;
1162
1163 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1164 if (!hdmi) {
1165 dev_err(&pdev->dev, "Cannot allocate device data\n");
1166 return -ENOMEM;
1167 }
1168
1169 mutex_init(&hdmi->mutex);
1170
1171 hdmi->dev = &pdev->dev;
1172
1173 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1174 if (IS_ERR(hdmi->hdmi_clk)) {
1175 ret = PTR_ERR(hdmi->hdmi_clk);
1176 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1177 goto egetclk;
1178 }
1179
1180 /* Some arbitrary relaxed pixclock just to get things started */
1181 rate = sh_hdmi_clk_configure(hdmi, 37037);
1182 if (rate < 0) {
1183 ret = rate;
1184 goto erate;
1185 }
1186
1187 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1188
1189 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1190 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1191 ret = -EBUSY;
1192 goto ereqreg;
1193 }
1194
1195 hdmi->base = ioremap(res->start, resource_size(res));
1196 if (!hdmi->base) {
1197 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1198 ret = -ENOMEM;
1199 goto emap;
1200 }
1201
1202 platform_set_drvdata(pdev, hdmi);
1203
1204 /* Product and revision IDs are 0 in sh-mobile version */
1205 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1206 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1207
1208 /* Set up LCDC callbacks */
1209 board_cfg = &pdata->lcd_chan->board_cfg;
1210 board_cfg->owner = THIS_MODULE;
1211 board_cfg->board_data = hdmi;
1212 board_cfg->display_on = sh_hdmi_display_on;
1213 board_cfg->display_off = sh_hdmi_display_off;
1214
1215 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1216
1217 pm_runtime_enable(&pdev->dev);
1218 pm_runtime_resume(&pdev->dev);
1219
1220 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1221 dev_name(&pdev->dev), hdmi);
1222 if (ret < 0) {
1223 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1224 goto ereqirq;
1225 }
1226
1227 ret = snd_soc_register_codec(&pdev->dev,
1228 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1229 if (ret < 0) {
1230 dev_err(&pdev->dev, "codec registration failed\n");
1231 goto ecodec;
1232 }
1233
1234 return 0;
1235
1236 ecodec:
1237 free_irq(irq, hdmi);
1238 ereqirq:
1239 pm_runtime_disable(&pdev->dev);
1240 iounmap(hdmi->base);
1241 emap:
1242 release_mem_region(res->start, resource_size(res));
1243 ereqreg:
1244 clk_disable(hdmi->hdmi_clk);
1245 erate:
1246 clk_put(hdmi->hdmi_clk);
1247 egetclk:
1248 mutex_destroy(&hdmi->mutex);
1249 kfree(hdmi);
1250
1251 return ret;
1252 }
1253
1254 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1255 {
1256 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1257 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1258 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1259 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1260 int irq = platform_get_irq(pdev, 0);
1261
1262 snd_soc_unregister_codec(&pdev->dev);
1263
1264 board_cfg->display_on = NULL;
1265 board_cfg->display_off = NULL;
1266 board_cfg->board_data = NULL;
1267 board_cfg->owner = NULL;
1268
1269 /* No new work will be scheduled, wait for running ISR */
1270 free_irq(irq, hdmi);
1271 /* Wait for already scheduled work */
1272 cancel_delayed_work_sync(&hdmi->edid_work);
1273 pm_runtime_disable(&pdev->dev);
1274 clk_disable(hdmi->hdmi_clk);
1275 clk_put(hdmi->hdmi_clk);
1276 iounmap(hdmi->base);
1277 release_mem_region(res->start, resource_size(res));
1278 mutex_destroy(&hdmi->mutex);
1279 kfree(hdmi);
1280
1281 return 0;
1282 }
1283
1284 static struct platform_driver sh_hdmi_driver = {
1285 .remove = __exit_p(sh_hdmi_remove),
1286 .driver = {
1287 .name = "sh-mobile-hdmi",
1288 },
1289 };
1290
1291 static int __init sh_hdmi_init(void)
1292 {
1293 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1294 }
1295 module_init(sh_hdmi_init);
1296
1297 static void __exit sh_hdmi_exit(void)
1298 {
1299 platform_driver_unregister(&sh_hdmi_driver);
1300 }
1301 module_exit(sh_hdmi_exit);
1302
1303 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1304 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1305 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree