2 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
4 * Additional SH4-202 support for the clock framework
6 * Copyright (C) 2005 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/clkdev.h>
17 #include <asm/clock.h>
20 #define CPG2_FRQCR3 0xfe0a0018
22 static int frqcr3_divisors
[] = { 1, 2, 3, 4, 6, 8, 16 };
23 static int frqcr3_values
[] = { 0, 1, 2, 3, 4, 5, 6 };
25 static unsigned long emi_clk_recalc(struct clk
*clk
)
27 int idx
= __raw_readl(CPG2_FRQCR3
) & 0x0007;
28 return clk
->parent
->rate
/ frqcr3_divisors
[idx
];
31 static inline int frqcr3_lookup(struct clk
*clk
, unsigned long rate
)
33 int divisor
= clk
->parent
->rate
/ rate
;
36 for (i
= 0; i
< ARRAY_SIZE(frqcr3_divisors
); i
++)
37 if (frqcr3_divisors
[i
] == divisor
)
38 return frqcr3_values
[i
];
44 static struct clk_ops sh4202_emi_clk_ops
= {
45 .recalc
= emi_clk_recalc
,
48 static struct clk sh4202_emi_clk
= {
49 .flags
= CLK_ENABLE_ON_INIT
,
50 .ops
= &sh4202_emi_clk_ops
,
53 static unsigned long femi_clk_recalc(struct clk
*clk
)
55 int idx
= (__raw_readl(CPG2_FRQCR3
) >> 3) & 0x0007;
56 return clk
->parent
->rate
/ frqcr3_divisors
[idx
];
59 static struct clk_ops sh4202_femi_clk_ops
= {
60 .recalc
= femi_clk_recalc
,
63 static struct clk sh4202_femi_clk
= {
64 .flags
= CLK_ENABLE_ON_INIT
,
65 .ops
= &sh4202_femi_clk_ops
,
68 static void shoc_clk_init(struct clk
*clk
)
73 * For some reason, the shoc_clk seems to be set to some really
74 * insane value at boot (values outside of the allowable frequency
75 * range for instance). We deal with this by scaling it back down
76 * to something sensible just in case.
78 * Start scaling from the high end down until we find something
79 * that passes rate verification..
81 for (i
= 0; i
< ARRAY_SIZE(frqcr3_divisors
); i
++) {
82 int divisor
= frqcr3_divisors
[i
];
84 if (clk
->ops
->set_rate(clk
, clk
->parent
->rate
/
89 WARN_ON(i
== ARRAY_SIZE(frqcr3_divisors
)); /* Undefined clock */
92 static unsigned long shoc_clk_recalc(struct clk
*clk
)
94 int idx
= (__raw_readl(CPG2_FRQCR3
) >> 6) & 0x0007;
95 return clk
->parent
->rate
/ frqcr3_divisors
[idx
];
98 static int shoc_clk_verify_rate(struct clk
*clk
, unsigned long rate
)
100 struct clk
*bclk
= clk_get(NULL
, "bus_clk");
101 unsigned long bclk_rate
= clk_get_rate(bclk
);
105 if (rate
> bclk_rate
)
113 static int shoc_clk_set_rate(struct clk
*clk
, unsigned long rate
, int algo_id
)
115 unsigned long frqcr3
;
118 /* Make sure we have something sensible to switch to */
119 if (shoc_clk_verify_rate(clk
, rate
) != 0)
122 tmp
= frqcr3_lookup(clk
, rate
);
124 frqcr3
= __raw_readl(CPG2_FRQCR3
);
125 frqcr3
&= ~(0x0007 << 6);
127 __raw_writel(frqcr3
, CPG2_FRQCR3
);
129 clk
->rate
= clk
->parent
->rate
/ frqcr3_divisors
[tmp
];
134 static struct clk_ops sh4202_shoc_clk_ops
= {
135 .init
= shoc_clk_init
,
136 .recalc
= shoc_clk_recalc
,
137 .set_rate
= shoc_clk_set_rate
,
140 static struct clk sh4202_shoc_clk
= {
141 .flags
= CLK_ENABLE_ON_INIT
,
142 .ops
= &sh4202_shoc_clk_ops
,
145 static struct clk
*sh4202_onchip_clocks
[] = {
151 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
153 static struct clk_lookup lookups
[] = {
155 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk
),
156 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk
),
157 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk
),
160 int __init
arch_clk_init(void)
167 clk
= clk_get(NULL
, "master_clk");
168 for (i
= 0; i
< ARRAY_SIZE(sh4202_onchip_clocks
); i
++) {
169 struct clk
*clkp
= sh4202_onchip_clocks
[i
];
172 ret
|= clk_register(clkp
);
177 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));