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sky2: fix ram buffer allocation settings
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.c
blobf0b1925931914754f839cdaea4fc5bfceac912ef
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
67
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
73
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
78
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static const struct pci_device_id sky2_id_table[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
119 { 0 }
120 };
121
122 MODULE_DEVICE_TABLE(pci, sky2_id_table);
123
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
126 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
127
128 /* This driver supports yukon2 chipset only */
129 static const char *yukon2_name[] = {
130 "XL", /* 0xb3 */
131 "EC Ultra", /* 0xb4 */
132 "UNKNOWN", /* 0xb5 */
133 "EC", /* 0xb6 */
134 "FE", /* 0xb7 */
135 };
136
137 /* Access to external PHY */
138 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
139 {
140 int i;
141
142 gma_write16(hw, port, GM_SMI_DATA, val);
143 gma_write16(hw, port, GM_SMI_CTRL,
144 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
145
146 for (i = 0; i < PHY_RETRIES; i++) {
147 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
148 return 0;
149 udelay(1);
150 }
151
152 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
153 return -ETIMEDOUT;
154 }
155
156 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
157 {
158 int i;
159
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
162
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
165 *val = gma_read16(hw, port, GM_SMI_DATA);
166 return 0;
167 }
168
169 udelay(1);
170 }
171
172 return -ETIMEDOUT;
173 }
174
175 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
176 {
177 u16 v;
178
179 if (__gm_phy_read(hw, port, reg, &v) != 0)
180 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
181 return v;
182 }
183
184 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
185 {
186 u16 power_control;
187 u32 reg1;
188 int vaux;
189 int ret = 0;
190
191 pr_debug("sky2_set_power_state %d\n", state);
192 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
193
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
195 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
196 (power_control & PCI_PM_CAP_PME_D3cold);
197
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
199
200 power_control |= PCI_PM_CTRL_PME_STATUS;
201 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
202
203 switch (state) {
204 case PCI_D0:
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208
209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220
221 /* Turn off phy power saving */
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
223 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
224
225 /* looks like this XL is back asswards .. */
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
227 reg1 |= PCI_Y2_PHY1_COMA;
228 if (hw->ports > 1)
229 reg1 |= PCI_Y2_PHY2_COMA;
230 }
231
232 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
235 reg1 &= P_ASPM_CONTROL_MSK;
236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
238 }
239
240 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
241
242 break;
243
244 case PCI_D3hot:
245 case PCI_D3cold:
246 /* Turn on phy power saving */
247 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
250 else
251 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
252 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
253
254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 else
257 /* enable bits are inverted */
258 sky2_write8(hw, B2_Y2_CLK_GATE,
259 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262
263 /* switch power to VAUX */
264 if (vaux && state != PCI_D3cold)
265 sky2_write8(hw, B0_POWER_CTRL,
266 (PC_VAUX_ENA | PC_VCC_ENA |
267 PC_VAUX_ON | PC_VCC_OFF));
268 break;
269 default:
270 printk(KERN_ERR PFX "Unknown power state %d\n", state);
271 ret = -1;
272 }
273
274 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
275 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
276 return ret;
277 }
278
279 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
280 {
281 u16 reg;
282
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
285 /* disable PHY IRQs */
286 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
287
288 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
289 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
290 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
291 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
292
293 reg = gma_read16(hw, port, GM_RX_CTRL);
294 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
295 gma_write16(hw, port, GM_RX_CTRL, reg);
296 }
297
298 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
299 {
300 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
301 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
302
303 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
304 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305
306 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
307 PHY_M_EC_MAC_S_MSK);
308 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309
310 if (hw->chip_id == CHIP_ID_YUKON_EC)
311 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 else
313 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (sky2_is_copper(hw)) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
330 if (sky2->autoneg == AUTONEG_ENABLE &&
331 hw->chip_id == CHIP_ID_YUKON_XL) {
332 ctrl &= ~PHY_M_PC_DSC_MSK;
333 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
334 }
335 }
336 } else {
337 /* workaround for deviation #4.88 (CRC errors) */
338 /* disable Automatic Crossover */
339
340 ctrl &= ~PHY_M_PC_MDIX_MSK;
341 }
342
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344
345 /* special setup for PHY 88E1112 Fiber */
346 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
347 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
348
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 if (hw->pmd_type == 'P') {
357 /* select page 1 to access Fiber registers */
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
359
360 /* for SFP-module set SIGDET polarity to low */
361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
362 ctrl |= PHY_M_FIB_SIGD_POL;
363 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
364 }
365
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
367 }
368
369 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
370 if (sky2->autoneg == AUTONEG_DISABLE)
371 ctrl &= ~PHY_CT_ANE;
372 else
373 ctrl |= PHY_CT_ANE;
374
375 ctrl |= PHY_CT_RESET;
376 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
377
378 ctrl = 0;
379 ct1000 = 0;
380 adv = PHY_AN_CSMA;
381
382 if (sky2->autoneg == AUTONEG_ENABLE) {
383 if (sky2_is_copper(hw)) {
384 if (sky2->advertising & ADVERTISED_1000baseT_Full)
385 ct1000 |= PHY_M_1000C_AFD;
386 if (sky2->advertising & ADVERTISED_1000baseT_Half)
387 ct1000 |= PHY_M_1000C_AHD;
388 if (sky2->advertising & ADVERTISED_100baseT_Full)
389 adv |= PHY_M_AN_100_FD;
390 if (sky2->advertising & ADVERTISED_100baseT_Half)
391 adv |= PHY_M_AN_100_HD;
392 if (sky2->advertising & ADVERTISED_10baseT_Full)
393 adv |= PHY_M_AN_10_FD;
394 if (sky2->advertising & ADVERTISED_10baseT_Half)
395 adv |= PHY_M_AN_10_HD;
396 } else { /* special defines for FIBER (88E1040S only) */
397 if (sky2->advertising & ADVERTISED_1000baseT_Full)
398 adv |= PHY_M_AN_1000X_AFD;
399 if (sky2->advertising & ADVERTISED_1000baseT_Half)
400 adv |= PHY_M_AN_1000X_AHD;
401 }
402
403 /* Set Flow-control capabilities */
404 if (sky2->tx_pause && sky2->rx_pause)
405 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
406 else if (sky2->rx_pause && !sky2->tx_pause)
407 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
408 else if (!sky2->rx_pause && sky2->tx_pause)
409 adv |= PHY_AN_PAUSE_ASYM; /* local */
410
411 /* Restart Auto-negotiation */
412 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
413 } else {
414 /* forced speed/duplex settings */
415 ct1000 = PHY_M_1000C_MSE;
416
417 if (sky2->duplex == DUPLEX_FULL)
418 ctrl |= PHY_CT_DUP_MD;
419
420 switch (sky2->speed) {
421 case SPEED_1000:
422 ctrl |= PHY_CT_SP1000;
423 break;
424 case SPEED_100:
425 ctrl |= PHY_CT_SP100;
426 break;
427 }
428
429 ctrl |= PHY_CT_RESET;
430 }
431
432 if (hw->chip_id != CHIP_ID_YUKON_FE)
433 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
434
435 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
436 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
437
438 /* Setup Phy LED's */
439 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
440 ledover = 0;
441
442 switch (hw->chip_id) {
443 case CHIP_ID_YUKON_FE:
444 /* on 88E3082 these bits are at 11..9 (shifted left) */
445 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
446
447 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
448
449 /* delete ACT LED control bits */
450 ctrl &= ~PHY_M_FELP_LED1_MSK;
451 /* change ACT LED control to blink mode */
452 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
453 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
454 break;
455
456 case CHIP_ID_YUKON_XL:
457 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
458
459 /* select page 3 to access LED control register */
460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
461
462 /* set LED Function Control register */
463 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
464 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
465 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
466 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
467
468 /* set Polarity Control register */
469 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
470 (PHY_M_POLC_LS1_P_MIX(4) |
471 PHY_M_POLC_IS0_P_MIX(4) |
472 PHY_M_POLC_LOS_CTRL(2) |
473 PHY_M_POLC_INIT_CTRL(2) |
474 PHY_M_POLC_STA1_CTRL(2) |
475 PHY_M_POLC_STA0_CTRL(2)));
476
477 /* restore page register */
478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
479 break;
480
481 default:
482 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
483 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
484 /* turn off the Rx LED (LED_RX) */
485 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
486 }
487
488 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
489 /* apply fixes in PHY AFE */
490 gm_phy_write(hw, port, 22, 255);
491 /* increase differential signal amplitude in 10BASE-T */
492 gm_phy_write(hw, port, 24, 0xaa99);
493 gm_phy_write(hw, port, 23, 0x2011);
494
495 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
496 gm_phy_write(hw, port, 24, 0xa204);
497 gm_phy_write(hw, port, 23, 0x2002);
498
499 /* set page register to 0 */
500 gm_phy_write(hw, port, 22, 0);
501 } else {
502 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
503
504 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
505 /* turn on 100 Mbps LED (LED_LINK100) */
506 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
507 }
508
509 if (ledover)
510 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
511
512 }
513 /* Enable phy interrupt on auto-negotiation complete (or link up) */
514 if (sky2->autoneg == AUTONEG_ENABLE)
515 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
516 else
517 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
518 }
519
520 /* Force a renegotiation */
521 static void sky2_phy_reinit(struct sky2_port *sky2)
522 {
523 down(&sky2->phy_sema);
524 sky2_phy_init(sky2->hw, sky2->port);
525 up(&sky2->phy_sema);
526 }
527
528 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
529 {
530 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
531 u16 reg;
532 int i;
533 const u8 *addr = hw->dev[port]->dev_addr;
534
535 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
536 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
537
538 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
539
540 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
541 /* WA DEV_472 -- looks like crossed wires on port 2 */
542 /* clear GMAC 1 Control reset */
543 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
544 do {
545 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
546 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
547 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
548 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
549 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
550 }
551
552 if (sky2->autoneg == AUTONEG_DISABLE) {
553 reg = gma_read16(hw, port, GM_GP_CTRL);
554 reg |= GM_GPCR_AU_ALL_DIS;
555 gma_write16(hw, port, GM_GP_CTRL, reg);
556 gma_read16(hw, port, GM_GP_CTRL);
557
558 switch (sky2->speed) {
559 case SPEED_1000:
560 reg &= ~GM_GPCR_SPEED_100;
561 reg |= GM_GPCR_SPEED_1000;
562 break;
563 case SPEED_100:
564 reg &= ~GM_GPCR_SPEED_1000;
565 reg |= GM_GPCR_SPEED_100;
566 break;
567 case SPEED_10:
568 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
569 break;
570 }
571
572 if (sky2->duplex == DUPLEX_FULL)
573 reg |= GM_GPCR_DUP_FULL;
574 } else
575 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
576
577 if (!sky2->tx_pause && !sky2->rx_pause) {
578 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
579 reg |=
580 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
581 } else if (sky2->tx_pause && !sky2->rx_pause) {
582 /* disable Rx flow-control */
583 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
584 }
585
586 gma_write16(hw, port, GM_GP_CTRL, reg);
587
588 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
589
590 down(&sky2->phy_sema);
591 sky2_phy_init(hw, port);
592 up(&sky2->phy_sema);
593
594 /* MIB clear */
595 reg = gma_read16(hw, port, GM_PHY_ADDR);
596 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
597
598 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
599 gma_read16(hw, port, i);
600 gma_write16(hw, port, GM_PHY_ADDR, reg);
601
602 /* transmit control */
603 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
604
605 /* receive control reg: unicast + multicast + no FCS */
606 gma_write16(hw, port, GM_RX_CTRL,
607 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
608
609 /* transmit flow control */
610 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
611
612 /* transmit parameter */
613 gma_write16(hw, port, GM_TX_PARAM,
614 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
615 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
616 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
617 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
618
619 /* serial mode register */
620 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
621 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
622
623 if (hw->dev[port]->mtu > ETH_DATA_LEN)
624 reg |= GM_SMOD_JUMBO_ENA;
625
626 gma_write16(hw, port, GM_SERIAL_MODE, reg);
627
628 /* virtual address for data */
629 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
630
631 /* physical address: used for pause frames */
632 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
633
634 /* ignore counter overflows */
635 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
636 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
637 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
638
639 /* Configure Rx MAC FIFO */
640 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
641 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
642 GMF_OPER_ON | GMF_RX_F_FL_ON);
643
644 /* Flush Rx MAC FIFO on any flow control or error */
645 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
646
647 /* Set threshold to 0xa (64 bytes)
648 * ASF disabled so no need to do WA dev #4.30
649 */
650 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
651
652 /* Configure Tx MAC FIFO */
653 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
654 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
655
656 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
657 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
658 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
659 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
660 /* set Tx GMAC FIFO Almost Empty Threshold */
661 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
662 /* Disable Store & Forward mode for TX */
663 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
664 }
665 }
666
667 }
668
669 /* Assign Ram Buffer allocation.
670 * start and end are in units of 4k bytes
671 * ram registers are in units of 64bit words
672 */
673 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
674 {
675 u32 end;
676
677 start *= 1024/8;
678 space *= 1024/8;
679 end = start + space - 1;
680
681 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
682 sky2_write32(hw, RB_ADDR(q, RB_START), start);
683 sky2_write32(hw, RB_ADDR(q, RB_END), end);
684 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
685 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
686
687 if (q == Q_R1 || q == Q_R2) {
688 u32 tp = space - space/4;
689
690 /* On receive queue's set the thresholds
691 * give receiver priority when > 3/4 full
692 * send pause when down to 2K
693 */
694 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
695 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
696
697 tp = space - 2048/8;
698 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
699 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
700 } else {
701 /* Enable store & forward on Tx queue's because
702 * Tx FIFO is only 1K on Yukon
703 */
704 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
705 }
706
707 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
708 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
709 }
710
711 /* Setup Bus Memory Interface */
712 static void sky2_qset(struct sky2_hw *hw, u16 q)
713 {
714 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
715 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
716 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
717 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
718 }
719
720 /* Setup prefetch unit registers. This is the interface between
721 * hardware and driver list elements
722 */
723 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
724 u64 addr, u32 last)
725 {
726 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
727 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
728 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
729 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
730 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
731 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
732
733 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
734 }
735
736 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
737 {
738 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
739
740 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
741 return le;
742 }
743
744 /*
745 * This is a workaround code taken from SysKonnect sk98lin driver
746 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
747 */
748 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
749 u16 idx, u16 *last, u16 size)
750 {
751 wmb();
752 if (is_ec_a1(hw) && idx < *last) {
753 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
754
755 if (hwget == 0) {
756 /* Start prefetching again */
757 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
758 goto setnew;
759 }
760
761 if (hwget == size - 1) {
762 /* set watermark to one list element */
763 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
764
765 /* set put index to first list element */
766 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
767 } else /* have hardware go to end of list */
768 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
769 size - 1);
770 } else {
771 setnew:
772 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
773 }
774 *last = idx;
775 mmiowb();
776 }
777
778
779 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
780 {
781 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
782 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
783 return le;
784 }
785
786 /* Return high part of DMA address (could be 32 or 64 bit) */
787 static inline u32 high32(dma_addr_t a)
788 {
789 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
790 }
791
792 /* Build description to hardware about buffer */
793 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
794 {
795 struct sky2_rx_le *le;
796 u32 hi = high32(map);
797 u16 len = sky2->rx_bufsize;
798
799 if (sky2->rx_addr64 != hi) {
800 le = sky2_next_rx(sky2);
801 le->addr = cpu_to_le32(hi);
802 le->ctrl = 0;
803 le->opcode = OP_ADDR64 | HW_OWNER;
804 sky2->rx_addr64 = high32(map + len);
805 }
806
807 le = sky2_next_rx(sky2);
808 le->addr = cpu_to_le32((u32) map);
809 le->length = cpu_to_le16(len);
810 le->ctrl = 0;
811 le->opcode = OP_PACKET | HW_OWNER;
812 }
813
814
815 /* Tell chip where to start receive checksum.
816 * Actually has two checksums, but set both same to avoid possible byte
817 * order problems.
818 */
819 static void rx_set_checksum(struct sky2_port *sky2)
820 {
821 struct sky2_rx_le *le;
822
823 le = sky2_next_rx(sky2);
824 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
825 le->ctrl = 0;
826 le->opcode = OP_TCPSTART | HW_OWNER;
827
828 sky2_write32(sky2->hw,
829 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
830 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
831
832 }
833
834 /*
835 * The RX Stop command will not work for Yukon-2 if the BMU does not
836 * reach the end of packet and since we can't make sure that we have
837 * incoming data, we must reset the BMU while it is not doing a DMA
838 * transfer. Since it is possible that the RX path is still active,
839 * the RX RAM buffer will be stopped first, so any possible incoming
840 * data will not trigger a DMA. After the RAM buffer is stopped, the
841 * BMU is polled until any DMA in progress is ended and only then it
842 * will be reset.
843 */
844 static void sky2_rx_stop(struct sky2_port *sky2)
845 {
846 struct sky2_hw *hw = sky2->hw;
847 unsigned rxq = rxqaddr[sky2->port];
848 int i;
849
850 /* disable the RAM Buffer receive queue */
851 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
852
853 for (i = 0; i < 0xffff; i++)
854 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
855 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
856 goto stopped;
857
858 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
859 sky2->netdev->name);
860 stopped:
861 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
862
863 /* reset the Rx prefetch unit */
864 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
865 }
866
867 /* Clean out receive buffer area, assumes receiver hardware stopped */
868 static void sky2_rx_clean(struct sky2_port *sky2)
869 {
870 unsigned i;
871
872 memset(sky2->rx_le, 0, RX_LE_BYTES);
873 for (i = 0; i < sky2->rx_pending; i++) {
874 struct ring_info *re = sky2->rx_ring + i;
875
876 if (re->skb) {
877 pci_unmap_single(sky2->hw->pdev,
878 re->mapaddr, sky2->rx_bufsize,
879 PCI_DMA_FROMDEVICE);
880 kfree_skb(re->skb);
881 re->skb = NULL;
882 }
883 }
884 }
885
886 /* Basic MII support */
887 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
888 {
889 struct mii_ioctl_data *data = if_mii(ifr);
890 struct sky2_port *sky2 = netdev_priv(dev);
891 struct sky2_hw *hw = sky2->hw;
892 int err = -EOPNOTSUPP;
893
894 if (!netif_running(dev))
895 return -ENODEV; /* Phy still in reset */
896
897 switch(cmd) {
898 case SIOCGMIIPHY:
899 data->phy_id = PHY_ADDR_MARV;
900
901 /* fallthru */
902 case SIOCGMIIREG: {
903 u16 val = 0;
904
905 down(&sky2->phy_sema);
906 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
907 up(&sky2->phy_sema);
908
909 data->val_out = val;
910 break;
911 }
912
913 case SIOCSMIIREG:
914 if (!capable(CAP_NET_ADMIN))
915 return -EPERM;
916
917 down(&sky2->phy_sema);
918 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
919 data->val_in);
920 up(&sky2->phy_sema);
921 break;
922 }
923 return err;
924 }
925
926 #ifdef SKY2_VLAN_TAG_USED
927 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
928 {
929 struct sky2_port *sky2 = netdev_priv(dev);
930 struct sky2_hw *hw = sky2->hw;
931 u16 port = sky2->port;
932
933 spin_lock_bh(&sky2->tx_lock);
934
935 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
936 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
937 sky2->vlgrp = grp;
938
939 spin_unlock_bh(&sky2->tx_lock);
940 }
941
942 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
943 {
944 struct sky2_port *sky2 = netdev_priv(dev);
945 struct sky2_hw *hw = sky2->hw;
946 u16 port = sky2->port;
947
948 spin_lock_bh(&sky2->tx_lock);
949
950 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
951 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
952 if (sky2->vlgrp)
953 sky2->vlgrp->vlan_devices[vid] = NULL;
954
955 spin_unlock_bh(&sky2->tx_lock);
956 }
957 #endif
958
959 /*
960 * It appears the hardware has a bug in the FIFO logic that
961 * cause it to hang if the FIFO gets overrun and the receive buffer
962 * is not aligned. Also dev_alloc_skb() won't align properly if slab
963 * debugging is enabled.
964 */
965 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
966 {
967 struct sk_buff *skb;
968
969 skb = __dev_alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
970 if (likely(skb)) {
971 unsigned long p = (unsigned long) skb->data;
972 skb_reserve(skb,
973 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
974 }
975
976 return skb;
977 }
978
979 /*
980 * Allocate and setup receiver buffer pool.
981 * In case of 64 bit dma, there are 2X as many list elements
982 * available as ring entries
983 * and need to reserve one list element so we don't wrap around.
984 */
985 static int sky2_rx_start(struct sky2_port *sky2)
986 {
987 struct sky2_hw *hw = sky2->hw;
988 unsigned rxq = rxqaddr[sky2->port];
989 int i;
990
991 sky2->rx_put = sky2->rx_next = 0;
992 sky2_qset(hw, rxq);
993
994 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
995 /* MAC Rx RAM Read is controlled by hardware */
996 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
997 }
998
999 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1000
1001 rx_set_checksum(sky2);
1002 for (i = 0; i < sky2->rx_pending; i++) {
1003 struct ring_info *re = sky2->rx_ring + i;
1004
1005 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
1006 if (!re->skb)
1007 goto nomem;
1008
1009 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1010 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1011 sky2_rx_add(sky2, re->mapaddr);
1012 }
1013
1014 /* Truncate oversize frames */
1015 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1016 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1017
1018 /* Tell chip about available buffers */
1019 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1020 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
1021 return 0;
1022 nomem:
1023 sky2_rx_clean(sky2);
1024 return -ENOMEM;
1025 }
1026
1027 /* Bring up network interface. */
1028 static int sky2_up(struct net_device *dev)
1029 {
1030 struct sky2_port *sky2 = netdev_priv(dev);
1031 struct sky2_hw *hw = sky2->hw;
1032 unsigned port = sky2->port;
1033 u32 ramsize, rxspace;
1034 int cap, err = -ENOMEM;
1035 struct net_device *otherdev = hw->dev[sky2->port^1];
1036
1037 /*
1038 * On dual port PCI-X card, there is an problem where status
1039 * can be received out of order due to split transactions
1040 */
1041 if (otherdev && netif_running(otherdev) &&
1042 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1043 struct sky2_port *osky2 = netdev_priv(otherdev);
1044 u16 cmd;
1045
1046 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1047 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1048 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1049
1050 sky2->rx_csum = 0;
1051 osky2->rx_csum = 0;
1052 }
1053
1054 if (netif_msg_ifup(sky2))
1055 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1056
1057 /* must be power of 2 */
1058 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1059 TX_RING_SIZE *
1060 sizeof(struct sky2_tx_le),
1061 &sky2->tx_le_map);
1062 if (!sky2->tx_le)
1063 goto err_out;
1064
1065 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1066 GFP_KERNEL);
1067 if (!sky2->tx_ring)
1068 goto err_out;
1069 sky2->tx_prod = sky2->tx_cons = 0;
1070
1071 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1072 &sky2->rx_le_map);
1073 if (!sky2->rx_le)
1074 goto err_out;
1075 memset(sky2->rx_le, 0, RX_LE_BYTES);
1076
1077 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1078 GFP_KERNEL);
1079 if (!sky2->rx_ring)
1080 goto err_out;
1081
1082 sky2_mac_init(hw, port);
1083
1084 /* Determine available ram buffer space (in 4K blocks). */
1085 ramsize = sky2_read8(hw, B2_E_0) * 4;
1086 if (ramsize != 0) {
1087 if (ramsize < 16)
1088 rxspace = ramsize / 2;
1089 else
1090 rxspace = 8 + (2*(ramsize - 16))/3;
1091
1092 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1093 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1094
1095 /* Make sure SyncQ is disabled */
1096 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1097 RB_RST_SET);
1098 }
1099
1100 sky2_qset(hw, txqaddr[port]);
1101
1102 /* Set almost empty threshold */
1103 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1104 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1105
1106 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1107 TX_RING_SIZE - 1);
1108
1109 err = sky2_rx_start(sky2);
1110 if (err)
1111 goto err_out;
1112
1113 /* Enable interrupts from phy/mac for port */
1114 spin_lock_irq(&hw->hw_lock);
1115 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1116 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1117 spin_unlock_irq(&hw->hw_lock);
1118 return 0;
1119
1120 err_out:
1121 if (sky2->rx_le) {
1122 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1123 sky2->rx_le, sky2->rx_le_map);
1124 sky2->rx_le = NULL;
1125 }
1126 if (sky2->tx_le) {
1127 pci_free_consistent(hw->pdev,
1128 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1129 sky2->tx_le, sky2->tx_le_map);
1130 sky2->tx_le = NULL;
1131 }
1132 kfree(sky2->tx_ring);
1133 kfree(sky2->rx_ring);
1134
1135 sky2->tx_ring = NULL;
1136 sky2->rx_ring = NULL;
1137 return err;
1138 }
1139
1140 /* Modular subtraction in ring */
1141 static inline int tx_dist(unsigned tail, unsigned head)
1142 {
1143 return (head - tail) % TX_RING_SIZE;
1144 }
1145
1146 /* Number of list elements available for next tx */
1147 static inline int tx_avail(const struct sky2_port *sky2)
1148 {
1149 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1150 }
1151
1152 /* Estimate of number of transmit list elements required */
1153 static unsigned tx_le_req(const struct sk_buff *skb)
1154 {
1155 unsigned count;
1156
1157 count = sizeof(dma_addr_t) / sizeof(u32);
1158 count += skb_shinfo(skb)->nr_frags * count;
1159
1160 if (skb_shinfo(skb)->tso_size)
1161 ++count;
1162
1163 if (skb->ip_summed == CHECKSUM_HW)
1164 ++count;
1165
1166 return count;
1167 }
1168
1169 /*
1170 * Put one packet in ring for transmit.
1171 * A single packet can generate multiple list elements, and
1172 * the number of ring elements will probably be less than the number
1173 * of list elements used.
1174 *
1175 * No BH disabling for tx_lock here (like tg3)
1176 */
1177 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1178 {
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 struct sky2_tx_le *le = NULL;
1182 struct tx_ring_info *re;
1183 unsigned i, len;
1184 int avail;
1185 dma_addr_t mapping;
1186 u32 addr64;
1187 u16 mss;
1188 u8 ctrl;
1189
1190 /* No BH disabling for tx_lock here. We are running in BH disabled
1191 * context and TX reclaim runs via poll inside of a software
1192 * interrupt, and no related locks in IRQ processing.
1193 */
1194 if (!spin_trylock(&sky2->tx_lock))
1195 return NETDEV_TX_LOCKED;
1196
1197 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1198 /* There is a known but harmless race with lockless tx
1199 * and netif_stop_queue.
1200 */
1201 if (!netif_queue_stopped(dev)) {
1202 netif_stop_queue(dev);
1203 if (net_ratelimit())
1204 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1205 dev->name);
1206 }
1207 spin_unlock(&sky2->tx_lock);
1208
1209 return NETDEV_TX_BUSY;
1210 }
1211
1212 if (unlikely(netif_msg_tx_queued(sky2)))
1213 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1214 dev->name, sky2->tx_prod, skb->len);
1215
1216 len = skb_headlen(skb);
1217 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1218 addr64 = high32(mapping);
1219
1220 re = sky2->tx_ring + sky2->tx_prod;
1221
1222 /* Send high bits if changed or crosses boundary */
1223 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1224 le = get_tx_le(sky2);
1225 le->tx.addr = cpu_to_le32(addr64);
1226 le->ctrl = 0;
1227 le->opcode = OP_ADDR64 | HW_OWNER;
1228 sky2->tx_addr64 = high32(mapping + len);
1229 }
1230
1231 /* Check for TCP Segmentation Offload */
1232 mss = skb_shinfo(skb)->tso_size;
1233 if (mss != 0) {
1234 /* just drop the packet if non-linear expansion fails */
1235 if (skb_header_cloned(skb) &&
1236 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1237 dev_kfree_skb_any(skb);
1238 goto out_unlock;
1239 }
1240
1241 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1242 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1243 mss += ETH_HLEN;
1244 }
1245
1246 if (mss != sky2->tx_last_mss) {
1247 le = get_tx_le(sky2);
1248 le->tx.tso.size = cpu_to_le16(mss);
1249 le->tx.tso.rsvd = 0;
1250 le->opcode = OP_LRGLEN | HW_OWNER;
1251 le->ctrl = 0;
1252 sky2->tx_last_mss = mss;
1253 }
1254
1255 ctrl = 0;
1256 #ifdef SKY2_VLAN_TAG_USED
1257 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1258 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1259 if (!le) {
1260 le = get_tx_le(sky2);
1261 le->tx.addr = 0;
1262 le->opcode = OP_VLAN|HW_OWNER;
1263 le->ctrl = 0;
1264 } else
1265 le->opcode |= OP_VLAN;
1266 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1267 ctrl |= INS_VLAN;
1268 }
1269 #endif
1270
1271 /* Handle TCP checksum offload */
1272 if (skb->ip_summed == CHECKSUM_HW) {
1273 u16 hdr = skb->h.raw - skb->data;
1274 u16 offset = hdr + skb->csum;
1275
1276 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1277 if (skb->nh.iph->protocol == IPPROTO_UDP)
1278 ctrl |= UDPTCP;
1279
1280 le = get_tx_le(sky2);
1281 le->tx.csum.start = cpu_to_le16(hdr);
1282 le->tx.csum.offset = cpu_to_le16(offset);
1283 le->length = 0; /* initial checksum value */
1284 le->ctrl = 1; /* one packet */
1285 le->opcode = OP_TCPLISW | HW_OWNER;
1286 }
1287
1288 le = get_tx_le(sky2);
1289 le->tx.addr = cpu_to_le32((u32) mapping);
1290 le->length = cpu_to_le16(len);
1291 le->ctrl = ctrl;
1292 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1293
1294 /* Record the transmit mapping info */
1295 re->skb = skb;
1296 pci_unmap_addr_set(re, mapaddr, mapping);
1297
1298 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1299 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1300 struct tx_ring_info *fre;
1301
1302 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1303 frag->size, PCI_DMA_TODEVICE);
1304 addr64 = high32(mapping);
1305 if (addr64 != sky2->tx_addr64) {
1306 le = get_tx_le(sky2);
1307 le->tx.addr = cpu_to_le32(addr64);
1308 le->ctrl = 0;
1309 le->opcode = OP_ADDR64 | HW_OWNER;
1310 sky2->tx_addr64 = addr64;
1311 }
1312
1313 le = get_tx_le(sky2);
1314 le->tx.addr = cpu_to_le32((u32) mapping);
1315 le->length = cpu_to_le16(frag->size);
1316 le->ctrl = ctrl;
1317 le->opcode = OP_BUFFER | HW_OWNER;
1318
1319 fre = sky2->tx_ring
1320 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1321 pci_unmap_addr_set(fre, mapaddr, mapping);
1322 }
1323
1324 re->idx = sky2->tx_prod;
1325 le->ctrl |= EOP;
1326
1327 avail = tx_avail(sky2);
1328 if (mss != 0 || avail < TX_MIN_PENDING) {
1329 le->ctrl |= FRC_STAT;
1330 if (avail <= MAX_SKB_TX_LE)
1331 netif_stop_queue(dev);
1332 }
1333
1334 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1335 &sky2->tx_last_put, TX_RING_SIZE);
1336
1337 out_unlock:
1338 spin_unlock(&sky2->tx_lock);
1339
1340 dev->trans_start = jiffies;
1341 return NETDEV_TX_OK;
1342 }
1343
1344 /*
1345 * Free ring elements from starting at tx_cons until "done"
1346 *
1347 * NB: the hardware will tell us about partial completion of multi-part
1348 * buffers; these are deferred until completion.
1349 */
1350 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1351 {
1352 struct net_device *dev = sky2->netdev;
1353 struct pci_dev *pdev = sky2->hw->pdev;
1354 u16 nxt, put;
1355 unsigned i;
1356
1357 BUG_ON(done >= TX_RING_SIZE);
1358
1359 if (unlikely(netif_msg_tx_done(sky2)))
1360 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1361 dev->name, done);
1362
1363 for (put = sky2->tx_cons; put != done; put = nxt) {
1364 struct tx_ring_info *re = sky2->tx_ring + put;
1365 struct sk_buff *skb = re->skb;
1366
1367 nxt = re->idx;
1368 BUG_ON(nxt >= TX_RING_SIZE);
1369 prefetch(sky2->tx_ring + nxt);
1370
1371 /* Check for partial status */
1372 if (tx_dist(put, done) < tx_dist(put, nxt))
1373 break;
1374
1375 skb = re->skb;
1376 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1377 skb_headlen(skb), PCI_DMA_TODEVICE);
1378
1379 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1380 struct tx_ring_info *fre;
1381 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1382 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1383 skb_shinfo(skb)->frags[i].size,
1384 PCI_DMA_TODEVICE);
1385 }
1386
1387 dev_kfree_skb_any(skb);
1388 }
1389
1390 sky2->tx_cons = put;
1391 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1392 netif_wake_queue(dev);
1393 }
1394
1395 /* Cleanup all untransmitted buffers, assume transmitter not running */
1396 static void sky2_tx_clean(struct sky2_port *sky2)
1397 {
1398 spin_lock_bh(&sky2->tx_lock);
1399 sky2_tx_complete(sky2, sky2->tx_prod);
1400 spin_unlock_bh(&sky2->tx_lock);
1401 }
1402
1403 /* Network shutdown */
1404 static int sky2_down(struct net_device *dev)
1405 {
1406 struct sky2_port *sky2 = netdev_priv(dev);
1407 struct sky2_hw *hw = sky2->hw;
1408 unsigned port = sky2->port;
1409 u16 ctrl;
1410
1411 /* Never really got started! */
1412 if (!sky2->tx_le)
1413 return 0;
1414
1415 if (netif_msg_ifdown(sky2))
1416 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1417
1418 /* Stop more packets from being queued */
1419 netif_stop_queue(dev);
1420
1421 /*
1422 * Both ports share the NAPI poll on port 0, so if necessary undo the
1423 * the disable that is done in dev_close.
1424 */
1425 if (sky2->port == 0 && hw->ports > 1)
1426 netif_poll_enable(dev);
1427
1428 /* Disable port IRQ */
1429 spin_lock_irq(&hw->hw_lock);
1430 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1431 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1432 spin_unlock_irq(&hw->hw_lock);
1433
1434 flush_scheduled_work();
1435
1436 sky2_phy_reset(hw, port);
1437
1438 /* Stop transmitter */
1439 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1440 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1441
1442 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1443 RB_RST_SET | RB_DIS_OP_MD);
1444
1445 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1446 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1447 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1448
1449 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1450
1451 /* Workaround shared GMAC reset */
1452 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1453 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1454 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1455
1456 /* Disable Force Sync bit and Enable Alloc bit */
1457 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1458 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1459
1460 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1461 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1462 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1463
1464 /* Reset the PCI FIFO of the async Tx queue */
1465 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1466 BMU_RST_SET | BMU_FIFO_RST);
1467
1468 /* Reset the Tx prefetch units */
1469 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1470 PREF_UNIT_RST_SET);
1471
1472 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1473
1474 sky2_rx_stop(sky2);
1475
1476 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1477 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1478
1479 /* turn off LED's */
1480 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1481
1482 synchronize_irq(hw->pdev->irq);
1483
1484 sky2_tx_clean(sky2);
1485 sky2_rx_clean(sky2);
1486
1487 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1488 sky2->rx_le, sky2->rx_le_map);
1489 kfree(sky2->rx_ring);
1490
1491 pci_free_consistent(hw->pdev,
1492 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1493 sky2->tx_le, sky2->tx_le_map);
1494 kfree(sky2->tx_ring);
1495
1496 sky2->tx_le = NULL;
1497 sky2->rx_le = NULL;
1498
1499 sky2->rx_ring = NULL;
1500 sky2->tx_ring = NULL;
1501
1502 return 0;
1503 }
1504
1505 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1506 {
1507 if (!sky2_is_copper(hw))
1508 return SPEED_1000;
1509
1510 if (hw->chip_id == CHIP_ID_YUKON_FE)
1511 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1512
1513 switch (aux & PHY_M_PS_SPEED_MSK) {
1514 case PHY_M_PS_SPEED_1000:
1515 return SPEED_1000;
1516 case PHY_M_PS_SPEED_100:
1517 return SPEED_100;
1518 default:
1519 return SPEED_10;
1520 }
1521 }
1522
1523 static void sky2_link_up(struct sky2_port *sky2)
1524 {
1525 struct sky2_hw *hw = sky2->hw;
1526 unsigned port = sky2->port;
1527 u16 reg;
1528
1529 /* Enable Transmit FIFO Underrun */
1530 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1531
1532 reg = gma_read16(hw, port, GM_GP_CTRL);
1533 if (sky2->autoneg == AUTONEG_DISABLE) {
1534 reg |= GM_GPCR_AU_ALL_DIS;
1535
1536 /* Is write/read necessary? Copied from sky2_mac_init */
1537 gma_write16(hw, port, GM_GP_CTRL, reg);
1538 gma_read16(hw, port, GM_GP_CTRL);
1539
1540 switch (sky2->speed) {
1541 case SPEED_1000:
1542 reg &= ~GM_GPCR_SPEED_100;
1543 reg |= GM_GPCR_SPEED_1000;
1544 break;
1545 case SPEED_100:
1546 reg &= ~GM_GPCR_SPEED_1000;
1547 reg |= GM_GPCR_SPEED_100;
1548 break;
1549 case SPEED_10:
1550 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1551 break;
1552 }
1553 } else
1554 reg &= ~GM_GPCR_AU_ALL_DIS;
1555
1556 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1557 reg |= GM_GPCR_DUP_FULL;
1558
1559 /* enable Rx/Tx */
1560 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1561 gma_write16(hw, port, GM_GP_CTRL, reg);
1562 gma_read16(hw, port, GM_GP_CTRL);
1563
1564 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1565
1566 netif_carrier_on(sky2->netdev);
1567 netif_wake_queue(sky2->netdev);
1568
1569 /* Turn on link LED */
1570 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1571 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1572
1573 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1574 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1575
1576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1577 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1578 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1579 SPEED_10 ? 7 : 0) |
1580 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1581 SPEED_100 ? 7 : 0) |
1582 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1583 SPEED_1000 ? 7 : 0));
1584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1585 }
1586
1587 if (netif_msg_link(sky2))
1588 printk(KERN_INFO PFX
1589 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1590 sky2->netdev->name, sky2->speed,
1591 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1592 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1593 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1594 }
1595
1596 static void sky2_link_down(struct sky2_port *sky2)
1597 {
1598 struct sky2_hw *hw = sky2->hw;
1599 unsigned port = sky2->port;
1600 u16 reg;
1601
1602 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1603
1604 reg = gma_read16(hw, port, GM_GP_CTRL);
1605 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1606 gma_write16(hw, port, GM_GP_CTRL, reg);
1607 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1608
1609 if (sky2->rx_pause && !sky2->tx_pause) {
1610 /* restore Asymmetric Pause bit */
1611 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1612 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1613 | PHY_M_AN_ASP);
1614 }
1615
1616 netif_carrier_off(sky2->netdev);
1617 netif_stop_queue(sky2->netdev);
1618
1619 /* Turn on link LED */
1620 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1621
1622 if (netif_msg_link(sky2))
1623 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1624 sky2_phy_init(hw, port);
1625 }
1626
1627 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1628 {
1629 struct sky2_hw *hw = sky2->hw;
1630 unsigned port = sky2->port;
1631 u16 lpa;
1632
1633 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1634
1635 if (lpa & PHY_M_AN_RF) {
1636 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1637 return -1;
1638 }
1639
1640 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1641 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1642 printk(KERN_ERR PFX "%s: master/slave fault",
1643 sky2->netdev->name);
1644 return -1;
1645 }
1646
1647 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1648 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1649 sky2->netdev->name);
1650 return -1;
1651 }
1652
1653 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1654
1655 sky2->speed = sky2_phy_speed(hw, aux);
1656
1657 /* Pause bits are offset (9..8) */
1658 if (hw->chip_id == CHIP_ID_YUKON_XL)
1659 aux >>= 6;
1660
1661 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1662 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1663
1664 if ((sky2->tx_pause || sky2->rx_pause)
1665 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1666 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1667 else
1668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1669
1670 return 0;
1671 }
1672
1673 /*
1674 * Interrupt from PHY are handled outside of interrupt context
1675 * because accessing phy registers requires spin wait which might
1676 * cause excess interrupt latency.
1677 */
1678 static void sky2_phy_task(void *arg)
1679 {
1680 struct sky2_port *sky2 = arg;
1681 struct sky2_hw *hw = sky2->hw;
1682 u16 istatus, phystat;
1683
1684 down(&sky2->phy_sema);
1685 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1686 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1687
1688 if (netif_msg_intr(sky2))
1689 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1690 sky2->netdev->name, istatus, phystat);
1691
1692 if (istatus & PHY_M_IS_AN_COMPL) {
1693 if (sky2_autoneg_done(sky2, phystat) == 0)
1694 sky2_link_up(sky2);
1695 goto out;
1696 }
1697
1698 if (istatus & PHY_M_IS_LSP_CHANGE)
1699 sky2->speed = sky2_phy_speed(hw, phystat);
1700
1701 if (istatus & PHY_M_IS_DUP_CHANGE)
1702 sky2->duplex =
1703 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1704
1705 if (istatus & PHY_M_IS_LST_CHANGE) {
1706 if (phystat & PHY_M_PS_LINK_UP)
1707 sky2_link_up(sky2);
1708 else
1709 sky2_link_down(sky2);
1710 }
1711 out:
1712 up(&sky2->phy_sema);
1713
1714 spin_lock_irq(&hw->hw_lock);
1715 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1716 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1717 spin_unlock_irq(&hw->hw_lock);
1718 }
1719
1720
1721 /* Transmit timeout is only called if we are running, carries is up
1722 * and tx queue is full (stopped).
1723 */
1724 static void sky2_tx_timeout(struct net_device *dev)
1725 {
1726 struct sky2_port *sky2 = netdev_priv(dev);
1727 struct sky2_hw *hw = sky2->hw;
1728 unsigned txq = txqaddr[sky2->port];
1729 u16 ridx;
1730
1731 /* Maybe we just missed an status interrupt */
1732 spin_lock(&sky2->tx_lock);
1733 ridx = sky2_read16(hw,
1734 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1735 sky2_tx_complete(sky2, ridx);
1736 spin_unlock(&sky2->tx_lock);
1737
1738 if (!netif_queue_stopped(dev)) {
1739 if (net_ratelimit())
1740 pr_info(PFX "transmit interrupt missed? recovered\n");
1741 return;
1742 }
1743
1744 if (netif_msg_timer(sky2))
1745 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1746
1747 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1748 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1749
1750 sky2_tx_clean(sky2);
1751
1752 sky2_qset(hw, txq);
1753 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1754 }
1755
1756
1757 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1758 /* Want receive buffer size to be multiple of 64 bits
1759 * and incl room for vlan and truncation
1760 */
1761 static inline unsigned sky2_buf_size(int mtu)
1762 {
1763 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1764 }
1765
1766 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1767 {
1768 struct sky2_port *sky2 = netdev_priv(dev);
1769 struct sky2_hw *hw = sky2->hw;
1770 int err;
1771 u16 ctl, mode;
1772
1773 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1774 return -EINVAL;
1775
1776 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1777 return -EINVAL;
1778
1779 if (!netif_running(dev)) {
1780 dev->mtu = new_mtu;
1781 return 0;
1782 }
1783
1784 sky2_write32(hw, B0_IMSK, 0);
1785
1786 dev->trans_start = jiffies; /* prevent tx timeout */
1787 netif_stop_queue(dev);
1788 netif_poll_disable(hw->dev[0]);
1789
1790 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1791 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1792 sky2_rx_stop(sky2);
1793 sky2_rx_clean(sky2);
1794
1795 dev->mtu = new_mtu;
1796 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1797 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1798 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1799
1800 if (dev->mtu > ETH_DATA_LEN)
1801 mode |= GM_SMOD_JUMBO_ENA;
1802
1803 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1804
1805 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1806
1807 err = sky2_rx_start(sky2);
1808 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1809
1810 if (err)
1811 dev_close(dev);
1812 else {
1813 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1814
1815 netif_poll_enable(hw->dev[0]);
1816 netif_wake_queue(dev);
1817 }
1818
1819 return err;
1820 }
1821
1822 /*
1823 * Receive one packet.
1824 * For small packets or errors, just reuse existing skb.
1825 * For larger packets, get new buffer.
1826 */
1827 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1828 u16 length, u32 status)
1829 {
1830 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1831 struct sk_buff *skb = NULL;
1832
1833 if (unlikely(netif_msg_rx_status(sky2)))
1834 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1835 sky2->netdev->name, sky2->rx_next, status, length);
1836
1837 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1838 prefetch(sky2->rx_ring + sky2->rx_next);
1839
1840 if (status & GMR_FS_ANY_ERR)
1841 goto error;
1842
1843 if (!(status & GMR_FS_RX_OK))
1844 goto resubmit;
1845
1846 if (length > sky2->netdev->mtu + ETH_HLEN)
1847 goto oversize;
1848
1849 if (length < copybreak) {
1850 skb = dev_alloc_skb(length + 2);
1851 if (!skb)
1852 goto resubmit;
1853
1854 skb_reserve(skb, 2);
1855 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1856 length, PCI_DMA_FROMDEVICE);
1857 memcpy(skb->data, re->skb->data, length);
1858 skb->ip_summed = re->skb->ip_summed;
1859 skb->csum = re->skb->csum;
1860 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1861 length, PCI_DMA_FROMDEVICE);
1862 } else {
1863 struct sk_buff *nskb;
1864
1865 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1866 if (!nskb)
1867 goto resubmit;
1868
1869 skb = re->skb;
1870 re->skb = nskb;
1871 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1872 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1873 prefetch(skb->data);
1874
1875 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1876 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1877 }
1878
1879 skb_put(skb, length);
1880 resubmit:
1881 re->skb->ip_summed = CHECKSUM_NONE;
1882 sky2_rx_add(sky2, re->mapaddr);
1883
1884 /* Tell receiver about new buffers. */
1885 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1886 &sky2->rx_last_put, RX_LE_SIZE);
1887
1888 return skb;
1889
1890 oversize:
1891 ++sky2->net_stats.rx_over_errors;
1892 goto resubmit;
1893
1894 error:
1895 ++sky2->net_stats.rx_errors;
1896
1897 if (netif_msg_rx_err(sky2) && net_ratelimit())
1898 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1899 sky2->netdev->name, status, length);
1900
1901 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1902 sky2->net_stats.rx_length_errors++;
1903 if (status & GMR_FS_FRAGMENT)
1904 sky2->net_stats.rx_frame_errors++;
1905 if (status & GMR_FS_CRC_ERR)
1906 sky2->net_stats.rx_crc_errors++;
1907 if (status & GMR_FS_RX_FF_OV)
1908 sky2->net_stats.rx_fifo_errors++;
1909
1910 goto resubmit;
1911 }
1912
1913 /*
1914 * Check for transmit complete
1915 */
1916 #define TX_NO_STATUS 0xffff
1917
1918 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1919 {
1920 if (last != TX_NO_STATUS) {
1921 struct net_device *dev = hw->dev[port];
1922 if (dev && netif_running(dev)) {
1923 struct sky2_port *sky2 = netdev_priv(dev);
1924
1925 spin_lock(&sky2->tx_lock);
1926 sky2_tx_complete(sky2, last);
1927 spin_unlock(&sky2->tx_lock);
1928 }
1929 }
1930 }
1931
1932 /*
1933 * Both ports share the same status interrupt, therefore there is only
1934 * one poll routine.
1935 */
1936 static int sky2_poll(struct net_device *dev0, int *budget)
1937 {
1938 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1939 unsigned int to_do = min(dev0->quota, *budget);
1940 unsigned int work_done = 0;
1941 u16 hwidx;
1942 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1943
1944 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1945
1946 /*
1947 * Kick the STAT_LEV_TIMER_CTRL timer.
1948 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1949 * The if clause is there to start the timer only if it has been
1950 * configured correctly and not been disabled via ethtool.
1951 */
1952 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1953 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1954 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1955 }
1956
1957 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1958 BUG_ON(hwidx >= STATUS_RING_SIZE);
1959 rmb();
1960
1961 while (hwidx != hw->st_idx) {
1962 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1963 struct net_device *dev;
1964 struct sky2_port *sky2;
1965 struct sk_buff *skb;
1966 u32 status;
1967 u16 length;
1968
1969 le = hw->st_le + hw->st_idx;
1970 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1971 prefetch(hw->st_le + hw->st_idx);
1972
1973 BUG_ON(le->link >= 2);
1974 dev = hw->dev[le->link];
1975 if (dev == NULL || !netif_running(dev))
1976 continue;
1977
1978 sky2 = netdev_priv(dev);
1979 status = le32_to_cpu(le->status);
1980 length = le16_to_cpu(le->length);
1981
1982 switch (le->opcode & ~HW_OWNER) {
1983 case OP_RXSTAT:
1984 skb = sky2_receive(sky2, length, status);
1985 if (!skb)
1986 break;
1987
1988 skb->dev = dev;
1989 skb->protocol = eth_type_trans(skb, dev);
1990 dev->last_rx = jiffies;
1991
1992 #ifdef SKY2_VLAN_TAG_USED
1993 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1994 vlan_hwaccel_receive_skb(skb,
1995 sky2->vlgrp,
1996 be16_to_cpu(sky2->rx_tag));
1997 } else
1998 #endif
1999 netif_receive_skb(skb);
2000
2001 if (++work_done >= to_do)
2002 goto exit_loop;
2003 break;
2004
2005 #ifdef SKY2_VLAN_TAG_USED
2006 case OP_RXVLAN:
2007 sky2->rx_tag = length;
2008 break;
2009
2010 case OP_RXCHKSVLAN:
2011 sky2->rx_tag = length;
2012 /* fall through */
2013 #endif
2014 case OP_RXCHKS:
2015 skb = sky2->rx_ring[sky2->rx_next].skb;
2016 skb->ip_summed = CHECKSUM_HW;
2017 skb->csum = le16_to_cpu(status);
2018 break;
2019
2020 case OP_TXINDEXLE:
2021 /* TX index reports status for both ports */
2022 tx_done[0] = status & 0xffff;
2023 tx_done[1] = ((status >> 24) & 0xff)
2024 | (u16)(length & 0xf) << 8;
2025 break;
2026
2027 default:
2028 if (net_ratelimit())
2029 printk(KERN_WARNING PFX
2030 "unknown status opcode 0x%x\n", le->opcode);
2031 break;
2032 }
2033 }
2034
2035 exit_loop:
2036 sky2_tx_check(hw, 0, tx_done[0]);
2037 sky2_tx_check(hw, 1, tx_done[1]);
2038
2039 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2040 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2041 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2042 }
2043
2044 if (likely(work_done < to_do)) {
2045 spin_lock_irq(&hw->hw_lock);
2046 __netif_rx_complete(dev0);
2047
2048 hw->intr_mask |= Y2_IS_STAT_BMU;
2049 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2050 spin_unlock_irq(&hw->hw_lock);
2051
2052 return 0;
2053 } else {
2054 *budget -= work_done;
2055 dev0->quota -= work_done;
2056 return 1;
2057 }
2058 }
2059
2060 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2061 {
2062 struct net_device *dev = hw->dev[port];
2063
2064 if (net_ratelimit())
2065 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2066 dev->name, status);
2067
2068 if (status & Y2_IS_PAR_RD1) {
2069 if (net_ratelimit())
2070 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2071 dev->name);
2072 /* Clear IRQ */
2073 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2074 }
2075
2076 if (status & Y2_IS_PAR_WR1) {
2077 if (net_ratelimit())
2078 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2079 dev->name);
2080
2081 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2082 }
2083
2084 if (status & Y2_IS_PAR_MAC1) {
2085 if (net_ratelimit())
2086 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2087 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2088 }
2089
2090 if (status & Y2_IS_PAR_RX1) {
2091 if (net_ratelimit())
2092 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2093 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2094 }
2095
2096 if (status & Y2_IS_TCP_TXA1) {
2097 if (net_ratelimit())
2098 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2099 dev->name);
2100 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2101 }
2102 }
2103
2104 static void sky2_hw_intr(struct sky2_hw *hw)
2105 {
2106 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2107
2108 if (status & Y2_IS_TIST_OV)
2109 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2110
2111 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2112 u16 pci_err;
2113
2114 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2115 if (net_ratelimit())
2116 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2117 pci_name(hw->pdev), pci_err);
2118
2119 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2120 sky2_pci_write16(hw, PCI_STATUS,
2121 pci_err | PCI_STATUS_ERROR_BITS);
2122 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2123 }
2124
2125 if (status & Y2_IS_PCI_EXP) {
2126 /* PCI-Express uncorrectable Error occurred */
2127 u32 pex_err;
2128
2129 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2130
2131 if (net_ratelimit())
2132 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2133 pci_name(hw->pdev), pex_err);
2134
2135 /* clear the interrupt */
2136 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2137 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2138 0xffffffffUL);
2139 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2140
2141 if (pex_err & PEX_FATAL_ERRORS) {
2142 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2143 hwmsk &= ~Y2_IS_PCI_EXP;
2144 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2145 }
2146 }
2147
2148 if (status & Y2_HWE_L1_MASK)
2149 sky2_hw_error(hw, 0, status);
2150 status >>= 8;
2151 if (status & Y2_HWE_L1_MASK)
2152 sky2_hw_error(hw, 1, status);
2153 }
2154
2155 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2156 {
2157 struct net_device *dev = hw->dev[port];
2158 struct sky2_port *sky2 = netdev_priv(dev);
2159 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2160
2161 if (netif_msg_intr(sky2))
2162 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2163 dev->name, status);
2164
2165 if (status & GM_IS_RX_FF_OR) {
2166 ++sky2->net_stats.rx_fifo_errors;
2167 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2168 }
2169
2170 if (status & GM_IS_TX_FF_UR) {
2171 ++sky2->net_stats.tx_fifo_errors;
2172 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2173 }
2174 }
2175
2176 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2177 {
2178 struct net_device *dev = hw->dev[port];
2179 struct sky2_port *sky2 = netdev_priv(dev);
2180
2181 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2182 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2183
2184 schedule_work(&sky2->phy_task);
2185 }
2186
2187 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2188 {
2189 struct sky2_hw *hw = dev_id;
2190 struct net_device *dev0 = hw->dev[0];
2191 u32 status;
2192
2193 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2194 if (status == 0 || status == ~0)
2195 return IRQ_NONE;
2196
2197 spin_lock(&hw->hw_lock);
2198 if (status & Y2_IS_HW_ERR)
2199 sky2_hw_intr(hw);
2200
2201 /* Do NAPI for Rx and Tx status */
2202 if (status & Y2_IS_STAT_BMU) {
2203 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2204 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2205
2206 if (likely(__netif_rx_schedule_prep(dev0))) {
2207 prefetch(&hw->st_le[hw->st_idx]);
2208 __netif_rx_schedule(dev0);
2209 }
2210 }
2211
2212 if (status & Y2_IS_IRQ_PHY1)
2213 sky2_phy_intr(hw, 0);
2214
2215 if (status & Y2_IS_IRQ_PHY2)
2216 sky2_phy_intr(hw, 1);
2217
2218 if (status & Y2_IS_IRQ_MAC1)
2219 sky2_mac_intr(hw, 0);
2220
2221 if (status & Y2_IS_IRQ_MAC2)
2222 sky2_mac_intr(hw, 1);
2223
2224 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2225
2226 spin_unlock(&hw->hw_lock);
2227
2228 return IRQ_HANDLED;
2229 }
2230
2231 #ifdef CONFIG_NET_POLL_CONTROLLER
2232 static void sky2_netpoll(struct net_device *dev)
2233 {
2234 struct sky2_port *sky2 = netdev_priv(dev);
2235
2236 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2237 }
2238 #endif
2239
2240 /* Chip internal frequency for clock calculations */
2241 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2242 {
2243 switch (hw->chip_id) {
2244 case CHIP_ID_YUKON_EC:
2245 case CHIP_ID_YUKON_EC_U:
2246 return 125; /* 125 Mhz */
2247 case CHIP_ID_YUKON_FE:
2248 return 100; /* 100 Mhz */
2249 default: /* YUKON_XL */
2250 return 156; /* 156 Mhz */
2251 }
2252 }
2253
2254 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2255 {
2256 return sky2_mhz(hw) * us;
2257 }
2258
2259 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2260 {
2261 return clk / sky2_mhz(hw);
2262 }
2263
2264
2265 static int sky2_reset(struct sky2_hw *hw)
2266 {
2267 u16 status;
2268 u8 t8;
2269 int i;
2270
2271 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2272
2273 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2274 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2275 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2276 pci_name(hw->pdev), hw->chip_id);
2277 return -EOPNOTSUPP;
2278 }
2279
2280 /* disable ASF */
2281 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2282 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2283 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2284 }
2285
2286 /* do a SW reset */
2287 sky2_write8(hw, B0_CTST, CS_RST_SET);
2288 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2289
2290 /* clear PCI errors, if any */
2291 status = sky2_pci_read16(hw, PCI_STATUS);
2292
2293 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2294 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2295
2296
2297 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2298
2299 /* clear any PEX errors */
2300 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2301 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2302
2303
2304 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2305 hw->ports = 1;
2306 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2307 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2308 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2309 ++hw->ports;
2310 }
2311 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2312
2313 sky2_set_power_state(hw, PCI_D0);
2314
2315 for (i = 0; i < hw->ports; i++) {
2316 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2317 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2318 }
2319
2320 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2321
2322 /* Clear I2C IRQ noise */
2323 sky2_write32(hw, B2_I2C_IRQ, 1);
2324
2325 /* turn off hardware timer (unused) */
2326 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2327 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2328
2329 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2330
2331 /* Turn off descriptor polling */
2332 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2333
2334 /* Turn off receive timestamp */
2335 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2336 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2337
2338 /* enable the Tx Arbiters */
2339 for (i = 0; i < hw->ports; i++)
2340 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2341
2342 /* Initialize ram interface */
2343 for (i = 0; i < hw->ports; i++) {
2344 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2345
2346 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2347 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2348 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2349 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2350 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2351 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2352 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2353 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2354 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2355 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2356 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2357 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2358 }
2359
2360 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2361
2362 for (i = 0; i < hw->ports; i++)
2363 sky2_phy_reset(hw, i);
2364
2365 memset(hw->st_le, 0, STATUS_LE_BYTES);
2366 hw->st_idx = 0;
2367
2368 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2369 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2370
2371 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2372 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2373
2374 /* Set the list last index */
2375 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2376
2377 /* These status setup values are copied from SysKonnect's driver */
2378 if (is_ec_a1(hw)) {
2379 /* WA for dev. #4.3 */
2380 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2381
2382 /* set Status-FIFO watermark */
2383 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2384
2385 /* set Status-FIFO ISR watermark */
2386 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2387 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2388 } else {
2389 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2390 sky2_write8(hw, STAT_FIFO_WM, 16);
2391
2392 /* set Status-FIFO ISR watermark */
2393 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2394 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2395 else
2396 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2397
2398 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2399 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2400 }
2401
2402 /* enable status unit */
2403 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2404
2405 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2406 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2407 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2408
2409 return 0;
2410 }
2411
2412 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2413 {
2414 if (sky2_is_copper(hw)) {
2415 u32 modes = SUPPORTED_10baseT_Half
2416 | SUPPORTED_10baseT_Full
2417 | SUPPORTED_100baseT_Half
2418 | SUPPORTED_100baseT_Full
2419 | SUPPORTED_Autoneg | SUPPORTED_TP;
2420
2421 if (hw->chip_id != CHIP_ID_YUKON_FE)
2422 modes |= SUPPORTED_1000baseT_Half
2423 | SUPPORTED_1000baseT_Full;
2424 return modes;
2425 } else
2426 return SUPPORTED_1000baseT_Half
2427 | SUPPORTED_1000baseT_Full
2428 | SUPPORTED_Autoneg
2429 | SUPPORTED_FIBRE;
2430 }
2431
2432 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2433 {
2434 struct sky2_port *sky2 = netdev_priv(dev);
2435 struct sky2_hw *hw = sky2->hw;
2436
2437 ecmd->transceiver = XCVR_INTERNAL;
2438 ecmd->supported = sky2_supported_modes(hw);
2439 ecmd->phy_address = PHY_ADDR_MARV;
2440 if (sky2_is_copper(hw)) {
2441 ecmd->supported = SUPPORTED_10baseT_Half
2442 | SUPPORTED_10baseT_Full
2443 | SUPPORTED_100baseT_Half
2444 | SUPPORTED_100baseT_Full
2445 | SUPPORTED_1000baseT_Half
2446 | SUPPORTED_1000baseT_Full
2447 | SUPPORTED_Autoneg | SUPPORTED_TP;
2448 ecmd->port = PORT_TP;
2449 ecmd->speed = sky2->speed;
2450 } else {
2451 ecmd->speed = SPEED_1000;
2452 ecmd->port = PORT_FIBRE;
2453 }
2454
2455 ecmd->advertising = sky2->advertising;
2456 ecmd->autoneg = sky2->autoneg;
2457 ecmd->duplex = sky2->duplex;
2458 return 0;
2459 }
2460
2461 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2462 {
2463 struct sky2_port *sky2 = netdev_priv(dev);
2464 const struct sky2_hw *hw = sky2->hw;
2465 u32 supported = sky2_supported_modes(hw);
2466
2467 if (ecmd->autoneg == AUTONEG_ENABLE) {
2468 ecmd->advertising = supported;
2469 sky2->duplex = -1;
2470 sky2->speed = -1;
2471 } else {
2472 u32 setting;
2473
2474 switch (ecmd->speed) {
2475 case SPEED_1000:
2476 if (ecmd->duplex == DUPLEX_FULL)
2477 setting = SUPPORTED_1000baseT_Full;
2478 else if (ecmd->duplex == DUPLEX_HALF)
2479 setting = SUPPORTED_1000baseT_Half;
2480 else
2481 return -EINVAL;
2482 break;
2483 case SPEED_100:
2484 if (ecmd->duplex == DUPLEX_FULL)
2485 setting = SUPPORTED_100baseT_Full;
2486 else if (ecmd->duplex == DUPLEX_HALF)
2487 setting = SUPPORTED_100baseT_Half;
2488 else
2489 return -EINVAL;
2490 break;
2491
2492 case SPEED_10:
2493 if (ecmd->duplex == DUPLEX_FULL)
2494 setting = SUPPORTED_10baseT_Full;
2495 else if (ecmd->duplex == DUPLEX_HALF)
2496 setting = SUPPORTED_10baseT_Half;
2497 else
2498 return -EINVAL;
2499 break;
2500 default:
2501 return -EINVAL;
2502 }
2503
2504 if ((setting & supported) == 0)
2505 return -EINVAL;
2506
2507 sky2->speed = ecmd->speed;
2508 sky2->duplex = ecmd->duplex;
2509 }
2510
2511 sky2->autoneg = ecmd->autoneg;
2512 sky2->advertising = ecmd->advertising;
2513
2514 if (netif_running(dev))
2515 sky2_phy_reinit(sky2);
2516
2517 return 0;
2518 }
2519
2520 static void sky2_get_drvinfo(struct net_device *dev,
2521 struct ethtool_drvinfo *info)
2522 {
2523 struct sky2_port *sky2 = netdev_priv(dev);
2524
2525 strcpy(info->driver, DRV_NAME);
2526 strcpy(info->version, DRV_VERSION);
2527 strcpy(info->fw_version, "N/A");
2528 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2529 }
2530
2531 static const struct sky2_stat {
2532 char name[ETH_GSTRING_LEN];
2533 u16 offset;
2534 } sky2_stats[] = {
2535 { "tx_bytes", GM_TXO_OK_HI },
2536 { "rx_bytes", GM_RXO_OK_HI },
2537 { "tx_broadcast", GM_TXF_BC_OK },
2538 { "rx_broadcast", GM_RXF_BC_OK },
2539 { "tx_multicast", GM_TXF_MC_OK },
2540 { "rx_multicast", GM_RXF_MC_OK },
2541 { "tx_unicast", GM_TXF_UC_OK },
2542 { "rx_unicast", GM_RXF_UC_OK },
2543 { "tx_mac_pause", GM_TXF_MPAUSE },
2544 { "rx_mac_pause", GM_RXF_MPAUSE },
2545 { "collisions", GM_TXF_SNG_COL },
2546 { "late_collision",GM_TXF_LAT_COL },
2547 { "aborted", GM_TXF_ABO_COL },
2548 { "multi_collisions", GM_TXF_MUL_COL },
2549 { "fifo_underrun", GM_TXE_FIFO_UR },
2550 { "fifo_overflow", GM_RXE_FIFO_OV },
2551 { "rx_toolong", GM_RXF_LNG_ERR },
2552 { "rx_jabber", GM_RXF_JAB_PKT },
2553 { "rx_runt", GM_RXE_FRAG },
2554 { "rx_too_long", GM_RXF_LNG_ERR },
2555 { "rx_fcs_error", GM_RXF_FCS_ERR },
2556 };
2557
2558 static u32 sky2_get_rx_csum(struct net_device *dev)
2559 {
2560 struct sky2_port *sky2 = netdev_priv(dev);
2561
2562 return sky2->rx_csum;
2563 }
2564
2565 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2566 {
2567 struct sky2_port *sky2 = netdev_priv(dev);
2568
2569 sky2->rx_csum = data;
2570
2571 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2572 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2573
2574 return 0;
2575 }
2576
2577 static u32 sky2_get_msglevel(struct net_device *netdev)
2578 {
2579 struct sky2_port *sky2 = netdev_priv(netdev);
2580 return sky2->msg_enable;
2581 }
2582
2583 static int sky2_nway_reset(struct net_device *dev)
2584 {
2585 struct sky2_port *sky2 = netdev_priv(dev);
2586
2587 if (sky2->autoneg != AUTONEG_ENABLE)
2588 return -EINVAL;
2589
2590 sky2_phy_reinit(sky2);
2591
2592 return 0;
2593 }
2594
2595 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2596 {
2597 struct sky2_hw *hw = sky2->hw;
2598 unsigned port = sky2->port;
2599 int i;
2600
2601 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2602 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2603 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2604 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2605
2606 for (i = 2; i < count; i++)
2607 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2608 }
2609
2610 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2611 {
2612 struct sky2_port *sky2 = netdev_priv(netdev);
2613 sky2->msg_enable = value;
2614 }
2615
2616 static int sky2_get_stats_count(struct net_device *dev)
2617 {
2618 return ARRAY_SIZE(sky2_stats);
2619 }
2620
2621 static void sky2_get_ethtool_stats(struct net_device *dev,
2622 struct ethtool_stats *stats, u64 * data)
2623 {
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625
2626 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2627 }
2628
2629 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2630 {
2631 int i;
2632
2633 switch (stringset) {
2634 case ETH_SS_STATS:
2635 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2636 memcpy(data + i * ETH_GSTRING_LEN,
2637 sky2_stats[i].name, ETH_GSTRING_LEN);
2638 break;
2639 }
2640 }
2641
2642 /* Use hardware MIB variables for critical path statistics and
2643 * transmit feedback not reported at interrupt.
2644 * Other errors are accounted for in interrupt handler.
2645 */
2646 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2647 {
2648 struct sky2_port *sky2 = netdev_priv(dev);
2649 u64 data[13];
2650
2651 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2652
2653 sky2->net_stats.tx_bytes = data[0];
2654 sky2->net_stats.rx_bytes = data[1];
2655 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2656 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2657 sky2->net_stats.multicast = data[5] + data[7];
2658 sky2->net_stats.collisions = data[10];
2659 sky2->net_stats.tx_aborted_errors = data[12];
2660
2661 return &sky2->net_stats;
2662 }
2663
2664 static int sky2_set_mac_address(struct net_device *dev, void *p)
2665 {
2666 struct sky2_port *sky2 = netdev_priv(dev);
2667 struct sky2_hw *hw = sky2->hw;
2668 unsigned port = sky2->port;
2669 const struct sockaddr *addr = p;
2670
2671 if (!is_valid_ether_addr(addr->sa_data))
2672 return -EADDRNOTAVAIL;
2673
2674 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2675 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2676 dev->dev_addr, ETH_ALEN);
2677 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2678 dev->dev_addr, ETH_ALEN);
2679
2680 /* virtual address for data */
2681 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2682
2683 /* physical address: used for pause frames */
2684 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2685
2686 return 0;
2687 }
2688
2689 static void sky2_set_multicast(struct net_device *dev)
2690 {
2691 struct sky2_port *sky2 = netdev_priv(dev);
2692 struct sky2_hw *hw = sky2->hw;
2693 unsigned port = sky2->port;
2694 struct dev_mc_list *list = dev->mc_list;
2695 u16 reg;
2696 u8 filter[8];
2697
2698 memset(filter, 0, sizeof(filter));
2699
2700 reg = gma_read16(hw, port, GM_RX_CTRL);
2701 reg |= GM_RXCR_UCF_ENA;
2702
2703 if (dev->flags & IFF_PROMISC) /* promiscuous */
2704 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2705 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2706 memset(filter, 0xff, sizeof(filter));
2707 else if (dev->mc_count == 0) /* no multicast */
2708 reg &= ~GM_RXCR_MCF_ENA;
2709 else {
2710 int i;
2711 reg |= GM_RXCR_MCF_ENA;
2712
2713 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2714 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2715 filter[bit / 8] |= 1 << (bit % 8);
2716 }
2717 }
2718
2719 gma_write16(hw, port, GM_MC_ADDR_H1,
2720 (u16) filter[0] | ((u16) filter[1] << 8));
2721 gma_write16(hw, port, GM_MC_ADDR_H2,
2722 (u16) filter[2] | ((u16) filter[3] << 8));
2723 gma_write16(hw, port, GM_MC_ADDR_H3,
2724 (u16) filter[4] | ((u16) filter[5] << 8));
2725 gma_write16(hw, port, GM_MC_ADDR_H4,
2726 (u16) filter[6] | ((u16) filter[7] << 8));
2727
2728 gma_write16(hw, port, GM_RX_CTRL, reg);
2729 }
2730
2731 /* Can have one global because blinking is controlled by
2732 * ethtool and that is always under RTNL mutex
2733 */
2734 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2735 {
2736 u16 pg;
2737
2738 switch (hw->chip_id) {
2739 case CHIP_ID_YUKON_XL:
2740 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2742 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2743 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2744 PHY_M_LEDC_INIT_CTRL(7) |
2745 PHY_M_LEDC_STA1_CTRL(7) |
2746 PHY_M_LEDC_STA0_CTRL(7))
2747 : 0);
2748
2749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2750 break;
2751
2752 default:
2753 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2754 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2755 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2756 PHY_M_LED_MO_10(MO_LED_ON) |
2757 PHY_M_LED_MO_100(MO_LED_ON) |
2758 PHY_M_LED_MO_1000(MO_LED_ON) |
2759 PHY_M_LED_MO_RX(MO_LED_ON)
2760 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2761 PHY_M_LED_MO_10(MO_LED_OFF) |
2762 PHY_M_LED_MO_100(MO_LED_OFF) |
2763 PHY_M_LED_MO_1000(MO_LED_OFF) |
2764 PHY_M_LED_MO_RX(MO_LED_OFF));
2765
2766 }
2767 }
2768
2769 /* blink LED's for finding board */
2770 static int sky2_phys_id(struct net_device *dev, u32 data)
2771 {
2772 struct sky2_port *sky2 = netdev_priv(dev);
2773 struct sky2_hw *hw = sky2->hw;
2774 unsigned port = sky2->port;
2775 u16 ledctrl, ledover = 0;
2776 long ms;
2777 int interrupted;
2778 int onoff = 1;
2779
2780 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2781 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2782 else
2783 ms = data * 1000;
2784
2785 /* save initial values */
2786 down(&sky2->phy_sema);
2787 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2788 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2789 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2790 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2791 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2792 } else {
2793 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2794 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2795 }
2796
2797 interrupted = 0;
2798 while (!interrupted && ms > 0) {
2799 sky2_led(hw, port, onoff);
2800 onoff = !onoff;
2801
2802 up(&sky2->phy_sema);
2803 interrupted = msleep_interruptible(250);
2804 down(&sky2->phy_sema);
2805
2806 ms -= 250;
2807 }
2808
2809 /* resume regularly scheduled programming */
2810 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2811 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2812 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2813 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2814 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2815 } else {
2816 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2817 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2818 }
2819 up(&sky2->phy_sema);
2820
2821 return 0;
2822 }
2823
2824 static void sky2_get_pauseparam(struct net_device *dev,
2825 struct ethtool_pauseparam *ecmd)
2826 {
2827 struct sky2_port *sky2 = netdev_priv(dev);
2828
2829 ecmd->tx_pause = sky2->tx_pause;
2830 ecmd->rx_pause = sky2->rx_pause;
2831 ecmd->autoneg = sky2->autoneg;
2832 }
2833
2834 static int sky2_set_pauseparam(struct net_device *dev,
2835 struct ethtool_pauseparam *ecmd)
2836 {
2837 struct sky2_port *sky2 = netdev_priv(dev);
2838 int err = 0;
2839
2840 sky2->autoneg = ecmd->autoneg;
2841 sky2->tx_pause = ecmd->tx_pause != 0;
2842 sky2->rx_pause = ecmd->rx_pause != 0;
2843
2844 sky2_phy_reinit(sky2);
2845
2846 return err;
2847 }
2848
2849 #ifdef CONFIG_PM
2850 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2851 {
2852 struct sky2_port *sky2 = netdev_priv(dev);
2853
2854 wol->supported = WAKE_MAGIC;
2855 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2856 }
2857
2858 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2859 {
2860 struct sky2_port *sky2 = netdev_priv(dev);
2861 struct sky2_hw *hw = sky2->hw;
2862
2863 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2864 return -EOPNOTSUPP;
2865
2866 sky2->wol = wol->wolopts == WAKE_MAGIC;
2867
2868 if (sky2->wol) {
2869 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2870
2871 sky2_write16(hw, WOL_CTRL_STAT,
2872 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2873 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2874 } else
2875 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2876
2877 return 0;
2878 }
2879 #endif
2880
2881 static int sky2_get_coalesce(struct net_device *dev,
2882 struct ethtool_coalesce *ecmd)
2883 {
2884 struct sky2_port *sky2 = netdev_priv(dev);
2885 struct sky2_hw *hw = sky2->hw;
2886
2887 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2888 ecmd->tx_coalesce_usecs = 0;
2889 else {
2890 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2891 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2892 }
2893 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2894
2895 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2896 ecmd->rx_coalesce_usecs = 0;
2897 else {
2898 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2899 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2900 }
2901 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2902
2903 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2904 ecmd->rx_coalesce_usecs_irq = 0;
2905 else {
2906 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2907 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2908 }
2909
2910 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2911
2912 return 0;
2913 }
2914
2915 /* Note: this affect both ports */
2916 static int sky2_set_coalesce(struct net_device *dev,
2917 struct ethtool_coalesce *ecmd)
2918 {
2919 struct sky2_port *sky2 = netdev_priv(dev);
2920 struct sky2_hw *hw = sky2->hw;
2921 const u32 tmin = sky2_clk2us(hw, 1);
2922 const u32 tmax = 5000;
2923
2924 if (ecmd->tx_coalesce_usecs != 0 &&
2925 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2926 return -EINVAL;
2927
2928 if (ecmd->rx_coalesce_usecs != 0 &&
2929 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2930 return -EINVAL;
2931
2932 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2933 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2934 return -EINVAL;
2935
2936 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2937 return -EINVAL;
2938 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2939 return -EINVAL;
2940 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2941 return -EINVAL;
2942
2943 if (ecmd->tx_coalesce_usecs == 0)
2944 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2945 else {
2946 sky2_write32(hw, STAT_TX_TIMER_INI,
2947 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2948 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2949 }
2950 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2951
2952 if (ecmd->rx_coalesce_usecs == 0)
2953 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2954 else {
2955 sky2_write32(hw, STAT_LEV_TIMER_INI,
2956 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2957 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2958 }
2959 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2960
2961 if (ecmd->rx_coalesce_usecs_irq == 0)
2962 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2963 else {
2964 sky2_write32(hw, STAT_ISR_TIMER_INI,
2965 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2966 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2967 }
2968 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2969 return 0;
2970 }
2971
2972 static void sky2_get_ringparam(struct net_device *dev,
2973 struct ethtool_ringparam *ering)
2974 {
2975 struct sky2_port *sky2 = netdev_priv(dev);
2976
2977 ering->rx_max_pending = RX_MAX_PENDING;
2978 ering->rx_mini_max_pending = 0;
2979 ering->rx_jumbo_max_pending = 0;
2980 ering->tx_max_pending = TX_RING_SIZE - 1;
2981
2982 ering->rx_pending = sky2->rx_pending;
2983 ering->rx_mini_pending = 0;
2984 ering->rx_jumbo_pending = 0;
2985 ering->tx_pending = sky2->tx_pending;
2986 }
2987
2988 static int sky2_set_ringparam(struct net_device *dev,
2989 struct ethtool_ringparam *ering)
2990 {
2991 struct sky2_port *sky2 = netdev_priv(dev);
2992 int err = 0;
2993
2994 if (ering->rx_pending > RX_MAX_PENDING ||
2995 ering->rx_pending < 8 ||
2996 ering->tx_pending < MAX_SKB_TX_LE ||
2997 ering->tx_pending > TX_RING_SIZE - 1)
2998 return -EINVAL;
2999
3000 if (netif_running(dev))
3001 sky2_down(dev);
3002
3003 sky2->rx_pending = ering->rx_pending;
3004 sky2->tx_pending = ering->tx_pending;
3005
3006 if (netif_running(dev)) {
3007 err = sky2_up(dev);
3008 if (err)
3009 dev_close(dev);
3010 else
3011 sky2_set_multicast(dev);
3012 }
3013
3014 return err;
3015 }
3016
3017 static int sky2_get_regs_len(struct net_device *dev)
3018 {
3019 return 0x4000;
3020 }
3021
3022 /*
3023 * Returns copy of control register region
3024 * Note: access to the RAM address register set will cause timeouts.
3025 */
3026 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3027 void *p)
3028 {
3029 const struct sky2_port *sky2 = netdev_priv(dev);
3030 const void __iomem *io = sky2->hw->regs;
3031
3032 BUG_ON(regs->len < B3_RI_WTO_R1);
3033 regs->version = 1;
3034 memset(p, 0, regs->len);
3035
3036 memcpy_fromio(p, io, B3_RAM_ADDR);
3037
3038 memcpy_fromio(p + B3_RI_WTO_R1,
3039 io + B3_RI_WTO_R1,
3040 regs->len - B3_RI_WTO_R1);
3041 }
3042
3043 static struct ethtool_ops sky2_ethtool_ops = {
3044 .get_settings = sky2_get_settings,
3045 .set_settings = sky2_set_settings,
3046 .get_drvinfo = sky2_get_drvinfo,
3047 .get_msglevel = sky2_get_msglevel,
3048 .set_msglevel = sky2_set_msglevel,
3049 .nway_reset = sky2_nway_reset,
3050 .get_regs_len = sky2_get_regs_len,
3051 .get_regs = sky2_get_regs,
3052 .get_link = ethtool_op_get_link,
3053 .get_sg = ethtool_op_get_sg,
3054 .set_sg = ethtool_op_set_sg,
3055 .get_tx_csum = ethtool_op_get_tx_csum,
3056 .set_tx_csum = ethtool_op_set_tx_csum,
3057 .get_tso = ethtool_op_get_tso,
3058 .set_tso = ethtool_op_set_tso,
3059 .get_rx_csum = sky2_get_rx_csum,
3060 .set_rx_csum = sky2_set_rx_csum,
3061 .get_strings = sky2_get_strings,
3062 .get_coalesce = sky2_get_coalesce,
3063 .set_coalesce = sky2_set_coalesce,
3064 .get_ringparam = sky2_get_ringparam,
3065 .set_ringparam = sky2_set_ringparam,
3066 .get_pauseparam = sky2_get_pauseparam,
3067 .set_pauseparam = sky2_set_pauseparam,
3068 #ifdef CONFIG_PM
3069 .get_wol = sky2_get_wol,
3070 .set_wol = sky2_set_wol,
3071 #endif
3072 .phys_id = sky2_phys_id,
3073 .get_stats_count = sky2_get_stats_count,
3074 .get_ethtool_stats = sky2_get_ethtool_stats,
3075 .get_perm_addr = ethtool_op_get_perm_addr,
3076 };
3077
3078 /* Initialize network device */
3079 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3080 unsigned port, int highmem)
3081 {
3082 struct sky2_port *sky2;
3083 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3084
3085 if (!dev) {
3086 printk(KERN_ERR "sky2 etherdev alloc failed");
3087 return NULL;
3088 }
3089
3090 SET_MODULE_OWNER(dev);
3091 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3092 dev->irq = hw->pdev->irq;
3093 dev->open = sky2_up;
3094 dev->stop = sky2_down;
3095 dev->do_ioctl = sky2_ioctl;
3096 dev->hard_start_xmit = sky2_xmit_frame;
3097 dev->get_stats = sky2_get_stats;
3098 dev->set_multicast_list = sky2_set_multicast;
3099 dev->set_mac_address = sky2_set_mac_address;
3100 dev->change_mtu = sky2_change_mtu;
3101 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3102 dev->tx_timeout = sky2_tx_timeout;
3103 dev->watchdog_timeo = TX_WATCHDOG;
3104 if (port == 0)
3105 dev->poll = sky2_poll;
3106 dev->weight = NAPI_WEIGHT;
3107 #ifdef CONFIG_NET_POLL_CONTROLLER
3108 dev->poll_controller = sky2_netpoll;
3109 #endif
3110
3111 sky2 = netdev_priv(dev);
3112 sky2->netdev = dev;
3113 sky2->hw = hw;
3114 sky2->msg_enable = netif_msg_init(debug, default_msg);
3115
3116 spin_lock_init(&sky2->tx_lock);
3117 /* Auto speed and flow control */
3118 sky2->autoneg = AUTONEG_ENABLE;
3119 sky2->tx_pause = 1;
3120 sky2->rx_pause = 1;
3121 sky2->duplex = -1;
3122 sky2->speed = -1;
3123 sky2->advertising = sky2_supported_modes(hw);
3124
3125 /* Receive checksum disabled for Yukon XL
3126 * because of observed problems with incorrect
3127 * values when multiple packets are received in one interrupt
3128 */
3129 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3130
3131 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3132 init_MUTEX(&sky2->phy_sema);
3133 sky2->tx_pending = TX_DEF_PENDING;
3134 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3135 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3136
3137 hw->dev[port] = dev;
3138
3139 sky2->port = port;
3140
3141 dev->features |= NETIF_F_LLTX;
3142 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3143 dev->features |= NETIF_F_TSO;
3144 if (highmem)
3145 dev->features |= NETIF_F_HIGHDMA;
3146 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3147
3148 #ifdef SKY2_VLAN_TAG_USED
3149 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3150 dev->vlan_rx_register = sky2_vlan_rx_register;
3151 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3152 #endif
3153
3154 /* read the mac address */
3155 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3156 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3157
3158 /* device is off until link detection */
3159 netif_carrier_off(dev);
3160 netif_stop_queue(dev);
3161
3162 return dev;
3163 }
3164
3165 static void __devinit sky2_show_addr(struct net_device *dev)
3166 {
3167 const struct sky2_port *sky2 = netdev_priv(dev);
3168
3169 if (netif_msg_probe(sky2))
3170 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3171 dev->name,
3172 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3173 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3174 }
3175
3176 static int __devinit sky2_probe(struct pci_dev *pdev,
3177 const struct pci_device_id *ent)
3178 {
3179 struct net_device *dev, *dev1 = NULL;
3180 struct sky2_hw *hw;
3181 int err, pm_cap, using_dac = 0;
3182
3183 err = pci_enable_device(pdev);
3184 if (err) {
3185 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3186 pci_name(pdev));
3187 goto err_out;
3188 }
3189
3190 err = pci_request_regions(pdev, DRV_NAME);
3191 if (err) {
3192 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3193 pci_name(pdev));
3194 goto err_out;
3195 }
3196
3197 pci_set_master(pdev);
3198
3199 /* Find power-management capability. */
3200 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3201 if (pm_cap == 0) {
3202 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3203 "aborting.\n");
3204 err = -EIO;
3205 goto err_out_free_regions;
3206 }
3207
3208 if (sizeof(dma_addr_t) > sizeof(u32) &&
3209 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3210 using_dac = 1;
3211 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3212 if (err < 0) {
3213 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3214 "for consistent allocations\n", pci_name(pdev));
3215 goto err_out_free_regions;
3216 }
3217
3218 } else {
3219 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3220 if (err) {
3221 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3222 pci_name(pdev));
3223 goto err_out_free_regions;
3224 }
3225 }
3226
3227 err = -ENOMEM;
3228 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3229 if (!hw) {
3230 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3231 pci_name(pdev));
3232 goto err_out_free_regions;
3233 }
3234
3235 hw->pdev = pdev;
3236
3237 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3238 if (!hw->regs) {
3239 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3240 pci_name(pdev));
3241 goto err_out_free_hw;
3242 }
3243 hw->pm_cap = pm_cap;
3244 spin_lock_init(&hw->hw_lock);
3245
3246 #ifdef __BIG_ENDIAN
3247 /* byte swap descriptors in hardware */
3248 {
3249 u32 reg;
3250
3251 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3252 reg |= PCI_REV_DESC;
3253 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3254 }
3255 #endif
3256
3257 /* ring for status responses */
3258 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3259 &hw->st_dma);
3260 if (!hw->st_le)
3261 goto err_out_iounmap;
3262
3263 err = sky2_reset(hw);
3264 if (err)
3265 goto err_out_iounmap;
3266
3267 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3268 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3269 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3270 hw->chip_id, hw->chip_rev);
3271
3272 dev = sky2_init_netdev(hw, 0, using_dac);
3273 if (!dev)
3274 goto err_out_free_pci;
3275
3276 err = register_netdev(dev);
3277 if (err) {
3278 printk(KERN_ERR PFX "%s: cannot register net device\n",
3279 pci_name(pdev));
3280 goto err_out_free_netdev;
3281 }
3282
3283 sky2_show_addr(dev);
3284
3285 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3286 if (register_netdev(dev1) == 0)
3287 sky2_show_addr(dev1);
3288 else {
3289 /* Failure to register second port need not be fatal */
3290 printk(KERN_WARNING PFX
3291 "register of second port failed\n");
3292 hw->dev[1] = NULL;
3293 free_netdev(dev1);
3294 }
3295 }
3296
3297 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3298 if (err) {
3299 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3300 pci_name(pdev), pdev->irq);
3301 goto err_out_unregister;
3302 }
3303
3304 hw->intr_mask = Y2_IS_BASE;
3305 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3306
3307 pci_set_drvdata(pdev, hw);
3308
3309 return 0;
3310
3311 err_out_unregister:
3312 if (dev1) {
3313 unregister_netdev(dev1);
3314 free_netdev(dev1);
3315 }
3316 unregister_netdev(dev);
3317 err_out_free_netdev:
3318 free_netdev(dev);
3319 err_out_free_pci:
3320 sky2_write8(hw, B0_CTST, CS_RST_SET);
3321 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3322 err_out_iounmap:
3323 iounmap(hw->regs);
3324 err_out_free_hw:
3325 kfree(hw);
3326 err_out_free_regions:
3327 pci_release_regions(pdev);
3328 pci_disable_device(pdev);
3329 err_out:
3330 return err;
3331 }
3332
3333 static void __devexit sky2_remove(struct pci_dev *pdev)
3334 {
3335 struct sky2_hw *hw = pci_get_drvdata(pdev);
3336 struct net_device *dev0, *dev1;
3337
3338 if (!hw)
3339 return;
3340
3341 dev0 = hw->dev[0];
3342 dev1 = hw->dev[1];
3343 if (dev1)
3344 unregister_netdev(dev1);
3345 unregister_netdev(dev0);
3346
3347 sky2_write32(hw, B0_IMSK, 0);
3348 sky2_set_power_state(hw, PCI_D3hot);
3349 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3350 sky2_write8(hw, B0_CTST, CS_RST_SET);
3351 sky2_read8(hw, B0_CTST);
3352
3353 free_irq(pdev->irq, hw);
3354 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3355 pci_release_regions(pdev);
3356 pci_disable_device(pdev);
3357
3358 if (dev1)
3359 free_netdev(dev1);
3360 free_netdev(dev0);
3361 iounmap(hw->regs);
3362 kfree(hw);
3363
3364 pci_set_drvdata(pdev, NULL);
3365 }
3366
3367 #ifdef CONFIG_PM
3368 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3369 {
3370 struct sky2_hw *hw = pci_get_drvdata(pdev);
3371 int i;
3372
3373 for (i = 0; i < 2; i++) {
3374 struct net_device *dev = hw->dev[i];
3375
3376 if (dev) {
3377 if (!netif_running(dev))
3378 continue;
3379
3380 sky2_down(dev);
3381 netif_device_detach(dev);
3382 }
3383 }
3384
3385 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3386 }
3387
3388 static int sky2_resume(struct pci_dev *pdev)
3389 {
3390 struct sky2_hw *hw = pci_get_drvdata(pdev);
3391 int i, err;
3392
3393 pci_restore_state(pdev);
3394 pci_enable_wake(pdev, PCI_D0, 0);
3395 err = sky2_set_power_state(hw, PCI_D0);
3396 if (err)
3397 goto out;
3398
3399 err = sky2_reset(hw);
3400 if (err)
3401 goto out;
3402
3403 for (i = 0; i < 2; i++) {
3404 struct net_device *dev = hw->dev[i];
3405 if (dev && netif_running(dev)) {
3406 netif_device_attach(dev);
3407 err = sky2_up(dev);
3408 if (err) {
3409 printk(KERN_ERR PFX "%s: could not up: %d\n",
3410 dev->name, err);
3411 dev_close(dev);
3412 break;
3413 }
3414 }
3415 }
3416 out:
3417 return err;
3418 }
3419 #endif
3420
3421 static struct pci_driver sky2_driver = {
3422 .name = DRV_NAME,
3423 .id_table = sky2_id_table,
3424 .probe = sky2_probe,
3425 .remove = __devexit_p(sky2_remove),
3426 #ifdef CONFIG_PM
3427 .suspend = sky2_suspend,
3428 .resume = sky2_resume,
3429 #endif
3430 };
3431
3432 static int __init sky2_init_module(void)
3433 {
3434 return pci_register_driver(&sky2_driver);
3435 }
3436
3437 static void __exit sky2_cleanup_module(void)
3438 {
3439 pci_unregister_driver(&sky2_driver);
3440 }
3441
3442 module_init(sky2_init_module);
3443 module_exit(sky2_cleanup_module);
3444
3445 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3446 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3447 MODULE_LICENSE("GPL");
3448 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree