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staging: Fix typos in rt2860
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rt2860 / chips / rt30xx.c
blobc8f728257197e13d12aa789449fa6e12681d6318
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rt30xx.c
29
30 Abstract:
31 Specific functions and variables for RT30xx.
32
33 Revision History:
34 Who When What
35 Justin P. Mattock 11/07/2010 Fix some typos
36 -------- ---------- ----------------------------------------------
37 */
38
39 #ifdef RT30xx
40
41 #ifndef RTMP_RF_RW_SUPPORT
42 #error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
43 #endif /* RTMP_RF_RW_SUPPORT // */
44
45 #include "../rt_config.h"
46
47 /* */
48 /* RF register initialization set */
49 /* */
50 struct rt_reg_pair RT30xx_RFRegTable[] = {
51 {RF_R04, 0x40}
52 ,
53 {RF_R05, 0x03}
54 ,
55 {RF_R06, 0x02}
56 ,
57 {RF_R07, 0x70}
58 ,
59 {RF_R09, 0x0F}
60 ,
61 {RF_R10, 0x41}
62 ,
63 {RF_R11, 0x21}
64 ,
65 {RF_R12, 0x7B}
66 ,
67 {RF_R14, 0x90}
68 ,
69 {RF_R15, 0x58}
70 ,
71 {RF_R16, 0xB3}
72 ,
73 {RF_R17, 0x92}
74 ,
75 {RF_R18, 0x2C}
76 ,
77 {RF_R19, 0x02}
78 ,
79 {RF_R20, 0xBA}
80 ,
81 {RF_R21, 0xDB}
82 ,
83 {RF_R24, 0x16}
84 ,
85 {RF_R25, 0x01}
86 ,
87 {RF_R29, 0x1F}
88 ,
89 };
90
91 u8 NUM_RF_REG_PARMS = (sizeof(RT30xx_RFRegTable) / sizeof(struct rt_reg_pair));
92
93 /* Antenna diversity use GPIO3 and EESK pin for control */
94 /* Antenna and EEPROM access are both using EESK pin, */
95 /* Therefor we should avoid accessing EESK at the same time */
96 /* Then restore antenna after EEPROM access */
97 /* The original name of this function is AsicSetRxAnt(), now change to */
98 /*void AsicSetRxAnt( */
99 void RT30xxSetRxAnt(struct rt_rtmp_adapter *pAd, u8 Ant)
100 {
101 u32 Value;
102 #ifdef RTMP_MAC_PCI
103 u32 x;
104 #endif
105
106 if ((pAd->EepromAccess) ||
107 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
108 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
109 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
110 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
111 return;
112 }
113 /* the antenna selection is through firmware and MAC register(GPIO3) */
114 if (Ant == 0) {
115 /* Main antenna */
116 #ifdef RTMP_MAC_PCI
117 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
118 x |= (EESK);
119 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
120 #else
121 AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0);
122 #endif /* RTMP_MAC_PCI // */
123
124 RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
125 Value &= ~(0x0808);
126 RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
127 DBGPRINT_RAW(RT_DEBUG_TRACE,
128 ("AsicSetRxAnt, switch to main antenna\n"));
129 } else {
130 /* Aux antenna */
131 #ifdef RTMP_MAC_PCI
132 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
133 x &= ~(EESK);
134 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
135 #else
136 AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0);
137 #endif /* RTMP_MAC_PCI // */
138 RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
139 Value &= ~(0x0808);
140 Value |= 0x08;
141 RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
142 DBGPRINT_RAW(RT_DEBUG_TRACE,
143 ("AsicSetRxAnt, switch to aux antenna\n"));
144 }
145 }
146
147 /*
148 ========================================================================
149
150 Routine Description:
151 For RF filter calibration purpose
152
153 Arguments:
154 pAd Pointer to our adapter
155
156 Return Value:
157 None
158
159 IRQL = PASSIVE_LEVEL
160
161 ========================================================================
162 */
163 void RTMPFilterCalibration(struct rt_rtmp_adapter *pAd)
164 {
165 u8 R55x = 0, value, FilterTarget = 0x1E, BBPValue = 0;
166 u32 loop = 0, count = 0, loopcnt = 0, ReTry = 0;
167 u8 RF_R24_Value = 0;
168
169 /* Give bbp filter initial value */
170 pAd->Mlme.CaliBW20RfR24 = 0x1F;
171 pAd->Mlme.CaliBW40RfR24 = 0x2F; /*Bit[5] must be 1 for BW 40 */
172
173 do {
174 if (loop == 1) { /*BandWidth = 40 MHz */
175 /* Write 0x27 to RF_R24 to program filter */
176 RF_R24_Value = 0x27;
177 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
178 if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
179 FilterTarget = 0x15;
180 else
181 FilterTarget = 0x19;
182
183 /* when calibrate BW40, BBP mask must set to BW40. */
184 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
185 BBPValue &= (~0x18);
186 BBPValue |= (0x10);
187 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
188
189 /* set to BW40 */
190 RT30xxReadRFRegister(pAd, RF_R31, &value);
191 value |= 0x20;
192 RT30xxWriteRFRegister(pAd, RF_R31, value);
193 } else { /*BandWidth = 20 MHz */
194 /* Write 0x07 to RF_R24 to program filter */
195 RF_R24_Value = 0x07;
196 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
197 if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
198 FilterTarget = 0x13;
199 else
200 FilterTarget = 0x16;
201
202 /* set to BW20 */
203 RT30xxReadRFRegister(pAd, RF_R31, &value);
204 value &= (~0x20);
205 RT30xxWriteRFRegister(pAd, RF_R31, value);
206 }
207
208 /* Write 0x01 to RF_R22 to enable baseband loopback mode */
209 RT30xxReadRFRegister(pAd, RF_R22, &value);
210 value |= 0x01;
211 RT30xxWriteRFRegister(pAd, RF_R22, value);
212
213 /* Write 0x00 to BBP_R24 to set power & frequency of passband test tone */
214 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
215
216 do {
217 /* Write 0x90 to BBP_R25 to transmit test tone */
218 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
219
220 RTMPusecDelay(1000);
221 /* Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0] */
222 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
223 R55x = value & 0xFF;
224
225 } while ((ReTry++ < 100) && (R55x == 0));
226
227 /* Write 0x06 to BBP_R24 to set power & frequency of stopband test tone */
228 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
229
230 while (TRUE) {
231 /* Write 0x90 to BBP_R25 to transmit test tone */
232 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
233
234 /*We need to wait for calibration */
235 RTMPusecDelay(1000);
236 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
237 value &= 0xFF;
238 if ((R55x - value) < FilterTarget) {
239 RF_R24_Value++;
240 } else if ((R55x - value) == FilterTarget) {
241 RF_R24_Value++;
242 count++;
243 } else {
244 break;
245 }
246
247 /* prevent infinite loop; causes driver hang. */
248 if (loopcnt++ > 100) {
249 DBGPRINT(RT_DEBUG_ERROR,
250 ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating",
251 loopcnt));
252 break;
253 }
254 /* Write RF_R24 to program filter */
255 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
256 }
257
258 if (count > 0) {
259 RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
260 }
261 /* Store for future usage */
262 if (loopcnt < 100) {
263 if (loop++ == 0) {
264 /*BandWidth = 20 MHz */
265 pAd->Mlme.CaliBW20RfR24 = (u8)RF_R24_Value;
266 } else {
267 /*BandWidth = 40 MHz */
268 pAd->Mlme.CaliBW40RfR24 = (u8)RF_R24_Value;
269 break;
270 }
271 } else
272 break;
273
274 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
275
276 /* reset count */
277 count = 0;
278 } while (TRUE);
279
280 /* */
281 /* Set back to initial state */
282 /* */
283 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
284
285 RT30xxReadRFRegister(pAd, RF_R22, &value);
286 value &= ~(0x01);
287 RT30xxWriteRFRegister(pAd, RF_R22, value);
288
289 /* set BBP back to BW20 */
290 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
291 BBPValue &= (~0x18);
292 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
293
294 DBGPRINT(RT_DEBUG_TRACE,
295 ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n",
296 pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
297 }
298
299 /* add by johnli, RF power sequence setup */
300 /*
301 ==========================================================================
302 Description:
303
304 Load RF normal operation-mode setup
305
306 ==========================================================================
307 */
308 void RT30xxLoadRFNormalModeSetup(struct rt_rtmp_adapter *pAd)
309 {
310 u8 RFValue;
311
312 /* RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1 */
313 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
314 RFValue = (RFValue & (~0x0C)) | 0x31;
315 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
316
317 /* TX_LO2_en, RF R15 register Bit 3 to 0 */
318 RT30xxReadRFRegister(pAd, RF_R15, &RFValue);
319 RFValue &= (~0x08);
320 RT30xxWriteRFRegister(pAd, RF_R15, RFValue);
321
322 /* move to NICInitRT30xxRFRegisters
323 // TX_LO1_en, RF R17 register Bit 3 to 0
324 RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
325 RFValue &= (~0x08);
326 // to fix rx long range issue
327 if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0))
328 {
329 RFValue |= 0x20;
330 }
331 // set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h
332 if (pAd->TxMixerGain24G >= 2)
333 {
334 RFValue &= (~0x7); // clean bit [2:0]
335 RFValue |= pAd->TxMixerGain24G;
336 }
337 RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
338 */
339
340 /* RX_LO1_en, RF R20 register Bit 3 to 0 */
341 RT30xxReadRFRegister(pAd, RF_R20, &RFValue);
342 RFValue &= (~0x08);
343 RT30xxWriteRFRegister(pAd, RF_R20, RFValue);
344
345 /* RX_LO2_en, RF R21 register Bit 3 to 0 */
346 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
347 RFValue &= (~0x08);
348 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
349
350 /* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */
351 /* LDORF_VC, RF R27 register Bit 2 to 0 */
352 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
353 /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). */
354 /* Raising RF voltage is no longer needed for RT3070(F) */
355 if (IS_RT3090(pAd)) { /* RT309x and RT3071/72 */
356 if ((pAd->MACVersion & 0xffff) < 0x0211)
357 RFValue = (RFValue & (~0x77)) | 0x3;
358 else
359 RFValue = (RFValue & (~0x77));
360 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
361 }
362 /* end johnli */
363 }
364
365 /*
366 ==========================================================================
367 Description:
368
369 Load RF sleep-mode setup
370
371 ==========================================================================
372 */
373 void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd)
374 {
375 u8 RFValue;
376 u32 MACValue;
377
378 #ifdef RTMP_MAC_USB
379 if (!IS_RT3572(pAd))
380 #endif /* RTMP_MAC_USB // */
381 {
382 /* RF_BLOCK_en. RF R1 register Bit 0 to 0 */
383 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
384 RFValue &= (~0x01);
385 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
386
387 /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 */
388 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
389 RFValue &= (~0x30);
390 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
391
392 /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 */
393 RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
394 RFValue &= (~0x0E);
395 RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
396
397 /* RX_CTB_en, RF R21 register Bit 7 to 0 */
398 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
399 RFValue &= (~0x80);
400 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
401 }
402
403 if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */
404 IS_RT3572(pAd) ||
405 (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) {
406 #ifdef RTMP_MAC_USB
407 if (!IS_RT3572(pAd))
408 #endif /* RTMP_MAC_USB // */
409 {
410 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
411 RFValue |= 0x77;
412 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
413 }
414
415 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
416 MACValue |= 0x1D000000;
417 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
418 }
419 }
420
421 /*
422 ==========================================================================
423 Description:
424
425 Reverse RF sleep-mode setup
426
427 ==========================================================================
428 */
429 void RT30xxReverseRFSleepModeSetup(struct rt_rtmp_adapter *pAd)
430 {
431 u8 RFValue;
432 u32 MACValue;
433
434 #ifdef RTMP_MAC_USB
435 if (!IS_RT3572(pAd))
436 #endif /* RTMP_MAC_USB // */
437 {
438 /* RF_BLOCK_en, RF R1 register Bit 0 to 1 */
439 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
440 RFValue |= 0x01;
441 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
442
443 /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1 */
444 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
445 RFValue |= 0x30;
446 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
447
448 /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 */
449 RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
450 RFValue |= 0x0E;
451 RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
452
453 /* RX_CTB_en, RF R21 register Bit 7 to 1 */
454 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
455 RFValue |= 0x80;
456 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
457 }
458
459 if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */
460 IS_RT3572(pAd) ||
461 IS_RT3390(pAd) ||
462 (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) {
463 #ifdef RTMP_MAC_USB
464 if (!IS_RT3572(pAd))
465 #endif /* RTMP_MAC_USB // */
466 {
467 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
468 if ((pAd->MACVersion & 0xffff) < 0x0211)
469 RFValue = (RFValue & (~0x77)) | 0x3;
470 else
471 RFValue = (RFValue & (~0x77));
472 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
473 }
474 /* RT3071 version E has fixed this issue */
475 if ((pAd->NicConfig2.field.DACTestBit == 1)
476 && ((pAd->MACVersion & 0xffff) < 0x0211)) {
477 /* patch tx EVM issue temporarily */
478 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
479 MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
480 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
481 } else {
482 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
483 MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
484 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
485 }
486 }
487
488 if (IS_RT3572(pAd))
489 RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
490 }
491
492 /* end johnli */
493
494 void RT30xxHaltAction(struct rt_rtmp_adapter *pAd)
495 {
496 u32 TxPinCfg = 0x00050F0F;
497
498 /* */
499 /* Turn off LNA_PE or TRSW_POL */
500 /* */
501 if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd)) {
502 if ((IS_RT3071(pAd) || IS_RT3572(pAd))
503 #ifdef RTMP_EFUSE_SUPPORT
504 && (pAd->bUseEfuse)
505 #endif /* RTMP_EFUSE_SUPPORT // */
506 ) {
507 TxPinCfg &= 0xFFFBF0F0; /* bit18 off */
508 } else {
509 TxPinCfg &= 0xFFFFF0F0;
510 }
511
512 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
513 }
514 }
515
516 #endif /* RT30xx // */
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