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e1000e: do not toggle LANPHYPC value bit when PHY reset is blocked
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / ich8lan.c
blob9b434c0cbc9f040143651dcab0322feb0ec93630
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
57 */
58
59 #include "e1000.h"
60
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
67
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
77
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
80
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
92
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
102
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114 #define E1000_ICH_RAR_ENTRIES 7
115
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
135
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
138
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142
143 /* EMI Registers */
144 #define I82579_EMI_ADDR 0x10
145 #define I82579_EMI_DATA 0x11
146 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
147
148 /* Strapping Option Register - RO */
149 #define E1000_STRAP 0x0000C
150 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
152
153 /* OEM Bits Phy Register */
154 #define HV_OEM_BITS PHY_REG(768, 25)
155 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
156 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
158
159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
160 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
161
162 /* KMRN Mode Control */
163 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
164 #define HV_KMRN_MDIO_SLOW 0x0400
165
166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
167 /* Offset 04h HSFSTS */
168 union ich8_hws_flash_status {
169 struct ich8_hsfsts {
170 u16 flcdone :1; /* bit 0 Flash Cycle Done */
171 u16 flcerr :1; /* bit 1 Flash Cycle Error */
172 u16 dael :1; /* bit 2 Direct Access error Log */
173 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
174 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
175 u16 reserved1 :2; /* bit 13:6 Reserved */
176 u16 reserved2 :6; /* bit 13:6 Reserved */
177 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
178 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
179 } hsf_status;
180 u16 regval;
181 };
182
183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
184 /* Offset 06h FLCTL */
185 union ich8_hws_flash_ctrl {
186 struct ich8_hsflctl {
187 u16 flcgo :1; /* 0 Flash Cycle Go */
188 u16 flcycle :2; /* 2:1 Flash Cycle */
189 u16 reserved :5; /* 7:3 Reserved */
190 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
191 u16 flockdn :6; /* 15:10 Reserved */
192 } hsf_ctrl;
193 u16 regval;
194 };
195
196 /* ICH Flash Region Access Permissions */
197 union ich8_hws_flash_regacc {
198 struct ich8_flracc {
199 u32 grra :8; /* 0:7 GbE region Read Access */
200 u32 grwa :8; /* 8:15 GbE region Write Access */
201 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
202 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
203 } hsf_flregacc;
204 u16 regval;
205 };
206
207 /* ICH Flash Protected Region */
208 union ich8_flash_protected_range {
209 struct ich8_pr {
210 u32 base:13; /* 0:12 Protected Range Base */
211 u32 reserved1:2; /* 13:14 Reserved */
212 u32 rpe:1; /* 15 Read Protection Enable */
213 u32 limit:13; /* 16:28 Protected Range Limit */
214 u32 reserved2:2; /* 29:30 Reserved */
215 u32 wpe:1; /* 31 Write Protection Enable */
216 } range;
217 u32 regval;
218 };
219
220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
225 u32 offset, u8 byte);
226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
227 u8 *data);
228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
229 u16 *data);
230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
231 u8 size, u16 *data);
232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
246 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
252
253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
254 {
255 return readw(hw->flash_address + reg);
256 }
257
258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
259 {
260 return readl(hw->flash_address + reg);
261 }
262
263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
264 {
265 writew(val, hw->flash_address + reg);
266 }
267
268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
269 {
270 writel(val, hw->flash_address + reg);
271 }
272
273 #define er16flash(reg) __er16flash(hw, (reg))
274 #define er32flash(reg) __er32flash(hw, (reg))
275 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
276 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
277
278 /**
279 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
280 * @hw: pointer to the HW structure
281 *
282 * Initialize family-specific PHY parameters and function pointers.
283 **/
284 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
285 {
286 struct e1000_phy_info *phy = &hw->phy;
287 u32 ctrl, fwsm;
288 s32 ret_val = 0;
289
290 phy->addr = 1;
291 phy->reset_delay_us = 100;
292
293 phy->ops.read_reg = e1000_read_phy_reg_hv;
294 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
295 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
296 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
297 phy->ops.write_reg = e1000_write_phy_reg_hv;
298 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
299 phy->ops.power_up = e1000_power_up_phy_copper;
300 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
301 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
302
303 /*
304 * The MAC-PHY interconnect may still be in SMBus mode
305 * after Sx->S0. If the manageability engine (ME) is
306 * disabled, then toggle the LANPHYPC Value bit to force
307 * the interconnect to PCIe mode.
308 */
309 fwsm = er32(FWSM);
310 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
311 ctrl = er32(CTRL);
312 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
313 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
314 ew32(CTRL, ctrl);
315 udelay(10);
316 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
317 ew32(CTRL, ctrl);
318 msleep(50);
319
320 /*
321 * Gate automatic PHY configuration by hardware on
322 * non-managed 82579
323 */
324 if (hw->mac.type == e1000_pch2lan)
325 e1000_gate_hw_phy_config_ich8lan(hw, true);
326 }
327
328 /*
329 * Reset the PHY before any access to it. Doing so, ensures that
330 * the PHY is in a known good state before we read/write PHY registers.
331 * The generic reset is sufficient here, because we haven't determined
332 * the PHY type yet.
333 */
334 ret_val = e1000e_phy_hw_reset_generic(hw);
335 if (ret_val)
336 goto out;
337
338 /* Ungate automatic PHY configuration on non-managed 82579 */
339 if ((hw->mac.type == e1000_pch2lan) &&
340 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
341 msleep(10);
342 e1000_gate_hw_phy_config_ich8lan(hw, false);
343 }
344
345 phy->id = e1000_phy_unknown;
346 switch (hw->mac.type) {
347 default:
348 ret_val = e1000e_get_phy_id(hw);
349 if (ret_val)
350 goto out;
351 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
352 break;
353 /* fall-through */
354 case e1000_pch2lan:
355 /*
356 * In case the PHY needs to be in mdio slow mode,
357 * set slow mode and try to get the PHY id again.
358 */
359 ret_val = e1000_set_mdio_slow_mode_hv(hw);
360 if (ret_val)
361 goto out;
362 ret_val = e1000e_get_phy_id(hw);
363 if (ret_val)
364 goto out;
365 break;
366 }
367 phy->type = e1000e_get_phy_type_from_id(phy->id);
368
369 switch (phy->type) {
370 case e1000_phy_82577:
371 case e1000_phy_82579:
372 phy->ops.check_polarity = e1000_check_polarity_82577;
373 phy->ops.force_speed_duplex =
374 e1000_phy_force_speed_duplex_82577;
375 phy->ops.get_cable_length = e1000_get_cable_length_82577;
376 phy->ops.get_info = e1000_get_phy_info_82577;
377 phy->ops.commit = e1000e_phy_sw_reset;
378 break;
379 case e1000_phy_82578:
380 phy->ops.check_polarity = e1000_check_polarity_m88;
381 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
382 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
383 phy->ops.get_info = e1000e_get_phy_info_m88;
384 break;
385 default:
386 ret_val = -E1000_ERR_PHY;
387 break;
388 }
389
390 out:
391 return ret_val;
392 }
393
394 /**
395 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
396 * @hw: pointer to the HW structure
397 *
398 * Initialize family-specific PHY parameters and function pointers.
399 **/
400 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
401 {
402 struct e1000_phy_info *phy = &hw->phy;
403 s32 ret_val;
404 u16 i = 0;
405
406 phy->addr = 1;
407 phy->reset_delay_us = 100;
408
409 phy->ops.power_up = e1000_power_up_phy_copper;
410 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
411
412 /*
413 * We may need to do this twice - once for IGP and if that fails,
414 * we'll set BM func pointers and try again
415 */
416 ret_val = e1000e_determine_phy_address(hw);
417 if (ret_val) {
418 phy->ops.write_reg = e1000e_write_phy_reg_bm;
419 phy->ops.read_reg = e1000e_read_phy_reg_bm;
420 ret_val = e1000e_determine_phy_address(hw);
421 if (ret_val) {
422 e_dbg("Cannot determine PHY addr. Erroring out\n");
423 return ret_val;
424 }
425 }
426
427 phy->id = 0;
428 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
429 (i++ < 100)) {
430 msleep(1);
431 ret_val = e1000e_get_phy_id(hw);
432 if (ret_val)
433 return ret_val;
434 }
435
436 /* Verify phy id */
437 switch (phy->id) {
438 case IGP03E1000_E_PHY_ID:
439 phy->type = e1000_phy_igp_3;
440 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
441 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
442 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
443 phy->ops.get_info = e1000e_get_phy_info_igp;
444 phy->ops.check_polarity = e1000_check_polarity_igp;
445 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
446 break;
447 case IFE_E_PHY_ID:
448 case IFE_PLUS_E_PHY_ID:
449 case IFE_C_E_PHY_ID:
450 phy->type = e1000_phy_ife;
451 phy->autoneg_mask = E1000_ALL_NOT_GIG;
452 phy->ops.get_info = e1000_get_phy_info_ife;
453 phy->ops.check_polarity = e1000_check_polarity_ife;
454 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
455 break;
456 case BME1000_E_PHY_ID:
457 phy->type = e1000_phy_bm;
458 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
459 phy->ops.read_reg = e1000e_read_phy_reg_bm;
460 phy->ops.write_reg = e1000e_write_phy_reg_bm;
461 phy->ops.commit = e1000e_phy_sw_reset;
462 phy->ops.get_info = e1000e_get_phy_info_m88;
463 phy->ops.check_polarity = e1000_check_polarity_m88;
464 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
465 break;
466 default:
467 return -E1000_ERR_PHY;
468 break;
469 }
470
471 return 0;
472 }
473
474 /**
475 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
476 * @hw: pointer to the HW structure
477 *
478 * Initialize family-specific NVM parameters and function
479 * pointers.
480 **/
481 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
482 {
483 struct e1000_nvm_info *nvm = &hw->nvm;
484 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
485 u32 gfpreg, sector_base_addr, sector_end_addr;
486 u16 i;
487
488 /* Can't read flash registers if the register set isn't mapped. */
489 if (!hw->flash_address) {
490 e_dbg("ERROR: Flash registers not mapped\n");
491 return -E1000_ERR_CONFIG;
492 }
493
494 nvm->type = e1000_nvm_flash_sw;
495
496 gfpreg = er32flash(ICH_FLASH_GFPREG);
497
498 /*
499 * sector_X_addr is a "sector"-aligned address (4096 bytes)
500 * Add 1 to sector_end_addr since this sector is included in
501 * the overall size.
502 */
503 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
504 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
505
506 /* flash_base_addr is byte-aligned */
507 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
508
509 /*
510 * find total size of the NVM, then cut in half since the total
511 * size represents two separate NVM banks.
512 */
513 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
514 << FLASH_SECTOR_ADDR_SHIFT;
515 nvm->flash_bank_size /= 2;
516 /* Adjust to word count */
517 nvm->flash_bank_size /= sizeof(u16);
518
519 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
520
521 /* Clear shadow ram */
522 for (i = 0; i < nvm->word_size; i++) {
523 dev_spec->shadow_ram[i].modified = false;
524 dev_spec->shadow_ram[i].value = 0xFFFF;
525 }
526
527 return 0;
528 }
529
530 /**
531 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
532 * @hw: pointer to the HW structure
533 *
534 * Initialize family-specific MAC parameters and function
535 * pointers.
536 **/
537 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
538 {
539 struct e1000_hw *hw = &adapter->hw;
540 struct e1000_mac_info *mac = &hw->mac;
541
542 /* Set media type function pointer */
543 hw->phy.media_type = e1000_media_type_copper;
544
545 /* Set mta register count */
546 mac->mta_reg_count = 32;
547 /* Set rar entry count */
548 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
549 if (mac->type == e1000_ich8lan)
550 mac->rar_entry_count--;
551 /* FWSM register */
552 mac->has_fwsm = true;
553 /* ARC subsystem not supported */
554 mac->arc_subsystem_valid = false;
555 /* Adaptive IFS supported */
556 mac->adaptive_ifs = true;
557
558 /* LED operations */
559 switch (mac->type) {
560 case e1000_ich8lan:
561 case e1000_ich9lan:
562 case e1000_ich10lan:
563 /* check management mode */
564 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
565 /* ID LED init */
566 mac->ops.id_led_init = e1000e_id_led_init;
567 /* setup LED */
568 mac->ops.setup_led = e1000e_setup_led_generic;
569 /* cleanup LED */
570 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
571 /* turn on/off LED */
572 mac->ops.led_on = e1000_led_on_ich8lan;
573 mac->ops.led_off = e1000_led_off_ich8lan;
574 break;
575 case e1000_pchlan:
576 case e1000_pch2lan:
577 /* check management mode */
578 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
579 /* ID LED init */
580 mac->ops.id_led_init = e1000_id_led_init_pchlan;
581 /* setup LED */
582 mac->ops.setup_led = e1000_setup_led_pchlan;
583 /* cleanup LED */
584 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
585 /* turn on/off LED */
586 mac->ops.led_on = e1000_led_on_pchlan;
587 mac->ops.led_off = e1000_led_off_pchlan;
588 break;
589 default:
590 break;
591 }
592
593 /* Enable PCS Lock-loss workaround for ICH8 */
594 if (mac->type == e1000_ich8lan)
595 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
596
597 /* Gate automatic PHY configuration by hardware on managed 82579 */
598 if ((mac->type == e1000_pch2lan) &&
599 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
600 e1000_gate_hw_phy_config_ich8lan(hw, true);
601
602 return 0;
603 }
604
605 /**
606 * e1000_set_eee_pchlan - Enable/disable EEE support
607 * @hw: pointer to the HW structure
608 *
609 * Enable/disable EEE based on setting in dev_spec structure. The bits in
610 * the LPI Control register will remain set only if/when link is up.
611 **/
612 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
613 {
614 s32 ret_val = 0;
615 u16 phy_reg;
616
617 if (hw->phy.type != e1000_phy_82579)
618 goto out;
619
620 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
621 if (ret_val)
622 goto out;
623
624 if (hw->dev_spec.ich8lan.eee_disable)
625 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
626 else
627 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
628
629 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
630 out:
631 return ret_val;
632 }
633
634 /**
635 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
636 * @hw: pointer to the HW structure
637 *
638 * Checks to see of the link status of the hardware has changed. If a
639 * change in link status has been detected, then we read the PHY registers
640 * to get the current speed/duplex if link exists.
641 **/
642 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
643 {
644 struct e1000_mac_info *mac = &hw->mac;
645 s32 ret_val;
646 bool link;
647
648 /*
649 * We only want to go out to the PHY registers to see if Auto-Neg
650 * has completed and/or if our link status has changed. The
651 * get_link_status flag is set upon receiving a Link Status
652 * Change or Rx Sequence Error interrupt.
653 */
654 if (!mac->get_link_status) {
655 ret_val = 0;
656 goto out;
657 }
658
659 /*
660 * First we want to see if the MII Status Register reports
661 * link. If so, then we want to get the current speed/duplex
662 * of the PHY.
663 */
664 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
665 if (ret_val)
666 goto out;
667
668 if (hw->mac.type == e1000_pchlan) {
669 ret_val = e1000_k1_gig_workaround_hv(hw, link);
670 if (ret_val)
671 goto out;
672 }
673
674 if (!link)
675 goto out; /* No link detected */
676
677 mac->get_link_status = false;
678
679 if (hw->phy.type == e1000_phy_82578) {
680 ret_val = e1000_link_stall_workaround_hv(hw);
681 if (ret_val)
682 goto out;
683 }
684
685 if (hw->mac.type == e1000_pch2lan) {
686 ret_val = e1000_k1_workaround_lv(hw);
687 if (ret_val)
688 goto out;
689 }
690
691 /*
692 * Check if there was DownShift, must be checked
693 * immediately after link-up
694 */
695 e1000e_check_downshift(hw);
696
697 /* Enable/Disable EEE after link up */
698 ret_val = e1000_set_eee_pchlan(hw);
699 if (ret_val)
700 goto out;
701
702 /*
703 * If we are forcing speed/duplex, then we simply return since
704 * we have already determined whether we have link or not.
705 */
706 if (!mac->autoneg) {
707 ret_val = -E1000_ERR_CONFIG;
708 goto out;
709 }
710
711 /*
712 * Auto-Neg is enabled. Auto Speed Detection takes care
713 * of MAC speed/duplex configuration. So we only need to
714 * configure Collision Distance in the MAC.
715 */
716 e1000e_config_collision_dist(hw);
717
718 /*
719 * Configure Flow Control now that Auto-Neg has completed.
720 * First, we need to restore the desired flow control
721 * settings because we may have had to re-autoneg with a
722 * different link partner.
723 */
724 ret_val = e1000e_config_fc_after_link_up(hw);
725 if (ret_val)
726 e_dbg("Error configuring flow control\n");
727
728 out:
729 return ret_val;
730 }
731
732 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
733 {
734 struct e1000_hw *hw = &adapter->hw;
735 s32 rc;
736
737 rc = e1000_init_mac_params_ich8lan(adapter);
738 if (rc)
739 return rc;
740
741 rc = e1000_init_nvm_params_ich8lan(hw);
742 if (rc)
743 return rc;
744
745 switch (hw->mac.type) {
746 case e1000_ich8lan:
747 case e1000_ich9lan:
748 case e1000_ich10lan:
749 rc = e1000_init_phy_params_ich8lan(hw);
750 break;
751 case e1000_pchlan:
752 case e1000_pch2lan:
753 rc = e1000_init_phy_params_pchlan(hw);
754 break;
755 default:
756 break;
757 }
758 if (rc)
759 return rc;
760
761 if (adapter->hw.phy.type == e1000_phy_ife) {
762 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
763 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
764 }
765
766 if ((adapter->hw.mac.type == e1000_ich8lan) &&
767 (adapter->hw.phy.type == e1000_phy_igp_3))
768 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
769
770 /* Disable EEE by default until IEEE802.3az spec is finalized */
771 if (adapter->flags2 & FLAG2_HAS_EEE)
772 adapter->hw.dev_spec.ich8lan.eee_disable = true;
773
774 return 0;
775 }
776
777 static DEFINE_MUTEX(nvm_mutex);
778
779 /**
780 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
781 * @hw: pointer to the HW structure
782 *
783 * Acquires the mutex for performing NVM operations.
784 **/
785 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
786 {
787 mutex_lock(&nvm_mutex);
788
789 return 0;
790 }
791
792 /**
793 * e1000_release_nvm_ich8lan - Release NVM mutex
794 * @hw: pointer to the HW structure
795 *
796 * Releases the mutex used while performing NVM operations.
797 **/
798 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
799 {
800 mutex_unlock(&nvm_mutex);
801 }
802
803 static DEFINE_MUTEX(swflag_mutex);
804
805 /**
806 * e1000_acquire_swflag_ich8lan - Acquire software control flag
807 * @hw: pointer to the HW structure
808 *
809 * Acquires the software control flag for performing PHY and select
810 * MAC CSR accesses.
811 **/
812 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
813 {
814 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
815 s32 ret_val = 0;
816
817 mutex_lock(&swflag_mutex);
818
819 while (timeout) {
820 extcnf_ctrl = er32(EXTCNF_CTRL);
821 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
822 break;
823
824 mdelay(1);
825 timeout--;
826 }
827
828 if (!timeout) {
829 e_dbg("SW/FW/HW has locked the resource for too long.\n");
830 ret_val = -E1000_ERR_CONFIG;
831 goto out;
832 }
833
834 timeout = SW_FLAG_TIMEOUT;
835
836 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
837 ew32(EXTCNF_CTRL, extcnf_ctrl);
838
839 while (timeout) {
840 extcnf_ctrl = er32(EXTCNF_CTRL);
841 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
842 break;
843
844 mdelay(1);
845 timeout--;
846 }
847
848 if (!timeout) {
849 e_dbg("Failed to acquire the semaphore.\n");
850 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
851 ew32(EXTCNF_CTRL, extcnf_ctrl);
852 ret_val = -E1000_ERR_CONFIG;
853 goto out;
854 }
855
856 out:
857 if (ret_val)
858 mutex_unlock(&swflag_mutex);
859
860 return ret_val;
861 }
862
863 /**
864 * e1000_release_swflag_ich8lan - Release software control flag
865 * @hw: pointer to the HW structure
866 *
867 * Releases the software control flag for performing PHY and select
868 * MAC CSR accesses.
869 **/
870 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
871 {
872 u32 extcnf_ctrl;
873
874 extcnf_ctrl = er32(EXTCNF_CTRL);
875 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
876 ew32(EXTCNF_CTRL, extcnf_ctrl);
877
878 mutex_unlock(&swflag_mutex);
879 }
880
881 /**
882 * e1000_check_mng_mode_ich8lan - Checks management mode
883 * @hw: pointer to the HW structure
884 *
885 * This checks if the adapter has any manageability enabled.
886 * This is a function pointer entry point only called by read/write
887 * routines for the PHY and NVM parts.
888 **/
889 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
890 {
891 u32 fwsm;
892
893 fwsm = er32(FWSM);
894 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
895 ((fwsm & E1000_FWSM_MODE_MASK) ==
896 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
897 }
898
899 /**
900 * e1000_check_mng_mode_pchlan - Checks management mode
901 * @hw: pointer to the HW structure
902 *
903 * This checks if the adapter has iAMT enabled.
904 * This is a function pointer entry point only called by read/write
905 * routines for the PHY and NVM parts.
906 **/
907 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
908 {
909 u32 fwsm;
910
911 fwsm = er32(FWSM);
912 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
913 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
914 }
915
916 /**
917 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
918 * @hw: pointer to the HW structure
919 *
920 * Checks if firmware is blocking the reset of the PHY.
921 * This is a function pointer entry point only called by
922 * reset routines.
923 **/
924 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
925 {
926 u32 fwsm;
927
928 fwsm = er32(FWSM);
929
930 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
931 }
932
933 /**
934 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
935 * @hw: pointer to the HW structure
936 *
937 * Assumes semaphore already acquired.
938 *
939 **/
940 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
941 {
942 u16 phy_data;
943 u32 strap = er32(STRAP);
944 s32 ret_val = 0;
945
946 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
947
948 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
949 if (ret_val)
950 goto out;
951
952 phy_data &= ~HV_SMB_ADDR_MASK;
953 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
954 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
955 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
956
957 out:
958 return ret_val;
959 }
960
961 /**
962 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
963 * @hw: pointer to the HW structure
964 *
965 * SW should configure the LCD from the NVM extended configuration region
966 * as a workaround for certain parts.
967 **/
968 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
969 {
970 struct e1000_phy_info *phy = &hw->phy;
971 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
972 s32 ret_val = 0;
973 u16 word_addr, reg_data, reg_addr, phy_page = 0;
974
975 /*
976 * Initialize the PHY from the NVM on ICH platforms. This
977 * is needed due to an issue where the NVM configuration is
978 * not properly autoloaded after power transitions.
979 * Therefore, after each PHY reset, we will load the
980 * configuration data out of the NVM manually.
981 */
982 switch (hw->mac.type) {
983 case e1000_ich8lan:
984 if (phy->type != e1000_phy_igp_3)
985 return ret_val;
986
987 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
988 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
989 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
990 break;
991 }
992 /* Fall-thru */
993 case e1000_pchlan:
994 case e1000_pch2lan:
995 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
996 break;
997 default:
998 return ret_val;
999 }
1000
1001 ret_val = hw->phy.ops.acquire(hw);
1002 if (ret_val)
1003 return ret_val;
1004
1005 data = er32(FEXTNVM);
1006 if (!(data & sw_cfg_mask))
1007 goto out;
1008
1009 /*
1010 * Make sure HW does not configure LCD from PHY
1011 * extended configuration before SW configuration
1012 */
1013 data = er32(EXTCNF_CTRL);
1014 if (!(hw->mac.type == e1000_pch2lan)) {
1015 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1016 goto out;
1017 }
1018
1019 cnf_size = er32(EXTCNF_SIZE);
1020 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1021 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1022 if (!cnf_size)
1023 goto out;
1024
1025 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1026 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1027
1028 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1029 (hw->mac.type == e1000_pchlan)) ||
1030 (hw->mac.type == e1000_pch2lan)) {
1031 /*
1032 * HW configures the SMBus address and LEDs when the
1033 * OEM and LCD Write Enable bits are set in the NVM.
1034 * When both NVM bits are cleared, SW will configure
1035 * them instead.
1036 */
1037 ret_val = e1000_write_smbus_addr(hw);
1038 if (ret_val)
1039 goto out;
1040
1041 data = er32(LEDCTL);
1042 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1043 (u16)data);
1044 if (ret_val)
1045 goto out;
1046 }
1047
1048 /* Configure LCD from extended configuration region. */
1049
1050 /* cnf_base_addr is in DWORD */
1051 word_addr = (u16)(cnf_base_addr << 1);
1052
1053 for (i = 0; i < cnf_size; i++) {
1054 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1055 &reg_data);
1056 if (ret_val)
1057 goto out;
1058
1059 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1060 1, &reg_addr);
1061 if (ret_val)
1062 goto out;
1063
1064 /* Save off the PHY page for future writes. */
1065 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1066 phy_page = reg_data;
1067 continue;
1068 }
1069
1070 reg_addr &= PHY_REG_MASK;
1071 reg_addr |= phy_page;
1072
1073 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1074 reg_data);
1075 if (ret_val)
1076 goto out;
1077 }
1078
1079 out:
1080 hw->phy.ops.release(hw);
1081 return ret_val;
1082 }
1083
1084 /**
1085 * e1000_k1_gig_workaround_hv - K1 Si workaround
1086 * @hw: pointer to the HW structure
1087 * @link: link up bool flag
1088 *
1089 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1090 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1091 * If link is down, the function will restore the default K1 setting located
1092 * in the NVM.
1093 **/
1094 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1095 {
1096 s32 ret_val = 0;
1097 u16 status_reg = 0;
1098 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1099
1100 if (hw->mac.type != e1000_pchlan)
1101 goto out;
1102
1103 /* Wrap the whole flow with the sw flag */
1104 ret_val = hw->phy.ops.acquire(hw);
1105 if (ret_val)
1106 goto out;
1107
1108 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1109 if (link) {
1110 if (hw->phy.type == e1000_phy_82578) {
1111 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1112 &status_reg);
1113 if (ret_val)
1114 goto release;
1115
1116 status_reg &= BM_CS_STATUS_LINK_UP |
1117 BM_CS_STATUS_RESOLVED |
1118 BM_CS_STATUS_SPEED_MASK;
1119
1120 if (status_reg == (BM_CS_STATUS_LINK_UP |
1121 BM_CS_STATUS_RESOLVED |
1122 BM_CS_STATUS_SPEED_1000))
1123 k1_enable = false;
1124 }
1125
1126 if (hw->phy.type == e1000_phy_82577) {
1127 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1128 &status_reg);
1129 if (ret_val)
1130 goto release;
1131
1132 status_reg &= HV_M_STATUS_LINK_UP |
1133 HV_M_STATUS_AUTONEG_COMPLETE |
1134 HV_M_STATUS_SPEED_MASK;
1135
1136 if (status_reg == (HV_M_STATUS_LINK_UP |
1137 HV_M_STATUS_AUTONEG_COMPLETE |
1138 HV_M_STATUS_SPEED_1000))
1139 k1_enable = false;
1140 }
1141
1142 /* Link stall fix for link up */
1143 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1144 0x0100);
1145 if (ret_val)
1146 goto release;
1147
1148 } else {
1149 /* Link stall fix for link down */
1150 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1151 0x4100);
1152 if (ret_val)
1153 goto release;
1154 }
1155
1156 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1157
1158 release:
1159 hw->phy.ops.release(hw);
1160 out:
1161 return ret_val;
1162 }
1163
1164 /**
1165 * e1000_configure_k1_ich8lan - Configure K1 power state
1166 * @hw: pointer to the HW structure
1167 * @enable: K1 state to configure
1168 *
1169 * Configure the K1 power state based on the provided parameter.
1170 * Assumes semaphore already acquired.
1171 *
1172 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1173 **/
1174 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1175 {
1176 s32 ret_val = 0;
1177 u32 ctrl_reg = 0;
1178 u32 ctrl_ext = 0;
1179 u32 reg = 0;
1180 u16 kmrn_reg = 0;
1181
1182 ret_val = e1000e_read_kmrn_reg_locked(hw,
1183 E1000_KMRNCTRLSTA_K1_CONFIG,
1184 &kmrn_reg);
1185 if (ret_val)
1186 goto out;
1187
1188 if (k1_enable)
1189 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1190 else
1191 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1192
1193 ret_val = e1000e_write_kmrn_reg_locked(hw,
1194 E1000_KMRNCTRLSTA_K1_CONFIG,
1195 kmrn_reg);
1196 if (ret_val)
1197 goto out;
1198
1199 udelay(20);
1200 ctrl_ext = er32(CTRL_EXT);
1201 ctrl_reg = er32(CTRL);
1202
1203 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1204 reg |= E1000_CTRL_FRCSPD;
1205 ew32(CTRL, reg);
1206
1207 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1208 udelay(20);
1209 ew32(CTRL, ctrl_reg);
1210 ew32(CTRL_EXT, ctrl_ext);
1211 udelay(20);
1212
1213 out:
1214 return ret_val;
1215 }
1216
1217 /**
1218 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1219 * @hw: pointer to the HW structure
1220 * @d0_state: boolean if entering d0 or d3 device state
1221 *
1222 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1223 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1224 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1225 **/
1226 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1227 {
1228 s32 ret_val = 0;
1229 u32 mac_reg;
1230 u16 oem_reg;
1231
1232 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1233 return ret_val;
1234
1235 ret_val = hw->phy.ops.acquire(hw);
1236 if (ret_val)
1237 return ret_val;
1238
1239 if (!(hw->mac.type == e1000_pch2lan)) {
1240 mac_reg = er32(EXTCNF_CTRL);
1241 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1242 goto out;
1243 }
1244
1245 mac_reg = er32(FEXTNVM);
1246 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1247 goto out;
1248
1249 mac_reg = er32(PHY_CTRL);
1250
1251 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1252 if (ret_val)
1253 goto out;
1254
1255 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1256
1257 if (d0_state) {
1258 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1259 oem_reg |= HV_OEM_BITS_GBE_DIS;
1260
1261 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1262 oem_reg |= HV_OEM_BITS_LPLU;
1263 } else {
1264 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1265 oem_reg |= HV_OEM_BITS_GBE_DIS;
1266
1267 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1268 oem_reg |= HV_OEM_BITS_LPLU;
1269 }
1270 /* Restart auto-neg to activate the bits */
1271 if (!e1000_check_reset_block(hw))
1272 oem_reg |= HV_OEM_BITS_RESTART_AN;
1273 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1274
1275 out:
1276 hw->phy.ops.release(hw);
1277
1278 return ret_val;
1279 }
1280
1281
1282 /**
1283 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1284 * @hw: pointer to the HW structure
1285 **/
1286 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1287 {
1288 s32 ret_val;
1289 u16 data;
1290
1291 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1292 if (ret_val)
1293 return ret_val;
1294
1295 data |= HV_KMRN_MDIO_SLOW;
1296
1297 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1298
1299 return ret_val;
1300 }
1301
1302 /**
1303 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1304 * done after every PHY reset.
1305 **/
1306 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1307 {
1308 s32 ret_val = 0;
1309 u16 phy_data;
1310
1311 if (hw->mac.type != e1000_pchlan)
1312 return ret_val;
1313
1314 /* Set MDIO slow mode before any other MDIO access */
1315 if (hw->phy.type == e1000_phy_82577) {
1316 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1317 if (ret_val)
1318 goto out;
1319 }
1320
1321 if (((hw->phy.type == e1000_phy_82577) &&
1322 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1323 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1324 /* Disable generation of early preamble */
1325 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1326 if (ret_val)
1327 return ret_val;
1328
1329 /* Preamble tuning for SSC */
1330 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1331 if (ret_val)
1332 return ret_val;
1333 }
1334
1335 if (hw->phy.type == e1000_phy_82578) {
1336 /*
1337 * Return registers to default by doing a soft reset then
1338 * writing 0x3140 to the control register.
1339 */
1340 if (hw->phy.revision < 2) {
1341 e1000e_phy_sw_reset(hw);
1342 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1343 }
1344 }
1345
1346 /* Select page 0 */
1347 ret_val = hw->phy.ops.acquire(hw);
1348 if (ret_val)
1349 return ret_val;
1350
1351 hw->phy.addr = 1;
1352 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1353 hw->phy.ops.release(hw);
1354 if (ret_val)
1355 goto out;
1356
1357 /*
1358 * Configure the K1 Si workaround during phy reset assuming there is
1359 * link so that it disables K1 if link is in 1Gbps.
1360 */
1361 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1362 if (ret_val)
1363 goto out;
1364
1365 /* Workaround for link disconnects on a busy hub in half duplex */
1366 ret_val = hw->phy.ops.acquire(hw);
1367 if (ret_val)
1368 goto out;
1369 ret_val = hw->phy.ops.read_reg_locked(hw,
1370 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1371 &phy_data);
1372 if (ret_val)
1373 goto release;
1374 ret_val = hw->phy.ops.write_reg_locked(hw,
1375 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1376 phy_data & 0x00FF);
1377 release:
1378 hw->phy.ops.release(hw);
1379 out:
1380 return ret_val;
1381 }
1382
1383 /**
1384 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1385 * @hw: pointer to the HW structure
1386 **/
1387 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1388 {
1389 u32 mac_reg;
1390 u16 i;
1391
1392 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1393 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1394 mac_reg = er32(RAL(i));
1395 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1396 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1397 mac_reg = er32(RAH(i));
1398 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1399 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1400 }
1401 }
1402
1403 /**
1404 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1405 * with 82579 PHY
1406 * @hw: pointer to the HW structure
1407 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1408 **/
1409 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1410 {
1411 s32 ret_val = 0;
1412 u16 phy_reg, data;
1413 u32 mac_reg;
1414 u16 i;
1415
1416 if (hw->mac.type != e1000_pch2lan)
1417 goto out;
1418
1419 /* disable Rx path while enabling/disabling workaround */
1420 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1421 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1422 if (ret_val)
1423 goto out;
1424
1425 if (enable) {
1426 /*
1427 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1428 * SHRAL/H) and initial CRC values to the MAC
1429 */
1430 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1431 u8 mac_addr[ETH_ALEN] = {0};
1432 u32 addr_high, addr_low;
1433
1434 addr_high = er32(RAH(i));
1435 if (!(addr_high & E1000_RAH_AV))
1436 continue;
1437 addr_low = er32(RAL(i));
1438 mac_addr[0] = (addr_low & 0xFF);
1439 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1440 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1441 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1442 mac_addr[4] = (addr_high & 0xFF);
1443 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1444
1445 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1446 }
1447
1448 /* Write Rx addresses to the PHY */
1449 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1450
1451 /* Enable jumbo frame workaround in the MAC */
1452 mac_reg = er32(FFLT_DBG);
1453 mac_reg &= ~(1 << 14);
1454 mac_reg |= (7 << 15);
1455 ew32(FFLT_DBG, mac_reg);
1456
1457 mac_reg = er32(RCTL);
1458 mac_reg |= E1000_RCTL_SECRC;
1459 ew32(RCTL, mac_reg);
1460
1461 ret_val = e1000e_read_kmrn_reg(hw,
1462 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1463 &data);
1464 if (ret_val)
1465 goto out;
1466 ret_val = e1000e_write_kmrn_reg(hw,
1467 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1468 data | (1 << 0));
1469 if (ret_val)
1470 goto out;
1471 ret_val = e1000e_read_kmrn_reg(hw,
1472 E1000_KMRNCTRLSTA_HD_CTRL,
1473 &data);
1474 if (ret_val)
1475 goto out;
1476 data &= ~(0xF << 8);
1477 data |= (0xB << 8);
1478 ret_val = e1000e_write_kmrn_reg(hw,
1479 E1000_KMRNCTRLSTA_HD_CTRL,
1480 data);
1481 if (ret_val)
1482 goto out;
1483
1484 /* Enable jumbo frame workaround in the PHY */
1485 e1e_rphy(hw, PHY_REG(769, 23), &data);
1486 data &= ~(0x7F << 5);
1487 data |= (0x37 << 5);
1488 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1489 if (ret_val)
1490 goto out;
1491 e1e_rphy(hw, PHY_REG(769, 16), &data);
1492 data &= ~(1 << 13);
1493 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1494 if (ret_val)
1495 goto out;
1496 e1e_rphy(hw, PHY_REG(776, 20), &data);
1497 data &= ~(0x3FF << 2);
1498 data |= (0x1A << 2);
1499 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1500 if (ret_val)
1501 goto out;
1502 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1503 if (ret_val)
1504 goto out;
1505 e1e_rphy(hw, HV_PM_CTRL, &data);
1506 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1507 if (ret_val)
1508 goto out;
1509 } else {
1510 /* Write MAC register values back to h/w defaults */
1511 mac_reg = er32(FFLT_DBG);
1512 mac_reg &= ~(0xF << 14);
1513 ew32(FFLT_DBG, mac_reg);
1514
1515 mac_reg = er32(RCTL);
1516 mac_reg &= ~E1000_RCTL_SECRC;
1517 ew32(RCTL, mac_reg);
1518
1519 ret_val = e1000e_read_kmrn_reg(hw,
1520 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1521 &data);
1522 if (ret_val)
1523 goto out;
1524 ret_val = e1000e_write_kmrn_reg(hw,
1525 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1526 data & ~(1 << 0));
1527 if (ret_val)
1528 goto out;
1529 ret_val = e1000e_read_kmrn_reg(hw,
1530 E1000_KMRNCTRLSTA_HD_CTRL,
1531 &data);
1532 if (ret_val)
1533 goto out;
1534 data &= ~(0xF << 8);
1535 data |= (0xB << 8);
1536 ret_val = e1000e_write_kmrn_reg(hw,
1537 E1000_KMRNCTRLSTA_HD_CTRL,
1538 data);
1539 if (ret_val)
1540 goto out;
1541
1542 /* Write PHY register values back to h/w defaults */
1543 e1e_rphy(hw, PHY_REG(769, 23), &data);
1544 data &= ~(0x7F << 5);
1545 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1546 if (ret_val)
1547 goto out;
1548 e1e_rphy(hw, PHY_REG(769, 16), &data);
1549 data |= (1 << 13);
1550 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1551 if (ret_val)
1552 goto out;
1553 e1e_rphy(hw, PHY_REG(776, 20), &data);
1554 data &= ~(0x3FF << 2);
1555 data |= (0x8 << 2);
1556 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1557 if (ret_val)
1558 goto out;
1559 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1560 if (ret_val)
1561 goto out;
1562 e1e_rphy(hw, HV_PM_CTRL, &data);
1563 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1564 if (ret_val)
1565 goto out;
1566 }
1567
1568 /* re-enable Rx path after enabling/disabling workaround */
1569 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1570
1571 out:
1572 return ret_val;
1573 }
1574
1575 /**
1576 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1577 * done after every PHY reset.
1578 **/
1579 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1580 {
1581 s32 ret_val = 0;
1582
1583 if (hw->mac.type != e1000_pch2lan)
1584 goto out;
1585
1586 /* Set MDIO slow mode before any other MDIO access */
1587 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1588
1589 out:
1590 return ret_val;
1591 }
1592
1593 /**
1594 * e1000_k1_gig_workaround_lv - K1 Si workaround
1595 * @hw: pointer to the HW structure
1596 *
1597 * Workaround to set the K1 beacon duration for 82579 parts
1598 **/
1599 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1600 {
1601 s32 ret_val = 0;
1602 u16 status_reg = 0;
1603 u32 mac_reg;
1604
1605 if (hw->mac.type != e1000_pch2lan)
1606 goto out;
1607
1608 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1609 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1610 if (ret_val)
1611 goto out;
1612
1613 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1614 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1615 mac_reg = er32(FEXTNVM4);
1616 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1617
1618 if (status_reg & HV_M_STATUS_SPEED_1000)
1619 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1620 else
1621 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1622
1623 ew32(FEXTNVM4, mac_reg);
1624 }
1625
1626 out:
1627 return ret_val;
1628 }
1629
1630 /**
1631 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1632 * @hw: pointer to the HW structure
1633 * @gate: boolean set to true to gate, false to ungate
1634 *
1635 * Gate/ungate the automatic PHY configuration via hardware; perform
1636 * the configuration via software instead.
1637 **/
1638 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1639 {
1640 u32 extcnf_ctrl;
1641
1642 if (hw->mac.type != e1000_pch2lan)
1643 return;
1644
1645 extcnf_ctrl = er32(EXTCNF_CTRL);
1646
1647 if (gate)
1648 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1649 else
1650 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1651
1652 ew32(EXTCNF_CTRL, extcnf_ctrl);
1653 return;
1654 }
1655
1656 /**
1657 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1658 * @hw: pointer to the HW structure
1659 *
1660 * Check the appropriate indication the MAC has finished configuring the
1661 * PHY after a software reset.
1662 **/
1663 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1664 {
1665 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1666
1667 /* Wait for basic configuration completes before proceeding */
1668 do {
1669 data = er32(STATUS);
1670 data &= E1000_STATUS_LAN_INIT_DONE;
1671 udelay(100);
1672 } while ((!data) && --loop);
1673
1674 /*
1675 * If basic configuration is incomplete before the above loop
1676 * count reaches 0, loading the configuration from NVM will
1677 * leave the PHY in a bad state possibly resulting in no link.
1678 */
1679 if (loop == 0)
1680 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1681
1682 /* Clear the Init Done bit for the next init event */
1683 data = er32(STATUS);
1684 data &= ~E1000_STATUS_LAN_INIT_DONE;
1685 ew32(STATUS, data);
1686 }
1687
1688 /**
1689 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1690 * @hw: pointer to the HW structure
1691 **/
1692 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1693 {
1694 s32 ret_val = 0;
1695 u16 reg;
1696
1697 if (e1000_check_reset_block(hw))
1698 goto out;
1699
1700 /* Allow time for h/w to get to quiescent state after reset */
1701 msleep(10);
1702
1703 /* Perform any necessary post-reset workarounds */
1704 switch (hw->mac.type) {
1705 case e1000_pchlan:
1706 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1707 if (ret_val)
1708 goto out;
1709 break;
1710 case e1000_pch2lan:
1711 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1712 if (ret_val)
1713 goto out;
1714 break;
1715 default:
1716 break;
1717 }
1718
1719 /* Dummy read to clear the phy wakeup bit after lcd reset */
1720 if (hw->mac.type >= e1000_pchlan)
1721 e1e_rphy(hw, BM_WUC, &reg);
1722
1723 /* Configure the LCD with the extended configuration region in NVM */
1724 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1725 if (ret_val)
1726 goto out;
1727
1728 /* Configure the LCD with the OEM bits in NVM */
1729 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1730
1731 if (hw->mac.type == e1000_pch2lan) {
1732 /* Ungate automatic PHY configuration on non-managed 82579 */
1733 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1734 msleep(10);
1735 e1000_gate_hw_phy_config_ich8lan(hw, false);
1736 }
1737
1738 /* Set EEE LPI Update Timer to 200usec */
1739 ret_val = hw->phy.ops.acquire(hw);
1740 if (ret_val)
1741 goto out;
1742 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1743 I82579_LPI_UPDATE_TIMER);
1744 if (ret_val)
1745 goto release;
1746 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1747 0x1387);
1748 release:
1749 hw->phy.ops.release(hw);
1750 }
1751
1752 out:
1753 return ret_val;
1754 }
1755
1756 /**
1757 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1758 * @hw: pointer to the HW structure
1759 *
1760 * Resets the PHY
1761 * This is a function pointer entry point called by drivers
1762 * or other shared routines.
1763 **/
1764 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1765 {
1766 s32 ret_val = 0;
1767
1768 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1769 if ((hw->mac.type == e1000_pch2lan) &&
1770 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1771 e1000_gate_hw_phy_config_ich8lan(hw, true);
1772
1773 ret_val = e1000e_phy_hw_reset_generic(hw);
1774 if (ret_val)
1775 goto out;
1776
1777 ret_val = e1000_post_phy_reset_ich8lan(hw);
1778
1779 out:
1780 return ret_val;
1781 }
1782
1783 /**
1784 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1785 * @hw: pointer to the HW structure
1786 * @active: true to enable LPLU, false to disable
1787 *
1788 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1789 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1790 * the phy speed. This function will manually set the LPLU bit and restart
1791 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1792 * since it configures the same bit.
1793 **/
1794 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1795 {
1796 s32 ret_val = 0;
1797 u16 oem_reg;
1798
1799 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1800 if (ret_val)
1801 goto out;
1802
1803 if (active)
1804 oem_reg |= HV_OEM_BITS_LPLU;
1805 else
1806 oem_reg &= ~HV_OEM_BITS_LPLU;
1807
1808 oem_reg |= HV_OEM_BITS_RESTART_AN;
1809 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1810
1811 out:
1812 return ret_val;
1813 }
1814
1815 /**
1816 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1817 * @hw: pointer to the HW structure
1818 * @active: true to enable LPLU, false to disable
1819 *
1820 * Sets the LPLU D0 state according to the active flag. When
1821 * activating LPLU this function also disables smart speed
1822 * and vice versa. LPLU will not be activated unless the
1823 * device autonegotiation advertisement meets standards of
1824 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1825 * This is a function pointer entry point only called by
1826 * PHY setup routines.
1827 **/
1828 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1829 {
1830 struct e1000_phy_info *phy = &hw->phy;
1831 u32 phy_ctrl;
1832 s32 ret_val = 0;
1833 u16 data;
1834
1835 if (phy->type == e1000_phy_ife)
1836 return ret_val;
1837
1838 phy_ctrl = er32(PHY_CTRL);
1839
1840 if (active) {
1841 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1842 ew32(PHY_CTRL, phy_ctrl);
1843
1844 if (phy->type != e1000_phy_igp_3)
1845 return 0;
1846
1847 /*
1848 * Call gig speed drop workaround on LPLU before accessing
1849 * any PHY registers
1850 */
1851 if (hw->mac.type == e1000_ich8lan)
1852 e1000e_gig_downshift_workaround_ich8lan(hw);
1853
1854 /* When LPLU is enabled, we should disable SmartSpeed */
1855 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1856 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1857 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1858 if (ret_val)
1859 return ret_val;
1860 } else {
1861 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1862 ew32(PHY_CTRL, phy_ctrl);
1863
1864 if (phy->type != e1000_phy_igp_3)
1865 return 0;
1866
1867 /*
1868 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1869 * during Dx states where the power conservation is most
1870 * important. During driver activity we should enable
1871 * SmartSpeed, so performance is maintained.
1872 */
1873 if (phy->smart_speed == e1000_smart_speed_on) {
1874 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1875 &data);
1876 if (ret_val)
1877 return ret_val;
1878
1879 data |= IGP01E1000_PSCFR_SMART_SPEED;
1880 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1881 data);
1882 if (ret_val)
1883 return ret_val;
1884 } else if (phy->smart_speed == e1000_smart_speed_off) {
1885 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1886 &data);
1887 if (ret_val)
1888 return ret_val;
1889
1890 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1891 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1892 data);
1893 if (ret_val)
1894 return ret_val;
1895 }
1896 }
1897
1898 return 0;
1899 }
1900
1901 /**
1902 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1903 * @hw: pointer to the HW structure
1904 * @active: true to enable LPLU, false to disable
1905 *
1906 * Sets the LPLU D3 state according to the active flag. When
1907 * activating LPLU this function also disables smart speed
1908 * and vice versa. LPLU will not be activated unless the
1909 * device autonegotiation advertisement meets standards of
1910 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1911 * This is a function pointer entry point only called by
1912 * PHY setup routines.
1913 **/
1914 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1915 {
1916 struct e1000_phy_info *phy = &hw->phy;
1917 u32 phy_ctrl;
1918 s32 ret_val;
1919 u16 data;
1920
1921 phy_ctrl = er32(PHY_CTRL);
1922
1923 if (!active) {
1924 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1925 ew32(PHY_CTRL, phy_ctrl);
1926
1927 if (phy->type != e1000_phy_igp_3)
1928 return 0;
1929
1930 /*
1931 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1932 * during Dx states where the power conservation is most
1933 * important. During driver activity we should enable
1934 * SmartSpeed, so performance is maintained.
1935 */
1936 if (phy->smart_speed == e1000_smart_speed_on) {
1937 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1938 &data);
1939 if (ret_val)
1940 return ret_val;
1941
1942 data |= IGP01E1000_PSCFR_SMART_SPEED;
1943 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1944 data);
1945 if (ret_val)
1946 return ret_val;
1947 } else if (phy->smart_speed == e1000_smart_speed_off) {
1948 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1949 &data);
1950 if (ret_val)
1951 return ret_val;
1952
1953 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1954 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1955 data);
1956 if (ret_val)
1957 return ret_val;
1958 }
1959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1962 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1963 ew32(PHY_CTRL, phy_ctrl);
1964
1965 if (phy->type != e1000_phy_igp_3)
1966 return 0;
1967
1968 /*
1969 * Call gig speed drop workaround on LPLU before accessing
1970 * any PHY registers
1971 */
1972 if (hw->mac.type == e1000_ich8lan)
1973 e1000e_gig_downshift_workaround_ich8lan(hw);
1974
1975 /* When LPLU is enabled, we should disable SmartSpeed */
1976 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1977 if (ret_val)
1978 return ret_val;
1979
1980 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1981 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1982 }
1983
1984 return 0;
1985 }
1986
1987 /**
1988 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1989 * @hw: pointer to the HW structure
1990 * @bank: pointer to the variable that returns the active bank
1991 *
1992 * Reads signature byte from the NVM using the flash access registers.
1993 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1994 **/
1995 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1996 {
1997 u32 eecd;
1998 struct e1000_nvm_info *nvm = &hw->nvm;
1999 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2000 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2001 u8 sig_byte = 0;
2002 s32 ret_val = 0;
2003
2004 switch (hw->mac.type) {
2005 case e1000_ich8lan:
2006 case e1000_ich9lan:
2007 eecd = er32(EECD);
2008 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2009 E1000_EECD_SEC1VAL_VALID_MASK) {
2010 if (eecd & E1000_EECD_SEC1VAL)
2011 *bank = 1;
2012 else
2013 *bank = 0;
2014
2015 return 0;
2016 }
2017 e_dbg("Unable to determine valid NVM bank via EEC - "
2018 "reading flash signature\n");
2019 /* fall-thru */
2020 default:
2021 /* set bank to 0 in case flash read fails */
2022 *bank = 0;
2023
2024 /* Check bank 0 */
2025 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2026 &sig_byte);
2027 if (ret_val)
2028 return ret_val;
2029 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2030 E1000_ICH_NVM_SIG_VALUE) {
2031 *bank = 0;
2032 return 0;
2033 }
2034
2035 /* Check bank 1 */
2036 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2037 bank1_offset,
2038 &sig_byte);
2039 if (ret_val)
2040 return ret_val;
2041 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2042 E1000_ICH_NVM_SIG_VALUE) {
2043 *bank = 1;
2044 return 0;
2045 }
2046
2047 e_dbg("ERROR: No valid NVM bank present\n");
2048 return -E1000_ERR_NVM;
2049 }
2050
2051 return 0;
2052 }
2053
2054 /**
2055 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2056 * @hw: pointer to the HW structure
2057 * @offset: The offset (in bytes) of the word(s) to read.
2058 * @words: Size of data to read in words
2059 * @data: Pointer to the word(s) to read at offset.
2060 *
2061 * Reads a word(s) from the NVM using the flash access registers.
2062 **/
2063 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2064 u16 *data)
2065 {
2066 struct e1000_nvm_info *nvm = &hw->nvm;
2067 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2068 u32 act_offset;
2069 s32 ret_val = 0;
2070 u32 bank = 0;
2071 u16 i, word;
2072
2073 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2074 (words == 0)) {
2075 e_dbg("nvm parameter(s) out of bounds\n");
2076 ret_val = -E1000_ERR_NVM;
2077 goto out;
2078 }
2079
2080 nvm->ops.acquire(hw);
2081
2082 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2083 if (ret_val) {
2084 e_dbg("Could not detect valid bank, assuming bank 0\n");
2085 bank = 0;
2086 }
2087
2088 act_offset = (bank) ? nvm->flash_bank_size : 0;
2089 act_offset += offset;
2090
2091 ret_val = 0;
2092 for (i = 0; i < words; i++) {
2093 if ((dev_spec->shadow_ram) &&
2094 (dev_spec->shadow_ram[offset+i].modified)) {
2095 data[i] = dev_spec->shadow_ram[offset+i].value;
2096 } else {
2097 ret_val = e1000_read_flash_word_ich8lan(hw,
2098 act_offset + i,
2099 &word);
2100 if (ret_val)
2101 break;
2102 data[i] = word;
2103 }
2104 }
2105
2106 nvm->ops.release(hw);
2107
2108 out:
2109 if (ret_val)
2110 e_dbg("NVM read error: %d\n", ret_val);
2111
2112 return ret_val;
2113 }
2114
2115 /**
2116 * e1000_flash_cycle_init_ich8lan - Initialize flash
2117 * @hw: pointer to the HW structure
2118 *
2119 * This function does initial flash setup so that a new read/write/erase cycle
2120 * can be started.
2121 **/
2122 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2123 {
2124 union ich8_hws_flash_status hsfsts;
2125 s32 ret_val = -E1000_ERR_NVM;
2126
2127 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2128
2129 /* Check if the flash descriptor is valid */
2130 if (hsfsts.hsf_status.fldesvalid == 0) {
2131 e_dbg("Flash descriptor invalid. "
2132 "SW Sequencing must be used.\n");
2133 return -E1000_ERR_NVM;
2134 }
2135
2136 /* Clear FCERR and DAEL in hw status by writing 1 */
2137 hsfsts.hsf_status.flcerr = 1;
2138 hsfsts.hsf_status.dael = 1;
2139
2140 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2141
2142 /*
2143 * Either we should have a hardware SPI cycle in progress
2144 * bit to check against, in order to start a new cycle or
2145 * FDONE bit should be changed in the hardware so that it
2146 * is 1 after hardware reset, which can then be used as an
2147 * indication whether a cycle is in progress or has been
2148 * completed.
2149 */
2150
2151 if (hsfsts.hsf_status.flcinprog == 0) {
2152 /*
2153 * There is no cycle running at present,
2154 * so we can start a cycle.
2155 * Begin by setting Flash Cycle Done.
2156 */
2157 hsfsts.hsf_status.flcdone = 1;
2158 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2159 ret_val = 0;
2160 } else {
2161 s32 i = 0;
2162
2163 /*
2164 * Otherwise poll for sometime so the current
2165 * cycle has a chance to end before giving up.
2166 */
2167 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2168 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2169 if (hsfsts.hsf_status.flcinprog == 0) {
2170 ret_val = 0;
2171 break;
2172 }
2173 udelay(1);
2174 }
2175 if (ret_val == 0) {
2176 /*
2177 * Successful in waiting for previous cycle to timeout,
2178 * now set the Flash Cycle Done.
2179 */
2180 hsfsts.hsf_status.flcdone = 1;
2181 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2182 } else {
2183 e_dbg("Flash controller busy, cannot get access\n");
2184 }
2185 }
2186
2187 return ret_val;
2188 }
2189
2190 /**
2191 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2192 * @hw: pointer to the HW structure
2193 * @timeout: maximum time to wait for completion
2194 *
2195 * This function starts a flash cycle and waits for its completion.
2196 **/
2197 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2198 {
2199 union ich8_hws_flash_ctrl hsflctl;
2200 union ich8_hws_flash_status hsfsts;
2201 s32 ret_val = -E1000_ERR_NVM;
2202 u32 i = 0;
2203
2204 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2205 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2206 hsflctl.hsf_ctrl.flcgo = 1;
2207 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2208
2209 /* wait till FDONE bit is set to 1 */
2210 do {
2211 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2212 if (hsfsts.hsf_status.flcdone == 1)
2213 break;
2214 udelay(1);
2215 } while (i++ < timeout);
2216
2217 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2218 return 0;
2219
2220 return ret_val;
2221 }
2222
2223 /**
2224 * e1000_read_flash_word_ich8lan - Read word from flash
2225 * @hw: pointer to the HW structure
2226 * @offset: offset to data location
2227 * @data: pointer to the location for storing the data
2228 *
2229 * Reads the flash word at offset into data. Offset is converted
2230 * to bytes before read.
2231 **/
2232 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2233 u16 *data)
2234 {
2235 /* Must convert offset into bytes. */
2236 offset <<= 1;
2237
2238 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2239 }
2240
2241 /**
2242 * e1000_read_flash_byte_ich8lan - Read byte from flash
2243 * @hw: pointer to the HW structure
2244 * @offset: The offset of the byte to read.
2245 * @data: Pointer to a byte to store the value read.
2246 *
2247 * Reads a single byte from the NVM using the flash access registers.
2248 **/
2249 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2250 u8 *data)
2251 {
2252 s32 ret_val;
2253 u16 word = 0;
2254
2255 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2256 if (ret_val)
2257 return ret_val;
2258
2259 *data = (u8)word;
2260
2261 return 0;
2262 }
2263
2264 /**
2265 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2266 * @hw: pointer to the HW structure
2267 * @offset: The offset (in bytes) of the byte or word to read.
2268 * @size: Size of data to read, 1=byte 2=word
2269 * @data: Pointer to the word to store the value read.
2270 *
2271 * Reads a byte or word from the NVM using the flash access registers.
2272 **/
2273 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2274 u8 size, u16 *data)
2275 {
2276 union ich8_hws_flash_status hsfsts;
2277 union ich8_hws_flash_ctrl hsflctl;
2278 u32 flash_linear_addr;
2279 u32 flash_data = 0;
2280 s32 ret_val = -E1000_ERR_NVM;
2281 u8 count = 0;
2282
2283 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2284 return -E1000_ERR_NVM;
2285
2286 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2287 hw->nvm.flash_base_addr;
2288
2289 do {
2290 udelay(1);
2291 /* Steps */
2292 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2293 if (ret_val != 0)
2294 break;
2295
2296 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2297 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2298 hsflctl.hsf_ctrl.fldbcount = size - 1;
2299 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2300 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2301
2302 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2303
2304 ret_val = e1000_flash_cycle_ich8lan(hw,
2305 ICH_FLASH_READ_COMMAND_TIMEOUT);
2306
2307 /*
2308 * Check if FCERR is set to 1, if set to 1, clear it
2309 * and try the whole sequence a few more times, else
2310 * read in (shift in) the Flash Data0, the order is
2311 * least significant byte first msb to lsb
2312 */
2313 if (ret_val == 0) {
2314 flash_data = er32flash(ICH_FLASH_FDATA0);
2315 if (size == 1)
2316 *data = (u8)(flash_data & 0x000000FF);
2317 else if (size == 2)
2318 *data = (u16)(flash_data & 0x0000FFFF);
2319 break;
2320 } else {
2321 /*
2322 * If we've gotten here, then things are probably
2323 * completely hosed, but if the error condition is
2324 * detected, it won't hurt to give it another try...
2325 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2326 */
2327 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2328 if (hsfsts.hsf_status.flcerr == 1) {
2329 /* Repeat for some time before giving up. */
2330 continue;
2331 } else if (hsfsts.hsf_status.flcdone == 0) {
2332 e_dbg("Timeout error - flash cycle "
2333 "did not complete.\n");
2334 break;
2335 }
2336 }
2337 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2338
2339 return ret_val;
2340 }
2341
2342 /**
2343 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2344 * @hw: pointer to the HW structure
2345 * @offset: The offset (in bytes) of the word(s) to write.
2346 * @words: Size of data to write in words
2347 * @data: Pointer to the word(s) to write at offset.
2348 *
2349 * Writes a byte or word to the NVM using the flash access registers.
2350 **/
2351 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2352 u16 *data)
2353 {
2354 struct e1000_nvm_info *nvm = &hw->nvm;
2355 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2356 u16 i;
2357
2358 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2359 (words == 0)) {
2360 e_dbg("nvm parameter(s) out of bounds\n");
2361 return -E1000_ERR_NVM;
2362 }
2363
2364 nvm->ops.acquire(hw);
2365
2366 for (i = 0; i < words; i++) {
2367 dev_spec->shadow_ram[offset+i].modified = true;
2368 dev_spec->shadow_ram[offset+i].value = data[i];
2369 }
2370
2371 nvm->ops.release(hw);
2372
2373 return 0;
2374 }
2375
2376 /**
2377 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2378 * @hw: pointer to the HW structure
2379 *
2380 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2381 * which writes the checksum to the shadow ram. The changes in the shadow
2382 * ram are then committed to the EEPROM by processing each bank at a time
2383 * checking for the modified bit and writing only the pending changes.
2384 * After a successful commit, the shadow ram is cleared and is ready for
2385 * future writes.
2386 **/
2387 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2388 {
2389 struct e1000_nvm_info *nvm = &hw->nvm;
2390 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2391 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2392 s32 ret_val;
2393 u16 data;
2394
2395 ret_val = e1000e_update_nvm_checksum_generic(hw);
2396 if (ret_val)
2397 goto out;
2398
2399 if (nvm->type != e1000_nvm_flash_sw)
2400 goto out;
2401
2402 nvm->ops.acquire(hw);
2403
2404 /*
2405 * We're writing to the opposite bank so if we're on bank 1,
2406 * write to bank 0 etc. We also need to erase the segment that
2407 * is going to be written
2408 */
2409 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2410 if (ret_val) {
2411 e_dbg("Could not detect valid bank, assuming bank 0\n");
2412 bank = 0;
2413 }
2414
2415 if (bank == 0) {
2416 new_bank_offset = nvm->flash_bank_size;
2417 old_bank_offset = 0;
2418 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2419 if (ret_val)
2420 goto release;
2421 } else {
2422 old_bank_offset = nvm->flash_bank_size;
2423 new_bank_offset = 0;
2424 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2425 if (ret_val)
2426 goto release;
2427 }
2428
2429 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2430 /*
2431 * Determine whether to write the value stored
2432 * in the other NVM bank or a modified value stored
2433 * in the shadow RAM
2434 */
2435 if (dev_spec->shadow_ram[i].modified) {
2436 data = dev_spec->shadow_ram[i].value;
2437 } else {
2438 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2439 old_bank_offset,
2440 &data);
2441 if (ret_val)
2442 break;
2443 }
2444
2445 /*
2446 * If the word is 0x13, then make sure the signature bits
2447 * (15:14) are 11b until the commit has completed.
2448 * This will allow us to write 10b which indicates the
2449 * signature is valid. We want to do this after the write
2450 * has completed so that we don't mark the segment valid
2451 * while the write is still in progress
2452 */
2453 if (i == E1000_ICH_NVM_SIG_WORD)
2454 data |= E1000_ICH_NVM_SIG_MASK;
2455
2456 /* Convert offset to bytes. */
2457 act_offset = (i + new_bank_offset) << 1;
2458
2459 udelay(100);
2460 /* Write the bytes to the new bank. */
2461 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2462 act_offset,
2463 (u8)data);
2464 if (ret_val)
2465 break;
2466
2467 udelay(100);
2468 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2469 act_offset + 1,
2470 (u8)(data >> 8));
2471 if (ret_val)
2472 break;
2473 }
2474
2475 /*
2476 * Don't bother writing the segment valid bits if sector
2477 * programming failed.
2478 */
2479 if (ret_val) {
2480 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2481 e_dbg("Flash commit failed.\n");
2482 goto release;
2483 }
2484
2485 /*
2486 * Finally validate the new segment by setting bit 15:14
2487 * to 10b in word 0x13 , this can be done without an
2488 * erase as well since these bits are 11 to start with
2489 * and we need to change bit 14 to 0b
2490 */
2491 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2492 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2493 if (ret_val)
2494 goto release;
2495
2496 data &= 0xBFFF;
2497 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2498 act_offset * 2 + 1,
2499 (u8)(data >> 8));
2500 if (ret_val)
2501 goto release;
2502
2503 /*
2504 * And invalidate the previously valid segment by setting
2505 * its signature word (0x13) high_byte to 0b. This can be
2506 * done without an erase because flash erase sets all bits
2507 * to 1's. We can write 1's to 0's without an erase
2508 */
2509 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2510 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2511 if (ret_val)
2512 goto release;
2513
2514 /* Great! Everything worked, we can now clear the cached entries. */
2515 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2516 dev_spec->shadow_ram[i].modified = false;
2517 dev_spec->shadow_ram[i].value = 0xFFFF;
2518 }
2519
2520 release:
2521 nvm->ops.release(hw);
2522
2523 /*
2524 * Reload the EEPROM, or else modifications will not appear
2525 * until after the next adapter reset.
2526 */
2527 if (!ret_val) {
2528 e1000e_reload_nvm(hw);
2529 msleep(10);
2530 }
2531
2532 out:
2533 if (ret_val)
2534 e_dbg("NVM update error: %d\n", ret_val);
2535
2536 return ret_val;
2537 }
2538
2539 /**
2540 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2541 * @hw: pointer to the HW structure
2542 *
2543 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2544 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2545 * calculated, in which case we need to calculate the checksum and set bit 6.
2546 **/
2547 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2548 {
2549 s32 ret_val;
2550 u16 data;
2551
2552 /*
2553 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2554 * needs to be fixed. This bit is an indication that the NVM
2555 * was prepared by OEM software and did not calculate the
2556 * checksum...a likely scenario.
2557 */
2558 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2559 if (ret_val)
2560 return ret_val;
2561
2562 if ((data & 0x40) == 0) {
2563 data |= 0x40;
2564 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2565 if (ret_val)
2566 return ret_val;
2567 ret_val = e1000e_update_nvm_checksum(hw);
2568 if (ret_val)
2569 return ret_val;
2570 }
2571
2572 return e1000e_validate_nvm_checksum_generic(hw);
2573 }
2574
2575 /**
2576 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2577 * @hw: pointer to the HW structure
2578 *
2579 * To prevent malicious write/erase of the NVM, set it to be read-only
2580 * so that the hardware ignores all write/erase cycles of the NVM via
2581 * the flash control registers. The shadow-ram copy of the NVM will
2582 * still be updated, however any updates to this copy will not stick
2583 * across driver reloads.
2584 **/
2585 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2586 {
2587 struct e1000_nvm_info *nvm = &hw->nvm;
2588 union ich8_flash_protected_range pr0;
2589 union ich8_hws_flash_status hsfsts;
2590 u32 gfpreg;
2591
2592 nvm->ops.acquire(hw);
2593
2594 gfpreg = er32flash(ICH_FLASH_GFPREG);
2595
2596 /* Write-protect GbE Sector of NVM */
2597 pr0.regval = er32flash(ICH_FLASH_PR0);
2598 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2599 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2600 pr0.range.wpe = true;
2601 ew32flash(ICH_FLASH_PR0, pr0.regval);
2602
2603 /*
2604 * Lock down a subset of GbE Flash Control Registers, e.g.
2605 * PR0 to prevent the write-protection from being lifted.
2606 * Once FLOCKDN is set, the registers protected by it cannot
2607 * be written until FLOCKDN is cleared by a hardware reset.
2608 */
2609 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2610 hsfsts.hsf_status.flockdn = true;
2611 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2612
2613 nvm->ops.release(hw);
2614 }
2615
2616 /**
2617 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2618 * @hw: pointer to the HW structure
2619 * @offset: The offset (in bytes) of the byte/word to read.
2620 * @size: Size of data to read, 1=byte 2=word
2621 * @data: The byte(s) to write to the NVM.
2622 *
2623 * Writes one/two bytes to the NVM using the flash access registers.
2624 **/
2625 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2626 u8 size, u16 data)
2627 {
2628 union ich8_hws_flash_status hsfsts;
2629 union ich8_hws_flash_ctrl hsflctl;
2630 u32 flash_linear_addr;
2631 u32 flash_data = 0;
2632 s32 ret_val;
2633 u8 count = 0;
2634
2635 if (size < 1 || size > 2 || data > size * 0xff ||
2636 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2637 return -E1000_ERR_NVM;
2638
2639 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2640 hw->nvm.flash_base_addr;
2641
2642 do {
2643 udelay(1);
2644 /* Steps */
2645 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2646 if (ret_val)
2647 break;
2648
2649 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2650 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2651 hsflctl.hsf_ctrl.fldbcount = size -1;
2652 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2653 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2654
2655 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2656
2657 if (size == 1)
2658 flash_data = (u32)data & 0x00FF;
2659 else
2660 flash_data = (u32)data;
2661
2662 ew32flash(ICH_FLASH_FDATA0, flash_data);
2663
2664 /*
2665 * check if FCERR is set to 1 , if set to 1, clear it
2666 * and try the whole sequence a few more times else done
2667 */
2668 ret_val = e1000_flash_cycle_ich8lan(hw,
2669 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2670 if (!ret_val)
2671 break;
2672
2673 /*
2674 * If we're here, then things are most likely
2675 * completely hosed, but if the error condition
2676 * is detected, it won't hurt to give it another
2677 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2678 */
2679 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2680 if (hsfsts.hsf_status.flcerr == 1)
2681 /* Repeat for some time before giving up. */
2682 continue;
2683 if (hsfsts.hsf_status.flcdone == 0) {
2684 e_dbg("Timeout error - flash cycle "
2685 "did not complete.");
2686 break;
2687 }
2688 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2689
2690 return ret_val;
2691 }
2692
2693 /**
2694 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2695 * @hw: pointer to the HW structure
2696 * @offset: The index of the byte to read.
2697 * @data: The byte to write to the NVM.
2698 *
2699 * Writes a single byte to the NVM using the flash access registers.
2700 **/
2701 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2702 u8 data)
2703 {
2704 u16 word = (u16)data;
2705
2706 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2707 }
2708
2709 /**
2710 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2711 * @hw: pointer to the HW structure
2712 * @offset: The offset of the byte to write.
2713 * @byte: The byte to write to the NVM.
2714 *
2715 * Writes a single byte to the NVM using the flash access registers.
2716 * Goes through a retry algorithm before giving up.
2717 **/
2718 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2719 u32 offset, u8 byte)
2720 {
2721 s32 ret_val;
2722 u16 program_retries;
2723
2724 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2725 if (!ret_val)
2726 return ret_val;
2727
2728 for (program_retries = 0; program_retries < 100; program_retries++) {
2729 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2730 udelay(100);
2731 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2732 if (!ret_val)
2733 break;
2734 }
2735 if (program_retries == 100)
2736 return -E1000_ERR_NVM;
2737
2738 return 0;
2739 }
2740
2741 /**
2742 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2743 * @hw: pointer to the HW structure
2744 * @bank: 0 for first bank, 1 for second bank, etc.
2745 *
2746 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2747 * bank N is 4096 * N + flash_reg_addr.
2748 **/
2749 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2750 {
2751 struct e1000_nvm_info *nvm = &hw->nvm;
2752 union ich8_hws_flash_status hsfsts;
2753 union ich8_hws_flash_ctrl hsflctl;
2754 u32 flash_linear_addr;
2755 /* bank size is in 16bit words - adjust to bytes */
2756 u32 flash_bank_size = nvm->flash_bank_size * 2;
2757 s32 ret_val;
2758 s32 count = 0;
2759 s32 j, iteration, sector_size;
2760
2761 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2762
2763 /*
2764 * Determine HW Sector size: Read BERASE bits of hw flash status
2765 * register
2766 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2767 * consecutive sectors. The start index for the nth Hw sector
2768 * can be calculated as = bank * 4096 + n * 256
2769 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2770 * The start index for the nth Hw sector can be calculated
2771 * as = bank * 4096
2772 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2773 * (ich9 only, otherwise error condition)
2774 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2775 */
2776 switch (hsfsts.hsf_status.berasesz) {
2777 case 0:
2778 /* Hw sector size 256 */
2779 sector_size = ICH_FLASH_SEG_SIZE_256;
2780 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2781 break;
2782 case 1:
2783 sector_size = ICH_FLASH_SEG_SIZE_4K;
2784 iteration = 1;
2785 break;
2786 case 2:
2787 sector_size = ICH_FLASH_SEG_SIZE_8K;
2788 iteration = 1;
2789 break;
2790 case 3:
2791 sector_size = ICH_FLASH_SEG_SIZE_64K;
2792 iteration = 1;
2793 break;
2794 default:
2795 return -E1000_ERR_NVM;
2796 }
2797
2798 /* Start with the base address, then add the sector offset. */
2799 flash_linear_addr = hw->nvm.flash_base_addr;
2800 flash_linear_addr += (bank) ? flash_bank_size : 0;
2801
2802 for (j = 0; j < iteration ; j++) {
2803 do {
2804 /* Steps */
2805 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2806 if (ret_val)
2807 return ret_val;
2808
2809 /*
2810 * Write a value 11 (block Erase) in Flash
2811 * Cycle field in hw flash control
2812 */
2813 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2814 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2815 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2816
2817 /*
2818 * Write the last 24 bits of an index within the
2819 * block into Flash Linear address field in Flash
2820 * Address.
2821 */
2822 flash_linear_addr += (j * sector_size);
2823 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2824
2825 ret_val = e1000_flash_cycle_ich8lan(hw,
2826 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2827 if (ret_val == 0)
2828 break;
2829
2830 /*
2831 * Check if FCERR is set to 1. If 1,
2832 * clear it and try the whole sequence
2833 * a few more times else Done
2834 */
2835 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2836 if (hsfsts.hsf_status.flcerr == 1)
2837 /* repeat for some time before giving up */
2838 continue;
2839 else if (hsfsts.hsf_status.flcdone == 0)
2840 return ret_val;
2841 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2842 }
2843
2844 return 0;
2845 }
2846
2847 /**
2848 * e1000_valid_led_default_ich8lan - Set the default LED settings
2849 * @hw: pointer to the HW structure
2850 * @data: Pointer to the LED settings
2851 *
2852 * Reads the LED default settings from the NVM to data. If the NVM LED
2853 * settings is all 0's or F's, set the LED default to a valid LED default
2854 * setting.
2855 **/
2856 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2857 {
2858 s32 ret_val;
2859
2860 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2861 if (ret_val) {
2862 e_dbg("NVM Read Error\n");
2863 return ret_val;
2864 }
2865
2866 if (*data == ID_LED_RESERVED_0000 ||
2867 *data == ID_LED_RESERVED_FFFF)
2868 *data = ID_LED_DEFAULT_ICH8LAN;
2869
2870 return 0;
2871 }
2872
2873 /**
2874 * e1000_id_led_init_pchlan - store LED configurations
2875 * @hw: pointer to the HW structure
2876 *
2877 * PCH does not control LEDs via the LEDCTL register, rather it uses
2878 * the PHY LED configuration register.
2879 *
2880 * PCH also does not have an "always on" or "always off" mode which
2881 * complicates the ID feature. Instead of using the "on" mode to indicate
2882 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2883 * use "link_up" mode. The LEDs will still ID on request if there is no
2884 * link based on logic in e1000_led_[on|off]_pchlan().
2885 **/
2886 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2887 {
2888 struct e1000_mac_info *mac = &hw->mac;
2889 s32 ret_val;
2890 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2891 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2892 u16 data, i, temp, shift;
2893
2894 /* Get default ID LED modes */
2895 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2896 if (ret_val)
2897 goto out;
2898
2899 mac->ledctl_default = er32(LEDCTL);
2900 mac->ledctl_mode1 = mac->ledctl_default;
2901 mac->ledctl_mode2 = mac->ledctl_default;
2902
2903 for (i = 0; i < 4; i++) {
2904 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2905 shift = (i * 5);
2906 switch (temp) {
2907 case ID_LED_ON1_DEF2:
2908 case ID_LED_ON1_ON2:
2909 case ID_LED_ON1_OFF2:
2910 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2911 mac->ledctl_mode1 |= (ledctl_on << shift);
2912 break;
2913 case ID_LED_OFF1_DEF2:
2914 case ID_LED_OFF1_ON2:
2915 case ID_LED_OFF1_OFF2:
2916 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2917 mac->ledctl_mode1 |= (ledctl_off << shift);
2918 break;
2919 default:
2920 /* Do nothing */
2921 break;
2922 }
2923 switch (temp) {
2924 case ID_LED_DEF1_ON2:
2925 case ID_LED_ON1_ON2:
2926 case ID_LED_OFF1_ON2:
2927 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2928 mac->ledctl_mode2 |= (ledctl_on << shift);
2929 break;
2930 case ID_LED_DEF1_OFF2:
2931 case ID_LED_ON1_OFF2:
2932 case ID_LED_OFF1_OFF2:
2933 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2934 mac->ledctl_mode2 |= (ledctl_off << shift);
2935 break;
2936 default:
2937 /* Do nothing */
2938 break;
2939 }
2940 }
2941
2942 out:
2943 return ret_val;
2944 }
2945
2946 /**
2947 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2948 * @hw: pointer to the HW structure
2949 *
2950 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2951 * register, so the the bus width is hard coded.
2952 **/
2953 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2954 {
2955 struct e1000_bus_info *bus = &hw->bus;
2956 s32 ret_val;
2957
2958 ret_val = e1000e_get_bus_info_pcie(hw);
2959
2960 /*
2961 * ICH devices are "PCI Express"-ish. They have
2962 * a configuration space, but do not contain
2963 * PCI Express Capability registers, so bus width
2964 * must be hardcoded.
2965 */
2966 if (bus->width == e1000_bus_width_unknown)
2967 bus->width = e1000_bus_width_pcie_x1;
2968
2969 return ret_val;
2970 }
2971
2972 /**
2973 * e1000_reset_hw_ich8lan - Reset the hardware
2974 * @hw: pointer to the HW structure
2975 *
2976 * Does a full reset of the hardware which includes a reset of the PHY and
2977 * MAC.
2978 **/
2979 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2980 {
2981 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2982 u16 reg;
2983 u32 ctrl, kab;
2984 s32 ret_val;
2985
2986 /*
2987 * Prevent the PCI-E bus from sticking if there is no TLP connection
2988 * on the last TLP read/write transaction when MAC is reset.
2989 */
2990 ret_val = e1000e_disable_pcie_master(hw);
2991 if (ret_val)
2992 e_dbg("PCI-E Master disable polling has failed.\n");
2993
2994 e_dbg("Masking off all interrupts\n");
2995 ew32(IMC, 0xffffffff);
2996
2997 /*
2998 * Disable the Transmit and Receive units. Then delay to allow
2999 * any pending transactions to complete before we hit the MAC
3000 * with the global reset.
3001 */
3002 ew32(RCTL, 0);
3003 ew32(TCTL, E1000_TCTL_PSP);
3004 e1e_flush();
3005
3006 msleep(10);
3007
3008 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3009 if (hw->mac.type == e1000_ich8lan) {
3010 /* Set Tx and Rx buffer allocation to 8k apiece. */
3011 ew32(PBA, E1000_PBA_8K);
3012 /* Set Packet Buffer Size to 16k. */
3013 ew32(PBS, E1000_PBS_16K);
3014 }
3015
3016 if (hw->mac.type == e1000_pchlan) {
3017 /* Save the NVM K1 bit setting*/
3018 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3019 if (ret_val)
3020 return ret_val;
3021
3022 if (reg & E1000_NVM_K1_ENABLE)
3023 dev_spec->nvm_k1_enabled = true;
3024 else
3025 dev_spec->nvm_k1_enabled = false;
3026 }
3027
3028 ctrl = er32(CTRL);
3029
3030 if (!e1000_check_reset_block(hw)) {
3031 /*
3032 * Full-chip reset requires MAC and PHY reset at the same
3033 * time to make sure the interface between MAC and the
3034 * external PHY is reset.
3035 */
3036 ctrl |= E1000_CTRL_PHY_RST;
3037
3038 /*
3039 * Gate automatic PHY configuration by hardware on
3040 * non-managed 82579
3041 */
3042 if ((hw->mac.type == e1000_pch2lan) &&
3043 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3044 e1000_gate_hw_phy_config_ich8lan(hw, true);
3045 }
3046 ret_val = e1000_acquire_swflag_ich8lan(hw);
3047 e_dbg("Issuing a global reset to ich8lan\n");
3048 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3049 msleep(20);
3050
3051 if (!ret_val)
3052 e1000_release_swflag_ich8lan(hw);
3053
3054 if (ctrl & E1000_CTRL_PHY_RST) {
3055 ret_val = hw->phy.ops.get_cfg_done(hw);
3056 if (ret_val)
3057 goto out;
3058
3059 ret_val = e1000_post_phy_reset_ich8lan(hw);
3060 if (ret_val)
3061 goto out;
3062 }
3063
3064 /*
3065 * For PCH, this write will make sure that any noise
3066 * will be detected as a CRC error and be dropped rather than show up
3067 * as a bad packet to the DMA engine.
3068 */
3069 if (hw->mac.type == e1000_pchlan)
3070 ew32(CRC_OFFSET, 0x65656565);
3071
3072 ew32(IMC, 0xffffffff);
3073 er32(ICR);
3074
3075 kab = er32(KABGTXD);
3076 kab |= E1000_KABGTXD_BGSQLBIAS;
3077 ew32(KABGTXD, kab);
3078
3079 out:
3080 return ret_val;
3081 }
3082
3083 /**
3084 * e1000_init_hw_ich8lan - Initialize the hardware
3085 * @hw: pointer to the HW structure
3086 *
3087 * Prepares the hardware for transmit and receive by doing the following:
3088 * - initialize hardware bits
3089 * - initialize LED identification
3090 * - setup receive address registers
3091 * - setup flow control
3092 * - setup transmit descriptors
3093 * - clear statistics
3094 **/
3095 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3096 {
3097 struct e1000_mac_info *mac = &hw->mac;
3098 u32 ctrl_ext, txdctl, snoop;
3099 s32 ret_val;
3100 u16 i;
3101
3102 e1000_initialize_hw_bits_ich8lan(hw);
3103
3104 /* Initialize identification LED */
3105 ret_val = mac->ops.id_led_init(hw);
3106 if (ret_val)
3107 e_dbg("Error initializing identification LED\n");
3108 /* This is not fatal and we should not stop init due to this */
3109
3110 /* Setup the receive address. */
3111 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3112
3113 /* Zero out the Multicast HASH table */
3114 e_dbg("Zeroing the MTA\n");
3115 for (i = 0; i < mac->mta_reg_count; i++)
3116 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3117
3118 /*
3119 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3120 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3121 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3122 */
3123 if (hw->phy.type == e1000_phy_82578) {
3124 e1e_rphy(hw, BM_WUC, &i);
3125 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3126 if (ret_val)
3127 return ret_val;
3128 }
3129
3130 /* Setup link and flow control */
3131 ret_val = e1000_setup_link_ich8lan(hw);
3132
3133 /* Set the transmit descriptor write-back policy for both queues */
3134 txdctl = er32(TXDCTL(0));
3135 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3136 E1000_TXDCTL_FULL_TX_DESC_WB;
3137 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3138 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3139 ew32(TXDCTL(0), txdctl);
3140 txdctl = er32(TXDCTL(1));
3141 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3142 E1000_TXDCTL_FULL_TX_DESC_WB;
3143 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3144 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3145 ew32(TXDCTL(1), txdctl);
3146
3147 /*
3148 * ICH8 has opposite polarity of no_snoop bits.
3149 * By default, we should use snoop behavior.
3150 */
3151 if (mac->type == e1000_ich8lan)
3152 snoop = PCIE_ICH8_SNOOP_ALL;
3153 else
3154 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3155 e1000e_set_pcie_no_snoop(hw, snoop);
3156
3157 ctrl_ext = er32(CTRL_EXT);
3158 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3159 ew32(CTRL_EXT, ctrl_ext);
3160
3161 /*
3162 * Clear all of the statistics registers (clear on read). It is
3163 * important that we do this after we have tried to establish link
3164 * because the symbol error count will increment wildly if there
3165 * is no link.
3166 */
3167 e1000_clear_hw_cntrs_ich8lan(hw);
3168
3169 return 0;
3170 }
3171 /**
3172 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3173 * @hw: pointer to the HW structure
3174 *
3175 * Sets/Clears required hardware bits necessary for correctly setting up the
3176 * hardware for transmit and receive.
3177 **/
3178 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3179 {
3180 u32 reg;
3181
3182 /* Extended Device Control */
3183 reg = er32(CTRL_EXT);
3184 reg |= (1 << 22);
3185 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3186 if (hw->mac.type >= e1000_pchlan)
3187 reg |= E1000_CTRL_EXT_PHYPDEN;
3188 ew32(CTRL_EXT, reg);
3189
3190 /* Transmit Descriptor Control 0 */
3191 reg = er32(TXDCTL(0));
3192 reg |= (1 << 22);
3193 ew32(TXDCTL(0), reg);
3194
3195 /* Transmit Descriptor Control 1 */
3196 reg = er32(TXDCTL(1));
3197 reg |= (1 << 22);
3198 ew32(TXDCTL(1), reg);
3199
3200 /* Transmit Arbitration Control 0 */
3201 reg = er32(TARC(0));
3202 if (hw->mac.type == e1000_ich8lan)
3203 reg |= (1 << 28) | (1 << 29);
3204 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3205 ew32(TARC(0), reg);
3206
3207 /* Transmit Arbitration Control 1 */
3208 reg = er32(TARC(1));
3209 if (er32(TCTL) & E1000_TCTL_MULR)
3210 reg &= ~(1 << 28);
3211 else
3212 reg |= (1 << 28);
3213 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3214 ew32(TARC(1), reg);
3215
3216 /* Device Status */
3217 if (hw->mac.type == e1000_ich8lan) {
3218 reg = er32(STATUS);
3219 reg &= ~(1 << 31);
3220 ew32(STATUS, reg);
3221 }
3222
3223 /*
3224 * work-around descriptor data corruption issue during nfs v2 udp
3225 * traffic, just disable the nfs filtering capability
3226 */
3227 reg = er32(RFCTL);
3228 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3229 ew32(RFCTL, reg);
3230 }
3231
3232 /**
3233 * e1000_setup_link_ich8lan - Setup flow control and link settings
3234 * @hw: pointer to the HW structure
3235 *
3236 * Determines which flow control settings to use, then configures flow
3237 * control. Calls the appropriate media-specific link configuration
3238 * function. Assuming the adapter has a valid link partner, a valid link
3239 * should be established. Assumes the hardware has previously been reset
3240 * and the transmitter and receiver are not enabled.
3241 **/
3242 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3243 {
3244 s32 ret_val;
3245
3246 if (e1000_check_reset_block(hw))
3247 return 0;
3248
3249 /*
3250 * ICH parts do not have a word in the NVM to determine
3251 * the default flow control setting, so we explicitly
3252 * set it to full.
3253 */
3254 if (hw->fc.requested_mode == e1000_fc_default) {
3255 /* Workaround h/w hang when Tx flow control enabled */
3256 if (hw->mac.type == e1000_pchlan)
3257 hw->fc.requested_mode = e1000_fc_rx_pause;
3258 else
3259 hw->fc.requested_mode = e1000_fc_full;
3260 }
3261
3262 /*
3263 * Save off the requested flow control mode for use later. Depending
3264 * on the link partner's capabilities, we may or may not use this mode.
3265 */
3266 hw->fc.current_mode = hw->fc.requested_mode;
3267
3268 e_dbg("After fix-ups FlowControl is now = %x\n",
3269 hw->fc.current_mode);
3270
3271 /* Continue to configure the copper link. */
3272 ret_val = e1000_setup_copper_link_ich8lan(hw);
3273 if (ret_val)
3274 return ret_val;
3275
3276 ew32(FCTTV, hw->fc.pause_time);
3277 if ((hw->phy.type == e1000_phy_82578) ||
3278 (hw->phy.type == e1000_phy_82579) ||
3279 (hw->phy.type == e1000_phy_82577)) {
3280 ew32(FCRTV_PCH, hw->fc.refresh_time);
3281
3282 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3283 hw->fc.pause_time);
3284 if (ret_val)
3285 return ret_val;
3286 }
3287
3288 return e1000e_set_fc_watermarks(hw);
3289 }
3290
3291 /**
3292 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3293 * @hw: pointer to the HW structure
3294 *
3295 * Configures the kumeran interface to the PHY to wait the appropriate time
3296 * when polling the PHY, then call the generic setup_copper_link to finish
3297 * configuring the copper link.
3298 **/
3299 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3300 {
3301 u32 ctrl;
3302 s32 ret_val;
3303 u16 reg_data;
3304
3305 ctrl = er32(CTRL);
3306 ctrl |= E1000_CTRL_SLU;
3307 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3308 ew32(CTRL, ctrl);
3309
3310 /*
3311 * Set the mac to wait the maximum time between each iteration
3312 * and increase the max iterations when polling the phy;
3313 * this fixes erroneous timeouts at 10Mbps.
3314 */
3315 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3316 if (ret_val)
3317 return ret_val;
3318 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3319 &reg_data);
3320 if (ret_val)
3321 return ret_val;
3322 reg_data |= 0x3F;
3323 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3324 reg_data);
3325 if (ret_val)
3326 return ret_val;
3327
3328 switch (hw->phy.type) {
3329 case e1000_phy_igp_3:
3330 ret_val = e1000e_copper_link_setup_igp(hw);
3331 if (ret_val)
3332 return ret_val;
3333 break;
3334 case e1000_phy_bm:
3335 case e1000_phy_82578:
3336 ret_val = e1000e_copper_link_setup_m88(hw);
3337 if (ret_val)
3338 return ret_val;
3339 break;
3340 case e1000_phy_82577:
3341 case e1000_phy_82579:
3342 ret_val = e1000_copper_link_setup_82577(hw);
3343 if (ret_val)
3344 return ret_val;
3345 break;
3346 case e1000_phy_ife:
3347 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3348 if (ret_val)
3349 return ret_val;
3350
3351 reg_data &= ~IFE_PMC_AUTO_MDIX;
3352
3353 switch (hw->phy.mdix) {
3354 case 1:
3355 reg_data &= ~IFE_PMC_FORCE_MDIX;
3356 break;
3357 case 2:
3358 reg_data |= IFE_PMC_FORCE_MDIX;
3359 break;
3360 case 0:
3361 default:
3362 reg_data |= IFE_PMC_AUTO_MDIX;
3363 break;
3364 }
3365 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3366 if (ret_val)
3367 return ret_val;
3368 break;
3369 default:
3370 break;
3371 }
3372 return e1000e_setup_copper_link(hw);
3373 }
3374
3375 /**
3376 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3377 * @hw: pointer to the HW structure
3378 * @speed: pointer to store current link speed
3379 * @duplex: pointer to store the current link duplex
3380 *
3381 * Calls the generic get_speed_and_duplex to retrieve the current link
3382 * information and then calls the Kumeran lock loss workaround for links at
3383 * gigabit speeds.
3384 **/
3385 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3386 u16 *duplex)
3387 {
3388 s32 ret_val;
3389
3390 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3391 if (ret_val)
3392 return ret_val;
3393
3394 if ((hw->mac.type == e1000_ich8lan) &&
3395 (hw->phy.type == e1000_phy_igp_3) &&
3396 (*speed == SPEED_1000)) {
3397 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3398 }
3399
3400 return ret_val;
3401 }
3402
3403 /**
3404 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3405 * @hw: pointer to the HW structure
3406 *
3407 * Work-around for 82566 Kumeran PCS lock loss:
3408 * On link status change (i.e. PCI reset, speed change) and link is up and
3409 * speed is gigabit-
3410 * 0) if workaround is optionally disabled do nothing
3411 * 1) wait 1ms for Kumeran link to come up
3412 * 2) check Kumeran Diagnostic register PCS lock loss bit
3413 * 3) if not set the link is locked (all is good), otherwise...
3414 * 4) reset the PHY
3415 * 5) repeat up to 10 times
3416 * Note: this is only called for IGP3 copper when speed is 1gb.
3417 **/
3418 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3419 {
3420 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3421 u32 phy_ctrl;
3422 s32 ret_val;
3423 u16 i, data;
3424 bool link;
3425
3426 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3427 return 0;
3428
3429 /*
3430 * Make sure link is up before proceeding. If not just return.
3431 * Attempting this while link is negotiating fouled up link
3432 * stability
3433 */
3434 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3435 if (!link)
3436 return 0;
3437
3438 for (i = 0; i < 10; i++) {
3439 /* read once to clear */
3440 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3441 if (ret_val)
3442 return ret_val;
3443 /* and again to get new status */
3444 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3445 if (ret_val)
3446 return ret_val;
3447
3448 /* check for PCS lock */
3449 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3450 return 0;
3451
3452 /* Issue PHY reset */
3453 e1000_phy_hw_reset(hw);
3454 mdelay(5);
3455 }
3456 /* Disable GigE link negotiation */
3457 phy_ctrl = er32(PHY_CTRL);
3458 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3459 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3460 ew32(PHY_CTRL, phy_ctrl);
3461
3462 /*
3463 * Call gig speed drop workaround on Gig disable before accessing
3464 * any PHY registers
3465 */
3466 e1000e_gig_downshift_workaround_ich8lan(hw);
3467
3468 /* unable to acquire PCS lock */
3469 return -E1000_ERR_PHY;
3470 }
3471
3472 /**
3473 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3474 * @hw: pointer to the HW structure
3475 * @state: boolean value used to set the current Kumeran workaround state
3476 *
3477 * If ICH8, set the current Kumeran workaround state (enabled - true
3478 * /disabled - false).
3479 **/
3480 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3481 bool state)
3482 {
3483 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3484
3485 if (hw->mac.type != e1000_ich8lan) {
3486 e_dbg("Workaround applies to ICH8 only.\n");
3487 return;
3488 }
3489
3490 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3491 }
3492
3493 /**
3494 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3495 * @hw: pointer to the HW structure
3496 *
3497 * Workaround for 82566 power-down on D3 entry:
3498 * 1) disable gigabit link
3499 * 2) write VR power-down enable
3500 * 3) read it back
3501 * Continue if successful, else issue LCD reset and repeat
3502 **/
3503 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3504 {
3505 u32 reg;
3506 u16 data;
3507 u8 retry = 0;
3508
3509 if (hw->phy.type != e1000_phy_igp_3)
3510 return;
3511
3512 /* Try the workaround twice (if needed) */
3513 do {
3514 /* Disable link */
3515 reg = er32(PHY_CTRL);
3516 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3517 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3518 ew32(PHY_CTRL, reg);
3519
3520 /*
3521 * Call gig speed drop workaround on Gig disable before
3522 * accessing any PHY registers
3523 */
3524 if (hw->mac.type == e1000_ich8lan)
3525 e1000e_gig_downshift_workaround_ich8lan(hw);
3526
3527 /* Write VR power-down enable */
3528 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3529 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3530 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3531
3532 /* Read it back and test */
3533 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3534 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3535 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3536 break;
3537
3538 /* Issue PHY reset and repeat at most one more time */
3539 reg = er32(CTRL);
3540 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3541 retry++;
3542 } while (retry);
3543 }
3544
3545 /**
3546 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3547 * @hw: pointer to the HW structure
3548 *
3549 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3550 * LPLU, Gig disable, MDIC PHY reset):
3551 * 1) Set Kumeran Near-end loopback
3552 * 2) Clear Kumeran Near-end loopback
3553 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3554 **/
3555 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3556 {
3557 s32 ret_val;
3558 u16 reg_data;
3559
3560 if ((hw->mac.type != e1000_ich8lan) ||
3561 (hw->phy.type != e1000_phy_igp_3))
3562 return;
3563
3564 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3565 &reg_data);
3566 if (ret_val)
3567 return;
3568 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3569 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3570 reg_data);
3571 if (ret_val)
3572 return;
3573 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3574 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3575 reg_data);
3576 }
3577
3578 /**
3579 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3580 * @hw: pointer to the HW structure
3581 *
3582 * During S0 to Sx transition, it is possible the link remains at gig
3583 * instead of negotiating to a lower speed. Before going to Sx, set
3584 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3585 * to a lower speed.
3586 *
3587 * Should only be called for applicable parts.
3588 **/
3589 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3590 {
3591 u32 phy_ctrl;
3592 s32 ret_val;
3593
3594 phy_ctrl = er32(PHY_CTRL);
3595 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3596 ew32(PHY_CTRL, phy_ctrl);
3597
3598 if (hw->mac.type >= e1000_pchlan) {
3599 e1000_oem_bits_config_ich8lan(hw, false);
3600 ret_val = hw->phy.ops.acquire(hw);
3601 if (ret_val)
3602 return;
3603 e1000_write_smbus_addr(hw);
3604 hw->phy.ops.release(hw);
3605 }
3606 }
3607
3608 /**
3609 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3610 * @hw: pointer to the HW structure
3611 *
3612 * Return the LED back to the default configuration.
3613 **/
3614 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3615 {
3616 if (hw->phy.type == e1000_phy_ife)
3617 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3618
3619 ew32(LEDCTL, hw->mac.ledctl_default);
3620 return 0;
3621 }
3622
3623 /**
3624 * e1000_led_on_ich8lan - Turn LEDs on
3625 * @hw: pointer to the HW structure
3626 *
3627 * Turn on the LEDs.
3628 **/
3629 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3630 {
3631 if (hw->phy.type == e1000_phy_ife)
3632 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3633 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3634
3635 ew32(LEDCTL, hw->mac.ledctl_mode2);
3636 return 0;
3637 }
3638
3639 /**
3640 * e1000_led_off_ich8lan - Turn LEDs off
3641 * @hw: pointer to the HW structure
3642 *
3643 * Turn off the LEDs.
3644 **/
3645 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3646 {
3647 if (hw->phy.type == e1000_phy_ife)
3648 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3649 (IFE_PSCL_PROBE_MODE |
3650 IFE_PSCL_PROBE_LEDS_OFF));
3651
3652 ew32(LEDCTL, hw->mac.ledctl_mode1);
3653 return 0;
3654 }
3655
3656 /**
3657 * e1000_setup_led_pchlan - Configures SW controllable LED
3658 * @hw: pointer to the HW structure
3659 *
3660 * This prepares the SW controllable LED for use.
3661 **/
3662 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3663 {
3664 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3665 }
3666
3667 /**
3668 * e1000_cleanup_led_pchlan - Restore the default LED operation
3669 * @hw: pointer to the HW structure
3670 *
3671 * Return the LED back to the default configuration.
3672 **/
3673 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3674 {
3675 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3676 }
3677
3678 /**
3679 * e1000_led_on_pchlan - Turn LEDs on
3680 * @hw: pointer to the HW structure
3681 *
3682 * Turn on the LEDs.
3683 **/
3684 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3685 {
3686 u16 data = (u16)hw->mac.ledctl_mode2;
3687 u32 i, led;
3688
3689 /*
3690 * If no link, then turn LED on by setting the invert bit
3691 * for each LED that's mode is "link_up" in ledctl_mode2.
3692 */
3693 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3694 for (i = 0; i < 3; i++) {
3695 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3696 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3697 E1000_LEDCTL_MODE_LINK_UP)
3698 continue;
3699 if (led & E1000_PHY_LED0_IVRT)
3700 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3701 else
3702 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3703 }
3704 }
3705
3706 return e1e_wphy(hw, HV_LED_CONFIG, data);
3707 }
3708
3709 /**
3710 * e1000_led_off_pchlan - Turn LEDs off
3711 * @hw: pointer to the HW structure
3712 *
3713 * Turn off the LEDs.
3714 **/
3715 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3716 {
3717 u16 data = (u16)hw->mac.ledctl_mode1;
3718 u32 i, led;
3719
3720 /*
3721 * If no link, then turn LED off by clearing the invert bit
3722 * for each LED that's mode is "link_up" in ledctl_mode1.
3723 */
3724 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3725 for (i = 0; i < 3; i++) {
3726 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3727 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3728 E1000_LEDCTL_MODE_LINK_UP)
3729 continue;
3730 if (led & E1000_PHY_LED0_IVRT)
3731 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3732 else
3733 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3734 }
3735 }
3736
3737 return e1e_wphy(hw, HV_LED_CONFIG, data);
3738 }
3739
3740 /**
3741 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3742 * @hw: pointer to the HW structure
3743 *
3744 * Read appropriate register for the config done bit for completion status
3745 * and configure the PHY through s/w for EEPROM-less parts.
3746 *
3747 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3748 * config done bit, so only an error is logged and continues. If we were
3749 * to return with error, EEPROM-less silicon would not be able to be reset
3750 * or change link.
3751 **/
3752 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3753 {
3754 s32 ret_val = 0;
3755 u32 bank = 0;
3756 u32 status;
3757
3758 e1000e_get_cfg_done(hw);
3759
3760 /* Wait for indication from h/w that it has completed basic config */
3761 if (hw->mac.type >= e1000_ich10lan) {
3762 e1000_lan_init_done_ich8lan(hw);
3763 } else {
3764 ret_val = e1000e_get_auto_rd_done(hw);
3765 if (ret_val) {
3766 /*
3767 * When auto config read does not complete, do not
3768 * return with an error. This can happen in situations
3769 * where there is no eeprom and prevents getting link.
3770 */
3771 e_dbg("Auto Read Done did not complete\n");
3772 ret_val = 0;
3773 }
3774 }
3775
3776 /* Clear PHY Reset Asserted bit */
3777 status = er32(STATUS);
3778 if (status & E1000_STATUS_PHYRA)
3779 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3780 else
3781 e_dbg("PHY Reset Asserted not set - needs delay\n");
3782
3783 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3784 if (hw->mac.type <= e1000_ich9lan) {
3785 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3786 (hw->phy.type == e1000_phy_igp_3)) {
3787 e1000e_phy_init_script_igp3(hw);
3788 }
3789 } else {
3790 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3791 /* Maybe we should do a basic PHY config */
3792 e_dbg("EEPROM not present\n");
3793 ret_val = -E1000_ERR_CONFIG;
3794 }
3795 }
3796
3797 return ret_val;
3798 }
3799
3800 /**
3801 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3802 * @hw: pointer to the HW structure
3803 *
3804 * In the case of a PHY power down to save power, or to turn off link during a
3805 * driver unload, or wake on lan is not enabled, remove the link.
3806 **/
3807 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3808 {
3809 /* If the management interface is not enabled, then power down */
3810 if (!(hw->mac.ops.check_mng_mode(hw) ||
3811 hw->phy.ops.check_reset_block(hw)))
3812 e1000_power_down_phy_copper(hw);
3813 }
3814
3815 /**
3816 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3817 * @hw: pointer to the HW structure
3818 *
3819 * Clears hardware counters specific to the silicon family and calls
3820 * clear_hw_cntrs_generic to clear all general purpose counters.
3821 **/
3822 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3823 {
3824 u16 phy_data;
3825
3826 e1000e_clear_hw_cntrs_base(hw);
3827
3828 er32(ALGNERRC);
3829 er32(RXERRC);
3830 er32(TNCRS);
3831 er32(CEXTERR);
3832 er32(TSCTC);
3833 er32(TSCTFC);
3834
3835 er32(MGTPRC);
3836 er32(MGTPDC);
3837 er32(MGTPTC);
3838
3839 er32(IAC);
3840 er32(ICRXOC);
3841
3842 /* Clear PHY statistics registers */
3843 if ((hw->phy.type == e1000_phy_82578) ||
3844 (hw->phy.type == e1000_phy_82579) ||
3845 (hw->phy.type == e1000_phy_82577)) {
3846 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3847 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3848 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3849 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3850 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3851 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3852 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3853 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3854 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3855 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3856 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3857 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3858 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3859 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3860 }
3861 }
3862
3863 static struct e1000_mac_operations ich8_mac_ops = {
3864 .id_led_init = e1000e_id_led_init,
3865 /* check_mng_mode dependent on mac type */
3866 .check_for_link = e1000_check_for_copper_link_ich8lan,
3867 /* cleanup_led dependent on mac type */
3868 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3869 .get_bus_info = e1000_get_bus_info_ich8lan,
3870 .set_lan_id = e1000_set_lan_id_single_port,
3871 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3872 /* led_on dependent on mac type */
3873 /* led_off dependent on mac type */
3874 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3875 .reset_hw = e1000_reset_hw_ich8lan,
3876 .init_hw = e1000_init_hw_ich8lan,
3877 .setup_link = e1000_setup_link_ich8lan,
3878 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3879 /* id_led_init dependent on mac type */
3880 };
3881
3882 static struct e1000_phy_operations ich8_phy_ops = {
3883 .acquire = e1000_acquire_swflag_ich8lan,
3884 .check_reset_block = e1000_check_reset_block_ich8lan,
3885 .commit = NULL,
3886 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3887 .get_cable_length = e1000e_get_cable_length_igp_2,
3888 .read_reg = e1000e_read_phy_reg_igp,
3889 .release = e1000_release_swflag_ich8lan,
3890 .reset = e1000_phy_hw_reset_ich8lan,
3891 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3892 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3893 .write_reg = e1000e_write_phy_reg_igp,
3894 };
3895
3896 static struct e1000_nvm_operations ich8_nvm_ops = {
3897 .acquire = e1000_acquire_nvm_ich8lan,
3898 .read = e1000_read_nvm_ich8lan,
3899 .release = e1000_release_nvm_ich8lan,
3900 .update = e1000_update_nvm_checksum_ich8lan,
3901 .valid_led_default = e1000_valid_led_default_ich8lan,
3902 .validate = e1000_validate_nvm_checksum_ich8lan,
3903 .write = e1000_write_nvm_ich8lan,
3904 };
3905
3906 struct e1000_info e1000_ich8_info = {
3907 .mac = e1000_ich8lan,
3908 .flags = FLAG_HAS_WOL
3909 | FLAG_IS_ICH
3910 | FLAG_RX_CSUM_ENABLED
3911 | FLAG_HAS_CTRLEXT_ON_LOAD
3912 | FLAG_HAS_AMT
3913 | FLAG_HAS_FLASH
3914 | FLAG_APME_IN_WUC,
3915 .pba = 8,
3916 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3917 .get_variants = e1000_get_variants_ich8lan,
3918 .mac_ops = &ich8_mac_ops,
3919 .phy_ops = &ich8_phy_ops,
3920 .nvm_ops = &ich8_nvm_ops,
3921 };
3922
3923 struct e1000_info e1000_ich9_info = {
3924 .mac = e1000_ich9lan,
3925 .flags = FLAG_HAS_JUMBO_FRAMES
3926 | FLAG_IS_ICH
3927 | FLAG_HAS_WOL
3928 | FLAG_RX_CSUM_ENABLED
3929 | FLAG_HAS_CTRLEXT_ON_LOAD
3930 | FLAG_HAS_AMT
3931 | FLAG_HAS_ERT
3932 | FLAG_HAS_FLASH
3933 | FLAG_APME_IN_WUC,
3934 .pba = 10,
3935 .max_hw_frame_size = DEFAULT_JUMBO,
3936 .get_variants = e1000_get_variants_ich8lan,
3937 .mac_ops = &ich8_mac_ops,
3938 .phy_ops = &ich8_phy_ops,
3939 .nvm_ops = &ich8_nvm_ops,
3940 };
3941
3942 struct e1000_info e1000_ich10_info = {
3943 .mac = e1000_ich10lan,
3944 .flags = FLAG_HAS_JUMBO_FRAMES
3945 | FLAG_IS_ICH
3946 | FLAG_HAS_WOL
3947 | FLAG_RX_CSUM_ENABLED
3948 | FLAG_HAS_CTRLEXT_ON_LOAD
3949 | FLAG_HAS_AMT
3950 | FLAG_HAS_ERT
3951 | FLAG_HAS_FLASH
3952 | FLAG_APME_IN_WUC,
3953 .pba = 10,
3954 .max_hw_frame_size = DEFAULT_JUMBO,
3955 .get_variants = e1000_get_variants_ich8lan,
3956 .mac_ops = &ich8_mac_ops,
3957 .phy_ops = &ich8_phy_ops,
3958 .nvm_ops = &ich8_nvm_ops,
3959 };
3960
3961 struct e1000_info e1000_pch_info = {
3962 .mac = e1000_pchlan,
3963 .flags = FLAG_IS_ICH
3964 | FLAG_HAS_WOL
3965 | FLAG_RX_CSUM_ENABLED
3966 | FLAG_HAS_CTRLEXT_ON_LOAD
3967 | FLAG_HAS_AMT
3968 | FLAG_HAS_FLASH
3969 | FLAG_HAS_JUMBO_FRAMES
3970 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3971 | FLAG_APME_IN_WUC,
3972 .flags2 = FLAG2_HAS_PHY_STATS,
3973 .pba = 26,
3974 .max_hw_frame_size = 4096,
3975 .get_variants = e1000_get_variants_ich8lan,
3976 .mac_ops = &ich8_mac_ops,
3977 .phy_ops = &ich8_phy_ops,
3978 .nvm_ops = &ich8_nvm_ops,
3979 };
3980
3981 struct e1000_info e1000_pch2_info = {
3982 .mac = e1000_pch2lan,
3983 .flags = FLAG_IS_ICH
3984 | FLAG_HAS_WOL
3985 | FLAG_RX_CSUM_ENABLED
3986 | FLAG_HAS_CTRLEXT_ON_LOAD
3987 | FLAG_HAS_AMT
3988 | FLAG_HAS_FLASH
3989 | FLAG_HAS_JUMBO_FRAMES
3990 | FLAG_APME_IN_WUC,
3991 .flags2 = FLAG2_HAS_PHY_STATS
3992 | FLAG2_HAS_EEE,
3993 .pba = 26,
3994 .max_hw_frame_size = DEFAULT_JUMBO,
3995 .get_variants = e1000_get_variants_ich8lan,
3996 .mac_ops = &ich8_mac_ops,
3997 .phy_ops = &ich8_phy_ops,
3998 .nvm_ops = &ich8_nvm_ops,
3999 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree