arch/i386/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/errno.h>
   4 #include <linux/hpet.h>
   5 #include <linux/init.h>
   6
   7 #include <asm/hpet.h>
   8 #include <asm/io.h>
   9
  10 extern struct clock_event_device *global_clock_event;
  11
  12 #define HPET_MASK       CLOCKSOURCE_MASK(32)
  13 #define HPET_SHIFT      22
  14
  15 /* FSEC = 10^-15 NSEC = 10^-9 */
  16 #define FSEC_PER_NSEC   1000000
  17
  18 /*
  19  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  20  */
  21 unsigned long hpet_address;
  22 static void __iomem * hpet_virt_address;
  23
  24 static inline unsigned long hpet_readl(unsigned long a)
  25 {
  26         return readl(hpet_virt_address + a);
  27 }
  28
  29 static inline void hpet_writel(unsigned long d, unsigned long a)
  30 {
  31         writel(d, hpet_virt_address + a);
  32 }
  33
  34 /*
  35  * HPET command line enable / disable
  36  */
  37 static int boot_hpet_disable;
  38
  39 static int __init hpet_setup(char* str)
  40 {
  41         if (str) {
  42                 if (!strncmp("disable", str, 7))
  43                         boot_hpet_disable = 1;
  44         }
  45         return 1;
  46 }
  47 __setup("hpet=", hpet_setup);
  48
  49 static inline int is_hpet_capable(void)
  50 {
  51         return (!boot_hpet_disable && hpet_address);
  52 }
  53
  54 /*
  55  * HPET timer interrupt enable / disable
  56  */
  57 static int hpet_legacy_int_enabled;
  58
  59 /**
  60  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
  61  */
  62 int is_hpet_enabled(void)
  63 {
  64         return is_hpet_capable() && hpet_legacy_int_enabled;
  65 }
  66
  67 /*
  68  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
  69  * timer 0 and timer 1 in case of RTC emulation.
  70  */
  71 #ifdef CONFIG_HPET
  72 static void hpet_reserve_platform_timers(unsigned long id)
  73 {
  74         struct hpet __iomem *hpet = hpet_virt_address;
  75         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
  76         unsigned int nrtimers, i;
  77         struct hpet_data hd;
  78
  79         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
  80
  81         memset(&hd, 0, sizeof (hd));
  82         hd.hd_phys_address = hpet_address;
  83         hd.hd_address = hpet_virt_address;
  84         hd.hd_nirqs = nrtimers;
  85         hd.hd_flags = HPET_DATA_PLATFORM;
  86         hpet_reserve_timer(&hd, 0);
  87
  88 #ifdef CONFIG_HPET_EMULATE_RTC
  89         hpet_reserve_timer(&hd, 1);
  90 #endif
  91
  92         hd.hd_irq[0] = HPET_LEGACY_8254;
  93         hd.hd_irq[1] = HPET_LEGACY_RTC;
  94
  95         for (i = 2; i < nrtimers; timer++, i++)
  96                 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
  97                         Tn_INT_ROUTE_CNF_SHIFT;
  98
  99         hpet_alloc(&hd);
 100
 101 }
 102 #else
 103 static void hpet_reserve_platform_timers(unsigned long id) { }
 104 #endif
 105
 106 /*
 107  * Common hpet info
 108  */
 109 static unsigned long hpet_period;
 110
 111 static void hpet_set_mode(enum clock_event_mode mode,
 112                           struct clock_event_device *evt);
 113 static int hpet_next_event(unsigned long delta,
 114                            struct clock_event_device *evt);
 115
 116 /*
 117  * The hpet clock event device
 118  */
 119 static struct clock_event_device hpet_clockevent = {
 120         .name           = "hpet",
 121         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 122         .set_mode       = hpet_set_mode,
 123         .set_next_event = hpet_next_event,
 124         .shift          = 32,
 125         .irq            = 0,
 126 };
 127
 128 static void hpet_start_counter(void)
 129 {
 130         unsigned long cfg = hpet_readl(HPET_CFG);
 131
 132         cfg &= ~HPET_CFG_ENABLE;
 133         hpet_writel(cfg, HPET_CFG);
 134         hpet_writel(0, HPET_COUNTER);
 135         hpet_writel(0, HPET_COUNTER + 4);
 136         cfg |= HPET_CFG_ENABLE;
 137         hpet_writel(cfg, HPET_CFG);
 138 }
 139
 140 static void hpet_enable_int(void)
 141 {
 142         unsigned long cfg = hpet_readl(HPET_CFG);
 143
 144         cfg |= HPET_CFG_LEGACY;
 145         hpet_writel(cfg, HPET_CFG);
 146         hpet_legacy_int_enabled = 1;
 147 }
 148
 149 static void hpet_set_mode(enum clock_event_mode mode,
 150                           struct clock_event_device *evt)
 151 {
 152         unsigned long cfg, cmp, now;
 153         uint64_t delta;
 154
 155         switch(mode) {
 156         case CLOCK_EVT_MODE_PERIODIC:
 157                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
 158                 delta >>= hpet_clockevent.shift;
 159                 now = hpet_readl(HPET_COUNTER);
 160                 cmp = now + (unsigned long) delta;
 161                 cfg = hpet_readl(HPET_T0_CFG);
 162                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 163                        HPET_TN_SETVAL | HPET_TN_32BIT;
 164                 hpet_writel(cfg, HPET_T0_CFG);
 165                 /*
 166                  * The first write after writing TN_SETVAL to the
 167                  * config register sets the counter value, the second
 168                  * write sets the period.
 169                  */
 170                 hpet_writel(cmp, HPET_T0_CMP);
 171                 udelay(1);
 172                 hpet_writel((unsigned long) delta, HPET_T0_CMP);
 173                 break;
 174
 175         case CLOCK_EVT_MODE_ONESHOT:
 176                 cfg = hpet_readl(HPET_T0_CFG);
 177                 cfg &= ~HPET_TN_PERIODIC;
 178                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 179                 hpet_writel(cfg, HPET_T0_CFG);
 180                 break;
 181
 182         case CLOCK_EVT_MODE_UNUSED:
 183         case CLOCK_EVT_MODE_SHUTDOWN:
 184                 cfg = hpet_readl(HPET_T0_CFG);
 185                 cfg &= ~HPET_TN_ENABLE;
 186                 hpet_writel(cfg, HPET_T0_CFG);
 187                 break;
 188         }
 189 }
 190
 191 static int hpet_next_event(unsigned long delta,
 192                            struct clock_event_device *evt)
 193 {
 194         unsigned long cnt;
 195
 196         cnt = hpet_readl(HPET_COUNTER);
 197         cnt += delta;
 198         hpet_writel(cnt, HPET_T0_CMP);
 199
 200         return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0);
 201 }
 202
 203 /*
 204  * Clock source related code
 205  */
 206 static cycle_t read_hpet(void)
 207 {
 208         return (cycle_t)hpet_readl(HPET_COUNTER);
 209 }
 210
 211 static struct clocksource clocksource_hpet = {
 212         .name           = "hpet",
 213         .rating         = 250,
 214         .read           = read_hpet,
 215         .mask           = HPET_MASK,
 216         .shift          = HPET_SHIFT,
 217         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 218 };
 219
 220 /*
 221  * Try to setup the HPET timer
 222  */
 223 int __init hpet_enable(void)
 224 {
 225         unsigned long id;
 226         uint64_t hpet_freq;
 227         u64 tmp;
 228
 229         if (!is_hpet_capable())
 230                 return 0;
 231
 232         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
 233
 234         /*
 235          * Read the period and check for a sane value:
 236          */
 237         hpet_period = hpet_readl(HPET_PERIOD);
 238         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 239                 goto out_nohpet;
 240
 241         /*
 242          * The period is a femto seconds value. We need to calculate the
 243          * scaled math multiplication factor for nanosecond to hpet tick
 244          * conversion.
 245          */
 246         hpet_freq = 1000000000000000ULL;
 247         do_div(hpet_freq, hpet_period);
 248         hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
 249                                       NSEC_PER_SEC, 32);
 250         /* Calculate the min / max delta */
 251         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 252                                                            &hpet_clockevent);
 253         hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
 254                                                            &hpet_clockevent);
 255
 256         /*
 257          * Read the HPET ID register to retrieve the IRQ routing
 258          * information and the number of channels
 259          */
 260         id = hpet_readl(HPET_ID);
 261
 262 #ifdef CONFIG_HPET_EMULATE_RTC
 263         /*
 264          * The legacy routing mode needs at least two channels, tick timer
 265          * and the rtc emulation channel.
 266          */
 267         if (!(id & HPET_ID_NUMBER))
 268                 goto out_nohpet;
 269 #endif
 270
 271         /* Start the counter */
 272         hpet_start_counter();
 273
 274         /* Initialize and register HPET clocksource
 275          *
 276          * hpet period is in femto seconds per cycle
 277          * so we need to convert this to ns/cyc units
 278          * aproximated by mult/2^shift
 279          *
 280          *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
 281          *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
 282          *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
 283          *  (fsec/cyc << shift)/1000000 = mult
 284          *  (hpet_period << shift)/FSEC_PER_NSEC = mult
 285          */
 286         tmp = (u64)hpet_period << HPET_SHIFT;
 287         do_div(tmp, FSEC_PER_NSEC);
 288         clocksource_hpet.mult = (u32)tmp;
 289
 290         clocksource_register(&clocksource_hpet);
 291
 292
 293         if (id & HPET_ID_LEGSUP) {
 294                 hpet_enable_int();
 295                 hpet_reserve_platform_timers(id);
 296                 /*
 297                  * Start hpet with the boot cpu mask and make it
 298                  * global after the IO_APIC has been initialized.
 299                  */
 300                 hpet_clockevent.cpumask =cpumask_of_cpu(0);
 301                 clockevents_register_device(&hpet_clockevent);
 302                 global_clock_event = &hpet_clockevent;
 303                 return 1;
 304         }
 305         return 0;
 306
 307 out_nohpet:
 308         iounmap(hpet_virt_address);
 309         hpet_virt_address = NULL;
 310         return 0;
 311 }
 312
 313
 314 #ifdef CONFIG_HPET_EMULATE_RTC
 315
 316 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 317  * is enabled, we support RTC interrupt functionality in software.
 318  * RTC has 3 kinds of interrupts:
 319  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 320  *    is updated
 321  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 322  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 323  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 324  * (1) and (2) above are implemented using polling at a frequency of
 325  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 326  * overhead. (DEFAULT_RTC_INT_FREQ)
 327  * For (3), we use interrupts at 64Hz or user specified periodic
 328  * frequency, whichever is higher.
 329  */
 330 #include <linux/mc146818rtc.h>
 331 #include <linux/rtc.h>
 332
 333 #define DEFAULT_RTC_INT_FREQ    64
 334 #define DEFAULT_RTC_SHIFT       6
 335 #define RTC_NUM_INTS            1
 336
 337 static unsigned long hpet_rtc_flags;
 338 static unsigned long hpet_prev_update_sec;
 339 static struct rtc_time hpet_alarm_time;
 340 static unsigned long hpet_pie_count;
 341 static unsigned long hpet_t1_cmp;
 342 static unsigned long hpet_default_delta;
 343 static unsigned long hpet_pie_delta;
 344 static unsigned long hpet_pie_limit;
 345
 346 /*
 347  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 348  * is not supported by all HPET implementations for timer 1.
 349  *
 350  * hpet_rtc_timer_init() is called when the rtc is initialized.
 351  */
 352 int hpet_rtc_timer_init(void)
 353 {
 354         unsigned long cfg, cnt, delta, flags;
 355
 356         if (!is_hpet_enabled())
 357                 return 0;
 358
 359         if (!hpet_default_delta) {
 360                 uint64_t clc;
 361
 362                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 363                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
 364                 hpet_default_delta = (unsigned long) clc;
 365         }
 366
 367         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 368                 delta = hpet_default_delta;
 369         else
 370                 delta = hpet_pie_delta;
 371
 372         local_irq_save(flags);
 373
 374         cnt = delta + hpet_readl(HPET_COUNTER);
 375         hpet_writel(cnt, HPET_T1_CMP);
 376         hpet_t1_cmp = cnt;
 377
 378         cfg = hpet_readl(HPET_T1_CFG);
 379         cfg &= ~HPET_TN_PERIODIC;
 380         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 381         hpet_writel(cfg, HPET_T1_CFG);
 382
 383         local_irq_restore(flags);
 384
 385         return 1;
 386 }
 387
 388 /*
 389  * The functions below are called from rtc driver.
 390  * Return 0 if HPET is not being used.
 391  * Otherwise do the necessary changes and return 1.
 392  */
 393 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
 394 {
 395         if (!is_hpet_enabled())
 396                 return 0;
 397
 398         hpet_rtc_flags &= ~bit_mask;
 399         return 1;
 400 }
 401
 402 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
 403 {
 404         unsigned long oldbits = hpet_rtc_flags;
 405
 406         if (!is_hpet_enabled())
 407                 return 0;
 408
 409         hpet_rtc_flags |= bit_mask;
 410
 411         if (!oldbits)
 412                 hpet_rtc_timer_init();
 413
 414         return 1;
 415 }
 416
 417 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
 418                         unsigned char sec)
 419 {
 420         if (!is_hpet_enabled())
 421                 return 0;
 422
 423         hpet_alarm_time.tm_hour = hrs;
 424         hpet_alarm_time.tm_min = min;
 425         hpet_alarm_time.tm_sec = sec;
 426
 427         return 1;
 428 }
 429
 430 int hpet_set_periodic_freq(unsigned long freq)
 431 {
 432         uint64_t clc;
 433
 434         if (!is_hpet_enabled())
 435                 return 0;
 436
 437         if (freq <= DEFAULT_RTC_INT_FREQ)
 438                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
 439         else {
 440                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 441                 do_div(clc, freq);
 442                 clc >>= hpet_clockevent.shift;
 443                 hpet_pie_delta = (unsigned long) clc;
 444         }
 445         return 1;
 446 }
 447
 448 int hpet_rtc_dropped_irq(void)
 449 {
 450         return is_hpet_enabled();
 451 }
 452
 453 static void hpet_rtc_timer_reinit(void)
 454 {
 455         unsigned long cfg, delta;
 456         int lost_ints = -1;
 457
 458         if (unlikely(!hpet_rtc_flags)) {
 459                 cfg = hpet_readl(HPET_T1_CFG);
 460                 cfg &= ~HPET_TN_ENABLE;
 461                 hpet_writel(cfg, HPET_T1_CFG);
 462                 return;
 463         }
 464
 465         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 466                 delta = hpet_default_delta;
 467         else
 468                 delta = hpet_pie_delta;
 469
 470         /*
 471          * Increment the comparator value until we are ahead of the
 472          * current count.
 473          */
 474         do {
 475                 hpet_t1_cmp += delta;
 476                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
 477                 lost_ints++;
 478         } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
 479
 480         if (lost_ints) {
 481                 if (hpet_rtc_flags & RTC_PIE)
 482                         hpet_pie_count += lost_ints;
 483                 if (printk_ratelimit())
 484                         printk(KERN_WARNING "rtc: lost %d interrupts\n",
 485                                 lost_ints);
 486         }
 487 }
 488
 489 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
 490 {
 491         struct rtc_time curr_time;
 492         unsigned long rtc_int_flag = 0;
 493
 494         hpet_rtc_timer_reinit();
 495
 496         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
 497                 rtc_get_rtc_time(&curr_time);
 498
 499         if (hpet_rtc_flags & RTC_UIE &&
 500             curr_time.tm_sec != hpet_prev_update_sec) {
 501                 rtc_int_flag = RTC_UF;
 502                 hpet_prev_update_sec = curr_time.tm_sec;
 503         }
 504
 505         if (hpet_rtc_flags & RTC_PIE &&
 506             ++hpet_pie_count >= hpet_pie_limit) {
 507                 rtc_int_flag |= RTC_PF;
 508                 hpet_pie_count = 0;
 509         }
 510
 511         if (hpet_rtc_flags & RTC_PIE &&
 512             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
 513             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
 514             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
 515                         rtc_int_flag |= RTC_AF;
 516
 517         if (rtc_int_flag) {
 518                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
 519                 rtc_interrupt(rtc_int_flag, dev_id);
 520         }
 521         return IRQ_HANDLED;
 522 }
 523 #endif