arch/x86/pci/i386.c

   1 /*
   2  *      Low-Level PCI Access for i386 machines
   3  *
   4  * Copyright 1993, 1994 Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      Drew@Colorado.EDU
   8  *      +1 (303) 786-7975
   9  *
  10  * Drew's work was sponsored by:
  11  *      iX Multiuser Multitasking Magazine
  12  *      Hannover, Germany
  13  *      hm@ix.de
  14  *
  15  * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
  16  *
  17  * For more information, please consult the following manuals (look at
  18  * http://www.pcisig.com/ for how to get them):
  19  *
  20  * PCI BIOS Specification
  21  * PCI Local Bus Specification
  22  * PCI to PCI Bridge Specification
  23  * PCI System Design Guide
  24  *
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/errno.h>
  33 #include <linux/bootmem.h>
  34
  35 #include <asm/pat.h>
  36 #include <asm/e820.h>
  37 #include <asm/pci_x86.h>
  38 #include <asm/io_apic.h>
  39
  40
  41 static int
  42 skip_isa_ioresource_align(struct pci_dev *dev) {
  43
  44         if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
  45             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
  46                 return 1;
  47         return 0;
  48 }
  49
  50 /*
  51  * We need to avoid collisions with `mirrored' VGA ports
  52  * and other strange ISA hardware, so we always want the
  53  * addresses to be allocated in the 0x000-0x0ff region
  54  * modulo 0x400.
  55  *
  56  * Why? Because some silly external IO cards only decode
  57  * the low 10 bits of the IO address. The 0x00-0xff region
  58  * is reserved for motherboard devices that decode all 16
  59  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  60  * but we want to try to avoid allocating at 0x2900-0x2bff
  61  * which might have be mirrored at 0x0100-0x03ff..
  62  */
  63 resource_size_t
  64 pcibios_align_resource(void *data, const struct resource *res,
  65                         resource_size_t size, resource_size_t align)
  66 {
  67         struct pci_dev *dev = data;
  68         resource_size_t start = round_down(res->end - size + 1, align);
  69
  70         if (res->flags & IORESOURCE_IO) {
  71
  72                 /*
  73                  * If we're avoiding ISA aliases, the largest contiguous I/O
  74                  * port space is 256 bytes.  Clearing bits 9 and 10 preserves
  75                  * all 256-byte and smaller alignments, so the result will
  76                  * still be correctly aligned.
  77                  */
  78                 if (!skip_isa_ioresource_align(dev))
  79                         start &= ~0x300;
  80         } else if (res->flags & IORESOURCE_MEM) {
  81                 if (start < BIOS_END)
  82                         start = res->end;       /* fail; no space */
  83         }
  84         return start;
  85 }
  86 EXPORT_SYMBOL(pcibios_align_resource);
  87
  88 /*
  89  *  Handle resources of PCI devices.  If the world were perfect, we could
  90  *  just allocate all the resource regions and do nothing more.  It isn't.
  91  *  On the other hand, we cannot just re-allocate all devices, as it would
  92  *  require us to know lots of host bridge internals.  So we attempt to
  93  *  keep as much of the original configuration as possible, but tweak it
  94  *  when it's found to be wrong.
  95  *
  96  *  Known BIOS problems we have to work around:
  97  *      - I/O or memory regions not configured
  98  *      - regions configured, but not enabled in the command register
  99  *      - bogus I/O addresses above 64K used
 100  *      - expansion ROMs left enabled (this may sound harmless, but given
 101  *        the fact the PCI specs explicitly allow address decoders to be
 102  *        shared between expansion ROMs and other resource regions, it's
 103  *        at least dangerous)
 104  *      - bad resource sizes or overlaps with other regions
 105  *
 106  *  Our solution:
 107  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 108  *          This gives us fixed barriers on where we can allocate.
 109  *      (2) Allocate resources for all enabled devices.  If there is
 110  *          a collision, just mark the resource as unallocated. Also
 111  *          disable expansion ROMs during this step.
 112  *      (3) Try to allocate resources for disabled devices.  If the
 113  *          resources were assigned correctly, everything goes well,
 114  *          if they weren't, they won't disturb allocation of other
 115  *          resources.
 116  *      (4) Assign new addresses to resources which were either
 117  *          not configured at all or misconfigured.  If explicitly
 118  *          requested by the user, configure expansion ROM address
 119  *          as well.
 120  */
 121
 122 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
 123 {
 124         struct pci_bus *bus;
 125         struct pci_dev *dev;
 126         int idx;
 127         struct resource *r;
 128
 129         /* Depth-First Search on bus tree */
 130         list_for_each_entry(bus, bus_list, node) {
 131                 if ((dev = bus->self)) {
 132                         for (idx = PCI_BRIDGE_RESOURCES;
 133                             idx < PCI_NUM_RESOURCES; idx++) {
 134                                 r = &dev->resource[idx];
 135                                 if (!r->flags)
 136                                         continue;
 137                                 if (!r->start ||
 138                                     pci_claim_resource(dev, idx) < 0) {
 139                                         /*
 140                                          * Something is wrong with the region.
 141                                          * Invalidate the resource to prevent
 142                                          * child resource allocations in this
 143                                          * range.
 144                                          */
 145                                         r->start = r->end = 0;
 146                                         r->flags = 0;
 147                                 }
 148                         }
 149                 }
 150                 pcibios_allocate_bus_resources(&bus->children);
 151         }
 152 }
 153
 154 struct pci_check_idx_range {
 155         int start;
 156         int end;
 157 };
 158
 159 static void __init pcibios_allocate_resources(int pass)
 160 {
 161         struct pci_dev *dev = NULL;
 162         int idx, disabled, i;
 163         u16 command;
 164         struct resource *r;
 165
 166         struct pci_check_idx_range idx_range[] = {
 167                 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
 168 #ifdef CONFIG_PCI_IOV
 169                 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
 170 #endif
 171         };
 172
 173         for_each_pci_dev(dev) {
 174                 pci_read_config_word(dev, PCI_COMMAND, &command);
 175                 for (i = 0; i < ARRAY_SIZE(idx_range); i++)
 176                 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
 177                         r = &dev->resource[idx];
 178                         if (r->parent)          /* Already allocated */
 179                                 continue;
 180                         if (!r->start)          /* Address not assigned at all */
 181                                 continue;
 182                         if (r->flags & IORESOURCE_IO)
 183                                 disabled = !(command & PCI_COMMAND_IO);
 184                         else
 185                                 disabled = !(command & PCI_COMMAND_MEMORY);
 186                         if (pass == disabled) {
 187                                 dev_dbg(&dev->dev,
 188                                         "BAR %d: reserving %pr (d=%d, p=%d)\n",
 189                                         idx, r, disabled, pass);
 190                                 if (pci_claim_resource(dev, idx) < 0) {
 191                                         /* We'll assign a new address later */
 192                                         dev->fw_addr[idx] = r->start;
 193                                         r->end -= r->start;
 194                                         r->start = 0;
 195                                 }
 196                         }
 197                 }
 198                 if (!pass) {
 199                         r = &dev->resource[PCI_ROM_RESOURCE];
 200                         if (r->flags & IORESOURCE_ROM_ENABLE) {
 201                                 /* Turn the ROM off, leave the resource region,
 202                                  * but keep it unregistered. */
 203                                 u32 reg;
 204                                 dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
 205                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 206                                 pci_read_config_dword(dev,
 207                                                 dev->rom_base_reg, &reg);
 208                                 pci_write_config_dword(dev, dev->rom_base_reg,
 209                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
 210                         }
 211                 }
 212         }
 213 }
 214
 215 static int __init pcibios_assign_resources(void)
 216 {
 217         struct pci_dev *dev = NULL;
 218         struct resource *r;
 219
 220         if (!(pci_probe & PCI_ASSIGN_ROMS)) {
 221                 /*
 222                  * Try to use BIOS settings for ROMs, otherwise let
 223                  * pci_assign_unassigned_resources() allocate the new
 224                  * addresses.
 225                  */
 226                 for_each_pci_dev(dev) {
 227                         r = &dev->resource[PCI_ROM_RESOURCE];
 228                         if (!r->flags || !r->start)
 229                                 continue;
 230                         if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
 231                                 r->end -= r->start;
 232                                 r->start = 0;
 233                         }
 234                 }
 235         }
 236
 237         pci_assign_unassigned_resources();
 238
 239         return 0;
 240 }
 241
 242 void __init pcibios_resource_survey(void)
 243 {
 244         DBG("PCI: Allocating resources\n");
 245         pcibios_allocate_bus_resources(&pci_root_buses);
 246         pcibios_allocate_resources(0);
 247         pcibios_allocate_resources(1);
 248
 249         e820_reserve_resources_late();
 250         /*
 251          * Insert the IO APIC resources after PCI initialization has
 252          * occured to handle IO APICS that are mapped in on a BAR in
 253          * PCI space, but before trying to assign unassigned pci res.
 254          */
 255         ioapic_insert_resources();
 256 }
 257
 258 /**
 259  * called in fs_initcall (one below subsys_initcall),
 260  * give a chance for motherboard reserve resources
 261  */
 262 fs_initcall(pcibios_assign_resources);
 263
 264 /*
 265  *  If we set up a device for bus mastering, we need to check the latency
 266  *  timer as certain crappy BIOSes forget to set it properly.
 267  */
 268 unsigned int pcibios_max_latency = 255;
 269
 270 void pcibios_set_master(struct pci_dev *dev)
 271 {
 272         u8 lat;
 273         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 274         if (lat < 16)
 275                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 276         else if (lat > pcibios_max_latency)
 277                 lat = pcibios_max_latency;
 278         else
 279                 return;
 280         dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
 281         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 282 }
 283
 284 static const struct vm_operations_struct pci_mmap_ops = {
 285         .access = generic_access_phys,
 286 };
 287
 288 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 289                         enum pci_mmap_state mmap_state, int write_combine)
 290 {
 291         unsigned long prot;
 292
 293         /* I/O space cannot be accessed via normal processor loads and
 294          * stores on this platform.
 295          */
 296         if (mmap_state == pci_mmap_io)
 297                 return -EINVAL;
 298
 299         prot = pgprot_val(vma->vm_page_prot);
 300
 301         /*
 302          * Return error if pat is not enabled and write_combine is requested.
 303          * Caller can followup with UC MINUS request and add a WC mtrr if there
 304          * is a free mtrr slot.
 305          */
 306         if (!pat_enabled && write_combine)
 307                 return -EINVAL;
 308
 309         if (pat_enabled && write_combine)
 310                 prot |= _PAGE_CACHE_WC;
 311         else if (pat_enabled || boot_cpu_data.x86 > 3)
 312                 /*
 313                  * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
 314                  * To avoid attribute conflicts, request UC MINUS here
 315                  * aswell.
 316                  */
 317                 prot |= _PAGE_CACHE_UC_MINUS;
 318
 319         prot |= _PAGE_IOMAP;    /* creating a mapping for IO */
 320
 321         vma->vm_page_prot = __pgprot(prot);
 322
 323         if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 324                                vma->vm_end - vma->vm_start,
 325                                vma->vm_page_prot))
 326                 return -EAGAIN;
 327
 328         vma->vm_ops = &pci_mmap_ops;
 329
 330         return 0;
 331 }