1 #include <linux/kernel.h>
2 #include <linux/init.h>
3 #include <linux/module.h>
6 #include <linux/device.h>
8 #include <scsi/scsi_host.h>
9 #include <linux/libata.h>
13 /* #define DBGPRINTF */
17 #define dbgprintf(format, arg...) printk(KERN_INFO format, ## arg)
21 #define dbgprintf(...)
26 #define DRIVER_NAME "pata_rdc" /* sata_rdc for SATA */
27 #define DRIVER_VERSION "2.6.28" /* based on kernel version. */
28 /* because each kernel main version has
29 * its libata, we follow kernel to
30 * determine the last libata version.
34 static const struct pci_device_id rdc_pata_id_table
[] = {
35 { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011
},
36 { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012
},
37 { } /* terminate list */
39 MODULE_DEVICE_TABLE(pci
, rdc_pata_id_table
);
41 static unsigned int in_module_init
= 1; /* hotplugging check??? */
45 /* see ATA Host Adapters Standards. */
46 static struct pci_bits ATA_Decode_Enable_Bits
[] = {
47 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port (Channel) 0 */
48 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port (Channel) 1 */
51 static uint
PCIDeviceIO_ReadPCIConfiguration(struct pci_dev
*pdev
, uint Offset
, uint Length
, void *pBuffer
)
61 for (i
= 0; i
< Length
; i
++) {
62 pci_read_config_byte(pdev
, Offset
, pchar
);
75 static uint
PCIDeviceIO_WritePCIConfiguration(struct pci_dev
*pdev
, uint Offset
, uint Length
, void *pBuffer
)
85 for (i
= 0; i
< Length
; i
++) {
86 pci_write_config_byte(pdev
, Offset
, *pchar
);
99 static uint
ATAHostAdapter_SetPrimaryPIO(struct pci_dev
*pdev
, uint DeviceID
,
100 uint PIOTimingMode
, uint DMAEnable
,
101 uint PrefetchPostingEnable
)
105 uint ATATimingRegister
;
106 uint Device1TimingRegister
;
110 ATATimingRegister
= 0;
111 Device1TimingRegister
= 0;
113 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
114 ATAConfiguration_ID_PrimaryTiming
+ ATAConfiguration_PCIOffset
,
115 ATAConfiguration_ID_PrimaryTiming_Size
,
117 if (result
== FALSE
) {
122 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
123 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
124 ATAConfiguration_ID_Device1Timing_Size
,
125 &Device1TimingRegister
);
126 if (result
== FALSE
) {
131 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable
;
136 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
|
137 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
|
138 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
|
139 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
|
140 ATAConfiguration_PrimaryTiming_Device0RecoveryMode
|
141 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
);
143 if (PIOTimingMode
> PIO0
)
144 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
;
146 if (PIOTimingMode
>= PIO3
)
147 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
;
149 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
150 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
;
152 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
153 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
;
155 if (PIOTimingMode
<= PIO2
)
156 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0
;
157 else if (PIOTimingMode
== PIO3
)
158 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1
;
159 else if (PIOTimingMode
== PIO4
)
160 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3
;
162 if (PIOTimingMode
<= PIO1
)
163 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0
;
164 else if (PIOTimingMode
== PIO2
)
165 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1
;
166 else if (PIOTimingMode
<= PIO4
)
167 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2
;
170 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
|
171 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
|
172 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
|
173 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
);
175 if (PIOTimingMode
> PIO0
)
176 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
;
178 if (PIOTimingMode
>= PIO3
)
179 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
;
181 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
182 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
;
184 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
185 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
;
187 Device1TimingRegister
&= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode
|
188 ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode
);
190 if (PIOTimingMode
<= PIO2
)
191 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0
;
192 else if (PIOTimingMode
== PIO3
)
193 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1
;
194 else if (PIOTimingMode
== PIO4
)
195 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3
;
197 if (PIOTimingMode
<= PIO1
)
198 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0
;
199 else if (PIOTimingMode
== PIO2
)
200 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1
;
201 else if (PIOTimingMode
<= PIO4
)
202 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2
;
210 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
211 ATAConfiguration_ID_PrimaryTiming
+ ATAConfiguration_PCIOffset
,
212 ATAConfiguration_ID_PrimaryTiming_Size
,
214 if (result
== FALSE
) {
219 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
220 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
221 ATAConfiguration_ID_Device1Timing_Size
,
222 &Device1TimingRegister
);
223 if (result
== FALSE
) {
234 static uint
ATAHostAdapter_SetSecondaryPIO(struct pci_dev
*pdev
, uint DeviceID
,
235 uint PIOTimingMode
, uint DMAEnable
,
236 uint PrefetchPostingEnable
)
240 uint ATATimingRegister
;
241 uint Device1TimingRegister
;
245 ATATimingRegister
= 0;
246 Device1TimingRegister
= 0;
248 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
249 ATAConfiguration_ID_SecondaryTiming
+ ATAConfiguration_PCIOffset
,
250 ATAConfiguration_ID_SecondaryTiming_Size
,
252 if (result
== FALSE
) {
257 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
258 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
259 ATAConfiguration_ID_Device1Timing_Size
,
260 &Device1TimingRegister
);
261 if (result
== FALSE
) {
266 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable
;
271 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
|
272 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
|
273 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
|
274 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
|
275 ATAConfiguration_PrimaryTiming_Device0RecoveryMode
|
276 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
);
278 if (PIOTimingMode
> PIO0
)
279 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
;
281 if (PIOTimingMode
>= PIO3
)
282 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
;
284 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
285 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
;
287 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
288 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
;
290 if (PIOTimingMode
<= PIO2
)
291 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0
;
292 else if (PIOTimingMode
== PIO3
)
293 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1
;
294 else if (PIOTimingMode
== PIO4
)
295 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3
;
297 if (PIOTimingMode
<= PIO1
)
298 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0
;
299 else if (PIOTimingMode
== PIO2
)
300 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1
;
301 else if (PIOTimingMode
<= PIO4
)
302 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2
;
305 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
|
306 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
|
307 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
|
308 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
);
310 if (PIOTimingMode
> PIO0
)
311 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
;
313 if (PIOTimingMode
>= PIO3
)
314 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
;
316 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
317 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
;
319 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
320 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
;
322 Device1TimingRegister
&= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode
|
323 ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode
);
325 if (PIOTimingMode
<= PIO2
)
326 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0
;
327 else if (PIOTimingMode
== PIO3
)
328 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1
;
329 else if (PIOTimingMode
== PIO4
)
330 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3
;
332 if (PIOTimingMode
<= PIO1
)
333 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0
;
334 else if (PIOTimingMode
== PIO2
)
335 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1
;
336 else if (PIOTimingMode
<= PIO4
)
337 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2
;
345 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
346 ATAConfiguration_ID_SecondaryTiming
+ ATAConfiguration_PCIOffset
,
347 ATAConfiguration_ID_SecondaryTiming_Size
,
349 if (result
== FALSE
) {
354 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
355 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
356 ATAConfiguration_ID_Device1Timing_Size
,
357 &Device1TimingRegister
);
358 if (result
== FALSE
) {
368 static uint
ATAHostAdapter_SetPrimaryUDMA(struct pci_dev
*pdev
, uint DeviceID
,
369 uint UDMAEnable
, uint UDMATimingMode
)
373 uint UDMAControlRegister
;
374 uint UDMATimingRegister
;
375 ulong IDEIOConfigurationRegister
;
378 UDMAControlRegister
= 0;
379 UDMATimingRegister
= 0;
380 IDEIOConfigurationRegister
= 0;
382 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
383 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
384 ATAConfiguration_ID_UDMAControl_Size
,
385 &UDMAControlRegister
);
386 if (result
== FALSE
) {
391 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
392 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
393 ATAConfiguration_ID_UDMATiming_Size
,
394 &UDMATimingRegister
);
395 if (result
== FALSE
) {
400 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
401 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
402 ATAConfiguration_ID_IDEIOConfiguration_Size
,
403 &IDEIOConfigurationRegister
);
404 if (result
== FALSE
) {
409 /*Rom Code will determine the device cable type and ATA 100.*/
410 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
411 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
415 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable
);
416 if (UDMAEnable
== TRUE
)
417 UDMAControlRegister
|= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable
;
419 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable
|
420 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable
);
422 if (UDMATimingMode
>= UDMA5
)
423 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable
;
424 else if (UDMATimingMode
>= UDMA3
)
425 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable
;
427 /* if 80 cable report */
428 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime
);
430 if (UDMATimingMode
== UDMA0
) {
431 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0
;
432 } else if (UDMATimingMode
== UDMA1
||
433 UDMATimingMode
== UDMA3
||
434 UDMATimingMode
== UDMA5
) {
435 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1
;
436 } else if (UDMATimingMode
== UDMA2
||
437 UDMATimingMode
== UDMA4
) {
438 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2
;
442 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable
);
443 if (UDMAEnable
== TRUE
)
444 UDMAControlRegister
|= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable
;
446 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable
|
447 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable
);
449 if (UDMATimingMode
>= UDMA5
)
450 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable
;
451 else if (UDMATimingMode
>= UDMA3
)
452 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable
;
454 /* if 80 cable report */
455 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime
);
457 if (UDMATimingMode
== UDMA0
) {
458 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0
;
459 } else if (UDMATimingMode
== UDMA1
||
460 UDMATimingMode
== UDMA3
||
461 UDMATimingMode
== UDMA5
) {
462 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1
;
463 } else if (UDMATimingMode
== UDMA2
||
464 UDMATimingMode
== UDMA4
) {
465 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2
;
474 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
475 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
476 ATAConfiguration_ID_UDMAControl_Size
,
477 &UDMAControlRegister
);
478 if (result
== FALSE
) {
483 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
484 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
485 ATAConfiguration_ID_UDMATiming_Size
,
486 &UDMATimingRegister
);
487 if (result
== FALSE
) {
492 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
493 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
494 ATAConfiguration_ID_IDEIOConfiguration_Size
,
495 &IDEIOConfigurationRegister
);
496 if (result
== FALSE
) {
506 static uint
ATAHostAdapter_SetSecondaryUDMA(struct pci_dev
*pdev
, uint DeviceID
,
507 uint UDMAEnable
, uint UDMATimingMode
)
511 uint UDMAControlRegister
;
512 uint UDMATimingRegister
;
513 ulong IDEIOConfigurationRegister
;
517 UDMAControlRegister
= 0;
518 UDMATimingRegister
= 0;
519 IDEIOConfigurationRegister
= 0;
521 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
522 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
523 ATAConfiguration_ID_UDMAControl_Size
,
524 &UDMAControlRegister
);
525 if (result
== FALSE
) {
530 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
531 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
532 ATAConfiguration_ID_UDMATiming_Size
,
533 &UDMATimingRegister
);
534 if (result
== FALSE
) {
539 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
540 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
541 ATAConfiguration_ID_IDEIOConfiguration_Size
,
542 &IDEIOConfigurationRegister
);
543 if (result
== FALSE
) {
548 /* Rom Code will determine the device cable type and ATA 100. */
549 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
550 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
554 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable
);
555 if (UDMAEnable
== TRUE
)
556 UDMAControlRegister
|= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable
;
558 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable
|
559 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable
);
561 if (UDMATimingMode
>= UDMA5
)
562 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable
;
563 else if (UDMATimingMode
>= UDMA3
)
564 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable
;
566 /* if 80 cable report */
567 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime
);
569 if (UDMATimingMode
== UDMA0
) {
570 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0
;
571 } else if (UDMATimingMode
== UDMA1
||
572 UDMATimingMode
== UDMA3
||
573 UDMATimingMode
== UDMA5
) {
574 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1
;
575 } else if (UDMATimingMode
== UDMA2
||
576 UDMATimingMode
== UDMA4
) {
577 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2
;
581 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable
);
582 if (UDMAEnable
== TRUE
)
583 UDMAControlRegister
|= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable
;
585 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable
|
586 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable
);
588 if (UDMATimingMode
>= UDMA5
)
589 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable
;
590 else if (UDMATimingMode
>= UDMA3
)
591 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable
;
593 /* if 80 cable report */
594 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime
);
596 if (UDMATimingMode
== UDMA0
) {
597 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0
;
598 } else if (UDMATimingMode
== UDMA1
||
599 UDMATimingMode
== UDMA3
||
600 UDMATimingMode
== UDMA5
) {
601 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1
;
602 } else if (UDMATimingMode
== UDMA2
||
603 UDMATimingMode
== UDMA4
) {
604 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2
;
613 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
614 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
615 ATAConfiguration_ID_UDMAControl_Size
,
616 &UDMAControlRegister
);
617 if (result
== FALSE
) {
622 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
623 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
624 ATAConfiguration_ID_UDMATiming_Size
,
625 &UDMATimingRegister
);
626 if (result
== FALSE
) {
631 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
632 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
633 ATAConfiguration_ID_IDEIOConfiguration_Size
,
634 &IDEIOConfigurationRegister
);
635 if (result
== FALSE
) {
646 * Set port up for dma.
647 * @ap: Port to initialize
649 * Called just after data structures for each port are
650 * initialized. Allocates space for PRD table if the device
651 * is DMA capable SFF.
653 Some drivers also use this entry point as a chance to allocate driverprivate
654 memory for ap->private_data.
657 * May be used as the port_start() entry in ata_port_operations.
660 * Inherited from caller.
662 static int rdc_pata_port_start(struct ata_port
*ap
)
666 Channel
= ap
->port_no
;
667 dbgprintf("rdc_pata_port_start Channel: %u \n", Channel
);
668 if (ap
->ioaddr
.bmdma_addr
) {
669 return ata_port_start(ap
);
671 dbgprintf("rdc_pata_port_start return 0 !!!\n");
676 static void rdc_pata_port_stop(struct ata_port
*ap
)
680 Channel
= ap
->port_no
;
682 dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel
);
686 * prereset for PATA host controller
688 * @deadline: deadline jiffies for the operation
691 * None (inherited from caller).
693 static int rdc_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
695 struct pci_dev
*pdev
;
699 dbgprintf("rdc_pata_prereset\n");
702 pdev
= to_pci_dev(ap
->host
->dev
);
704 Channel
= ap
->port_no
;
706 /* test ATA Decode Enable Bits, should be enable. */
707 if (!pci_test_config_bits(pdev
, &ATA_Decode_Enable_Bits
[Channel
])) {
708 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel
);
711 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel
);
712 return ata_std_prereset(link
, deadline
);
717 * Probe host controller cable detect info
718 * @ap: Port for which cable detect info is desired
720 * Read cable indicator from ATA PCI device's PCI config
721 * register. This register is normally set by firmware (BIOS).
724 * None (inherited from caller).
726 static int rdc_pata_cable_detect(struct ata_port
*ap
)
728 struct pci_dev
*pdev
;
733 dbgprintf("rdc_pata_cable_detect\n");
735 pdev
= to_pci_dev(ap
->host
->dev
);
737 Channel
= ap
->port_no
;
740 Mask
= ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report
;
742 Mask
= ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report
;
744 /* check BIOS cable detect results */
745 pci_read_config_dword(pdev
, ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
, &u32Value
);
747 if ((u32Value
& Mask
) == 0) {
748 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel
);
749 return ATA_CBL_PATA40
;
751 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel
);
752 return ATA_CBL_PATA80
;
757 * Initialize host controller PATA PIO timings
758 * @ap: Port whose timings we are configuring
761 * Set PIO mode for device, in host controller PCI config space.
764 * None (inherited from caller).
766 static void rdc_pata_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
768 struct pci_dev
*pdev
;
772 uint PrefetchPostingEnable
;
774 dbgprintf("rdc_pata_set_piomode\n");
776 pdev
= to_pci_dev(ap
->host
->dev
);
778 Channel
= ap
->port_no
;
779 DeviceID
= adev
->devno
;
781 * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
782 * XFER_PIO_2, XFER_PIO_3...
784 PIOTimingMode
= adev
->pio_mode
- XFER_PIO_0
;
786 if (adev
->class == ATA_DEV_ATA
) {
787 PrefetchPostingEnable
= TRUE
;
789 /* ATAPI, CD DVD Rom */
790 PrefetchPostingEnable
= FALSE
;
793 /* PIO configuration clears DTE unconditionally. It will be
794 * programmed in set_dmamode which is guaranteed to be called
795 * after set_piomode if any DMA mode is available.
798 /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
802 ATAHostAdapter_SetPrimaryPIO(
806 TRUE
,/* DMAEnable, */
807 PrefetchPostingEnable
810 ATAHostAdapter_SetPrimaryUDMA(
813 FALSE
,/* UDMAEnable, */
817 ATAHostAdapter_SetSecondaryPIO(
821 TRUE
,/* DMAEnable, */
822 PrefetchPostingEnable
825 ATAHostAdapter_SetSecondaryUDMA(
828 FALSE
,/* UDMAEnable, */
832 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel
, DeviceID
, PIOTimingMode
);
836 * Initialize host controller PATA DMA timings
837 * @ap: Port whose timings we are configuring
840 * Set MW/UDMA mode for device, in host controller PCI config space.
843 * None (inherited from caller).
845 static void rdc_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
847 struct pci_dev
*pdev
;
851 uint PrefetchPostingEnable
;
855 dbgprintf("rdc_pata_set_dmamode\n");
857 pdev
= to_pci_dev(ap
->host
->dev
);
859 Channel
= ap
->port_no
;
860 DeviceID
= adev
->devno
;
861 PIOTimingMode
= adev
->pio_mode
- XFER_PIO_0
; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
862 DMATimingMode
= adev
->dma_mode
; /* UDMA or MDMA */
864 if (adev
->class == ATA_DEV_ATA
) {
865 PrefetchPostingEnable
= TRUE
;
867 /* ATAPI, CD DVD Rom */
868 PrefetchPostingEnable
= FALSE
;
871 if (ap
->udma_mask
== 0) {
872 /* ata_port dont support udma. depend on hardware spec. */
878 /*if (ap->mdma_mask == 0) {
882 if (DMATimingMode
>= XFER_UDMA_0
) {
884 ATAHostAdapter_SetPrimaryPIO(pdev
,
888 PrefetchPostingEnable
);
890 ATAHostAdapter_SetPrimaryUDMA(pdev
,
893 DMATimingMode
- XFER_UDMA_0
);
894 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel
, DeviceID
, (uint
)(DMATimingMode
- XFER_UDMA_0
));
897 ATAHostAdapter_SetPrimaryPIO(pdev
,
899 (DMATimingMode
- XFER_MW_DMA_0
) + PIO2
, /* MDMA0 = PIO2 */
901 PrefetchPostingEnable
);
903 ATAHostAdapter_SetPrimaryUDMA(pdev
,
905 FALSE
,/*UDMAEnable,*/
907 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel
, DeviceID
, (uint
)(DMATimingMode
- XFER_MW_DMA_0
));
910 if (DMATimingMode
>= XFER_UDMA_0
) {
912 ATAHostAdapter_SetSecondaryPIO(pdev
,
916 PrefetchPostingEnable
);
918 ATAHostAdapter_SetSecondaryUDMA(pdev
,
921 DMATimingMode
- XFER_UDMA_0
);
922 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel
, DeviceID
, (uint
)(DMATimingMode
- XFER_UDMA_0
));
925 ATAHostAdapter_SetSecondaryPIO(pdev
,
927 (DMATimingMode
- XFER_MW_DMA_0
) + PIO2
, /* MDMA0 = PIO2 */
929 PrefetchPostingEnable
);
931 ATAHostAdapter_SetSecondaryUDMA(pdev
,
933 FALSE
,/*UDMAEnable,*/
935 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel
, DeviceID
, (uint
)(DMATimingMode
- XFER_MW_DMA_0
));
940 /* pata host template */
941 static struct scsi_host_template rdc_pata_sht
= {
942 ATA_BMDMA_SHT(DRIVER_NAME
),
945 static struct ata_port_operations rdc_pata_ops
= {
946 .inherits
= &ata_bmdma_port_ops
,
948 .port_start
= rdc_pata_port_start
,
949 .port_stop
= rdc_pata_port_stop
,
950 .prereset
= rdc_pata_prereset
,
951 .cable_detect
= rdc_pata_cable_detect
,
952 .set_piomode
= rdc_pata_set_piomode
,
953 .set_dmamode
= rdc_pata_set_dmamode
,
956 static struct ata_port_info rdc_pata_port_info
[] = {
958 .flags
= ATA_FLAG_SLAVE_POSS
,
959 .pio_mask
= 0x1f, /* pio0-4 */
960 .mwdma_mask
= 0x07, /* mwdma0-2 */
961 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
962 .port_ops
= &rdc_pata_ops
,
966 .flags
= ATA_FLAG_SLAVE_POSS
,
967 .pio_mask
= 0x1f, /* pio0-4 */
968 .mwdma_mask
= 0x07, /* mwdma0-2 */
969 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
970 .port_ops
= &rdc_pata_ops
,
974 static int __devinit
rdc_init_one(struct pci_dev
*pdev
,
975 const struct pci_device_id
*ent
)
977 /*struct device *dev = &pdev->dev; */
978 struct ata_port_info port_info
[2];
979 const struct ata_port_info
*ppinfo
[] = { &port_info
[0], &port_info
[1] };
983 dbgprintf("rdc_init_one\n");
985 /* no hotplugging support (FIXME) */ /* why??? */
986 if (!in_module_init
) {
987 dbgprintf("rdc_init_one in_module_init == 0 failed \n");
990 port_info
[0] = rdc_pata_port_info
[ent
->driver_data
];
991 port_info
[1] = rdc_pata_port_info
[ent
->driver_data
];
993 /* enable device and prepare host */
994 rc
= pci_enable_device(pdev
);
996 dbgprintf("rdc_init_one pci_enable_device failed \n");
999 /* initialize controller */
1001 pci_intx(pdev
, 1); /* enable interrupt */
1003 return ata_pci_sff_init_one(pdev
, ppinfo
, &rdc_pata_sht
, NULL
);
1007 static struct pci_driver rdc_pata_driver
= {
1008 .name
= DRIVER_NAME
,
1009 .id_table
= rdc_pata_id_table
,
1010 .probe
= rdc_init_one
,
1011 .remove
= ata_pci_remove_one
,
1013 .suspend
= ata_pci_device_suspend
,
1014 .resume
= ata_pci_device_resume
,
1018 static int __init
pata_rdc_init(void)
1022 dbgprintf("pata_rdc_init\n");
1023 rc
= pci_register_driver(&rdc_pata_driver
);
1025 dbgprintf("pata_rdc_init faile\n");
1034 static void __exit
pata_rdc_exit(void)
1036 dbgprintf("pata_rdc_exit\n");
1037 pci_unregister_driver(&rdc_pata_driver
);
1040 module_init(pata_rdc_init
);
1041 module_exit(pata_rdc_exit
);
1043 MODULE_LICENSE("GPL");
1044 MODULE_DESCRIPTION("RDC PCI IDE Driver");
1045 MODULE_VERSION(DRIVER_VERSION
);