Fix iwlan DMA mapping direction
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ide / pmac.c
blob74625e821a43bc078f6c1efe88312bb438872141
1 /*
2 * Support for IDE interfaces on PowerMacs.
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * Some code taken from drivers/ide/ide-dma.c:
17 * Copyright (c) 1995-1998 Mark Lord
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
37 #include <asm/prom.h>
38 #include <asm/io.h>
39 #include <asm/dbdma.h>
40 #include <asm/ide.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
45 #include <asm/irq.h>
47 #ifndef CONFIG_PPC64
48 #include <asm/mediabay.h>
49 #endif
51 #define DRV_NAME "ide-pmac"
53 #undef IDE_PMAC_DEBUG
55 #define DMA_WAIT_TIMEOUT 50
57 typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned mediabay : 1;
63 unsigned broken_dma : 1;
64 unsigned broken_dma_warn : 1;
65 struct device_node* node;
66 struct macio_dev *mdev;
67 u32 timings[4];
68 volatile u32 __iomem * *kauai_fcr;
69 /* Those fields are duplicating what is in hwif. We currently
70 * can't use the hwif ones because of some assumptions that are
71 * beeing done by the generic code about the kind of dma controller
72 * and format of the dma table. This will have to be fixed though.
74 volatile struct dbdma_regs __iomem * dma_regs;
75 struct dbdma_cmd* dma_table_cpu;
76 } pmac_ide_hwif_t;
78 enum {
79 controller_ohare, /* OHare based */
80 controller_heathrow, /* Heathrow/Paddington */
81 controller_kl_ata3, /* KeyLargo ATA-3 */
82 controller_kl_ata4, /* KeyLargo ATA-4 */
83 controller_un_ata6, /* UniNorth2 ATA-6 */
84 controller_k2_ata6, /* K2 ATA-6 */
85 controller_sh_ata6, /* Shasta ATA-6 */
88 static const char* model_name[] = {
89 "OHare ATA", /* OHare based */
90 "Heathrow ATA", /* Heathrow/Paddington */
91 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
92 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
93 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
94 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
95 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
99 * Extra registers, both 32-bit little-endian
101 #define IDE_TIMING_CONFIG 0x200
102 #define IDE_INTERRUPT 0x300
104 /* Kauai (U2) ATA has different register setup */
105 #define IDE_KAUAI_PIO_CONFIG 0x200
106 #define IDE_KAUAI_ULTRA_CONFIG 0x210
107 #define IDE_KAUAI_POLL_CONFIG 0x220
110 * Timing configuration register definitions
113 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
114 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
115 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
116 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
117 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
119 /* 133Mhz cell, found in shasta.
120 * See comments about 100 Mhz Uninorth 2...
121 * Note that PIO_MASK and MDMA_MASK seem to overlap
123 #define TR_133_PIOREG_PIO_MASK 0xff000fff
124 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
125 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
126 #define TR_133_UDMAREG_UDMA_EN 0x00000001
128 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
129 * this one yet, it appears as a pci device (106b/0033) on uninorth
130 * internal PCI bus and it's clock is controlled like gem or fw. It
131 * appears to be an evolution of keylargo ATA4 with a timing register
132 * extended to 2 32bits registers and a similar DBDMA channel. Other
133 * registers seem to exist but I can't tell much about them.
135 * So far, I'm using pre-calculated tables for this extracted from
136 * the values used by the MacOS X driver.
138 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
139 * register controls the UDMA timings. At least, it seems bit 0
140 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
141 * cycle time in units of 10ns. Bits 8..15 are used by I don't
142 * know their meaning yet
144 #define TR_100_PIOREG_PIO_MASK 0xff000fff
145 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
146 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
147 #define TR_100_UDMAREG_UDMA_EN 0x00000001
150 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
151 * 40 connector cable and to 4 on 80 connector one.
152 * Clock unit is 15ns (66Mhz)
154 * 3 Values can be programmed:
155 * - Write data setup, which appears to match the cycle time. They
156 * also call it DIOW setup.
157 * - Ready to pause time (from spec)
158 * - Address setup. That one is weird. I don't see where exactly
159 * it fits in UDMA cycles, I got it's name from an obscure piece
160 * of commented out code in Darwin. They leave it to 0, we do as
161 * well, despite a comment that would lead to think it has a
162 * min value of 45ns.
163 * Apple also add 60ns to the write data setup (or cycle time ?) on
164 * reads.
166 #define TR_66_UDMA_MASK 0xfff00000
167 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
168 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
169 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
170 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
171 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
172 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
173 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
174 #define TR_66_MDMA_MASK 0x000ffc00
175 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
176 #define TR_66_MDMA_RECOVERY_SHIFT 15
177 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
178 #define TR_66_MDMA_ACCESS_SHIFT 10
179 #define TR_66_PIO_MASK 0x000003ff
180 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
181 #define TR_66_PIO_RECOVERY_SHIFT 5
182 #define TR_66_PIO_ACCESS_MASK 0x0000001f
183 #define TR_66_PIO_ACCESS_SHIFT 0
185 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
186 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
188 * The access time and recovery time can be programmed. Some older
189 * Darwin code base limit OHare to 150ns cycle time. I decided to do
190 * the same here fore safety against broken old hardware ;)
191 * The HalfTick bit, when set, adds half a clock (15ns) to the access
192 * time and removes one from recovery. It's not supported on KeyLargo
193 * implementation afaik. The E bit appears to be set for PIO mode 0 and
194 * is used to reach long timings used in this mode.
196 #define TR_33_MDMA_MASK 0x003ff800
197 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
198 #define TR_33_MDMA_RECOVERY_SHIFT 16
199 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
200 #define TR_33_MDMA_ACCESS_SHIFT 11
201 #define TR_33_MDMA_HALFTICK 0x00200000
202 #define TR_33_PIO_MASK 0x000007ff
203 #define TR_33_PIO_E 0x00000400
204 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
205 #define TR_33_PIO_RECOVERY_SHIFT 5
206 #define TR_33_PIO_ACCESS_MASK 0x0000001f
207 #define TR_33_PIO_ACCESS_SHIFT 0
210 * Interrupt register definitions
212 #define IDE_INTR_DMA 0x80000000
213 #define IDE_INTR_DEVICE 0x40000000
216 * FCR Register on Kauai. Not sure what bit 0x4 is ...
218 #define KAUAI_FCR_UATA_MAGIC 0x00000004
219 #define KAUAI_FCR_UATA_RESET_N 0x00000002
220 #define KAUAI_FCR_UATA_ENABLE 0x00000001
222 /* Rounded Multiword DMA timings
224 * I gave up finding a generic formula for all controller
225 * types and instead, built tables based on timing values
226 * used by Apple in Darwin's implementation.
228 struct mdma_timings_t {
229 int accessTime;
230 int recoveryTime;
231 int cycleTime;
234 struct mdma_timings_t mdma_timings_33[] =
236 { 240, 240, 480 },
237 { 180, 180, 360 },
238 { 135, 135, 270 },
239 { 120, 120, 240 },
240 { 105, 105, 210 },
241 { 90, 90, 180 },
242 { 75, 75, 150 },
243 { 75, 45, 120 },
244 { 0, 0, 0 }
247 struct mdma_timings_t mdma_timings_33k[] =
249 { 240, 240, 480 },
250 { 180, 180, 360 },
251 { 150, 150, 300 },
252 { 120, 120, 240 },
253 { 90, 120, 210 },
254 { 90, 90, 180 },
255 { 90, 60, 150 },
256 { 90, 30, 120 },
257 { 0, 0, 0 }
260 struct mdma_timings_t mdma_timings_66[] =
262 { 240, 240, 480 },
263 { 180, 180, 360 },
264 { 135, 135, 270 },
265 { 120, 120, 240 },
266 { 105, 105, 210 },
267 { 90, 90, 180 },
268 { 90, 75, 165 },
269 { 75, 45, 120 },
270 { 0, 0, 0 }
273 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
274 struct {
275 int addrSetup; /* ??? */
276 int rdy2pause;
277 int wrDataSetup;
278 } kl66_udma_timings[] =
280 { 0, 180, 120 }, /* Mode 0 */
281 { 0, 150, 90 }, /* 1 */
282 { 0, 120, 60 }, /* 2 */
283 { 0, 90, 45 }, /* 3 */
284 { 0, 90, 30 } /* 4 */
287 /* UniNorth 2 ATA/100 timings */
288 struct kauai_timing {
289 int cycle_time;
290 u32 timing_reg;
293 static struct kauai_timing kauai_pio_timings[] =
295 { 930 , 0x08000fff },
296 { 600 , 0x08000a92 },
297 { 383 , 0x0800060f },
298 { 360 , 0x08000492 },
299 { 330 , 0x0800048f },
300 { 300 , 0x080003cf },
301 { 270 , 0x080003cc },
302 { 240 , 0x0800038b },
303 { 239 , 0x0800030c },
304 { 180 , 0x05000249 },
305 { 120 , 0x04000148 },
306 { 0 , 0 },
309 static struct kauai_timing kauai_mdma_timings[] =
311 { 1260 , 0x00fff000 },
312 { 480 , 0x00618000 },
313 { 360 , 0x00492000 },
314 { 270 , 0x0038e000 },
315 { 240 , 0x0030c000 },
316 { 210 , 0x002cb000 },
317 { 180 , 0x00249000 },
318 { 150 , 0x00209000 },
319 { 120 , 0x00148000 },
320 { 0 , 0 },
323 static struct kauai_timing kauai_udma_timings[] =
325 { 120 , 0x000070c0 },
326 { 90 , 0x00005d80 },
327 { 60 , 0x00004a60 },
328 { 45 , 0x00003a50 },
329 { 30 , 0x00002a30 },
330 { 20 , 0x00002921 },
331 { 0 , 0 },
334 static struct kauai_timing shasta_pio_timings[] =
336 { 930 , 0x08000fff },
337 { 600 , 0x0A000c97 },
338 { 383 , 0x07000712 },
339 { 360 , 0x040003cd },
340 { 330 , 0x040003cd },
341 { 300 , 0x040003cd },
342 { 270 , 0x040003cd },
343 { 240 , 0x040003cd },
344 { 239 , 0x040003cd },
345 { 180 , 0x0400028b },
346 { 120 , 0x0400010a },
347 { 0 , 0 },
350 static struct kauai_timing shasta_mdma_timings[] =
352 { 1260 , 0x00fff000 },
353 { 480 , 0x00820800 },
354 { 360 , 0x00820800 },
355 { 270 , 0x00820800 },
356 { 240 , 0x00820800 },
357 { 210 , 0x00820800 },
358 { 180 , 0x00820800 },
359 { 150 , 0x0028b000 },
360 { 120 , 0x001ca000 },
361 { 0 , 0 },
364 static struct kauai_timing shasta_udma133_timings[] =
366 { 120 , 0x00035901, },
367 { 90 , 0x000348b1, },
368 { 60 , 0x00033881, },
369 { 45 , 0x00033861, },
370 { 30 , 0x00033841, },
371 { 20 , 0x00033031, },
372 { 15 , 0x00033021, },
373 { 0 , 0 },
377 static inline u32
378 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
380 int i;
382 for (i=0; table[i].cycle_time; i++)
383 if (cycle_time > table[i+1].cycle_time)
384 return table[i].timing_reg;
385 BUG();
386 return 0;
389 /* allow up to 256 DBDMA commands per xfer */
390 #define MAX_DCMDS 256
393 * Wait 1s for disk to answer on IDE bus after a hard reset
394 * of the device (via GPIO/FCR).
396 * Some devices seem to "pollute" the bus even after dropping
397 * the BSY bit (typically some combo drives slave on the UDMA
398 * bus) after a hard reset. Since we hard reset all drives on
399 * KeyLargo ATA66, we have to keep that delay around. I may end
400 * up not hard resetting anymore on these and keep the delay only
401 * for older interfaces instead (we have to reset when coming
402 * from MacOS...) --BenH.
404 #define IDE_WAKEUP_DELAY (1*HZ)
406 static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
407 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
408 static void pmac_ide_selectproc(ide_drive_t *drive);
409 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
411 #define PMAC_IDE_REG(x) \
412 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
415 * Apply the timings of the proper unit (master/slave) to the shared
416 * timing register when selecting that unit. This version is for
417 * ASICs with a single timing register
419 static void
420 pmac_ide_selectproc(ide_drive_t *drive)
422 ide_hwif_t *hwif = drive->hwif;
423 pmac_ide_hwif_t *pmif =
424 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
426 if (drive->dn & 1)
427 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
428 else
429 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
430 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
434 * Apply the timings of the proper unit (master/slave) to the shared
435 * timing register when selecting that unit. This version is for
436 * ASICs with a dual timing register (Kauai)
438 static void
439 pmac_ide_kauai_selectproc(ide_drive_t *drive)
441 ide_hwif_t *hwif = drive->hwif;
442 pmac_ide_hwif_t *pmif =
443 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
445 if (drive->dn & 1) {
446 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
447 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
448 } else {
449 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
450 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
452 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
456 * Force an update of controller timing values for a given drive
458 static void
459 pmac_ide_do_update_timings(ide_drive_t *drive)
461 ide_hwif_t *hwif = drive->hwif;
462 pmac_ide_hwif_t *pmif =
463 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
465 if (pmif->kind == controller_sh_ata6 ||
466 pmif->kind == controller_un_ata6 ||
467 pmif->kind == controller_k2_ata6)
468 pmac_ide_kauai_selectproc(drive);
469 else
470 pmac_ide_selectproc(drive);
473 static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
475 writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
476 (void)readl((void __iomem *)(hwif->io_ports.data_addr
477 + IDE_TIMING_CONFIG));
480 static void pmac_set_irq(ide_hwif_t *hwif, int on)
482 u8 ctl = ATA_DEVCTL_OBS;
484 if (on == 4) { /* hack for SRST */
485 ctl |= 4;
486 on &= ~4;
489 ctl |= on ? 0 : 2;
491 writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
492 (void)readl((void __iomem *)(hwif->io_ports.data_addr
493 + IDE_TIMING_CONFIG));
497 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
499 static void
500 pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
502 ide_hwif_t *hwif = drive->hwif;
503 pmac_ide_hwif_t *pmif =
504 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
505 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
506 u32 *timings, t;
507 unsigned accessTicks, recTicks;
508 unsigned accessTime, recTime;
509 unsigned int cycle_time;
511 /* which drive is it ? */
512 timings = &pmif->timings[drive->dn & 1];
513 t = *timings;
515 cycle_time = ide_pio_cycle_time(drive, pio);
517 switch (pmif->kind) {
518 case controller_sh_ata6: {
519 /* 133Mhz cell */
520 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
521 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
522 break;
524 case controller_un_ata6:
525 case controller_k2_ata6: {
526 /* 100Mhz cell */
527 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
528 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
529 break;
531 case controller_kl_ata4:
532 /* 66Mhz cell */
533 recTime = cycle_time - tim->active - tim->setup;
534 recTime = max(recTime, 150U);
535 accessTime = tim->active;
536 accessTime = max(accessTime, 150U);
537 accessTicks = SYSCLK_TICKS_66(accessTime);
538 accessTicks = min(accessTicks, 0x1fU);
539 recTicks = SYSCLK_TICKS_66(recTime);
540 recTicks = min(recTicks, 0x1fU);
541 t = (t & ~TR_66_PIO_MASK) |
542 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
543 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
544 break;
545 default: {
546 /* 33Mhz cell */
547 int ebit = 0;
548 recTime = cycle_time - tim->active - tim->setup;
549 recTime = max(recTime, 150U);
550 accessTime = tim->active;
551 accessTime = max(accessTime, 150U);
552 accessTicks = SYSCLK_TICKS(accessTime);
553 accessTicks = min(accessTicks, 0x1fU);
554 accessTicks = max(accessTicks, 4U);
555 recTicks = SYSCLK_TICKS(recTime);
556 recTicks = min(recTicks, 0x1fU);
557 recTicks = max(recTicks, 5U) - 4;
558 if (recTicks > 9) {
559 recTicks--; /* guess, but it's only for PIO0, so... */
560 ebit = 1;
562 t = (t & ~TR_33_PIO_MASK) |
563 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
564 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
565 if (ebit)
566 t |= TR_33_PIO_E;
567 break;
571 #ifdef IDE_PMAC_DEBUG
572 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
573 drive->name, pio, *timings);
574 #endif
576 *timings = t;
577 pmac_ide_do_update_timings(drive);
581 * Calculate KeyLargo ATA/66 UDMA timings
583 static int
584 set_timings_udma_ata4(u32 *timings, u8 speed)
586 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
588 if (speed > XFER_UDMA_4)
589 return 1;
591 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
592 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
593 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
595 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
596 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
597 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
598 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
599 TR_66_UDMA_EN;
600 #ifdef IDE_PMAC_DEBUG
601 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
602 speed & 0xf, *timings);
603 #endif
605 return 0;
609 * Calculate Kauai ATA/100 UDMA timings
611 static int
612 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
614 struct ide_timing *t = ide_timing_find_mode(speed);
615 u32 tr;
617 if (speed > XFER_UDMA_5 || t == NULL)
618 return 1;
619 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
620 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
621 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
623 return 0;
627 * Calculate Shasta ATA/133 UDMA timings
629 static int
630 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
632 struct ide_timing *t = ide_timing_find_mode(speed);
633 u32 tr;
635 if (speed > XFER_UDMA_6 || t == NULL)
636 return 1;
637 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
638 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
639 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
641 return 0;
645 * Calculate MDMA timings for all cells
647 static void
648 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
649 u8 speed)
651 u16 *id = drive->id;
652 int cycleTime, accessTime = 0, recTime = 0;
653 unsigned accessTicks, recTicks;
654 struct mdma_timings_t* tm = NULL;
655 int i;
657 /* Get default cycle time for mode */
658 switch(speed & 0xf) {
659 case 0: cycleTime = 480; break;
660 case 1: cycleTime = 150; break;
661 case 2: cycleTime = 120; break;
662 default:
663 BUG();
664 break;
667 /* Check if drive provides explicit DMA cycle time */
668 if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
669 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
671 /* OHare limits according to some old Apple sources */
672 if ((intf_type == controller_ohare) && (cycleTime < 150))
673 cycleTime = 150;
674 /* Get the proper timing array for this controller */
675 switch(intf_type) {
676 case controller_sh_ata6:
677 case controller_un_ata6:
678 case controller_k2_ata6:
679 break;
680 case controller_kl_ata4:
681 tm = mdma_timings_66;
682 break;
683 case controller_kl_ata3:
684 tm = mdma_timings_33k;
685 break;
686 default:
687 tm = mdma_timings_33;
688 break;
690 if (tm != NULL) {
691 /* Lookup matching access & recovery times */
692 i = -1;
693 for (;;) {
694 if (tm[i+1].cycleTime < cycleTime)
695 break;
696 i++;
698 cycleTime = tm[i].cycleTime;
699 accessTime = tm[i].accessTime;
700 recTime = tm[i].recoveryTime;
702 #ifdef IDE_PMAC_DEBUG
703 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
704 drive->name, cycleTime, accessTime, recTime);
705 #endif
707 switch(intf_type) {
708 case controller_sh_ata6: {
709 /* 133Mhz cell */
710 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
711 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
712 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
714 case controller_un_ata6:
715 case controller_k2_ata6: {
716 /* 100Mhz cell */
717 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
718 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
719 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
721 break;
722 case controller_kl_ata4:
723 /* 66Mhz cell */
724 accessTicks = SYSCLK_TICKS_66(accessTime);
725 accessTicks = min(accessTicks, 0x1fU);
726 accessTicks = max(accessTicks, 0x1U);
727 recTicks = SYSCLK_TICKS_66(recTime);
728 recTicks = min(recTicks, 0x1fU);
729 recTicks = max(recTicks, 0x3U);
730 /* Clear out mdma bits and disable udma */
731 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
732 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
733 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
734 break;
735 case controller_kl_ata3:
736 /* 33Mhz cell on KeyLargo */
737 accessTicks = SYSCLK_TICKS(accessTime);
738 accessTicks = max(accessTicks, 1U);
739 accessTicks = min(accessTicks, 0x1fU);
740 accessTime = accessTicks * IDE_SYSCLK_NS;
741 recTicks = SYSCLK_TICKS(recTime);
742 recTicks = max(recTicks, 1U);
743 recTicks = min(recTicks, 0x1fU);
744 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
745 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
746 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
747 break;
748 default: {
749 /* 33Mhz cell on others */
750 int halfTick = 0;
751 int origAccessTime = accessTime;
752 int origRecTime = recTime;
754 accessTicks = SYSCLK_TICKS(accessTime);
755 accessTicks = max(accessTicks, 1U);
756 accessTicks = min(accessTicks, 0x1fU);
757 accessTime = accessTicks * IDE_SYSCLK_NS;
758 recTicks = SYSCLK_TICKS(recTime);
759 recTicks = max(recTicks, 2U) - 1;
760 recTicks = min(recTicks, 0x1fU);
761 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
762 if ((accessTicks > 1) &&
763 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
764 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
765 halfTick = 1;
766 accessTicks--;
768 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
769 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
770 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
771 if (halfTick)
772 *timings |= TR_33_MDMA_HALFTICK;
775 #ifdef IDE_PMAC_DEBUG
776 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
777 drive->name, speed & 0xf, *timings);
778 #endif
781 static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
783 ide_hwif_t *hwif = drive->hwif;
784 pmac_ide_hwif_t *pmif =
785 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
786 int ret = 0;
787 u32 *timings, *timings2, tl[2];
788 u8 unit = drive->dn & 1;
790 timings = &pmif->timings[unit];
791 timings2 = &pmif->timings[unit+2];
793 /* Copy timings to local image */
794 tl[0] = *timings;
795 tl[1] = *timings2;
797 if (speed >= XFER_UDMA_0) {
798 if (pmif->kind == controller_kl_ata4)
799 ret = set_timings_udma_ata4(&tl[0], speed);
800 else if (pmif->kind == controller_un_ata6
801 || pmif->kind == controller_k2_ata6)
802 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
803 else if (pmif->kind == controller_sh_ata6)
804 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
805 else
806 ret = -1;
807 } else
808 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
810 if (ret)
811 return;
813 /* Apply timings to controller */
814 *timings = tl[0];
815 *timings2 = tl[1];
817 pmac_ide_do_update_timings(drive);
821 * Blast some well known "safe" values to the timing registers at init or
822 * wakeup from sleep time, before we do real calculation
824 static void
825 sanitize_timings(pmac_ide_hwif_t *pmif)
827 unsigned int value, value2 = 0;
829 switch(pmif->kind) {
830 case controller_sh_ata6:
831 value = 0x0a820c97;
832 value2 = 0x00033031;
833 break;
834 case controller_un_ata6:
835 case controller_k2_ata6:
836 value = 0x08618a92;
837 value2 = 0x00002921;
838 break;
839 case controller_kl_ata4:
840 value = 0x0008438c;
841 break;
842 case controller_kl_ata3:
843 value = 0x00084526;
844 break;
845 case controller_heathrow:
846 case controller_ohare:
847 default:
848 value = 0x00074526;
849 break;
851 pmif->timings[0] = pmif->timings[1] = value;
852 pmif->timings[2] = pmif->timings[3] = value2;
855 /* Suspend call back, should be called after the child devices
856 * have actually been suspended
858 static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
860 /* We clear the timings */
861 pmif->timings[0] = 0;
862 pmif->timings[1] = 0;
864 disable_irq(pmif->irq);
866 /* The media bay will handle itself just fine */
867 if (pmif->mediabay)
868 return 0;
870 /* Kauai has bus control FCRs directly here */
871 if (pmif->kauai_fcr) {
872 u32 fcr = readl(pmif->kauai_fcr);
873 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
874 writel(fcr, pmif->kauai_fcr);
877 /* Disable the bus on older machines and the cell on kauai */
878 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
881 return 0;
884 /* Resume call back, should be called before the child devices
885 * are resumed
887 static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
889 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
890 if (!pmif->mediabay) {
891 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
892 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
893 msleep(10);
894 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
896 /* Kauai has it different */
897 if (pmif->kauai_fcr) {
898 u32 fcr = readl(pmif->kauai_fcr);
899 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
900 writel(fcr, pmif->kauai_fcr);
903 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
906 /* Sanitize drive timings */
907 sanitize_timings(pmif);
909 enable_irq(pmif->irq);
911 return 0;
914 static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
916 pmac_ide_hwif_t *pmif =
917 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
918 struct device_node *np = pmif->node;
919 const char *cable = of_get_property(np, "cable-type", NULL);
921 /* Get cable type from device-tree. */
922 if (cable && !strncmp(cable, "80-", 3))
923 return ATA_CBL_PATA80;
926 * G5's seem to have incorrect cable type in device-tree.
927 * Let's assume they have a 80 conductor cable, this seem
928 * to be always the case unless the user mucked around.
930 if (of_device_is_compatible(np, "K2-UATA") ||
931 of_device_is_compatible(np, "shasta-ata"))
932 return ATA_CBL_PATA80;
934 return ATA_CBL_PATA40;
937 static void pmac_ide_init_dev(ide_drive_t *drive)
939 ide_hwif_t *hwif = drive->hwif;
940 pmac_ide_hwif_t *pmif =
941 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
943 if (pmif->mediabay) {
944 #ifdef CONFIG_PMAC_MEDIABAY
945 if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
946 drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
947 return;
949 #endif
950 drive->dev_flags |= IDE_DFLAG_NOPROBE;
954 static const struct ide_tp_ops pmac_tp_ops = {
955 .exec_command = pmac_exec_command,
956 .read_status = ide_read_status,
957 .read_altstatus = ide_read_altstatus,
959 .set_irq = pmac_set_irq,
961 .tf_load = ide_tf_load,
962 .tf_read = ide_tf_read,
964 .input_data = ide_input_data,
965 .output_data = ide_output_data,
968 static const struct ide_port_ops pmac_ide_ata6_port_ops = {
969 .init_dev = pmac_ide_init_dev,
970 .set_pio_mode = pmac_ide_set_pio_mode,
971 .set_dma_mode = pmac_ide_set_dma_mode,
972 .selectproc = pmac_ide_kauai_selectproc,
973 .cable_detect = pmac_ide_cable_detect,
976 static const struct ide_port_ops pmac_ide_ata4_port_ops = {
977 .init_dev = pmac_ide_init_dev,
978 .set_pio_mode = pmac_ide_set_pio_mode,
979 .set_dma_mode = pmac_ide_set_dma_mode,
980 .selectproc = pmac_ide_selectproc,
981 .cable_detect = pmac_ide_cable_detect,
984 static const struct ide_port_ops pmac_ide_port_ops = {
985 .init_dev = pmac_ide_init_dev,
986 .set_pio_mode = pmac_ide_set_pio_mode,
987 .set_dma_mode = pmac_ide_set_dma_mode,
988 .selectproc = pmac_ide_selectproc,
991 static const struct ide_dma_ops pmac_dma_ops;
993 static const struct ide_port_info pmac_port_info = {
994 .name = DRV_NAME,
995 .init_dma = pmac_ide_init_dma,
996 .chipset = ide_pmac,
997 .tp_ops = &pmac_tp_ops,
998 .port_ops = &pmac_ide_port_ops,
999 .dma_ops = &pmac_dma_ops,
1000 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1001 IDE_HFLAG_POST_SET_MODE |
1002 IDE_HFLAG_MMIO |
1003 IDE_HFLAG_UNMASK_IRQS,
1004 .pio_mask = ATA_PIO4,
1005 .mwdma_mask = ATA_MWDMA2,
1009 * Setup, register & probe an IDE channel driven by this driver, this is
1010 * called by one of the 2 probe functions (macio or PCI).
1012 static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, hw_regs_t *hw)
1014 struct device_node *np = pmif->node;
1015 const int *bidp;
1016 struct ide_host *host;
1017 ide_hwif_t *hwif;
1018 hw_regs_t *hws[] = { hw, NULL, NULL, NULL };
1019 struct ide_port_info d = pmac_port_info;
1020 int rc;
1022 pmif->broken_dma = pmif->broken_dma_warn = 0;
1023 if (of_device_is_compatible(np, "shasta-ata")) {
1024 pmif->kind = controller_sh_ata6;
1025 d.port_ops = &pmac_ide_ata6_port_ops;
1026 d.udma_mask = ATA_UDMA6;
1027 } else if (of_device_is_compatible(np, "kauai-ata")) {
1028 pmif->kind = controller_un_ata6;
1029 d.port_ops = &pmac_ide_ata6_port_ops;
1030 d.udma_mask = ATA_UDMA5;
1031 } else if (of_device_is_compatible(np, "K2-UATA")) {
1032 pmif->kind = controller_k2_ata6;
1033 d.port_ops = &pmac_ide_ata6_port_ops;
1034 d.udma_mask = ATA_UDMA5;
1035 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1036 if (strcmp(np->name, "ata-4") == 0) {
1037 pmif->kind = controller_kl_ata4;
1038 d.port_ops = &pmac_ide_ata4_port_ops;
1039 d.udma_mask = ATA_UDMA4;
1040 } else
1041 pmif->kind = controller_kl_ata3;
1042 } else if (of_device_is_compatible(np, "heathrow-ata")) {
1043 pmif->kind = controller_heathrow;
1044 } else {
1045 pmif->kind = controller_ohare;
1046 pmif->broken_dma = 1;
1049 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1050 pmif->aapl_bus_id = bidp ? *bidp : 0;
1052 /* On Kauai-type controllers, we make sure the FCR is correct */
1053 if (pmif->kauai_fcr)
1054 writel(KAUAI_FCR_UATA_MAGIC |
1055 KAUAI_FCR_UATA_RESET_N |
1056 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1058 pmif->mediabay = 0;
1060 /* Make sure we have sane timings */
1061 sanitize_timings(pmif);
1063 host = ide_host_alloc(&d, hws);
1064 if (host == NULL)
1065 return -ENOMEM;
1066 hwif = host->ports[0];
1068 #ifndef CONFIG_PPC64
1069 /* XXX FIXME: Media bay stuff need re-organizing */
1070 if (np->parent && np->parent->name
1071 && strcasecmp(np->parent->name, "media-bay") == 0) {
1072 #ifdef CONFIG_PMAC_MEDIABAY
1073 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1074 hwif);
1075 #endif /* CONFIG_PMAC_MEDIABAY */
1076 pmif->mediabay = 1;
1077 if (!bidp)
1078 pmif->aapl_bus_id = 1;
1079 } else if (pmif->kind == controller_ohare) {
1080 /* The code below is having trouble on some ohare machines
1081 * (timing related ?). Until I can put my hand on one of these
1082 * units, I keep the old way
1084 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1085 } else
1086 #endif
1088 /* This is necessary to enable IDE when net-booting */
1089 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1090 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1091 msleep(10);
1092 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1093 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1096 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1097 "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1098 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1099 pmif->mediabay ? " (mediabay)" : "", hw->irq);
1101 rc = ide_host_register(host, &d, hws);
1102 if (rc) {
1103 ide_host_free(host);
1104 return rc;
1107 return 0;
1110 static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1112 int i;
1114 for (i = 0; i < 8; ++i)
1115 hw->io_ports_array[i] = base + i * 0x10;
1117 hw->io_ports.ctl_addr = base + 0x160;
1121 * Attach to a macio probed interface
1123 static int __devinit
1124 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1126 void __iomem *base;
1127 unsigned long regbase;
1128 pmac_ide_hwif_t *pmif;
1129 int irq, rc;
1130 hw_regs_t hw;
1132 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1133 if (pmif == NULL)
1134 return -ENOMEM;
1136 if (macio_resource_count(mdev) == 0) {
1137 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1138 mdev->ofdev.node->full_name);
1139 rc = -ENXIO;
1140 goto out_free_pmif;
1143 /* Request memory resource for IO ports */
1144 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1145 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1146 "%s!\n", mdev->ofdev.node->full_name);
1147 rc = -EBUSY;
1148 goto out_free_pmif;
1151 /* XXX This is bogus. Should be fixed in the registry by checking
1152 * the kind of host interrupt controller, a bit like gatwick
1153 * fixes in irq.c. That works well enough for the single case
1154 * where that happens though...
1156 if (macio_irq_count(mdev) == 0) {
1157 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1158 "13\n", mdev->ofdev.node->full_name);
1159 irq = irq_create_mapping(NULL, 13);
1160 } else
1161 irq = macio_irq(mdev, 0);
1163 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1164 regbase = (unsigned long) base;
1166 pmif->mdev = mdev;
1167 pmif->node = mdev->ofdev.node;
1168 pmif->regbase = regbase;
1169 pmif->irq = irq;
1170 pmif->kauai_fcr = NULL;
1172 if (macio_resource_count(mdev) >= 2) {
1173 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1174 printk(KERN_WARNING "ide-pmac: can't request DMA "
1175 "resource for %s!\n",
1176 mdev->ofdev.node->full_name);
1177 else
1178 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1179 } else
1180 pmif->dma_regs = NULL;
1182 dev_set_drvdata(&mdev->ofdev.dev, pmif);
1184 memset(&hw, 0, sizeof(hw));
1185 pmac_ide_init_ports(&hw, pmif->regbase);
1186 hw.irq = irq;
1187 hw.dev = &mdev->bus->pdev->dev;
1188 hw.parent = &mdev->ofdev.dev;
1190 rc = pmac_ide_setup_device(pmif, &hw);
1191 if (rc != 0) {
1192 /* The inteface is released to the common IDE layer */
1193 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1194 iounmap(base);
1195 if (pmif->dma_regs) {
1196 iounmap(pmif->dma_regs);
1197 macio_release_resource(mdev, 1);
1199 macio_release_resource(mdev, 0);
1200 kfree(pmif);
1203 return rc;
1205 out_free_pmif:
1206 kfree(pmif);
1207 return rc;
1210 static int
1211 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1213 pmac_ide_hwif_t *pmif =
1214 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1215 int rc = 0;
1217 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1218 && (mesg.event & PM_EVENT_SLEEP)) {
1219 rc = pmac_ide_do_suspend(pmif);
1220 if (rc == 0)
1221 mdev->ofdev.dev.power.power_state = mesg;
1224 return rc;
1227 static int
1228 pmac_ide_macio_resume(struct macio_dev *mdev)
1230 pmac_ide_hwif_t *pmif =
1231 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1232 int rc = 0;
1234 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1235 rc = pmac_ide_do_resume(pmif);
1236 if (rc == 0)
1237 mdev->ofdev.dev.power.power_state = PMSG_ON;
1240 return rc;
1244 * Attach to a PCI probed interface
1246 static int __devinit
1247 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1249 struct device_node *np;
1250 pmac_ide_hwif_t *pmif;
1251 void __iomem *base;
1252 unsigned long rbase, rlen;
1253 int rc;
1254 hw_regs_t hw;
1256 np = pci_device_to_OF_node(pdev);
1257 if (np == NULL) {
1258 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1259 return -ENODEV;
1262 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1263 if (pmif == NULL)
1264 return -ENOMEM;
1266 if (pci_enable_device(pdev)) {
1267 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1268 "%s\n", np->full_name);
1269 rc = -ENXIO;
1270 goto out_free_pmif;
1272 pci_set_master(pdev);
1274 if (pci_request_regions(pdev, "Kauai ATA")) {
1275 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1276 "%s\n", np->full_name);
1277 rc = -ENXIO;
1278 goto out_free_pmif;
1281 pmif->mdev = NULL;
1282 pmif->node = np;
1284 rbase = pci_resource_start(pdev, 0);
1285 rlen = pci_resource_len(pdev, 0);
1287 base = ioremap(rbase, rlen);
1288 pmif->regbase = (unsigned long) base + 0x2000;
1289 pmif->dma_regs = base + 0x1000;
1290 pmif->kauai_fcr = base;
1291 pmif->irq = pdev->irq;
1293 pci_set_drvdata(pdev, pmif);
1295 memset(&hw, 0, sizeof(hw));
1296 pmac_ide_init_ports(&hw, pmif->regbase);
1297 hw.irq = pdev->irq;
1298 hw.dev = &pdev->dev;
1300 rc = pmac_ide_setup_device(pmif, &hw);
1301 if (rc != 0) {
1302 /* The inteface is released to the common IDE layer */
1303 pci_set_drvdata(pdev, NULL);
1304 iounmap(base);
1305 pci_release_regions(pdev);
1306 kfree(pmif);
1309 return rc;
1311 out_free_pmif:
1312 kfree(pmif);
1313 return rc;
1316 static int
1317 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1319 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1320 int rc = 0;
1322 if (mesg.event != pdev->dev.power.power_state.event
1323 && (mesg.event & PM_EVENT_SLEEP)) {
1324 rc = pmac_ide_do_suspend(pmif);
1325 if (rc == 0)
1326 pdev->dev.power.power_state = mesg;
1329 return rc;
1332 static int
1333 pmac_ide_pci_resume(struct pci_dev *pdev)
1335 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1336 int rc = 0;
1338 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1339 rc = pmac_ide_do_resume(pmif);
1340 if (rc == 0)
1341 pdev->dev.power.power_state = PMSG_ON;
1344 return rc;
1347 static struct of_device_id pmac_ide_macio_match[] =
1350 .name = "IDE",
1353 .name = "ATA",
1356 .type = "ide",
1359 .type = "ata",
1364 static struct macio_driver pmac_ide_macio_driver =
1366 .name = "ide-pmac",
1367 .match_table = pmac_ide_macio_match,
1368 .probe = pmac_ide_macio_attach,
1369 .suspend = pmac_ide_macio_suspend,
1370 .resume = pmac_ide_macio_resume,
1373 static const struct pci_device_id pmac_ide_pci_match[] = {
1374 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1375 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1376 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1377 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1378 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1382 static struct pci_driver pmac_ide_pci_driver = {
1383 .name = "ide-pmac",
1384 .id_table = pmac_ide_pci_match,
1385 .probe = pmac_ide_pci_attach,
1386 .suspend = pmac_ide_pci_suspend,
1387 .resume = pmac_ide_pci_resume,
1389 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1391 int __init pmac_ide_probe(void)
1393 int error;
1395 if (!machine_is(powermac))
1396 return -ENODEV;
1398 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1399 error = pci_register_driver(&pmac_ide_pci_driver);
1400 if (error)
1401 goto out;
1402 error = macio_register_driver(&pmac_ide_macio_driver);
1403 if (error) {
1404 pci_unregister_driver(&pmac_ide_pci_driver);
1405 goto out;
1407 #else
1408 error = macio_register_driver(&pmac_ide_macio_driver);
1409 if (error)
1410 goto out;
1411 error = pci_register_driver(&pmac_ide_pci_driver);
1412 if (error) {
1413 macio_unregister_driver(&pmac_ide_macio_driver);
1414 goto out;
1416 #endif
1417 out:
1418 return error;
1422 * pmac_ide_build_dmatable builds the DBDMA command list
1423 * for a transfer and sets the DBDMA channel to point to it.
1425 static int
1426 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1428 ide_hwif_t *hwif = drive->hwif;
1429 pmac_ide_hwif_t *pmif =
1430 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1431 struct dbdma_cmd *table;
1432 int i, count = 0;
1433 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1434 struct scatterlist *sg;
1435 int wr = (rq_data_dir(rq) == WRITE);
1437 /* DMA table is already aligned */
1438 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1440 /* Make sure DMA controller is stopped (necessary ?) */
1441 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1442 while (readl(&dma->status) & RUN)
1443 udelay(1);
1445 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1447 if (!i)
1448 return 0;
1450 /* Build DBDMA commands list */
1451 sg = hwif->sg_table;
1452 while (i && sg_dma_len(sg)) {
1453 u32 cur_addr;
1454 u32 cur_len;
1456 cur_addr = sg_dma_address(sg);
1457 cur_len = sg_dma_len(sg);
1459 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1460 if (pmif->broken_dma_warn == 0) {
1461 printk(KERN_WARNING "%s: DMA on non aligned address, "
1462 "switching to PIO on Ohare chipset\n", drive->name);
1463 pmif->broken_dma_warn = 1;
1465 goto use_pio_instead;
1467 while (cur_len) {
1468 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1470 if (count++ >= MAX_DCMDS) {
1471 printk(KERN_WARNING "%s: DMA table too small\n",
1472 drive->name);
1473 goto use_pio_instead;
1475 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1476 st_le16(&table->req_count, tc);
1477 st_le32(&table->phy_addr, cur_addr);
1478 table->cmd_dep = 0;
1479 table->xfer_status = 0;
1480 table->res_count = 0;
1481 cur_addr += tc;
1482 cur_len -= tc;
1483 ++table;
1485 sg = sg_next(sg);
1486 i--;
1489 /* convert the last command to an input/output last command */
1490 if (count) {
1491 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1492 /* add the stop command to the end of the list */
1493 memset(table, 0, sizeof(struct dbdma_cmd));
1494 st_le16(&table->command, DBDMA_STOP);
1495 mb();
1496 writel(hwif->dmatable_dma, &dma->cmdptr);
1497 return 1;
1500 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1502 use_pio_instead:
1503 ide_destroy_dmatable(drive);
1505 return 0; /* revert to PIO for this request */
1509 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1510 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1512 static int
1513 pmac_ide_dma_setup(ide_drive_t *drive)
1515 ide_hwif_t *hwif = drive->hwif;
1516 pmac_ide_hwif_t *pmif =
1517 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1518 struct request *rq = hwif->rq;
1519 u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1521 if (!pmac_ide_build_dmatable(drive, rq)) {
1522 ide_map_sg(drive, rq);
1523 return 1;
1526 /* Apple adds 60ns to wrDataSetup on reads */
1527 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1528 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1529 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1530 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1533 drive->waiting_for_dma = 1;
1535 return 0;
1538 static void
1539 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1541 /* issue cmd to drive */
1542 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1546 * Kick the DMA controller into life after the DMA command has been issued
1547 * to the drive.
1549 static void
1550 pmac_ide_dma_start(ide_drive_t *drive)
1552 ide_hwif_t *hwif = drive->hwif;
1553 pmac_ide_hwif_t *pmif =
1554 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1555 volatile struct dbdma_regs __iomem *dma;
1557 dma = pmif->dma_regs;
1559 writel((RUN << 16) | RUN, &dma->control);
1560 /* Make sure it gets to the controller right now */
1561 (void)readl(&dma->control);
1565 * After a DMA transfer, make sure the controller is stopped
1567 static int
1568 pmac_ide_dma_end (ide_drive_t *drive)
1570 ide_hwif_t *hwif = drive->hwif;
1571 pmac_ide_hwif_t *pmif =
1572 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1573 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1574 u32 dstat;
1576 drive->waiting_for_dma = 0;
1577 dstat = readl(&dma->status);
1578 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1580 ide_destroy_dmatable(drive);
1582 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1583 * in theory, but with ATAPI decices doing buffer underruns, that would
1584 * cause us to disable DMA, which isn't what we want
1586 return (dstat & (RUN|DEAD)) != RUN;
1590 * Check out that the interrupt we got was for us. We can't always know this
1591 * for sure with those Apple interfaces (well, we could on the recent ones but
1592 * that's not implemented yet), on the other hand, we don't have shared interrupts
1593 * so it's not really a problem
1595 static int
1596 pmac_ide_dma_test_irq (ide_drive_t *drive)
1598 ide_hwif_t *hwif = drive->hwif;
1599 pmac_ide_hwif_t *pmif =
1600 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1601 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1602 unsigned long status, timeout;
1604 /* We have to things to deal with here:
1606 * - The dbdma won't stop if the command was started
1607 * but completed with an error without transferring all
1608 * datas. This happens when bad blocks are met during
1609 * a multi-block transfer.
1611 * - The dbdma fifo hasn't yet finished flushing to
1612 * to system memory when the disk interrupt occurs.
1616 /* If ACTIVE is cleared, the STOP command have passed and
1617 * transfer is complete.
1619 status = readl(&dma->status);
1620 if (!(status & ACTIVE))
1621 return 1;
1623 /* If dbdma didn't execute the STOP command yet, the
1624 * active bit is still set. We consider that we aren't
1625 * sharing interrupts (which is hopefully the case with
1626 * those controllers) and so we just try to flush the
1627 * channel for pending data in the fifo
1629 udelay(1);
1630 writel((FLUSH << 16) | FLUSH, &dma->control);
1631 timeout = 0;
1632 for (;;) {
1633 udelay(1);
1634 status = readl(&dma->status);
1635 if ((status & FLUSH) == 0)
1636 break;
1637 if (++timeout > 100) {
1638 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1639 timeout flushing channel\n", hwif->index);
1640 break;
1643 return 1;
1646 static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1650 static void
1651 pmac_ide_dma_lost_irq (ide_drive_t *drive)
1653 ide_hwif_t *hwif = drive->hwif;
1654 pmac_ide_hwif_t *pmif =
1655 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1656 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1657 unsigned long status = readl(&dma->status);
1659 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1662 static const struct ide_dma_ops pmac_dma_ops = {
1663 .dma_host_set = pmac_ide_dma_host_set,
1664 .dma_setup = pmac_ide_dma_setup,
1665 .dma_exec_cmd = pmac_ide_dma_exec_cmd,
1666 .dma_start = pmac_ide_dma_start,
1667 .dma_end = pmac_ide_dma_end,
1668 .dma_test_irq = pmac_ide_dma_test_irq,
1669 .dma_timeout = ide_dma_timeout,
1670 .dma_lost_irq = pmac_ide_dma_lost_irq,
1674 * Allocate the data structures needed for using DMA with an interface
1675 * and fill the proper list of functions pointers
1677 static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1678 const struct ide_port_info *d)
1680 pmac_ide_hwif_t *pmif =
1681 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1682 struct pci_dev *dev = to_pci_dev(hwif->dev);
1684 /* We won't need pci_dev if we switch to generic consistent
1685 * DMA routines ...
1687 if (dev == NULL || pmif->dma_regs == 0)
1688 return -ENODEV;
1690 * Allocate space for the DBDMA commands.
1691 * The +2 is +1 for the stop command and +1 to allow for
1692 * aligning the start address to a multiple of 16 bytes.
1694 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1695 dev,
1696 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1697 &hwif->dmatable_dma);
1698 if (pmif->dma_table_cpu == NULL) {
1699 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1700 hwif->name);
1701 return -ENOMEM;
1704 hwif->sg_max_nents = MAX_DCMDS;
1706 return 0;
1709 module_init(pmac_ide_probe);
1711 MODULE_LICENSE("GPL");