drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72
  73 #include "radeon_family.h"
  74 #include "radeon_mode.h"
  75 #include "radeon_reg.h"
  76
  77 /*
  78  * Modules parameters.
  79  */
  80 extern int radeon_no_wb;
  81 extern int radeon_modeset;
  82 extern int radeon_dynclks;
  83 extern int radeon_r4xx_atom;
  84 extern int radeon_agpmode;
  85 extern int radeon_vram_limit;
  86 extern int radeon_gart_size;
  87 extern int radeon_benchmarking;
  88 extern int radeon_testing;
  89 extern int radeon_connector_table;
  90 extern int radeon_tv;
  91 extern int radeon_new_pll;
  92 extern int radeon_audio;
  93
  94 /*
  95  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  96  * symbol;
  97  */
  98 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  99 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 100 #define RADEON_IB_POOL_SIZE             16
 101 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 102 #define RADEONFB_CONN_LIMIT             4
 103 #define RADEON_BIOS_NUM_SCRATCH         8
 104
 105 /*
 106  * Errata workarounds.
 107  */
 108 enum radeon_pll_errata {
 109         CHIP_ERRATA_R300_CG             = 0x00000001,
 110         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 111         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 112 };
 113
 114
 115 struct radeon_device;
 116
 117
 118 /*
 119  * BIOS.
 120  */
 121 #define ATRM_BIOS_PAGE 4096
 122
 123 bool radeon_atrm_supported(struct pci_dev *pdev);
 124 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 125 bool radeon_get_bios(struct radeon_device *rdev);
 126
 127
 128 /*
 129  * Dummy page
 130  */
 131 struct radeon_dummy_page {
 132         struct page     *page;
 133         dma_addr_t      addr;
 134 };
 135 int radeon_dummy_page_init(struct radeon_device *rdev);
 136 void radeon_dummy_page_fini(struct radeon_device *rdev);
 137
 138
 139 /*
 140  * Clocks
 141  */
 142 struct radeon_clock {
 143         struct radeon_pll p1pll;
 144         struct radeon_pll p2pll;
 145         struct radeon_pll spll;
 146         struct radeon_pll mpll;
 147         /* 10 Khz units */
 148         uint32_t default_mclk;
 149         uint32_t default_sclk;
 150 };
 151
 152 /*
 153  * Power management
 154  */
 155 int radeon_pm_init(struct radeon_device *rdev);
 156
 157 /*
 158  * Fences.
 159  */
 160 struct radeon_fence_driver {
 161         uint32_t                        scratch_reg;
 162         atomic_t                        seq;
 163         uint32_t                        last_seq;
 164         unsigned long                   count_timeout;
 165         wait_queue_head_t               queue;
 166         rwlock_t                        lock;
 167         struct list_head                created;
 168         struct list_head                emited;
 169         struct list_head                signaled;
 170         bool                            initialized;
 171 };
 172
 173 struct radeon_fence {
 174         struct radeon_device            *rdev;
 175         struct kref                     kref;
 176         struct list_head                list;
 177         /* protected by radeon_fence.lock */
 178         uint32_t                        seq;
 179         unsigned long                   timeout;
 180         bool                            emited;
 181         bool                            signaled;
 182 };
 183
 184 int radeon_fence_driver_init(struct radeon_device *rdev);
 185 void radeon_fence_driver_fini(struct radeon_device *rdev);
 186 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 187 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 188 void radeon_fence_process(struct radeon_device *rdev);
 189 bool radeon_fence_signaled(struct radeon_fence *fence);
 190 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 191 int radeon_fence_wait_next(struct radeon_device *rdev);
 192 int radeon_fence_wait_last(struct radeon_device *rdev);
 193 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 194 void radeon_fence_unref(struct radeon_fence **fence);
 195
 196 /*
 197  * Tiling registers
 198  */
 199 struct radeon_surface_reg {
 200         struct radeon_bo *bo;
 201 };
 202
 203 #define RADEON_GEM_MAX_SURFACES 8
 204
 205 /*
 206  * TTM.
 207  */
 208 struct radeon_mman {
 209         struct ttm_bo_global_ref        bo_global_ref;
 210         struct ttm_global_reference     mem_global_ref;
 211         struct ttm_bo_device            bdev;
 212         bool                            mem_global_referenced;
 213         bool                            initialized;
 214 };
 215
 216 struct radeon_bo {
 217         /* Protected by gem.mutex */
 218         struct list_head                list;
 219         /* Protected by tbo.reserved */
 220         u32                             placements[3];
 221         struct ttm_placement            placement;
 222         struct ttm_buffer_object        tbo;
 223         struct ttm_bo_kmap_obj          kmap;
 224         unsigned                        pin_count;
 225         void                            *kptr;
 226         u32                             tiling_flags;
 227         u32                             pitch;
 228         int                             surface_reg;
 229         /* Constant after initialization */
 230         struct radeon_device            *rdev;
 231         struct drm_gem_object           *gobj;
 232 };
 233
 234 struct radeon_bo_list {
 235         struct list_head        list;
 236         struct radeon_bo        *bo;
 237         uint64_t                gpu_offset;
 238         unsigned                rdomain;
 239         unsigned                wdomain;
 240         u32                     tiling_flags;
 241 };
 242
 243 /*
 244  * GEM objects.
 245  */
 246 struct radeon_gem {
 247         struct mutex            mutex;
 248         struct list_head        objects;
 249 };
 250
 251 int radeon_gem_init(struct radeon_device *rdev);
 252 void radeon_gem_fini(struct radeon_device *rdev);
 253 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 254                                 int alignment, int initial_domain,
 255                                 bool discardable, bool kernel,
 256                                 struct drm_gem_object **obj);
 257 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 258                           uint64_t *gpu_addr);
 259 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 260
 261
 262 /*
 263  * GART structures, functions & helpers
 264  */
 265 struct radeon_mc;
 266
 267 struct radeon_gart_table_ram {
 268         volatile uint32_t               *ptr;
 269 };
 270
 271 struct radeon_gart_table_vram {
 272         struct radeon_bo                *robj;
 273         volatile uint32_t               *ptr;
 274 };
 275
 276 union radeon_gart_table {
 277         struct radeon_gart_table_ram    ram;
 278         struct radeon_gart_table_vram   vram;
 279 };
 280
 281 #define RADEON_GPU_PAGE_SIZE 4096
 282
 283 struct radeon_gart {
 284         dma_addr_t                      table_addr;
 285         unsigned                        num_gpu_pages;
 286         unsigned                        num_cpu_pages;
 287         unsigned                        table_size;
 288         union radeon_gart_table         table;
 289         struct page                     **pages;
 290         dma_addr_t                      *pages_addr;
 291         bool                            ready;
 292 };
 293
 294 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 295 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 296 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 297 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 298 int radeon_gart_init(struct radeon_device *rdev);
 299 void radeon_gart_fini(struct radeon_device *rdev);
 300 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 301                         int pages);
 302 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 303                      int pages, struct page **pagelist);
 304
 305
 306 /*
 307  * GPU MC structures, functions & helpers
 308  */
 309 struct radeon_mc {
 310         resource_size_t         aper_size;
 311         resource_size_t         aper_base;
 312         resource_size_t         agp_base;
 313         /* for some chips with <= 32MB we need to lie
 314          * about vram size near mc fb location */
 315         u64                     mc_vram_size;
 316         u64                     gtt_location;
 317         u64                     gtt_size;
 318         u64                     gtt_start;
 319         u64                     gtt_end;
 320         u64                     vram_location;
 321         u64                     vram_start;
 322         u64                     vram_end;
 323         unsigned                vram_width;
 324         u64                     real_vram_size;
 325         int                     vram_mtrr;
 326         bool                    vram_is_ddr;
 327         bool                    igp_sideport_enabled;
 328 };
 329
 330 int radeon_mc_setup(struct radeon_device *rdev);
 331 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 332 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 333
 334 /*
 335  * GPU scratch registers structures, functions & helpers
 336  */
 337 struct radeon_scratch {
 338         unsigned                num_reg;
 339         bool                    free[32];
 340         uint32_t                reg[32];
 341 };
 342
 343 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 344 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 345
 346
 347 /*
 348  * IRQS.
 349  */
 350 struct radeon_irq {
 351         bool            installed;
 352         bool            sw_int;
 353         /* FIXME: use a define max crtc rather than hardcode it */
 354         bool            crtc_vblank_int[2];
 355         /* FIXME: use defines for max hpd/dacs */
 356         bool            hpd[6];
 357         spinlock_t sw_lock;
 358         int sw_refcount;
 359 };
 360
 361 int radeon_irq_kms_init(struct radeon_device *rdev);
 362 void radeon_irq_kms_fini(struct radeon_device *rdev);
 363 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 364 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 365
 366 /*
 367  * CP & ring.
 368  */
 369 struct radeon_ib {
 370         struct list_head        list;
 371         unsigned                idx;
 372         uint64_t                gpu_addr;
 373         struct radeon_fence     *fence;
 374         uint32_t                *ptr;
 375         uint32_t                length_dw;
 376         bool                    free;
 377 };
 378
 379 /*
 380  * locking -
 381  * mutex protects scheduled_ibs, ready, alloc_bm
 382  */
 383 struct radeon_ib_pool {
 384         struct mutex            mutex;
 385         struct radeon_bo        *robj;
 386         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 387         bool                    ready;
 388         unsigned                head_id;
 389 };
 390
 391 struct radeon_cp {
 392         struct radeon_bo        *ring_obj;
 393         volatile uint32_t       *ring;
 394         unsigned                rptr;
 395         unsigned                wptr;
 396         unsigned                wptr_old;
 397         unsigned                ring_size;
 398         unsigned                ring_free_dw;
 399         int                     count_dw;
 400         uint64_t                gpu_addr;
 401         uint32_t                align_mask;
 402         uint32_t                ptr_mask;
 403         struct mutex            mutex;
 404         bool                    ready;
 405 };
 406
 407 /*
 408  * R6xx+ IH ring
 409  */
 410 struct r600_ih {
 411         struct radeon_bo        *ring_obj;
 412         volatile uint32_t       *ring;
 413         unsigned                rptr;
 414         unsigned                wptr;
 415         unsigned                wptr_old;
 416         unsigned                ring_size;
 417         uint64_t                gpu_addr;
 418         uint32_t                ptr_mask;
 419         spinlock_t              lock;
 420         bool                    enabled;
 421 };
 422
 423 struct r600_blit {
 424         struct mutex            mutex;
 425         struct radeon_bo        *shader_obj;
 426         u64 shader_gpu_addr;
 427         u32 vs_offset, ps_offset;
 428         u32 state_offset;
 429         u32 state_len;
 430         u32 vb_used, vb_total;
 431         struct radeon_ib *vb_ib;
 432 };
 433
 434 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 435 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 436 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 437 int radeon_ib_pool_init(struct radeon_device *rdev);
 438 void radeon_ib_pool_fini(struct radeon_device *rdev);
 439 int radeon_ib_test(struct radeon_device *rdev);
 440 /* Ring access between begin & end cannot sleep */
 441 void radeon_ring_free_size(struct radeon_device *rdev);
 442 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 443 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 444 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 445 int radeon_ring_test(struct radeon_device *rdev);
 446 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 447 void radeon_ring_fini(struct radeon_device *rdev);
 448
 449
 450 /*
 451  * CS.
 452  */
 453 struct radeon_cs_reloc {
 454         struct drm_gem_object           *gobj;
 455         struct radeon_bo                *robj;
 456         struct radeon_bo_list           lobj;
 457         uint32_t                        handle;
 458         uint32_t                        flags;
 459 };
 460
 461 struct radeon_cs_chunk {
 462         uint32_t                chunk_id;
 463         uint32_t                length_dw;
 464         int kpage_idx[2];
 465         uint32_t                *kpage[2];
 466         uint32_t                *kdata;
 467         void __user *user_ptr;
 468         int last_copied_page;
 469         int last_page_index;
 470 };
 471
 472 struct radeon_cs_parser {
 473         struct device           *dev;
 474         struct radeon_device    *rdev;
 475         struct drm_file         *filp;
 476         /* chunks */
 477         unsigned                nchunks;
 478         struct radeon_cs_chunk  *chunks;
 479         uint64_t                *chunks_array;
 480         /* IB */
 481         unsigned                idx;
 482         /* relocations */
 483         unsigned                nrelocs;
 484         struct radeon_cs_reloc  *relocs;
 485         struct radeon_cs_reloc  **relocs_ptr;
 486         struct list_head        validated;
 487         /* indices of various chunks */
 488         int                     chunk_ib_idx;
 489         int                     chunk_relocs_idx;
 490         struct radeon_ib        *ib;
 491         void                    *track;
 492         unsigned                family;
 493         int parser_error;
 494 };
 495
 496 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 497 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 498
 499
 500 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 501 {
 502         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 503         u32 pg_idx, pg_offset;
 504         u32 idx_value = 0;
 505         int new_page;
 506
 507         pg_idx = (idx * 4) / PAGE_SIZE;
 508         pg_offset = (idx * 4) % PAGE_SIZE;
 509
 510         if (ibc->kpage_idx[0] == pg_idx)
 511                 return ibc->kpage[0][pg_offset/4];
 512         if (ibc->kpage_idx[1] == pg_idx)
 513                 return ibc->kpage[1][pg_offset/4];
 514
 515         new_page = radeon_cs_update_pages(p, pg_idx);
 516         if (new_page < 0) {
 517                 p->parser_error = new_page;
 518                 return 0;
 519         }
 520
 521         idx_value = ibc->kpage[new_page][pg_offset/4];
 522         return idx_value;
 523 }
 524
 525 struct radeon_cs_packet {
 526         unsigned        idx;
 527         unsigned        type;
 528         unsigned        reg;
 529         unsigned        opcode;
 530         int             count;
 531         unsigned        one_reg_wr;
 532 };
 533
 534 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 535                                       struct radeon_cs_packet *pkt,
 536                                       unsigned idx, unsigned reg);
 537 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 538                                       struct radeon_cs_packet *pkt);
 539
 540
 541 /*
 542  * AGP
 543  */
 544 int radeon_agp_init(struct radeon_device *rdev);
 545 void radeon_agp_resume(struct radeon_device *rdev);
 546 void radeon_agp_fini(struct radeon_device *rdev);
 547
 548
 549 /*
 550  * Writeback
 551  */
 552 struct radeon_wb {
 553         struct radeon_bo        *wb_obj;
 554         volatile uint32_t       *wb;
 555         uint64_t                gpu_addr;
 556 };
 557
 558 /**
 559  * struct radeon_pm - power management datas
 560  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 561  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 562  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 563  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 564  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 565  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 566  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 567  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 568  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 569  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 570  * @needed_bandwidth:   current bandwidth needs
 571  *
 572  * It keeps track of various data needed to take powermanagement decision.
 573  * Bandwith need is used to determine minimun clock of the GPU and memory.
 574  * Equation between gpu/memory clock and available bandwidth is hw dependent
 575  * (type of memory, bus size, efficiency, ...)
 576  */
 577 struct radeon_pm {
 578         fixed20_12              max_bandwidth;
 579         fixed20_12              igp_sideport_mclk;
 580         fixed20_12              igp_system_mclk;
 581         fixed20_12              igp_ht_link_clk;
 582         fixed20_12              igp_ht_link_width;
 583         fixed20_12              k8_bandwidth;
 584         fixed20_12              sideport_bandwidth;
 585         fixed20_12              ht_bandwidth;
 586         fixed20_12              core_bandwidth;
 587         fixed20_12              sclk;
 588         fixed20_12              needed_bandwidth;
 589 };
 590
 591
 592 /*
 593  * Benchmarking
 594  */
 595 void radeon_benchmark(struct radeon_device *rdev);
 596
 597
 598 /*
 599  * Testing
 600  */
 601 void radeon_test_moves(struct radeon_device *rdev);
 602
 603
 604 /*
 605  * Debugfs
 606  */
 607 int radeon_debugfs_add_files(struct radeon_device *rdev,
 608                              struct drm_info_list *files,
 609                              unsigned nfiles);
 610 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 611 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 612 int r100_debugfs_cp_init(struct radeon_device *rdev);
 613
 614
 615 /*
 616  * ASIC specific functions.
 617  */
 618 struct radeon_asic {
 619         int (*init)(struct radeon_device *rdev);
 620         void (*fini)(struct radeon_device *rdev);
 621         int (*resume)(struct radeon_device *rdev);
 622         int (*suspend)(struct radeon_device *rdev);
 623         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 624         int (*gpu_reset)(struct radeon_device *rdev);
 625         void (*gart_tlb_flush)(struct radeon_device *rdev);
 626         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 627         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 628         void (*cp_fini)(struct radeon_device *rdev);
 629         void (*cp_disable)(struct radeon_device *rdev);
 630         void (*cp_commit)(struct radeon_device *rdev);
 631         void (*ring_start)(struct radeon_device *rdev);
 632         int (*ring_test)(struct radeon_device *rdev);
 633         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 634         int (*irq_set)(struct radeon_device *rdev);
 635         int (*irq_process)(struct radeon_device *rdev);
 636         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 637         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 638         int (*cs_parse)(struct radeon_cs_parser *p);
 639         int (*copy_blit)(struct radeon_device *rdev,
 640                          uint64_t src_offset,
 641                          uint64_t dst_offset,
 642                          unsigned num_pages,
 643                          struct radeon_fence *fence);
 644         int (*copy_dma)(struct radeon_device *rdev,
 645                         uint64_t src_offset,
 646                         uint64_t dst_offset,
 647                         unsigned num_pages,
 648                         struct radeon_fence *fence);
 649         int (*copy)(struct radeon_device *rdev,
 650                     uint64_t src_offset,
 651                     uint64_t dst_offset,
 652                     unsigned num_pages,
 653                     struct radeon_fence *fence);
 654         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 655         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 656         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 657         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 658         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 659         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 660         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 661                                uint32_t tiling_flags, uint32_t pitch,
 662                                uint32_t offset, uint32_t obj_size);
 663         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 664         void (*bandwidth_update)(struct radeon_device *rdev);
 665         void (*hpd_init)(struct radeon_device *rdev);
 666         void (*hpd_fini)(struct radeon_device *rdev);
 667         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 668         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 669         /* ioctl hw specific callback. Some hw might want to perform special
 670          * operation on specific ioctl. For instance on wait idle some hw
 671          * might want to perform and HDP flush through MMIO as it seems that
 672          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 673          * through ring.
 674          */
 675         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 676 };
 677
 678 /*
 679  * Asic structures
 680  */
 681 struct r100_asic {
 682         const unsigned  *reg_safe_bm;
 683         unsigned        reg_safe_bm_size;
 684         u32             hdp_cntl;
 685 };
 686
 687 struct r300_asic {
 688         const unsigned  *reg_safe_bm;
 689         unsigned        reg_safe_bm_size;
 690         u32             resync_scratch;
 691         u32             hdp_cntl;
 692 };
 693
 694 struct r600_asic {
 695         unsigned max_pipes;
 696         unsigned max_tile_pipes;
 697         unsigned max_simds;
 698         unsigned max_backends;
 699         unsigned max_gprs;
 700         unsigned max_threads;
 701         unsigned max_stack_entries;
 702         unsigned max_hw_contexts;
 703         unsigned max_gs_threads;
 704         unsigned sx_max_export_size;
 705         unsigned sx_max_export_pos_size;
 706         unsigned sx_max_export_smx_size;
 707         unsigned sq_num_cf_insts;
 708 };
 709
 710 struct rv770_asic {
 711         unsigned max_pipes;
 712         unsigned max_tile_pipes;
 713         unsigned max_simds;
 714         unsigned max_backends;
 715         unsigned max_gprs;
 716         unsigned max_threads;
 717         unsigned max_stack_entries;
 718         unsigned max_hw_contexts;
 719         unsigned max_gs_threads;
 720         unsigned sx_max_export_size;
 721         unsigned sx_max_export_pos_size;
 722         unsigned sx_max_export_smx_size;
 723         unsigned sq_num_cf_insts;
 724         unsigned sx_num_of_sets;
 725         unsigned sc_prim_fifo_size;
 726         unsigned sc_hiz_tile_fifo_size;
 727         unsigned sc_earlyz_tile_fifo_fize;
 728 };
 729
 730 union radeon_asic_config {
 731         struct r300_asic        r300;
 732         struct r100_asic        r100;
 733         struct r600_asic        r600;
 734         struct rv770_asic       rv770;
 735 };
 736
 737
 738 /*
 739  * IOCTL.
 740  */
 741 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 742                           struct drm_file *filp);
 743 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 744                             struct drm_file *filp);
 745 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 746                          struct drm_file *file_priv);
 747 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 748                            struct drm_file *file_priv);
 749 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 750                             struct drm_file *file_priv);
 751 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 752                            struct drm_file *file_priv);
 753 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 754                                 struct drm_file *filp);
 755 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 756                           struct drm_file *filp);
 757 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 758                           struct drm_file *filp);
 759 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 760                               struct drm_file *filp);
 761 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 762 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 763                                 struct drm_file *filp);
 764 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 765                                 struct drm_file *filp);
 766
 767
 768 /*
 769  * Core structure, functions and helpers.
 770  */
 771 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 772 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 773
 774 struct radeon_device {
 775         struct device                   *dev;
 776         struct drm_device               *ddev;
 777         struct pci_dev                  *pdev;
 778         /* ASIC */
 779         union radeon_asic_config        config;
 780         enum radeon_family              family;
 781         unsigned long                   flags;
 782         int                             usec_timeout;
 783         enum radeon_pll_errata          pll_errata;
 784         int                             num_gb_pipes;
 785         int                             num_z_pipes;
 786         int                             disp_priority;
 787         /* BIOS */
 788         uint8_t                         *bios;
 789         bool                            is_atom_bios;
 790         uint16_t                        bios_header_start;
 791         struct radeon_bo                *stollen_vga_memory;
 792         struct fb_info                  *fbdev_info;
 793         struct radeon_bo                *fbdev_rbo;
 794         struct radeon_framebuffer       *fbdev_rfb;
 795         /* Register mmio */
 796         resource_size_t                 rmmio_base;
 797         resource_size_t                 rmmio_size;
 798         void                            *rmmio;
 799         radeon_rreg_t                   mc_rreg;
 800         radeon_wreg_t                   mc_wreg;
 801         radeon_rreg_t                   pll_rreg;
 802         radeon_wreg_t                   pll_wreg;
 803         uint32_t                        pcie_reg_mask;
 804         radeon_rreg_t                   pciep_rreg;
 805         radeon_wreg_t                   pciep_wreg;
 806         struct radeon_clock             clock;
 807         struct radeon_mc                mc;
 808         struct radeon_gart              gart;
 809         struct radeon_mode_info         mode_info;
 810         struct radeon_scratch           scratch;
 811         struct radeon_mman              mman;
 812         struct radeon_fence_driver      fence_drv;
 813         struct radeon_cp                cp;
 814         struct radeon_ib_pool           ib_pool;
 815         struct radeon_irq               irq;
 816         struct radeon_asic              *asic;
 817         struct radeon_gem               gem;
 818         struct radeon_pm                pm;
 819         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 820         struct mutex                    cs_mutex;
 821         struct radeon_wb                wb;
 822         struct radeon_dummy_page        dummy_page;
 823         bool                            gpu_lockup;
 824         bool                            shutdown;
 825         bool                            suspend;
 826         bool                            need_dma32;
 827         bool                            accel_working;
 828         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 829         const struct firmware *me_fw;   /* all family ME firmware */
 830         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 831         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
 832         struct r600_blit r600_blit;
 833         int msi_enabled; /* msi enabled */
 834         struct r600_ih ih; /* r6/700 interrupt ring */
 835         struct workqueue_struct *wq;
 836         struct work_struct hotplug_work;
 837
 838         /* audio stuff */
 839         struct timer_list       audio_timer;
 840         int                     audio_channels;
 841         int                     audio_rate;
 842         int                     audio_bits_per_sample;
 843         uint8_t                 audio_status_bits;
 844         uint8_t                 audio_category_code;
 845
 846         bool powered_down;
 847 };
 848
 849 int radeon_device_init(struct radeon_device *rdev,
 850                        struct drm_device *ddev,
 851                        struct pci_dev *pdev,
 852                        uint32_t flags);
 853 void radeon_device_fini(struct radeon_device *rdev);
 854 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 855
 856 /* r600 blit */
 857 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 858 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 859 void r600_kms_blit_copy(struct radeon_device *rdev,
 860                         u64 src_gpu_addr, u64 dst_gpu_addr,
 861                         int size_bytes);
 862
 863 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 864 {
 865         if (reg < rdev->rmmio_size)
 866                 return readl(((void __iomem *)rdev->rmmio) + reg);
 867         else {
 868                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 869                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 870         }
 871 }
 872
 873 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 874 {
 875         if (reg < rdev->rmmio_size)
 876                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 877         else {
 878                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 879                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 880         }
 881 }
 882
 883 /*
 884  * Cast helper
 885  */
 886 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
 887
 888 /*
 889  * Registers read & write functions.
 890  */
 891 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 892 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 893 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 894 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 895 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 896 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 897 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 898 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 899 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 900 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 901 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 902 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 903 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 904 #define WREG32_P(reg, val, mask)                                \
 905         do {                                                    \
 906                 uint32_t tmp_ = RREG32(reg);                    \
 907                 tmp_ &= (mask);                                 \
 908                 tmp_ |= ((val) & ~(mask));                      \
 909                 WREG32(reg, tmp_);                              \
 910         } while (0)
 911 #define WREG32_PLL_P(reg, val, mask)                            \
 912         do {                                                    \
 913                 uint32_t tmp_ = RREG32_PLL(reg);                \
 914                 tmp_ &= (mask);                                 \
 915                 tmp_ |= ((val) & ~(mask));                      \
 916                 WREG32_PLL(reg, tmp_);                          \
 917         } while (0)
 918 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 919
 920 /*
 921  * Indirect registers accessor
 922  */
 923 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 924 {
 925         uint32_t r;
 926
 927         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 928         r = RREG32(RADEON_PCIE_DATA);
 929         return r;
 930 }
 931
 932 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 933 {
 934         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 935         WREG32(RADEON_PCIE_DATA, (v));
 936 }
 937
 938 void r100_pll_errata_after_index(struct radeon_device *rdev);
 939
 940
 941 /*
 942  * ASICs helpers.
 943  */
 944 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 945                             (rdev->pdev->device == 0x5969))
 946 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 947                 (rdev->family == CHIP_RV200) || \
 948                 (rdev->family == CHIP_RS100) || \
 949                 (rdev->family == CHIP_RS200) || \
 950                 (rdev->family == CHIP_RV250) || \
 951                 (rdev->family == CHIP_RV280) || \
 952                 (rdev->family == CHIP_RS300))
 953 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 954                 (rdev->family == CHIP_RV350) ||                 \
 955                 (rdev->family == CHIP_R350)  ||                 \
 956                 (rdev->family == CHIP_RV380) ||                 \
 957                 (rdev->family == CHIP_R420)  ||                 \
 958                 (rdev->family == CHIP_R423)  ||                 \
 959                 (rdev->family == CHIP_RV410) ||                 \
 960                 (rdev->family == CHIP_RS400) ||                 \
 961                 (rdev->family == CHIP_RS480))
 962 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 963 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 964 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 965
 966
 967 /*
 968  * BIOS helpers.
 969  */
 970 #define RBIOS8(i) (rdev->bios[i])
 971 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 972 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 973
 974 int radeon_combios_init(struct radeon_device *rdev);
 975 void radeon_combios_fini(struct radeon_device *rdev);
 976 int radeon_atombios_init(struct radeon_device *rdev);
 977 void radeon_atombios_fini(struct radeon_device *rdev);
 978
 979
 980 /*
 981  * RING helpers.
 982  */
 983 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 984 {
 985 #if DRM_DEBUG_CODE
 986         if (rdev->cp.count_dw <= 0) {
 987                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 988         }
 989 #endif
 990         rdev->cp.ring[rdev->cp.wptr++] = v;
 991         rdev->cp.wptr &= rdev->cp.ptr_mask;
 992         rdev->cp.count_dw--;
 993         rdev->cp.ring_free_dw--;
 994 }
 995
 996
 997 /*
 998  * ASICs macro.
 999  */
1000 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1001 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1002 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1003 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1004 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1005 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1006 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1007 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1008 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1009 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1010 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1011 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1012 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1013 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1014 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1015 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1016 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1017 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1018 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1019 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1020 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1021 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1022 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1023 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1024 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1025 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1026 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1027 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1028 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1029 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1030 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1031 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1032 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1033
1034 /* Common functions */
1035 /* AGP */
1036 extern void radeon_agp_disable(struct radeon_device *rdev);
1037 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1038 extern int radeon_modeset_init(struct radeon_device *rdev);
1039 extern void radeon_modeset_fini(struct radeon_device *rdev);
1040 extern bool radeon_card_posted(struct radeon_device *rdev);
1041 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1042 extern int radeon_clocks_init(struct radeon_device *rdev);
1043 extern void radeon_clocks_fini(struct radeon_device *rdev);
1044 extern void radeon_scratch_init(struct radeon_device *rdev);
1045 extern void radeon_surface_init(struct radeon_device *rdev);
1046 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1047 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1048 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1049 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1050 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1051 extern int radeon_resume_kms(struct drm_device *dev);
1052 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1053
1054 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1055 struct r100_mc_save {
1056         u32     GENMO_WT;
1057         u32     CRTC_EXT_CNTL;
1058         u32     CRTC_GEN_CNTL;
1059         u32     CRTC2_GEN_CNTL;
1060         u32     CUR_OFFSET;
1061         u32     CUR2_OFFSET;
1062 };
1063 extern void r100_cp_disable(struct radeon_device *rdev);
1064 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1065 extern void r100_cp_fini(struct radeon_device *rdev);
1066 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1067 extern int r100_pci_gart_init(struct radeon_device *rdev);
1068 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1069 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1070 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1071 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1072 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1073 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1074 extern void r100_ib_fini(struct radeon_device *rdev);
1075 extern int r100_ib_init(struct radeon_device *rdev);
1076 extern void r100_irq_disable(struct radeon_device *rdev);
1077 extern int r100_irq_set(struct radeon_device *rdev);
1078 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1079 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1080 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1081 extern void r100_wb_disable(struct radeon_device *rdev);
1082 extern void r100_wb_fini(struct radeon_device *rdev);
1083 extern int r100_wb_init(struct radeon_device *rdev);
1084 extern void r100_hdp_reset(struct radeon_device *rdev);
1085 extern int r100_rb2d_reset(struct radeon_device *rdev);
1086 extern int r100_cp_reset(struct radeon_device *rdev);
1087 extern void r100_vga_render_disable(struct radeon_device *rdev);
1088 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1089                                                 struct radeon_cs_packet *pkt,
1090                                                 struct radeon_bo *robj);
1091 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1092                                 struct radeon_cs_packet *pkt,
1093                                 const unsigned *auth, unsigned n,
1094                                 radeon_packet0_check_t check);
1095 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1096                                 struct radeon_cs_packet *pkt,
1097                                 unsigned idx);
1098 extern void r100_enable_bm(struct radeon_device *rdev);
1099 extern void r100_set_common_regs(struct radeon_device *rdev);
1100
1101 /* rv200,rv250,rv280 */
1102 extern void r200_set_safe_registers(struct radeon_device *rdev);
1103
1104 /* r300,r350,rv350,rv370,rv380 */
1105 extern void r300_set_reg_safe(struct radeon_device *rdev);
1106 extern void r300_mc_program(struct radeon_device *rdev);
1107 extern void r300_vram_info(struct radeon_device *rdev);
1108 extern void r300_clock_startup(struct radeon_device *rdev);
1109 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1110 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1111 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1112 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1113 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1114
1115 /* r420,r423,rv410 */
1116 extern int r420_mc_init(struct radeon_device *rdev);
1117 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1118 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1119 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1120 extern void r420_pipes_init(struct radeon_device *rdev);
1121
1122 /* rv515 */
1123 struct rv515_mc_save {
1124         u32 d1vga_control;
1125         u32 d2vga_control;
1126         u32 vga_render_control;
1127         u32 vga_hdp_control;
1128         u32 d1crtc_control;
1129         u32 d2crtc_control;
1130 };
1131 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1132 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1133 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1134 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1135 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1136 extern void rv515_clock_startup(struct radeon_device *rdev);
1137 extern void rv515_debugfs(struct radeon_device *rdev);
1138 extern int rv515_suspend(struct radeon_device *rdev);
1139
1140 /* rs400 */
1141 extern int rs400_gart_init(struct radeon_device *rdev);
1142 extern int rs400_gart_enable(struct radeon_device *rdev);
1143 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1144 extern void rs400_gart_disable(struct radeon_device *rdev);
1145 extern void rs400_gart_fini(struct radeon_device *rdev);
1146
1147 /* rs600 */
1148 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1149 extern int rs600_irq_set(struct radeon_device *rdev);
1150 extern void rs600_irq_disable(struct radeon_device *rdev);
1151
1152 /* rs690, rs740 */
1153 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1154                                         struct drm_display_mode *mode1,
1155                                         struct drm_display_mode *mode2);
1156
1157 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1158 extern bool r600_card_posted(struct radeon_device *rdev);
1159 extern void r600_cp_stop(struct radeon_device *rdev);
1160 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1161 extern int r600_cp_resume(struct radeon_device *rdev);
1162 extern void r600_cp_fini(struct radeon_device *rdev);
1163 extern int r600_count_pipe_bits(uint32_t val);
1164 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1165 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1166 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1167 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1168 extern int r600_ib_test(struct radeon_device *rdev);
1169 extern int r600_ring_test(struct radeon_device *rdev);
1170 extern void r600_wb_fini(struct radeon_device *rdev);
1171 extern int r600_wb_enable(struct radeon_device *rdev);
1172 extern void r600_wb_disable(struct radeon_device *rdev);
1173 extern void r600_scratch_init(struct radeon_device *rdev);
1174 extern int r600_blit_init(struct radeon_device *rdev);
1175 extern void r600_blit_fini(struct radeon_device *rdev);
1176 extern int r600_init_microcode(struct radeon_device *rdev);
1177 extern int r600_gpu_reset(struct radeon_device *rdev);
1178 /* r600 irq */
1179 extern int r600_irq_init(struct radeon_device *rdev);
1180 extern void r600_irq_fini(struct radeon_device *rdev);
1181 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1182 extern int r600_irq_set(struct radeon_device *rdev);
1183 extern void r600_irq_suspend(struct radeon_device *rdev);
1184 /* r600 audio */
1185 extern int r600_audio_init(struct radeon_device *rdev);
1186 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1187 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1188 extern void r600_audio_fini(struct radeon_device *rdev);
1189 extern void r600_hdmi_init(struct drm_encoder *encoder);
1190 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1191 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1192 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1193 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1194                                             int channels,
1195                                             int rate,
1196                                             int bps,
1197                                             uint8_t status_bits,
1198                                             uint8_t category_code);
1199
1200 #include "radeon_object.h"
1201
1202 #endif