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PM/Suspend: Introduce two new platform callbacks to avoid breakage
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / i810 / i810_main.c
blob2e940199fc892b40ceac2630019ef3cea9456c61
1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
3 *
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
5 * All Rights Reserved
6 *
7 * Contributors:
8 * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
9 * and enabling the power-on state of
10 * external VGA connectors for
11 * secondary displays
12 *
13 * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
14 * the VESA GTF
15 *
16 * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
17 * timings support
18 *
19 * The code framework is a modification of vfb.c by Geert Uytterhoeven.
20 * DotClock and PLL calculations are partly based on i810_driver.c
21 * in xfree86 v4.0.3 by Precision Insight.
22 * Watermark calculation and tables are based on i810_wmark.c
23 * in xfre86 v4.0.3 by Precision Insight. Slight modifications
24 * only to allow for integer operations instead of floating point.
25 *
26 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file COPYING in the main directory of this archive for
28 * more details.
29 */
30
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mm.h>
36 #include <linux/slab.h>
37 #include <linux/fb.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/pci_ids.h>
41 #include <linux/resource.h>
42 #include <linux/unistd.h>
43 #include <linux/console.h>
44
45 #include <asm/io.h>
46 #include <asm/div64.h>
47 #include <asm/page.h>
48
49 #include "i810_regs.h"
50 #include "i810.h"
51 #include "i810_main.h"
52
53 /*
54 * voffset - framebuffer offset in MiB from aperture start address. In order for
55 * the driver to work with X, we must try to use memory holes left untouched by X. The
56 * following table lists where X's different surfaces start at.
57 *
58 * ---------------------------------------------
59 * : : 64 MiB : 32 MiB :
60 * ----------------------------------------------
61 * : FrontBuffer : 0 : 0 :
62 * : DepthBuffer : 48 : 16 :
63 * : BackBuffer : 56 : 24 :
64 * ----------------------------------------------
65 *
66 * So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to
67 * 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should
68 * work, allowing 7 + 1 MiB of Framebuffer memory.
69 * Note, the size of the hole may change depending on how much memory you allocate to X,
70 * and how the memory is split up between these surfaces.
71 *
72 * Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with
73 * DRI disabled. But if the Frontbuffer is overlapped, X will fail to load.
74 *
75 * Experiment with v_offset to find out which works best for you.
76 */
77 static u32 v_offset_default __devinitdata; /* For 32 MiB Aper size, 8 should be the default */
78 static u32 voffset __devinitdata;
79
80 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
81 static int __devinit i810fb_init_pci (struct pci_dev *dev,
82 const struct pci_device_id *entry);
83 static void __exit i810fb_remove_pci(struct pci_dev *dev);
84 static int i810fb_resume(struct pci_dev *dev);
85 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state);
86
87 /* Chipset Specific Functions */
88 static int i810fb_set_par (struct fb_info *info);
89 static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue,
90 u8 *transp, struct fb_info *info);
91 static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue,
92 unsigned transp, struct fb_info *info);
93 static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
94 static int i810fb_blank (int blank_mode, struct fb_info *info);
95
96 /* Initialization */
97 static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
98
99 /* PCI */
100 static const char *i810_pci_list[] __devinitdata = {
101 "Intel(R) 810 Framebuffer Device" ,
102 "Intel(R) 810-DC100 Framebuffer Device" ,
103 "Intel(R) 810E Framebuffer Device" ,
104 "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
105 "Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
106 "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
107 };
108
109 static struct pci_device_id i810fb_pci_tbl[] = {
110 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
112 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
116 /* mvo: added i815 PCI-ID */
117 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
119 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
121 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
123 { 0 },
124 };
125
126 static struct pci_driver i810fb_driver = {
127 .name = "i810fb",
128 .id_table = i810fb_pci_tbl,
129 .probe = i810fb_init_pci,
130 .remove = __exit_p(i810fb_remove_pci),
131 .suspend = i810fb_suspend,
132 .resume = i810fb_resume,
133 };
134
135 static char *mode_option __devinitdata = NULL;
136 static int vram __devinitdata = 4;
137 static int bpp __devinitdata = 8;
138 static int mtrr __devinitdata;
139 static int accel __devinitdata;
140 static int hsync1 __devinitdata;
141 static int hsync2 __devinitdata;
142 static int vsync1 __devinitdata;
143 static int vsync2 __devinitdata;
144 static int xres __devinitdata;
145 static int yres;
146 static int vyres __devinitdata;
147 static int sync __devinitdata;
148 static int extvga __devinitdata;
149 static int dcolor __devinitdata;
150 static int ddc3 __devinitdata = 2;
151
152 /*------------------------------------------------------------*/
153
154 /**************************************************************
155 * Hardware Low Level Routines *
156 **************************************************************/
157
158 /**
159 * i810_screen_off - turns off/on display
160 * @mmio: address of register space
161 * @mode: on or off
162 *
163 * DESCRIPTION:
164 * Blanks/unblanks the display
165 */
166 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
167 {
168 u32 count = WAIT_COUNT;
169 u8 val;
170
171 i810_writeb(SR_INDEX, mmio, SR01);
172 val = i810_readb(SR_DATA, mmio);
173 val = (mode == OFF) ? val | SCR_OFF :
174 val & ~SCR_OFF;
175
176 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
177 i810_writeb(SR_INDEX, mmio, SR01);
178 i810_writeb(SR_DATA, mmio, val);
179 }
180
181 /**
182 * i810_dram_off - turns off/on dram refresh
183 * @mmio: address of register space
184 * @mode: on or off
185 *
186 * DESCRIPTION:
187 * Turns off DRAM refresh. Must be off for only 2 vsyncs
188 * before data becomes corrupt
189 */
190 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
191 {
192 u8 val;
193
194 val = i810_readb(DRAMCH, mmio);
195 val &= DRAM_OFF;
196 val = (mode == OFF) ? val : val | DRAM_ON;
197 i810_writeb(DRAMCH, mmio, val);
198 }
199
200 /**
201 * i810_protect_regs - allows rw/ro mode of certain VGA registers
202 * @mmio: address of register space
203 * @mode: protect/unprotect
204 *
205 * DESCRIPTION:
206 * The IBM VGA standard allows protection of certain VGA registers.
207 * This will protect or unprotect them.
208 */
209 static void i810_protect_regs(u8 __iomem *mmio, int mode)
210 {
211 u8 reg;
212
213 i810_writeb(CR_INDEX_CGA, mmio, CR11);
214 reg = i810_readb(CR_DATA_CGA, mmio);
215 reg = (mode == OFF) ? reg & ~0x80 :
216 reg | 0x80;
217
218 i810_writeb(CR_INDEX_CGA, mmio, CR11);
219 i810_writeb(CR_DATA_CGA, mmio, reg);
220 }
221
222 /**
223 * i810_load_pll - loads values for the hardware PLL clock
224 * @par: pointer to i810fb_par structure
225 *
226 * DESCRIPTION:
227 * Loads the P, M, and N registers.
228 */
229 static void i810_load_pll(struct i810fb_par *par)
230 {
231 u32 tmp1, tmp2;
232 u8 __iomem *mmio = par->mmio_start_virtual;
233
234 tmp1 = par->regs.M | par->regs.N << 16;
235 tmp2 = i810_readl(DCLK_2D, mmio);
236 tmp2 &= ~MN_MASK;
237 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
238
239 tmp1 = par->regs.P;
240 tmp2 = i810_readl(DCLK_0DS, mmio);
241 tmp2 &= ~(P_OR << 16);
242 i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
243
244 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
245
246 }
247
248 /**
249 * i810_load_vga - load standard VGA registers
250 * @par: pointer to i810fb_par structure
251 *
252 * DESCRIPTION:
253 * Load values to VGA registers
254 */
255 static void i810_load_vga(struct i810fb_par *par)
256 {
257 u8 __iomem *mmio = par->mmio_start_virtual;
258
259 /* interlace */
260 i810_writeb(CR_INDEX_CGA, mmio, CR70);
261 i810_writeb(CR_DATA_CGA, mmio, par->interlace);
262
263 i810_writeb(CR_INDEX_CGA, mmio, CR00);
264 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
265 i810_writeb(CR_INDEX_CGA, mmio, CR01);
266 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
267 i810_writeb(CR_INDEX_CGA, mmio, CR02);
268 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
269 i810_writeb(CR_INDEX_CGA, mmio, CR03);
270 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
271 i810_writeb(CR_INDEX_CGA, mmio, CR04);
272 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
273 i810_writeb(CR_INDEX_CGA, mmio, CR05);
274 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
275 i810_writeb(CR_INDEX_CGA, mmio, CR06);
276 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
277 i810_writeb(CR_INDEX_CGA, mmio, CR09);
278 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
279 i810_writeb(CR_INDEX_CGA, mmio, CR10);
280 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
281 i810_writeb(CR_INDEX_CGA, mmio, CR11);
282 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
283 i810_writeb(CR_INDEX_CGA, mmio, CR12);
284 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
285 i810_writeb(CR_INDEX_CGA, mmio, CR15);
286 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
287 i810_writeb(CR_INDEX_CGA, mmio, CR16);
288 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
289 }
290
291 /**
292 * i810_load_vgax - load extended VGA registers
293 * @par: pointer to i810fb_par structure
294 *
295 * DESCRIPTION:
296 * Load values to extended VGA registers
297 */
298 static void i810_load_vgax(struct i810fb_par *par)
299 {
300 u8 __iomem *mmio = par->mmio_start_virtual;
301
302 i810_writeb(CR_INDEX_CGA, mmio, CR30);
303 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
304 i810_writeb(CR_INDEX_CGA, mmio, CR31);
305 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
306 i810_writeb(CR_INDEX_CGA, mmio, CR32);
307 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
308 i810_writeb(CR_INDEX_CGA, mmio, CR33);
309 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
310 i810_writeb(CR_INDEX_CGA, mmio, CR35);
311 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
312 i810_writeb(CR_INDEX_CGA, mmio, CR39);
313 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
314 }
315
316 /**
317 * i810_load_2d - load grahics registers
318 * @par: pointer to i810fb_par structure
319 *
320 * DESCRIPTION:
321 * Load values to graphics registers
322 */
323 static void i810_load_2d(struct i810fb_par *par)
324 {
325 u32 tmp;
326 u8 tmp8;
327 u8 __iomem *mmio = par->mmio_start_virtual;
328
329 i810_writel(FW_BLC, mmio, par->watermark);
330 tmp = i810_readl(PIXCONF, mmio);
331 tmp |= 1 | 1 << 20;
332 i810_writel(PIXCONF, mmio, tmp);
333
334 i810_writel(OVRACT, mmio, par->ovract);
335
336 i810_writeb(GR_INDEX, mmio, GR10);
337 tmp8 = i810_readb(GR_DATA, mmio);
338 tmp8 |= 2;
339 i810_writeb(GR_INDEX, mmio, GR10);
340 i810_writeb(GR_DATA, mmio, tmp8);
341 }
342
343 /**
344 * i810_hires - enables high resolution mode
345 * @mmio: address of register space
346 */
347 static void i810_hires(u8 __iomem *mmio)
348 {
349 u8 val;
350
351 i810_writeb(CR_INDEX_CGA, mmio, CR80);
352 val = i810_readb(CR_DATA_CGA, mmio);
353 i810_writeb(CR_INDEX_CGA, mmio, CR80);
354 i810_writeb(CR_DATA_CGA, mmio, val | 1);
355 /* Stop LCD displays from flickering */
356 i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4);
357 }
358
359 /**
360 * i810_load_pitch - loads the characters per line of the display
361 * @par: pointer to i810fb_par structure
362 *
363 * DESCRIPTION:
364 * Loads the characters per line
365 */
366 static void i810_load_pitch(struct i810fb_par *par)
367 {
368 u32 tmp, pitch;
369 u8 val;
370 u8 __iomem *mmio = par->mmio_start_virtual;
371
372 pitch = par->pitch >> 3;
373 i810_writeb(SR_INDEX, mmio, SR01);
374 val = i810_readb(SR_DATA, mmio);
375 val &= 0xE0;
376 val |= 1 | 1 << 2;
377 i810_writeb(SR_INDEX, mmio, SR01);
378 i810_writeb(SR_DATA, mmio, val);
379
380 tmp = pitch & 0xFF;
381 i810_writeb(CR_INDEX_CGA, mmio, CR13);
382 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
383
384 tmp = pitch >> 8;
385 i810_writeb(CR_INDEX_CGA, mmio, CR41);
386 val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
387 i810_writeb(CR_INDEX_CGA, mmio, CR41);
388 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
389 }
390
391 /**
392 * i810_load_color - loads the color depth of the display
393 * @par: pointer to i810fb_par structure
394 *
395 * DESCRIPTION:
396 * Loads the color depth of the display and the graphics engine
397 */
398 static void i810_load_color(struct i810fb_par *par)
399 {
400 u8 __iomem *mmio = par->mmio_start_virtual;
401 u32 reg1;
402 u16 reg2;
403
404 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
405 reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
406
407 reg1 |= 0x8000 | par->pixconf;
408 reg2 |= par->bltcntl;
409 i810_writel(PIXCONF, mmio, reg1);
410 i810_writew(BLTCNTL, mmio, reg2);
411 }
412
413 /**
414 * i810_load_regs - loads all registers for the mode
415 * @par: pointer to i810fb_par structure
416 *
417 * DESCRIPTION:
418 * Loads registers
419 */
420 static void i810_load_regs(struct i810fb_par *par)
421 {
422 u8 __iomem *mmio = par->mmio_start_virtual;
423
424 i810_screen_off(mmio, OFF);
425 i810_protect_regs(mmio, OFF);
426 i810_dram_off(mmio, OFF);
427 i810_load_pll(par);
428 i810_load_vga(par);
429 i810_load_vgax(par);
430 i810_dram_off(mmio, ON);
431 i810_load_2d(par);
432 i810_hires(mmio);
433 i810_screen_off(mmio, ON);
434 i810_protect_regs(mmio, ON);
435 i810_load_color(par);
436 i810_load_pitch(par);
437 }
438
439 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
440 u8 __iomem *mmio)
441 {
442 i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
443 i810_writeb(CLUT_DATA, mmio, red);
444 i810_writeb(CLUT_DATA, mmio, green);
445 i810_writeb(CLUT_DATA, mmio, blue);
446 }
447
448 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
449 u8 __iomem *mmio)
450 {
451 i810_writeb(CLUT_INDEX_READ, mmio, regno);
452 *red = i810_readb(CLUT_DATA, mmio);
453 *green = i810_readb(CLUT_DATA, mmio);
454 *blue = i810_readb(CLUT_DATA, mmio);
455 }
456
457 /************************************************************
458 * VGA State Restore *
459 ************************************************************/
460 static void i810_restore_pll(struct i810fb_par *par)
461 {
462 u32 tmp1, tmp2;
463 u8 __iomem *mmio = par->mmio_start_virtual;
464
465 tmp1 = par->hw_state.dclk_2d;
466 tmp2 = i810_readl(DCLK_2D, mmio);
467 tmp1 &= ~MN_MASK;
468 tmp2 &= MN_MASK;
469 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
470
471 tmp1 = par->hw_state.dclk_1d;
472 tmp2 = i810_readl(DCLK_1D, mmio);
473 tmp1 &= ~MN_MASK;
474 tmp2 &= MN_MASK;
475 i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
476
477 i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
478 }
479
480 static void i810_restore_dac(struct i810fb_par *par)
481 {
482 u32 tmp1, tmp2;
483 u8 __iomem *mmio = par->mmio_start_virtual;
484
485 tmp1 = par->hw_state.pixconf;
486 tmp2 = i810_readl(PIXCONF, mmio);
487 tmp1 &= DAC_BIT;
488 tmp2 &= ~DAC_BIT;
489 i810_writel(PIXCONF, mmio, tmp1 | tmp2);
490 }
491
492 static void i810_restore_vgax(struct i810fb_par *par)
493 {
494 u8 i, j;
495 u8 __iomem *mmio = par->mmio_start_virtual;
496
497 for (i = 0; i < 4; i++) {
498 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
499 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
500 }
501 i810_writeb(CR_INDEX_CGA, mmio, CR35);
502 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
503 i810_writeb(CR_INDEX_CGA, mmio, CR39);
504 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
505 i810_writeb(CR_INDEX_CGA, mmio, CR41);
506 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
507
508 /*restore interlace*/
509 i810_writeb(CR_INDEX_CGA, mmio, CR70);
510 i = par->hw_state.cr70;
511 i &= INTERLACE_BIT;
512 j = i810_readb(CR_DATA_CGA, mmio);
513 i810_writeb(CR_INDEX_CGA, mmio, CR70);
514 i810_writeb(CR_DATA_CGA, mmio, j | i);
515
516 i810_writeb(CR_INDEX_CGA, mmio, CR80);
517 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
518 i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
519 i810_writeb(SR_INDEX, mmio, SR01);
520 i = (par->hw_state.sr01) & ~0xE0 ;
521 j = i810_readb(SR_DATA, mmio) & 0xE0;
522 i810_writeb(SR_INDEX, mmio, SR01);
523 i810_writeb(SR_DATA, mmio, i | j);
524 }
525
526 static void i810_restore_vga(struct i810fb_par *par)
527 {
528 u8 i;
529 u8 __iomem *mmio = par->mmio_start_virtual;
530
531 for (i = 0; i < 10; i++) {
532 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
533 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
534 }
535 for (i = 0; i < 8; i++) {
536 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
537 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
538 }
539 }
540
541 static void i810_restore_addr_map(struct i810fb_par *par)
542 {
543 u8 tmp;
544 u8 __iomem *mmio = par->mmio_start_virtual;
545
546 i810_writeb(GR_INDEX, mmio, GR10);
547 tmp = i810_readb(GR_DATA, mmio);
548 tmp &= ADDR_MAP_MASK;
549 tmp |= par->hw_state.gr10;
550 i810_writeb(GR_INDEX, mmio, GR10);
551 i810_writeb(GR_DATA, mmio, tmp);
552 }
553
554 static void i810_restore_2d(struct i810fb_par *par)
555 {
556 u32 tmp_long;
557 u16 tmp_word;
558 u8 __iomem *mmio = par->mmio_start_virtual;
559
560 tmp_word = i810_readw(BLTCNTL, mmio);
561 tmp_word &= ~(3 << 4);
562 tmp_word |= par->hw_state.bltcntl;
563 i810_writew(BLTCNTL, mmio, tmp_word);
564
565 i810_dram_off(mmio, OFF);
566 i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
567 i810_dram_off(mmio, ON);
568
569 tmp_word = i810_readw(HWSTAM, mmio);
570 tmp_word &= 3 << 13;
571 tmp_word |= par->hw_state.hwstam;
572 i810_writew(HWSTAM, mmio, tmp_word);
573
574 tmp_long = i810_readl(FW_BLC, mmio);
575 tmp_long &= FW_BLC_MASK;
576 tmp_long |= par->hw_state.fw_blc;
577 i810_writel(FW_BLC, mmio, tmp_long);
578
579 i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
580 i810_writew(IER, mmio, par->hw_state.ier);
581 i810_writew(IMR, mmio, par->hw_state.imr);
582 i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
583 }
584
585 static void i810_restore_vga_state(struct i810fb_par *par)
586 {
587 u8 __iomem *mmio = par->mmio_start_virtual;
588
589 i810_screen_off(mmio, OFF);
590 i810_protect_regs(mmio, OFF);
591 i810_dram_off(mmio, OFF);
592 i810_restore_pll(par);
593 i810_restore_dac(par);
594 i810_restore_vga(par);
595 i810_restore_vgax(par);
596 i810_restore_addr_map(par);
597 i810_dram_off(mmio, ON);
598 i810_restore_2d(par);
599 i810_screen_off(mmio, ON);
600 i810_protect_regs(mmio, ON);
601 }
602
603 /***********************************************************************
604 * VGA State Save *
605 ***********************************************************************/
606
607 static void i810_save_vgax(struct i810fb_par *par)
608 {
609 u8 i;
610 u8 __iomem *mmio = par->mmio_start_virtual;
611
612 for (i = 0; i < 4; i++) {
613 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
614 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
615 }
616 i810_writeb(CR_INDEX_CGA, mmio, CR35);
617 par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
618 i810_writeb(CR_INDEX_CGA, mmio, CR39);
619 par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
620 i810_writeb(CR_INDEX_CGA, mmio, CR41);
621 par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
622 i810_writeb(CR_INDEX_CGA, mmio, CR70);
623 par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
624 par->hw_state.msr = i810_readb(MSR_READ, mmio);
625 i810_writeb(CR_INDEX_CGA, mmio, CR80);
626 par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
627 i810_writeb(SR_INDEX, mmio, SR01);
628 par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
629 }
630
631 static void i810_save_vga(struct i810fb_par *par)
632 {
633 u8 i;
634 u8 __iomem *mmio = par->mmio_start_virtual;
635
636 for (i = 0; i < 10; i++) {
637 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
638 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
639 }
640 for (i = 0; i < 8; i++) {
641 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
642 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
643 }
644 }
645
646 static void i810_save_2d(struct i810fb_par *par)
647 {
648 u8 __iomem *mmio = par->mmio_start_virtual;
649
650 par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
651 par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
652 par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
653 par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
654 par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
655 par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
656 par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
657 par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
658 par->hw_state.ier = i810_readw(IER, mmio);
659 par->hw_state.imr = i810_readw(IMR, mmio);
660 par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
661 }
662
663 static void i810_save_vga_state(struct i810fb_par *par)
664 {
665 i810_save_vga(par);
666 i810_save_vgax(par);
667 i810_save_2d(par);
668 }
669
670 /************************************************************
671 * Helpers *
672 ************************************************************/
673 /**
674 * get_line_length - calculates buffer pitch in bytes
675 * @par: pointer to i810fb_par structure
676 * @xres_virtual: virtual resolution of the frame
677 * @bpp: bits per pixel
678 *
679 * DESCRIPTION:
680 * Calculates buffer pitch in bytes.
681 */
682 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
683 {
684 u32 length;
685
686 length = xres_virtual*bpp;
687 length = (length+31)&-32;
688 length >>= 3;
689 return length;
690 }
691
692 /**
693 * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
694 * @freq: target pixelclock in picoseconds
695 * @m: where to write M register
696 * @n: where to write N register
697 * @p: where to write P register
698 *
699 * DESCRIPTION:
700 * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
701 * Repeatedly computes the Freq until the actual Freq is equal to
702 * the target Freq or until the loop count is zero. In the latter
703 * case, the actual frequency nearest the target will be used.
704 */
705 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
706 {
707 u32 m_reg, n_reg, p_divisor, n_target_max;
708 u32 m_target, n_target, p_target, n_best, m_best, mod;
709 u32 f_out, target_freq, diff = 0, mod_min, diff_min;
710
711 diff_min = mod_min = 0xFFFFFFFF;
712 n_best = m_best = m_target = f_out = 0;
713
714 target_freq = freq;
715 n_target_max = 30;
716
717 /*
718 * find P such that target freq is 16x reference freq (Hz).
719 */
720 p_divisor = 1;
721 p_target = 0;
722 while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
723 p_divisor <= 32) {
724 p_divisor <<= 1;
725 p_target++;
726 }
727
728 n_reg = m_reg = n_target = 3;
729 while (diff_min && mod_min && (n_target < n_target_max)) {
730 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
731 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
732 m_target = m_reg;
733 n_target = n_reg;
734 if (f_out <= target_freq) {
735 n_reg++;
736 diff = target_freq - f_out;
737 } else {
738 m_reg++;
739 diff = f_out - target_freq;
740 }
741
742 if (diff_min > diff) {
743 diff_min = diff;
744 n_best = n_target;
745 m_best = m_target;
746 }
747
748 if (!diff && mod_min > mod) {
749 mod_min = mod;
750 n_best = n_target;
751 m_best = m_target;
752 }
753 }
754 if (m) *m = (m_best - 2) & 0x3FF;
755 if (n) *n = (n_best - 2) & 0x3FF;
756 if (p) *p = (p_target << 4);
757 }
758
759 /*************************************************************
760 * Hardware Cursor Routines *
761 *************************************************************/
762
763 /**
764 * i810_enable_cursor - show or hide the hardware cursor
765 * @mmio: address of register space
766 * @mode: show (1) or hide (0)
767 *
768 * Description:
769 * Shows or hides the hardware cursor
770 */
771 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
772 {
773 u32 temp;
774
775 temp = i810_readl(PIXCONF, mmio);
776 temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
777 temp & ~CURSOR_ENABLE_MASK;
778
779 i810_writel(PIXCONF, mmio, temp);
780 }
781
782 static void i810_reset_cursor_image(struct i810fb_par *par)
783 {
784 u8 __iomem *addr = par->cursor_heap.virtual;
785 int i, j;
786
787 for (i = 64; i--; ) {
788 for (j = 0; j < 8; j++) {
789 i810_writeb(j, addr, 0xff);
790 i810_writeb(j+8, addr, 0x00);
791 }
792 addr +=16;
793 }
794 }
795
796 static void i810_load_cursor_image(int width, int height, u8 *data,
797 struct i810fb_par *par)
798 {
799 u8 __iomem *addr = par->cursor_heap.virtual;
800 int i, j, w = width/8;
801 int mod = width % 8, t_mask, d_mask;
802
803 t_mask = 0xff >> mod;
804 d_mask = ~(0xff >> mod);
805 for (i = height; i--; ) {
806 for (j = 0; j < w; j++) {
807 i810_writeb(j+0, addr, 0x00);
808 i810_writeb(j+8, addr, *data++);
809 }
810 if (mod) {
811 i810_writeb(j+0, addr, t_mask);
812 i810_writeb(j+8, addr, *data++ & d_mask);
813 }
814 addr += 16;
815 }
816 }
817
818 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
819 {
820 struct i810fb_par *par = info->par;
821 u8 __iomem *mmio = par->mmio_start_virtual;
822 u8 red, green, blue, trans, temp;
823
824 i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
825
826 temp = i810_readb(PIXCONF1, mmio);
827 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
828
829 i810_write_dac(4, red, green, blue, mmio);
830
831 i810_writeb(PIXCONF1, mmio, temp);
832
833 i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
834 temp = i810_readb(PIXCONF1, mmio);
835 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
836
837 i810_write_dac(5, red, green, blue, mmio);
838
839 i810_writeb(PIXCONF1, mmio, temp);
840 }
841
842 /**
843 * i810_init_cursor - initializes the cursor
844 * @par: pointer to i810fb_par structure
845 *
846 * DESCRIPTION:
847 * Initializes the cursor registers
848 */
849 static void i810_init_cursor(struct i810fb_par *par)
850 {
851 u8 __iomem *mmio = par->mmio_start_virtual;
852
853 i810_enable_cursor(mmio, OFF);
854 i810_writel(CURBASE, mmio, par->cursor_heap.physical);
855 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
856 }
857
858 /*********************************************************************
859 * Framebuffer hook helpers *
860 *********************************************************************/
861 /**
862 * i810_round_off - Round off values to capability of hardware
863 * @var: pointer to fb_var_screeninfo structure
864 *
865 * DESCRIPTION:
866 * @var contains user-defined information for the mode to be set.
867 * This will try modify those values to ones nearest the
868 * capability of the hardware
869 */
870 static void i810_round_off(struct fb_var_screeninfo *var)
871 {
872 u32 xres, yres, vxres, vyres;
873
874 /*
875 * Presently supports only these configurations
876 */
877
878 xres = var->xres;
879 yres = var->yres;
880 vxres = var->xres_virtual;
881 vyres = var->yres_virtual;
882
883 var->bits_per_pixel += 7;
884 var->bits_per_pixel &= ~7;
885
886 if (var->bits_per_pixel < 8)
887 var->bits_per_pixel = 8;
888 if (var->bits_per_pixel > 32)
889 var->bits_per_pixel = 32;
890
891 round_off_xres(&xres);
892 if (xres < 40)
893 xres = 40;
894 if (xres > 2048)
895 xres = 2048;
896 xres = (xres + 7) & ~7;
897
898 if (vxres < xres)
899 vxres = xres;
900
901 round_off_yres(&xres, &yres);
902 if (yres < 1)
903 yres = 1;
904 if (yres >= 2048)
905 yres = 2048;
906
907 if (vyres < yres)
908 vyres = yres;
909
910 if (var->bits_per_pixel == 32)
911 var->accel_flags = 0;
912
913 /* round of horizontal timings to nearest 8 pixels */
914 var->left_margin = (var->left_margin + 4) & ~7;
915 var->right_margin = (var->right_margin + 4) & ~7;
916 var->hsync_len = (var->hsync_len + 4) & ~7;
917
918 if (var->vmode & FB_VMODE_INTERLACED) {
919 if (!((yres + var->upper_margin + var->vsync_len +
920 var->lower_margin) & 1))
921 var->upper_margin++;
922 }
923
924 var->xres = xres;
925 var->yres = yres;
926 var->xres_virtual = vxres;
927 var->yres_virtual = vyres;
928 }
929
930 /**
931 * set_color_bitfields - sets rgba fields
932 * @var: pointer to fb_var_screeninfo
933 *
934 * DESCRIPTION:
935 * The length, offset and ordering for each color field
936 * (red, green, blue) will be set as specified
937 * by the hardware
938 */
939 static void set_color_bitfields(struct fb_var_screeninfo *var)
940 {
941 switch (var->bits_per_pixel) {
942 case 8:
943 var->red.offset = 0;
944 var->red.length = 8;
945 var->green.offset = 0;
946 var->green.length = 8;
947 var->blue.offset = 0;
948 var->blue.length = 8;
949 var->transp.offset = 0;
950 var->transp.length = 0;
951 break;
952 case 16:
953 var->green.length = (var->green.length == 5) ? 5 : 6;
954 var->red.length = 5;
955 var->blue.length = 5;
956 var->transp.length = 6 - var->green.length;
957 var->blue.offset = 0;
958 var->green.offset = 5;
959 var->red.offset = 5 + var->green.length;
960 var->transp.offset = (5 + var->red.offset) & 15;
961 break;
962 case 24: /* RGB 888 */
963 case 32: /* RGBA 8888 */
964 var->red.offset = 16;
965 var->red.length = 8;
966 var->green.offset = 8;
967 var->green.length = 8;
968 var->blue.offset = 0;
969 var->blue.length = 8;
970 var->transp.length = var->bits_per_pixel - 24;
971 var->transp.offset = (var->transp.length) ? 24 : 0;
972 break;
973 }
974 var->red.msb_right = 0;
975 var->green.msb_right = 0;
976 var->blue.msb_right = 0;
977 var->transp.msb_right = 0;
978 }
979
980 /**
981 * i810_check_params - check if contents in var are valid
982 * @var: pointer to fb_var_screeninfo
983 * @info: pointer to fb_info
984 *
985 * DESCRIPTION:
986 * This will check if the framebuffer size is sufficient
987 * for the current mode and if the user's monitor has the
988 * required specifications to display the current mode.
989 */
990 static int i810_check_params(struct fb_var_screeninfo *var,
991 struct fb_info *info)
992 {
993 struct i810fb_par *par = info->par;
994 int line_length, vidmem, mode_valid = 0, retval = 0;
995 u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
996
997 /*
998 * Memory limit
999 */
1000 line_length = get_line_length(par, vxres, var->bits_per_pixel);
1001 vidmem = line_length*vyres;
1002
1003 if (vidmem > par->fb.size) {
1004 vyres = par->fb.size/line_length;
1005 if (vyres < var->yres) {
1006 vyres = info->var.yres;
1007 vxres = par->fb.size/vyres;
1008 vxres /= var->bits_per_pixel >> 3;
1009 line_length = get_line_length(par, vxres,
1010 var->bits_per_pixel);
1011 vidmem = line_length * info->var.yres;
1012 if (vxres < var->xres) {
1013 printk("i810fb: required video memory, "
1014 "%d bytes, for %dx%d-%d (virtual) "
1015 "is out of range\n",
1016 vidmem, vxres, vyres,
1017 var->bits_per_pixel);
1018 return -ENOMEM;
1019 }
1020 }
1021 }
1022
1023 var->xres_virtual = vxres;
1024 var->yres_virtual = vyres;
1025
1026 /*
1027 * Monitor limit
1028 */
1029 switch (var->bits_per_pixel) {
1030 case 8:
1031 info->monspecs.dclkmax = 234000000;
1032 break;
1033 case 16:
1034 info->monspecs.dclkmax = 229000000;
1035 break;
1036 case 24:
1037 case 32:
1038 info->monspecs.dclkmax = 204000000;
1039 break;
1040 }
1041
1042 info->monspecs.dclkmin = 15000000;
1043
1044 if (!fb_validate_mode(var, info))
1045 mode_valid = 1;
1046
1047 #ifdef CONFIG_FB_I810_I2C
1048 if (!mode_valid && info->monspecs.gtf &&
1049 !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1050 mode_valid = 1;
1051
1052 if (!mode_valid && info->monspecs.modedb_len) {
1053 const struct fb_videomode *mode;
1054
1055 mode = fb_find_best_mode(var, &info->modelist);
1056 if (mode) {
1057 fb_videomode_to_var(var, mode);
1058 mode_valid = 1;
1059 }
1060 }
1061 #endif
1062 if (!mode_valid && info->monspecs.modedb_len == 0) {
1063 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1064 int default_sync = (info->monspecs.hfmin-HFMIN)
1065 |(info->monspecs.hfmax-HFMAX)
1066 |(info->monspecs.vfmin-VFMIN)
1067 |(info->monspecs.vfmax-VFMAX);
1068 printk("i810fb: invalid video mode%s\n",
1069 default_sync ? "" : ". Specifying "
1070 "vsyncN/hsyncN parameters may help");
1071 retval = -EINVAL;
1072 }
1073 }
1074
1075 return retval;
1076 }
1077
1078 /**
1079 * encode_fix - fill up fb_fix_screeninfo structure
1080 * @fix: pointer to fb_fix_screeninfo
1081 * @info: pointer to fb_info
1082 *
1083 * DESCRIPTION:
1084 * This will set up parameters that are unmodifiable by the user.
1085 */
1086 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1087 {
1088 struct i810fb_par *par = info->par;
1089
1090 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1091
1092 strcpy(fix->id, "I810");
1093 fix->smem_start = par->fb.physical;
1094 fix->smem_len = par->fb.size;
1095 fix->type = FB_TYPE_PACKED_PIXELS;
1096 fix->type_aux = 0;
1097 fix->xpanstep = 8;
1098 fix->ypanstep = 1;
1099
1100 switch (info->var.bits_per_pixel) {
1101 case 8:
1102 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1103 break;
1104 case 16:
1105 case 24:
1106 case 32:
1107 if (info->var.nonstd)
1108 fix->visual = FB_VISUAL_DIRECTCOLOR;
1109 else
1110 fix->visual = FB_VISUAL_TRUECOLOR;
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115 fix->ywrapstep = 0;
1116 fix->line_length = par->pitch;
1117 fix->mmio_start = par->mmio_start_phys;
1118 fix->mmio_len = MMIO_SIZE;
1119 fix->accel = FB_ACCEL_I810;
1120
1121 return 0;
1122 }
1123
1124 /**
1125 * decode_var - modify par according to contents of var
1126 * @var: pointer to fb_var_screeninfo
1127 * @par: pointer to i810fb_par
1128 *
1129 * DESCRIPTION:
1130 * Based on the contents of @var, @par will be dynamically filled up.
1131 * @par contains all information necessary to modify the hardware.
1132 */
1133 static void decode_var(const struct fb_var_screeninfo *var,
1134 struct i810fb_par *par)
1135 {
1136 u32 xres, yres, vxres, vyres;
1137
1138 xres = var->xres;
1139 yres = var->yres;
1140 vxres = var->xres_virtual;
1141 vyres = var->yres_virtual;
1142
1143 switch (var->bits_per_pixel) {
1144 case 8:
1145 par->pixconf = PIXCONF8;
1146 par->bltcntl = 0;
1147 par->depth = 1;
1148 par->blit_bpp = BPP8;
1149 break;
1150 case 16:
1151 if (var->green.length == 5)
1152 par->pixconf = PIXCONF15;
1153 else
1154 par->pixconf = PIXCONF16;
1155 par->bltcntl = 16;
1156 par->depth = 2;
1157 par->blit_bpp = BPP16;
1158 break;
1159 case 24:
1160 par->pixconf = PIXCONF24;
1161 par->bltcntl = 32;
1162 par->depth = 3;
1163 par->blit_bpp = BPP24;
1164 break;
1165 case 32:
1166 par->pixconf = PIXCONF32;
1167 par->bltcntl = 0;
1168 par->depth = 4;
1169 par->blit_bpp = 3 << 24;
1170 break;
1171 }
1172 if (var->nonstd && var->bits_per_pixel != 8)
1173 par->pixconf |= 1 << 27;
1174
1175 i810_calc_dclk(var->pixclock, &par->regs.M,
1176 &par->regs.N, &par->regs.P);
1177 i810fb_encode_registers(var, par, xres, yres);
1178
1179 par->watermark = i810_get_watermark(var, par);
1180 par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1181 }
1182
1183 /**
1184 * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1185 * @regno: DAC index
1186 * @red: red
1187 * @green: green
1188 * @blue: blue
1189 * @transp: transparency (alpha)
1190 * @info: pointer to fb_info
1191 *
1192 * DESCRIPTION:
1193 * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1194 * and writes them to @red, @green and @blue respectively
1195 */
1196 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1197 u8 *transp, struct fb_info *info)
1198 {
1199 struct i810fb_par *par = info->par;
1200 u8 __iomem *mmio = par->mmio_start_virtual;
1201 u8 temp;
1202
1203 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1204 if ((info->var.green.length == 5 && regno > 31) ||
1205 (info->var.green.length == 6 && regno > 63))
1206 return 1;
1207 }
1208
1209 temp = i810_readb(PIXCONF1, mmio);
1210 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1211
1212 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1213 info->var.green.length == 5)
1214 i810_read_dac(regno * 8, red, green, blue, mmio);
1215
1216 else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1217 info->var.green.length == 6) {
1218 u8 tmp;
1219
1220 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1221 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1222 }
1223 else
1224 i810_read_dac(regno, red, green, blue, mmio);
1225
1226 *transp = 0;
1227 i810_writeb(PIXCONF1, mmio, temp);
1228
1229 return 0;
1230 }
1231
1232 /******************************************************************
1233 * Framebuffer device-specific hooks *
1234 ******************************************************************/
1235
1236 static int i810fb_open(struct fb_info *info, int user)
1237 {
1238 struct i810fb_par *par = info->par;
1239
1240 mutex_lock(&par->open_lock);
1241 if (par->use_count == 0) {
1242 memset(&par->state, 0, sizeof(struct vgastate));
1243 par->state.flags = VGA_SAVE_CMAP;
1244 par->state.vgabase = par->mmio_start_virtual;
1245 save_vga(&par->state);
1246
1247 i810_save_vga_state(par);
1248 }
1249
1250 par->use_count++;
1251 mutex_unlock(&par->open_lock);
1252
1253 return 0;
1254 }
1255
1256 static int i810fb_release(struct fb_info *info, int user)
1257 {
1258 struct i810fb_par *par = info->par;
1259
1260 mutex_lock(&par->open_lock);
1261 if (par->use_count == 0) {
1262 mutex_unlock(&par->open_lock);
1263 return -EINVAL;
1264 }
1265
1266 if (par->use_count == 1) {
1267 i810_restore_vga_state(par);
1268 restore_vga(&par->state);
1269 }
1270
1271 par->use_count--;
1272 mutex_unlock(&par->open_lock);
1273
1274 return 0;
1275 }
1276
1277
1278 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1279 unsigned blue, unsigned transp,
1280 struct fb_info *info)
1281 {
1282 struct i810fb_par *par = info->par;
1283 u8 __iomem *mmio = par->mmio_start_virtual;
1284 u8 temp;
1285 int i;
1286
1287 if (regno > 255) return 1;
1288
1289 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1290 if ((info->var.green.length == 5 && regno > 31) ||
1291 (info->var.green.length == 6 && regno > 63))
1292 return 1;
1293 }
1294
1295 if (info->var.grayscale)
1296 red = green = blue = (19595 * red + 38470 * green +
1297 7471 * blue) >> 16;
1298
1299 temp = i810_readb(PIXCONF1, mmio);
1300 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1301
1302 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1303 info->var.green.length == 5) {
1304 for (i = 0; i < 8; i++)
1305 i810_write_dac((u8) (regno * 8) + i, (u8) red,
1306 (u8) green, (u8) blue, mmio);
1307 } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1308 info->var.green.length == 6) {
1309 u8 r, g, b;
1310
1311 if (regno < 32) {
1312 for (i = 0; i < 8; i++)
1313 i810_write_dac((u8) (regno * 8) + i,
1314 (u8) red, (u8) green,
1315 (u8) blue, mmio);
1316 }
1317 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1318 for (i = 0; i < 4; i++)
1319 i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1320 b, mmio);
1321 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1322 i810_write_dac((u8) regno, (u8) red, (u8) green,
1323 (u8) blue, mmio);
1324 }
1325
1326 i810_writeb(PIXCONF1, mmio, temp);
1327
1328 if (regno < 16) {
1329 switch (info->var.bits_per_pixel) {
1330 case 16:
1331 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1332 if (info->var.green.length == 5)
1333 ((u32 *)info->pseudo_palette)[regno] =
1334 (regno << 10) | (regno << 5) |
1335 regno;
1336 else
1337 ((u32 *)info->pseudo_palette)[regno] =
1338 (regno << 11) | (regno << 5) |
1339 regno;
1340 } else {
1341 if (info->var.green.length == 5) {
1342 /* RGB 555 */
1343 ((u32 *)info->pseudo_palette)[regno] =
1344 ((red & 0xf800) >> 1) |
1345 ((green & 0xf800) >> 6) |
1346 ((blue & 0xf800) >> 11);
1347 } else {
1348 /* RGB 565 */
1349 ((u32 *)info->pseudo_palette)[regno] =
1350 (red & 0xf800) |
1351 ((green & 0xf800) >> 5) |
1352 ((blue & 0xf800) >> 11);
1353 }
1354 }
1355 break;
1356 case 24: /* RGB 888 */
1357 case 32: /* RGBA 8888 */
1358 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1359 ((u32 *)info->pseudo_palette)[regno] =
1360 (regno << 16) | (regno << 8) |
1361 regno;
1362 else
1363 ((u32 *)info->pseudo_palette)[regno] =
1364 ((red & 0xff00) << 8) |
1365 (green & 0xff00) |
1366 ((blue & 0xff00) >> 8);
1367 break;
1368 }
1369 }
1370 return 0;
1371 }
1372
1373 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1374 struct fb_info *info)
1375 {
1376 struct i810fb_par *par = info->par;
1377 u32 total;
1378
1379 total = var->xoffset * par->depth +
1380 var->yoffset * info->fix.line_length;
1381 i810fb_load_front(total, info);
1382
1383 return 0;
1384 }
1385
1386 static int i810fb_blank (int blank_mode, struct fb_info *info)
1387 {
1388 struct i810fb_par *par = info->par;
1389 u8 __iomem *mmio = par->mmio_start_virtual;
1390 int mode = 0, pwr, scr_off = 0;
1391
1392 pwr = i810_readl(PWR_CLKC, mmio);
1393
1394 switch (blank_mode) {
1395 case FB_BLANK_UNBLANK:
1396 mode = POWERON;
1397 pwr |= 1;
1398 scr_off = ON;
1399 break;
1400 case FB_BLANK_NORMAL:
1401 mode = POWERON;
1402 pwr |= 1;
1403 scr_off = OFF;
1404 break;
1405 case FB_BLANK_VSYNC_SUSPEND:
1406 mode = STANDBY;
1407 pwr |= 1;
1408 scr_off = OFF;
1409 break;
1410 case FB_BLANK_HSYNC_SUSPEND:
1411 mode = SUSPEND;
1412 pwr |= 1;
1413 scr_off = OFF;
1414 break;
1415 case FB_BLANK_POWERDOWN:
1416 mode = POWERDOWN;
1417 pwr &= ~1;
1418 scr_off = OFF;
1419 break;
1420 default:
1421 return -EINVAL;
1422 }
1423
1424 i810_screen_off(mmio, scr_off);
1425 i810_writel(HVSYNC, mmio, mode);
1426 i810_writel(PWR_CLKC, mmio, pwr);
1427
1428 return 0;
1429 }
1430
1431 static int i810fb_set_par(struct fb_info *info)
1432 {
1433 struct i810fb_par *par = info->par;
1434
1435 decode_var(&info->var, par);
1436 i810_load_regs(par);
1437 i810_init_cursor(par);
1438 encode_fix(&info->fix, info);
1439
1440 if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1441 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1442 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1443 FBINFO_HWACCEL_IMAGEBLIT;
1444 info->pixmap.scan_align = 2;
1445 } else {
1446 info->pixmap.scan_align = 1;
1447 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1448 }
1449 return 0;
1450 }
1451
1452 static int i810fb_check_var(struct fb_var_screeninfo *var,
1453 struct fb_info *info)
1454 {
1455 int err;
1456
1457 if (IS_DVT) {
1458 var->vmode &= ~FB_VMODE_MASK;
1459 var->vmode |= FB_VMODE_NONINTERLACED;
1460 }
1461 if (var->vmode & FB_VMODE_DOUBLE) {
1462 var->vmode &= ~FB_VMODE_MASK;
1463 var->vmode |= FB_VMODE_NONINTERLACED;
1464 }
1465
1466 i810_round_off(var);
1467 if ((err = i810_check_params(var, info)))
1468 return err;
1469
1470 i810fb_fill_var_timings(var);
1471 set_color_bitfields(var);
1472 return 0;
1473 }
1474
1475 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1476 {
1477 struct i810fb_par *par = info->par;
1478 u8 __iomem *mmio = par->mmio_start_virtual;
1479
1480 if (par->dev_flags & LOCKUP)
1481 return -ENXIO;
1482
1483 if (cursor->image.width > 64 || cursor->image.height > 64)
1484 return -ENXIO;
1485
1486 if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1487 i810_init_cursor(par);
1488 cursor->set |= FB_CUR_SETALL;
1489 }
1490
1491 i810_enable_cursor(mmio, OFF);
1492
1493 if (cursor->set & FB_CUR_SETPOS) {
1494 u32 tmp;
1495
1496 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1497 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1498 i810_writel(CURPOS, mmio, tmp);
1499 }
1500
1501 if (cursor->set & FB_CUR_SETSIZE)
1502 i810_reset_cursor_image(par);
1503
1504 if (cursor->set & FB_CUR_SETCMAP)
1505 i810_load_cursor_colors(cursor->image.fg_color,
1506 cursor->image.bg_color,
1507 info);
1508
1509 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1510 int size = ((cursor->image.width + 7) >> 3) *
1511 cursor->image.height;
1512 int i;
1513 u8 *data = kmalloc(64 * 8, GFP_ATOMIC);
1514
1515 if (data == NULL)
1516 return -ENOMEM;
1517
1518 switch (cursor->rop) {
1519 case ROP_XOR:
1520 for (i = 0; i < size; i++)
1521 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1522 break;
1523 case ROP_COPY:
1524 default:
1525 for (i = 0; i < size; i++)
1526 data[i] = cursor->image.data[i] & cursor->mask[i];
1527 break;
1528 }
1529
1530 i810_load_cursor_image(cursor->image.width,
1531 cursor->image.height, data,
1532 par);
1533 kfree(data);
1534 }
1535
1536 if (cursor->enable)
1537 i810_enable_cursor(mmio, ON);
1538
1539 return 0;
1540 }
1541
1542 static struct fb_ops i810fb_ops __devinitdata = {
1543 .owner = THIS_MODULE,
1544 .fb_open = i810fb_open,
1545 .fb_release = i810fb_release,
1546 .fb_check_var = i810fb_check_var,
1547 .fb_set_par = i810fb_set_par,
1548 .fb_setcolreg = i810fb_setcolreg,
1549 .fb_blank = i810fb_blank,
1550 .fb_pan_display = i810fb_pan_display,
1551 .fb_fillrect = i810fb_fillrect,
1552 .fb_copyarea = i810fb_copyarea,
1553 .fb_imageblit = i810fb_imageblit,
1554 .fb_cursor = i810fb_cursor,
1555 .fb_sync = i810fb_sync,
1556 };
1557
1558 /***********************************************************************
1559 * Power Management *
1560 ***********************************************************************/
1561 static int i810fb_suspend(struct pci_dev *dev, pm_message_t mesg)
1562 {
1563 struct fb_info *info = pci_get_drvdata(dev);
1564 struct i810fb_par *par = info->par;
1565
1566 par->cur_state = mesg.event;
1567
1568 switch (mesg.event) {
1569 case PM_EVENT_FREEZE:
1570 case PM_EVENT_PRETHAW:
1571 dev->dev.power.power_state = mesg;
1572 return 0;
1573 }
1574
1575 acquire_console_sem();
1576 fb_set_suspend(info, 1);
1577
1578 if (info->fbops->fb_sync)
1579 info->fbops->fb_sync(info);
1580
1581 i810fb_blank(FB_BLANK_POWERDOWN, info);
1582 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1583 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1584
1585 pci_save_state(dev);
1586 pci_disable_device(dev);
1587 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1588 release_console_sem();
1589
1590 return 0;
1591 }
1592
1593 static int i810fb_resume(struct pci_dev *dev)
1594 {
1595 struct fb_info *info = pci_get_drvdata(dev);
1596 struct i810fb_par *par = info->par;
1597 int cur_state = par->cur_state;
1598
1599 par->cur_state = PM_EVENT_ON;
1600
1601 if (cur_state == PM_EVENT_FREEZE) {
1602 pci_set_power_state(dev, PCI_D0);
1603 return 0;
1604 }
1605
1606 acquire_console_sem();
1607 pci_set_power_state(dev, PCI_D0);
1608 pci_restore_state(dev);
1609
1610 if (pci_enable_device(dev))
1611 goto fail;
1612
1613 pci_set_master(dev);
1614 agp_bind_memory(par->i810_gtt.i810_fb_memory,
1615 par->fb.offset);
1616 agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1617 par->cursor_heap.offset);
1618 i810fb_set_par(info);
1619 fb_set_suspend (info, 0);
1620 info->fbops->fb_blank(VESA_NO_BLANKING, info);
1621 fail:
1622 release_console_sem();
1623 return 0;
1624 }
1625 /***********************************************************************
1626 * AGP resource allocation *
1627 ***********************************************************************/
1628
1629 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1630 {
1631 par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1632 par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1633 par->iring.physical = par->aperture.physical +
1634 (par->iring.offset << 12);
1635 par->iring.virtual = par->aperture.virtual +
1636 (par->iring.offset << 12);
1637 par->cursor_heap.virtual = par->aperture.virtual+
1638 (par->cursor_heap.offset << 12);
1639 }
1640
1641 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1642 {
1643 if (vram + 1 > par->aperture.size >> 20)
1644 vram = (par->aperture.size >> 20) - 1;
1645 if (v_offset_default > (par->aperture.size >> 20))
1646 v_offset_default = (par->aperture.size >> 20);
1647 if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1648 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1649
1650 par->fb.size = vram << 20;
1651 par->fb.offset = v_offset_default << 20;
1652 par->fb.offset >>= 12;
1653
1654 par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1655 par->iring.size = RINGBUFFER_SIZE;
1656
1657 par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1658 par->cursor_heap.size = 4096;
1659 }
1660
1661 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1662 {
1663 struct i810fb_par *par = info->par;
1664 int size;
1665 struct agp_bridge_data *bridge;
1666
1667 i810_fix_offsets(par);
1668 size = par->fb.size + par->iring.size;
1669
1670 if (!(bridge = agp_backend_acquire(par->dev))) {
1671 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1672 return -ENODEV;
1673 }
1674 if (!(par->i810_gtt.i810_fb_memory =
1675 agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1676 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1677 "memory\n");
1678 agp_backend_release(bridge);
1679 return -ENOMEM;
1680 }
1681 if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1682 par->fb.offset)) {
1683 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1684 agp_backend_release(bridge);
1685 return -EBUSY;
1686 }
1687
1688 if (!(par->i810_gtt.i810_cursor_memory =
1689 agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1690 AGP_PHYSICAL_MEMORY))) {
1691 printk("i810fb_alloc_cursormem: can't allocate"
1692 "cursor memory\n");
1693 agp_backend_release(bridge);
1694 return -ENOMEM;
1695 }
1696 if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1697 par->cursor_heap.offset)) {
1698 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1699 agp_backend_release(bridge);
1700 return -EBUSY;
1701 }
1702
1703 par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1704
1705 i810_fix_pointers(par);
1706
1707 agp_backend_release(bridge);
1708
1709 return 0;
1710 }
1711
1712 /***************************************************************
1713 * Initialization *
1714 ***************************************************************/
1715
1716 /**
1717 * i810_init_monspecs
1718 * @info: pointer to device specific info structure
1719 *
1720 * DESCRIPTION:
1721 * Sets the user monitor's horizontal and vertical
1722 * frequency limits
1723 */
1724 static void __devinit i810_init_monspecs(struct fb_info *info)
1725 {
1726 if (!hsync1)
1727 hsync1 = HFMIN;
1728 if (!hsync2)
1729 hsync2 = HFMAX;
1730 if (!info->monspecs.hfmax)
1731 info->monspecs.hfmax = hsync2;
1732 if (!info->monspecs.hfmin)
1733 info->monspecs.hfmin = hsync1;
1734 if (hsync2 < hsync1)
1735 info->monspecs.hfmin = hsync2;
1736
1737 if (!vsync1)
1738 vsync1 = VFMIN;
1739 if (!vsync2)
1740 vsync2 = VFMAX;
1741 if (IS_DVT && vsync1 < 60)
1742 vsync1 = 60;
1743 if (!info->monspecs.vfmax)
1744 info->monspecs.vfmax = vsync2;
1745 if (!info->monspecs.vfmin)
1746 info->monspecs.vfmin = vsync1;
1747 if (vsync2 < vsync1)
1748 info->monspecs.vfmin = vsync2;
1749 }
1750
1751 /**
1752 * i810_init_defaults - initializes default values to use
1753 * @par: pointer to i810fb_par structure
1754 * @info: pointer to current fb_info structure
1755 */
1756 static void __devinit i810_init_defaults(struct i810fb_par *par,
1757 struct fb_info *info)
1758 {
1759 mutex_init(&par->open_lock);
1760
1761 if (voffset)
1762 v_offset_default = voffset;
1763 else if (par->aperture.size > 32 * 1024 * 1024)
1764 v_offset_default = 16;
1765 else
1766 v_offset_default = 8;
1767
1768 if (!vram)
1769 vram = 1;
1770
1771 if (accel)
1772 par->dev_flags |= HAS_ACCELERATION;
1773
1774 if (sync)
1775 par->dev_flags |= ALWAYS_SYNC;
1776
1777 par->ddc_num = ddc3;
1778
1779 if (bpp < 8)
1780 bpp = 8;
1781
1782 par->i810fb_ops = i810fb_ops;
1783
1784 if (xres)
1785 info->var.xres = xres;
1786 else
1787 info->var.xres = 640;
1788
1789 if (yres)
1790 info->var.yres = yres;
1791 else
1792 info->var.yres = 480;
1793
1794 if (!vyres)
1795 vyres = (vram << 20)/(info->var.xres*bpp >> 3);
1796
1797 info->var.yres_virtual = vyres;
1798 info->var.bits_per_pixel = bpp;
1799
1800 if (dcolor)
1801 info->var.nonstd = 1;
1802
1803 if (par->dev_flags & HAS_ACCELERATION)
1804 info->var.accel_flags = 1;
1805
1806 i810_init_monspecs(info);
1807 }
1808
1809 /**
1810 * i810_init_device - initialize device
1811 * @par: pointer to i810fb_par structure
1812 */
1813 static void __devinit i810_init_device(struct i810fb_par *par)
1814 {
1815 u8 reg;
1816 u8 __iomem *mmio = par->mmio_start_virtual;
1817
1818 if (mtrr) set_mtrr(par);
1819
1820 i810_init_cursor(par);
1821
1822 /* mvo: enable external vga-connector (for laptops) */
1823 if (extvga) {
1824 i810_writel(HVSYNC, mmio, 0);
1825 i810_writel(PWR_CLKC, mmio, 3);
1826 }
1827
1828 pci_read_config_byte(par->dev, 0x50, &reg);
1829 reg &= FREQ_MASK;
1830 par->mem_freq = (reg) ? 133 : 100;
1831
1832 }
1833
1834 static int __devinit
1835 i810_allocate_pci_resource(struct i810fb_par *par,
1836 const struct pci_device_id *entry)
1837 {
1838 int err;
1839
1840 if ((err = pci_enable_device(par->dev))) {
1841 printk("i810fb_init: cannot enable device\n");
1842 return err;
1843 }
1844 par->res_flags |= PCI_DEVICE_ENABLED;
1845
1846 if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1847 par->aperture.physical = pci_resource_start(par->dev, 0);
1848 par->aperture.size = pci_resource_len(par->dev, 0);
1849 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1850 } else {
1851 par->aperture.physical = pci_resource_start(par->dev, 1);
1852 par->aperture.size = pci_resource_len(par->dev, 1);
1853 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1854 }
1855 if (!par->aperture.size) {
1856 printk("i810fb_init: device is disabled\n");
1857 return -ENOMEM;
1858 }
1859
1860 if (!request_mem_region(par->aperture.physical,
1861 par->aperture.size,
1862 i810_pci_list[entry->driver_data])) {
1863 printk("i810fb_init: cannot request framebuffer region\n");
1864 return -ENODEV;
1865 }
1866 par->res_flags |= FRAMEBUFFER_REQ;
1867
1868 par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1869 par->aperture.size);
1870 if (!par->aperture.virtual) {
1871 printk("i810fb_init: cannot remap framebuffer region\n");
1872 return -ENODEV;
1873 }
1874
1875 if (!request_mem_region(par->mmio_start_phys,
1876 MMIO_SIZE,
1877 i810_pci_list[entry->driver_data])) {
1878 printk("i810fb_init: cannot request mmio region\n");
1879 return -ENODEV;
1880 }
1881 par->res_flags |= MMIO_REQ;
1882
1883 par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1884 MMIO_SIZE);
1885 if (!par->mmio_start_virtual) {
1886 printk("i810fb_init: cannot remap mmio region\n");
1887 return -ENODEV;
1888 }
1889
1890 return 0;
1891 }
1892
1893 static void __devinit i810fb_find_init_mode(struct fb_info *info)
1894 {
1895 struct fb_videomode mode;
1896 struct fb_var_screeninfo var;
1897 struct fb_monspecs *specs = &info->monspecs;
1898 int found = 0;
1899 #ifdef CONFIG_FB_I810_I2C
1900 int i;
1901 int err = 1;
1902 struct i810fb_par *par = info->par;
1903 #endif
1904
1905 INIT_LIST_HEAD(&info->modelist);
1906 memset(&mode, 0, sizeof(struct fb_videomode));
1907 var = info->var;
1908 #ifdef CONFIG_FB_I810_I2C
1909 i810_create_i2c_busses(par);
1910
1911 for (i = 0; i < par->ddc_num + 1; i++) {
1912 err = i810_probe_i2c_connector(info, &par->edid, i);
1913 if (!err)
1914 break;
1915 }
1916
1917 if (!err)
1918 printk("i810fb_init_pci: DDC probe successful\n");
1919
1920 fb_edid_to_monspecs(par->edid, specs);
1921
1922 if (specs->modedb == NULL)
1923 printk("i810fb_init_pci: Unable to get Mode Database\n");
1924
1925 fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
1926 &info->modelist);
1927 if (specs->modedb != NULL) {
1928 const struct fb_videomode *m;
1929
1930 if (xres && yres) {
1931 if ((m = fb_find_best_mode(&var, &info->modelist))) {
1932 mode = *m;
1933 found = 1;
1934 }
1935 }
1936
1937 if (!found) {
1938 m = fb_find_best_display(&info->monspecs, &info->modelist);
1939 mode = *m;
1940 found = 1;
1941 }
1942
1943 fb_videomode_to_var(&var, &mode);
1944 }
1945 #endif
1946 if (mode_option)
1947 fb_find_mode(&var, info, mode_option, specs->modedb,
1948 specs->modedb_len, (found) ? &mode : NULL,
1949 info->var.bits_per_pixel);
1950
1951 info->var = var;
1952 fb_destroy_modedb(specs->modedb);
1953 specs->modedb = NULL;
1954 }
1955
1956 #ifndef MODULE
1957 static int __devinit i810fb_setup(char *options)
1958 {
1959 char *this_opt, *suffix = NULL;
1960
1961 if (!options || !*options)
1962 return 0;
1963
1964 while ((this_opt = strsep(&options, ",")) != NULL) {
1965 if (!strncmp(this_opt, "mtrr", 4))
1966 mtrr = 1;
1967 else if (!strncmp(this_opt, "accel", 5))
1968 accel = 1;
1969 else if (!strncmp(this_opt, "extvga", 6))
1970 extvga = 1;
1971 else if (!strncmp(this_opt, "sync", 4))
1972 sync = 1;
1973 else if (!strncmp(this_opt, "vram:", 5))
1974 vram = (simple_strtoul(this_opt+5, NULL, 0));
1975 else if (!strncmp(this_opt, "voffset:", 8))
1976 voffset = (simple_strtoul(this_opt+8, NULL, 0));
1977 else if (!strncmp(this_opt, "xres:", 5))
1978 xres = simple_strtoul(this_opt+5, NULL, 0);
1979 else if (!strncmp(this_opt, "yres:", 5))
1980 yres = simple_strtoul(this_opt+5, NULL, 0);
1981 else if (!strncmp(this_opt, "vyres:", 6))
1982 vyres = simple_strtoul(this_opt+6, NULL, 0);
1983 else if (!strncmp(this_opt, "bpp:", 4))
1984 bpp = simple_strtoul(this_opt+4, NULL, 0);
1985 else if (!strncmp(this_opt, "hsync1:", 7)) {
1986 hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1987 if (strncmp(suffix, "H", 1))
1988 hsync1 *= 1000;
1989 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1990 hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1991 if (strncmp(suffix, "H", 1))
1992 hsync2 *= 1000;
1993 } else if (!strncmp(this_opt, "vsync1:", 7))
1994 vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1995 else if (!strncmp(this_opt, "vsync2:", 7))
1996 vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1997 else if (!strncmp(this_opt, "dcolor", 6))
1998 dcolor = 1;
1999 else if (!strncmp(this_opt, "ddc3", 4))
2000 ddc3 = 3;
2001 else
2002 mode_option = this_opt;
2003 }
2004 return 0;
2005 }
2006 #endif
2007
2008 static int __devinit i810fb_init_pci (struct pci_dev *dev,
2009 const struct pci_device_id *entry)
2010 {
2011 struct fb_info *info;
2012 struct i810fb_par *par = NULL;
2013 struct fb_videomode mode;
2014 int i, err = -1, vfreq, hfreq, pixclock;
2015
2016 i = 0;
2017
2018 info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
2019 if (!info)
2020 return -ENOMEM;
2021
2022 par = info->par;
2023 par->dev = dev;
2024
2025 if (!(info->pixmap.addr = kzalloc(8*1024, GFP_KERNEL))) {
2026 i810fb_release_resource(info, par);
2027 return -ENOMEM;
2028 }
2029 info->pixmap.size = 8*1024;
2030 info->pixmap.buf_align = 8;
2031 info->pixmap.access_align = 32;
2032 info->pixmap.flags = FB_PIXMAP_SYSTEM;
2033
2034 if ((err = i810_allocate_pci_resource(par, entry))) {
2035 i810fb_release_resource(info, par);
2036 return err;
2037 }
2038
2039 i810_init_defaults(par, info);
2040
2041 if ((err = i810_alloc_agp_mem(info))) {
2042 i810fb_release_resource(info, par);
2043 return err;
2044 }
2045
2046 i810_init_device(par);
2047
2048 info->screen_base = par->fb.virtual;
2049 info->fbops = &par->i810fb_ops;
2050 info->pseudo_palette = par->pseudo_palette;
2051 fb_alloc_cmap(&info->cmap, 256, 0);
2052 i810fb_find_init_mode(info);
2053
2054 if ((err = info->fbops->fb_check_var(&info->var, info))) {
2055 i810fb_release_resource(info, par);
2056 return err;
2057 }
2058
2059 fb_var_to_videomode(&mode, &info->var);
2060 fb_add_videomode(&mode, &info->modelist);
2061 encode_fix(&info->fix, info);
2062
2063 i810fb_init_ringbuffer(info);
2064 err = register_framebuffer(info);
2065
2066 if (err < 0) {
2067 i810fb_release_resource(info, par);
2068 printk("i810fb_init: cannot register framebuffer device\n");
2069 return err;
2070 }
2071
2072 pci_set_drvdata(dev, info);
2073 pixclock = 1000000000/(info->var.pixclock);
2074 pixclock *= 1000;
2075 hfreq = pixclock/(info->var.xres + info->var.left_margin +
2076 info->var.hsync_len + info->var.right_margin);
2077 vfreq = hfreq/(info->var.yres + info->var.upper_margin +
2078 info->var.vsync_len + info->var.lower_margin);
2079
2080 printk("I810FB: fb%d : %s v%d.%d.%d%s\n"
2081 "I810FB: Video RAM : %dK\n"
2082 "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n"
2083 "I810FB: Mode : %dx%d-%dbpp@%dHz\n",
2084 info->node,
2085 i810_pci_list[entry->driver_data],
2086 VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
2087 (int) par->fb.size>>10, info->monspecs.hfmin/1000,
2088 info->monspecs.hfmax/1000, info->monspecs.vfmin,
2089 info->monspecs.vfmax, info->var.xres,
2090 info->var.yres, info->var.bits_per_pixel, vfreq);
2091 return 0;
2092 }
2093
2094 /***************************************************************
2095 * De-initialization *
2096 ***************************************************************/
2097
2098 static void i810fb_release_resource(struct fb_info *info,
2099 struct i810fb_par *par)
2100 {
2101 struct gtt_data *gtt = &par->i810_gtt;
2102 unset_mtrr(par);
2103
2104 i810_delete_i2c_busses(par);
2105
2106 if (par->i810_gtt.i810_cursor_memory)
2107 agp_free_memory(gtt->i810_cursor_memory);
2108 if (par->i810_gtt.i810_fb_memory)
2109 agp_free_memory(gtt->i810_fb_memory);
2110
2111 if (par->mmio_start_virtual)
2112 iounmap(par->mmio_start_virtual);
2113 if (par->aperture.virtual)
2114 iounmap(par->aperture.virtual);
2115 kfree(par->edid);
2116 if (par->res_flags & FRAMEBUFFER_REQ)
2117 release_mem_region(par->aperture.physical,
2118 par->aperture.size);
2119 if (par->res_flags & MMIO_REQ)
2120 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
2121
2122 framebuffer_release(info);
2123
2124 }
2125
2126 static void __exit i810fb_remove_pci(struct pci_dev *dev)
2127 {
2128 struct fb_info *info = pci_get_drvdata(dev);
2129 struct i810fb_par *par = info->par;
2130
2131 unregister_framebuffer(info);
2132 i810fb_release_resource(info, par);
2133 pci_set_drvdata(dev, NULL);
2134 printk("cleanup_module: unloaded i810 framebuffer device\n");
2135 }
2136
2137 #ifndef MODULE
2138 static int __devinit i810fb_init(void)
2139 {
2140 char *option = NULL;
2141
2142 if (fb_get_options("i810fb", &option))
2143 return -ENODEV;
2144 i810fb_setup(option);
2145
2146 return pci_register_driver(&i810fb_driver);
2147 }
2148 #endif
2149
2150 /*********************************************************************
2151 * Modularization *
2152 *********************************************************************/
2153
2154 #ifdef MODULE
2155
2156 static int __devinit i810fb_init(void)
2157 {
2158 hsync1 *= 1000;
2159 hsync2 *= 1000;
2160
2161 return pci_register_driver(&i810fb_driver);
2162 }
2163
2164 module_param(vram, int, 0);
2165 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2166 " (default=4)");
2167 module_param(voffset, int, 0);
2168 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2169 "memory (0 to maximum aperture size), in MiB (default = 48)");
2170 module_param(bpp, int, 0);
2171 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2172 " (default = 8)");
2173 module_param(xres, int, 0);
2174 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2175 module_param(yres, int, 0);
2176 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2177 module_param(vyres,int, 0);
2178 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2179 " (default = 480)");
2180 module_param(hsync1, int, 0);
2181 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2182 " (default = 29)");
2183 module_param(hsync2, int, 0);
2184 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2185 " (default = 30)");
2186 module_param(vsync1, int, 0);
2187 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2188 " (default = 50)");
2189 module_param(vsync2, int, 0);
2190 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2191 " (default = 60)");
2192 module_param(accel, bool, 0);
2193 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2194 module_param(mtrr, bool, 0);
2195 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2196 module_param(extvga, bool, 0);
2197 MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)");
2198 module_param(sync, bool, 0);
2199 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2200 " (default = 0)");
2201 module_param(dcolor, bool, 0);
2202 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2203 " (default = 0 = TrueColor)");
2204 module_param(ddc3, bool, 0);
2205 MODULE_PARM_DESC(ddc3, "Probe DDC bus 3 (default = 0 = no)");
2206 module_param(mode_option, charp, 0);
2207 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2208
2209 MODULE_AUTHOR("Tony A. Daplas");
2210 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2211 " compatible cards");
2212 MODULE_LICENSE("GPL");
2213
2214 static void __exit i810fb_exit(void)
2215 {
2216 pci_unregister_driver(&i810fb_driver);
2217 }
2218 module_exit(i810fb_exit);
2219
2220 #endif /* MODULE */
2221
2222 module_init(i810fb_init);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree