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drm/nouveau: add per-channel mutex, use to lock access to drm's channel
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
blobd8817b4bb1894c04fb48bb74524f437212436683
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include "drmP.h"
31
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35
36 #include <linux/log2.h>
37 #include <linux/slab.h>
38
39 static void
40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
41 {
42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
43 struct drm_device *dev = dev_priv->dev;
44 struct nouveau_bo *nvbo = nouveau_bo(bo);
45
46 if (unlikely(nvbo->gem))
47 DRM_ERROR("bo %p still attached to GEM object\n", bo);
48
49 if (nvbo->tile)
50 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
51
52 kfree(nvbo);
53 }
54
55 static void
56 nouveau_bo_fixup_align(struct drm_device *dev,
57 uint32_t tile_mode, uint32_t tile_flags,
58 int *align, int *size)
59 {
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
61
62 /*
63 * Some of the tile_flags have a periodic structure of N*4096 bytes,
64 * align to to that as well as the page size. Align the size to the
65 * appropriate boundaries. This does imply that sizes are rounded up
66 * 3-7 pages, so be aware of this and do not waste memory by allocating
67 * many small buffers.
68 */
69 if (dev_priv->card_type == NV_50) {
70 uint32_t block_size = dev_priv->vram_size >> 15;
71 int i;
72
73 switch (tile_flags) {
74 case 0x1800:
75 case 0x2800:
76 case 0x4800:
77 case 0x7a00:
78 if (is_power_of_2(block_size)) {
79 for (i = 1; i < 10; i++) {
80 *align = 12 * i * block_size;
81 if (!(*align % 65536))
82 break;
83 }
84 } else {
85 for (i = 1; i < 10; i++) {
86 *align = 8 * i * block_size;
87 if (!(*align % 65536))
88 break;
89 }
90 }
91 *size = roundup(*size, *align);
92 break;
93 default:
94 break;
95 }
96
97 } else {
98 if (tile_mode) {
99 if (dev_priv->chipset >= 0x40) {
100 *align = 65536;
101 *size = roundup(*size, 64 * tile_mode);
102
103 } else if (dev_priv->chipset >= 0x30) {
104 *align = 32768;
105 *size = roundup(*size, 64 * tile_mode);
106
107 } else if (dev_priv->chipset >= 0x20) {
108 *align = 16384;
109 *size = roundup(*size, 64 * tile_mode);
110
111 } else if (dev_priv->chipset >= 0x10) {
112 *align = 16384;
113 *size = roundup(*size, 32 * tile_mode);
114 }
115 }
116 }
117
118 /* ALIGN works only on powers of two. */
119 *size = roundup(*size, PAGE_SIZE);
120
121 if (dev_priv->card_type == NV_50) {
122 *size = roundup(*size, 65536);
123 *align = max(65536, *align);
124 }
125 }
126
127 int
128 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
129 int size, int align, uint32_t flags, uint32_t tile_mode,
130 uint32_t tile_flags, bool no_vm, bool mappable,
131 struct nouveau_bo **pnvbo)
132 {
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nouveau_bo *nvbo;
135 int ret = 0;
136
137 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
138 if (!nvbo)
139 return -ENOMEM;
140 INIT_LIST_HEAD(&nvbo->head);
141 INIT_LIST_HEAD(&nvbo->entry);
142 nvbo->mappable = mappable;
143 nvbo->no_vm = no_vm;
144 nvbo->tile_mode = tile_mode;
145 nvbo->tile_flags = tile_flags;
146 nvbo->bo.bdev = &dev_priv->ttm.bdev;
147
148 nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo),
149 &align, &size);
150 align >>= PAGE_SHIFT;
151
152 nouveau_bo_placement_set(nvbo, flags, 0);
153
154 nvbo->channel = chan;
155 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
156 ttm_bo_type_device, &nvbo->placement, align, 0,
157 false, NULL, size, nouveau_bo_del_ttm);
158 if (ret) {
159 /* ttm will call nouveau_bo_del_ttm if it fails.. */
160 return ret;
161 }
162 nvbo->channel = NULL;
163
164 *pnvbo = nvbo;
165 return 0;
166 }
167
168 static void
169 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
170 {
171 *n = 0;
172
173 if (type & TTM_PL_FLAG_VRAM)
174 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
175 if (type & TTM_PL_FLAG_TT)
176 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
177 if (type & TTM_PL_FLAG_SYSTEM)
178 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
179 }
180
181 static void
182 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
183 {
184 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
185
186 if (dev_priv->card_type == NV_10 &&
187 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) {
188 /*
189 * Make sure that the color and depth buffers are handled
190 * by independent memory controller units. Up to a 9x
191 * speed up when alpha-blending and depth-test are enabled
192 * at the same time.
193 */
194 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
195
196 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
197 nvbo->placement.fpfn = vram_pages / 2;
198 nvbo->placement.lpfn = ~0;
199 } else {
200 nvbo->placement.fpfn = 0;
201 nvbo->placement.lpfn = vram_pages / 2;
202 }
203 }
204 }
205
206 void
207 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
208 {
209 struct ttm_placement *pl = &nvbo->placement;
210 uint32_t flags = TTM_PL_MASK_CACHING |
211 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
212
213 pl->placement = nvbo->placements;
214 set_placement_list(nvbo->placements, &pl->num_placement,
215 type, flags);
216
217 pl->busy_placement = nvbo->busy_placements;
218 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
219 type | busy, flags);
220
221 set_placement_range(nvbo, type);
222 }
223
224 int
225 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
226 {
227 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
228 struct ttm_buffer_object *bo = &nvbo->bo;
229 int ret;
230
231 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
232 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
233 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
234 1 << bo->mem.mem_type, memtype);
235 return -EINVAL;
236 }
237
238 if (nvbo->pin_refcnt++)
239 return 0;
240
241 ret = ttm_bo_reserve(bo, false, false, false, 0);
242 if (ret)
243 goto out;
244
245 nouveau_bo_placement_set(nvbo, memtype, 0);
246
247 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
248 if (ret == 0) {
249 switch (bo->mem.mem_type) {
250 case TTM_PL_VRAM:
251 dev_priv->fb_aper_free -= bo->mem.size;
252 break;
253 case TTM_PL_TT:
254 dev_priv->gart_info.aper_free -= bo->mem.size;
255 break;
256 default:
257 break;
258 }
259 }
260 ttm_bo_unreserve(bo);
261 out:
262 if (unlikely(ret))
263 nvbo->pin_refcnt--;
264 return ret;
265 }
266
267 int
268 nouveau_bo_unpin(struct nouveau_bo *nvbo)
269 {
270 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
271 struct ttm_buffer_object *bo = &nvbo->bo;
272 int ret;
273
274 if (--nvbo->pin_refcnt)
275 return 0;
276
277 ret = ttm_bo_reserve(bo, false, false, false, 0);
278 if (ret)
279 return ret;
280
281 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
282
283 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
284 if (ret == 0) {
285 switch (bo->mem.mem_type) {
286 case TTM_PL_VRAM:
287 dev_priv->fb_aper_free += bo->mem.size;
288 break;
289 case TTM_PL_TT:
290 dev_priv->gart_info.aper_free += bo->mem.size;
291 break;
292 default:
293 break;
294 }
295 }
296
297 ttm_bo_unreserve(bo);
298 return ret;
299 }
300
301 int
302 nouveau_bo_map(struct nouveau_bo *nvbo)
303 {
304 int ret;
305
306 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
307 if (ret)
308 return ret;
309
310 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
311 ttm_bo_unreserve(&nvbo->bo);
312 return ret;
313 }
314
315 void
316 nouveau_bo_unmap(struct nouveau_bo *nvbo)
317 {
318 if (nvbo)
319 ttm_bo_kunmap(&nvbo->kmap);
320 }
321
322 u16
323 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
324 {
325 bool is_iomem;
326 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 return ioread16_native((void __force __iomem *)mem);
330 else
331 return *mem;
332 }
333
334 void
335 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
336 {
337 bool is_iomem;
338 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 iowrite16_native(val, (void __force __iomem *)mem);
342 else
343 *mem = val;
344 }
345
346 u32
347 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
348 {
349 bool is_iomem;
350 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
351 mem = &mem[index];
352 if (is_iomem)
353 return ioread32_native((void __force __iomem *)mem);
354 else
355 return *mem;
356 }
357
358 void
359 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
360 {
361 bool is_iomem;
362 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
363 mem = &mem[index];
364 if (is_iomem)
365 iowrite32_native(val, (void __force __iomem *)mem);
366 else
367 *mem = val;
368 }
369
370 static struct ttm_backend *
371 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
372 {
373 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
374 struct drm_device *dev = dev_priv->dev;
375
376 switch (dev_priv->gart_info.type) {
377 #if __OS_HAS_AGP
378 case NOUVEAU_GART_AGP:
379 return ttm_agp_backend_init(bdev, dev->agp->bridge);
380 #endif
381 case NOUVEAU_GART_SGDMA:
382 return nouveau_sgdma_init_ttm(dev);
383 default:
384 NV_ERROR(dev, "Unknown GART type %d\n",
385 dev_priv->gart_info.type);
386 break;
387 }
388
389 return NULL;
390 }
391
392 static int
393 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
394 {
395 /* We'll do this from user space. */
396 return 0;
397 }
398
399 static int
400 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
401 struct ttm_mem_type_manager *man)
402 {
403 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
404 struct drm_device *dev = dev_priv->dev;
405
406 switch (type) {
407 case TTM_PL_SYSTEM:
408 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
409 man->available_caching = TTM_PL_MASK_CACHING;
410 man->default_caching = TTM_PL_FLAG_CACHED;
411 break;
412 case TTM_PL_VRAM:
413 man->func = &ttm_bo_manager_func;
414 man->flags = TTM_MEMTYPE_FLAG_FIXED |
415 TTM_MEMTYPE_FLAG_MAPPABLE;
416 man->available_caching = TTM_PL_FLAG_UNCACHED |
417 TTM_PL_FLAG_WC;
418 man->default_caching = TTM_PL_FLAG_WC;
419 if (dev_priv->card_type == NV_50)
420 man->gpu_offset = 0x40000000;
421 else
422 man->gpu_offset = 0;
423 break;
424 case TTM_PL_TT:
425 man->func = &ttm_bo_manager_func;
426 switch (dev_priv->gart_info.type) {
427 case NOUVEAU_GART_AGP:
428 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
429 man->available_caching = TTM_PL_FLAG_UNCACHED;
430 man->default_caching = TTM_PL_FLAG_UNCACHED;
431 break;
432 case NOUVEAU_GART_SGDMA:
433 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
434 TTM_MEMTYPE_FLAG_CMA;
435 man->available_caching = TTM_PL_MASK_CACHING;
436 man->default_caching = TTM_PL_FLAG_CACHED;
437 break;
438 default:
439 NV_ERROR(dev, "Unknown GART type: %d\n",
440 dev_priv->gart_info.type);
441 return -EINVAL;
442 }
443 man->gpu_offset = dev_priv->vm_gart_base;
444 break;
445 default:
446 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
447 return -EINVAL;
448 }
449 return 0;
450 }
451
452 static void
453 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
454 {
455 struct nouveau_bo *nvbo = nouveau_bo(bo);
456
457 switch (bo->mem.mem_type) {
458 case TTM_PL_VRAM:
459 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
460 TTM_PL_FLAG_SYSTEM);
461 break;
462 default:
463 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
464 break;
465 }
466
467 *pl = nvbo->placement;
468 }
469
470
471 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
472 * TTM_PL_{VRAM,TT} directly.
473 */
474
475 static int
476 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
477 struct nouveau_bo *nvbo, bool evict,
478 bool no_wait_reserve, bool no_wait_gpu,
479 struct ttm_mem_reg *new_mem)
480 {
481 struct nouveau_fence *fence = NULL;
482 int ret;
483
484 ret = nouveau_fence_new(chan, &fence, true);
485 if (ret)
486 return ret;
487
488 if (nvbo->channel) {
489 ret = nouveau_fence_sync(fence, nvbo->channel);
490 if (ret)
491 goto out;
492 }
493
494 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
495 no_wait_reserve, no_wait_gpu, new_mem);
496 out:
497 nouveau_fence_unref((void *)&fence);
498 return ret;
499 }
500
501 static inline uint32_t
502 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
503 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
504 {
505 struct nouveau_bo *nvbo = nouveau_bo(bo);
506
507 if (nvbo->no_vm) {
508 if (mem->mem_type == TTM_PL_TT)
509 return NvDmaGART;
510 return NvDmaVRAM;
511 }
512
513 if (mem->mem_type == TTM_PL_TT)
514 return chan->gart_handle;
515 return chan->vram_handle;
516 }
517
518 static int
519 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
520 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
521 {
522 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
523 struct nouveau_bo *nvbo = nouveau_bo(bo);
524 u64 length = (new_mem->num_pages << PAGE_SHIFT);
525 u64 src_offset, dst_offset;
526 int ret;
527
528 src_offset = old_mem->start << PAGE_SHIFT;
529 dst_offset = new_mem->start << PAGE_SHIFT;
530 if (!nvbo->no_vm) {
531 if (old_mem->mem_type == TTM_PL_VRAM)
532 src_offset += dev_priv->vm_vram_base;
533 else
534 src_offset += dev_priv->vm_gart_base;
535
536 if (new_mem->mem_type == TTM_PL_VRAM)
537 dst_offset += dev_priv->vm_vram_base;
538 else
539 dst_offset += dev_priv->vm_gart_base;
540 }
541
542 ret = RING_SPACE(chan, 3);
543 if (ret)
544 return ret;
545
546 BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
547 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
548 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
549
550 while (length) {
551 u32 amount, stride, height;
552
553 amount = min(length, (u64)(4 * 1024 * 1024));
554 stride = 16 * 4;
555 height = amount / stride;
556
557 if (new_mem->mem_type == TTM_PL_VRAM &&
558 nouveau_bo_tile_layout(nvbo)) {
559 ret = RING_SPACE(chan, 8);
560 if (ret)
561 return ret;
562
563 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
564 OUT_RING (chan, 0);
565 OUT_RING (chan, 0);
566 OUT_RING (chan, stride);
567 OUT_RING (chan, height);
568 OUT_RING (chan, 1);
569 OUT_RING (chan, 0);
570 OUT_RING (chan, 0);
571 } else {
572 ret = RING_SPACE(chan, 2);
573 if (ret)
574 return ret;
575
576 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
577 OUT_RING (chan, 1);
578 }
579 if (old_mem->mem_type == TTM_PL_VRAM &&
580 nouveau_bo_tile_layout(nvbo)) {
581 ret = RING_SPACE(chan, 8);
582 if (ret)
583 return ret;
584
585 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
586 OUT_RING (chan, 0);
587 OUT_RING (chan, 0);
588 OUT_RING (chan, stride);
589 OUT_RING (chan, height);
590 OUT_RING (chan, 1);
591 OUT_RING (chan, 0);
592 OUT_RING (chan, 0);
593 } else {
594 ret = RING_SPACE(chan, 2);
595 if (ret)
596 return ret;
597
598 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
599 OUT_RING (chan, 1);
600 }
601
602 ret = RING_SPACE(chan, 14);
603 if (ret)
604 return ret;
605
606 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
607 OUT_RING (chan, upper_32_bits(src_offset));
608 OUT_RING (chan, upper_32_bits(dst_offset));
609 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
610 OUT_RING (chan, lower_32_bits(src_offset));
611 OUT_RING (chan, lower_32_bits(dst_offset));
612 OUT_RING (chan, stride);
613 OUT_RING (chan, stride);
614 OUT_RING (chan, stride);
615 OUT_RING (chan, height);
616 OUT_RING (chan, 0x00000101);
617 OUT_RING (chan, 0x00000000);
618 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
619 OUT_RING (chan, 0);
620
621 length -= amount;
622 src_offset += amount;
623 dst_offset += amount;
624 }
625
626 return 0;
627 }
628
629 static int
630 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
631 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
632 {
633 u32 src_offset = old_mem->start << PAGE_SHIFT;
634 u32 dst_offset = new_mem->start << PAGE_SHIFT;
635 u32 page_count = new_mem->num_pages;
636 int ret;
637
638 ret = RING_SPACE(chan, 3);
639 if (ret)
640 return ret;
641
642 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
643 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
644 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
645
646 page_count = new_mem->num_pages;
647 while (page_count) {
648 int line_count = (page_count > 2047) ? 2047 : page_count;
649
650 ret = RING_SPACE(chan, 11);
651 if (ret)
652 return ret;
653
654 BEGIN_RING(chan, NvSubM2MF,
655 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
656 OUT_RING (chan, src_offset);
657 OUT_RING (chan, dst_offset);
658 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
659 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
660 OUT_RING (chan, PAGE_SIZE); /* line_length */
661 OUT_RING (chan, line_count);
662 OUT_RING (chan, 0x00000101);
663 OUT_RING (chan, 0x00000000);
664 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
665 OUT_RING (chan, 0);
666
667 page_count -= line_count;
668 src_offset += (PAGE_SIZE * line_count);
669 dst_offset += (PAGE_SIZE * line_count);
670 }
671
672 return 0;
673 }
674
675 static int
676 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
677 bool no_wait_reserve, bool no_wait_gpu,
678 struct ttm_mem_reg *new_mem)
679 {
680 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
681 struct nouveau_bo *nvbo = nouveau_bo(bo);
682 struct nouveau_channel *chan;
683 int ret;
684
685 chan = nvbo->channel;
686 if (!chan || nvbo->no_vm) {
687 chan = dev_priv->channel;
688 mutex_lock(&chan->mutex);
689 }
690
691 if (dev_priv->card_type < NV_50)
692 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
693 else
694 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
695 if (ret == 0) {
696 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
697 no_wait_reserve,
698 no_wait_gpu, new_mem);
699 }
700
701 if (chan == dev_priv->channel)
702 mutex_unlock(&chan->mutex);
703 return ret;
704 }
705
706 static int
707 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
708 bool no_wait_reserve, bool no_wait_gpu,
709 struct ttm_mem_reg *new_mem)
710 {
711 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
712 struct ttm_placement placement;
713 struct ttm_mem_reg tmp_mem;
714 int ret;
715
716 placement.fpfn = placement.lpfn = 0;
717 placement.num_placement = placement.num_busy_placement = 1;
718 placement.placement = placement.busy_placement = &placement_memtype;
719
720 tmp_mem = *new_mem;
721 tmp_mem.mm_node = NULL;
722 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
723 if (ret)
724 return ret;
725
726 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
727 if (ret)
728 goto out;
729
730 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
731 if (ret)
732 goto out;
733
734 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
735 out:
736 ttm_bo_mem_put(bo, &tmp_mem);
737 return ret;
738 }
739
740 static int
741 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
742 bool no_wait_reserve, bool no_wait_gpu,
743 struct ttm_mem_reg *new_mem)
744 {
745 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
746 struct ttm_placement placement;
747 struct ttm_mem_reg tmp_mem;
748 int ret;
749
750 placement.fpfn = placement.lpfn = 0;
751 placement.num_placement = placement.num_busy_placement = 1;
752 placement.placement = placement.busy_placement = &placement_memtype;
753
754 tmp_mem = *new_mem;
755 tmp_mem.mm_node = NULL;
756 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
757 if (ret)
758 return ret;
759
760 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
761 if (ret)
762 goto out;
763
764 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
765 if (ret)
766 goto out;
767
768 out:
769 ttm_bo_mem_put(bo, &tmp_mem);
770 return ret;
771 }
772
773 static int
774 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
775 struct nouveau_tile_reg **new_tile)
776 {
777 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
778 struct drm_device *dev = dev_priv->dev;
779 struct nouveau_bo *nvbo = nouveau_bo(bo);
780 uint64_t offset;
781 int ret;
782
783 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
784 /* Nothing to do. */
785 *new_tile = NULL;
786 return 0;
787 }
788
789 offset = new_mem->start << PAGE_SHIFT;
790
791 if (dev_priv->card_type == NV_50) {
792 ret = nv50_mem_vm_bind_linear(dev,
793 offset + dev_priv->vm_vram_base,
794 new_mem->size,
795 nouveau_bo_tile_layout(nvbo),
796 offset);
797 if (ret)
798 return ret;
799
800 } else if (dev_priv->card_type >= NV_10) {
801 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
802 nvbo->tile_mode);
803 }
804
805 return 0;
806 }
807
808 static void
809 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
810 struct nouveau_tile_reg *new_tile,
811 struct nouveau_tile_reg **old_tile)
812 {
813 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
814 struct drm_device *dev = dev_priv->dev;
815
816 if (dev_priv->card_type >= NV_10 &&
817 dev_priv->card_type < NV_50) {
818 if (*old_tile)
819 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
820
821 *old_tile = new_tile;
822 }
823 }
824
825 static int
826 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
827 bool no_wait_reserve, bool no_wait_gpu,
828 struct ttm_mem_reg *new_mem)
829 {
830 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
831 struct nouveau_bo *nvbo = nouveau_bo(bo);
832 struct ttm_mem_reg *old_mem = &bo->mem;
833 struct nouveau_tile_reg *new_tile = NULL;
834 int ret = 0;
835
836 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
837 if (ret)
838 return ret;
839
840 /* Fake bo copy. */
841 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
842 BUG_ON(bo->mem.mm_node != NULL);
843 bo->mem = *new_mem;
844 new_mem->mm_node = NULL;
845 goto out;
846 }
847
848 /* Software copy if the card isn't up and running yet. */
849 if (!dev_priv->channel) {
850 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
851 goto out;
852 }
853
854 /* Hardware assisted copy. */
855 if (new_mem->mem_type == TTM_PL_SYSTEM)
856 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
857 else if (old_mem->mem_type == TTM_PL_SYSTEM)
858 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
859 else
860 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
861
862 if (!ret)
863 goto out;
864
865 /* Fallback to software copy. */
866 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
867
868 out:
869 if (ret)
870 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
871 else
872 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
873
874 return ret;
875 }
876
877 static int
878 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
879 {
880 return 0;
881 }
882
883 static int
884 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
885 {
886 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
887 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
888 struct drm_device *dev = dev_priv->dev;
889
890 mem->bus.addr = NULL;
891 mem->bus.offset = 0;
892 mem->bus.size = mem->num_pages << PAGE_SHIFT;
893 mem->bus.base = 0;
894 mem->bus.is_iomem = false;
895 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
896 return -EINVAL;
897 switch (mem->mem_type) {
898 case TTM_PL_SYSTEM:
899 /* System memory */
900 return 0;
901 case TTM_PL_TT:
902 #if __OS_HAS_AGP
903 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
904 mem->bus.offset = mem->start << PAGE_SHIFT;
905 mem->bus.base = dev_priv->gart_info.aper_base;
906 mem->bus.is_iomem = true;
907 }
908 #endif
909 break;
910 case TTM_PL_VRAM:
911 mem->bus.offset = mem->start << PAGE_SHIFT;
912 mem->bus.base = pci_resource_start(dev->pdev, 1);
913 mem->bus.is_iomem = true;
914 break;
915 default:
916 return -EINVAL;
917 }
918 return 0;
919 }
920
921 static void
922 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
923 {
924 }
925
926 static int
927 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
928 {
929 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
930 struct nouveau_bo *nvbo = nouveau_bo(bo);
931
932 /* as long as the bo isn't in vram, and isn't tiled, we've got
933 * nothing to do here.
934 */
935 if (bo->mem.mem_type != TTM_PL_VRAM) {
936 if (dev_priv->card_type < NV_50 ||
937 !nouveau_bo_tile_layout(nvbo))
938 return 0;
939 }
940
941 /* make sure bo is in mappable vram */
942 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
943 return 0;
944
945
946 nvbo->placement.fpfn = 0;
947 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
948 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
949 return ttm_bo_validate(bo, &nvbo->placement, false, true, false);
950 }
951
952 struct ttm_bo_driver nouveau_bo_driver = {
953 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
954 .invalidate_caches = nouveau_bo_invalidate_caches,
955 .init_mem_type = nouveau_bo_init_mem_type,
956 .evict_flags = nouveau_bo_evict_flags,
957 .move = nouveau_bo_move,
958 .verify_access = nouveau_bo_verify_access,
959 .sync_obj_signaled = nouveau_fence_signalled,
960 .sync_obj_wait = nouveau_fence_wait,
961 .sync_obj_flush = nouveau_fence_flush,
962 .sync_obj_unref = nouveau_fence_unref,
963 .sync_obj_ref = nouveau_fence_ref,
964 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
965 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
966 .io_mem_free = &nouveau_ttm_io_mem_free,
967 };
968
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree