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Blackfin arch: merge adeos blackfin part to arch/blackfin/
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / blackfin / mach-common / ints-priority.c
blob1bba6030dce97e7d3521e6cf43c45e03c9118755
1 /*
2 * File: arch/blackfin/mach-common/ints-priority.c
3 *
4 * Description: Set up the interrupt priorities
5 *
6 * Modified:
7 * 1996 Roman Zippel
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
10 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
11 * 2003 Metrowerks/Motorola
12 * 2003 Bas Vermeulen <bas@buyways.nl>
13 * Copyright 2004-2008 Analog Devices Inc.
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, see the file COPYING, or write
29 * to the Free Software Foundation, Inc.,
30 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 */
32
33 #include <linux/module.h>
34 #include <linux/kernel_stat.h>
35 #include <linux/seq_file.h>
36 #include <linux/irq.h>
37 #ifdef CONFIG_IPIPE
38 #include <linux/ipipe.h>
39 #endif
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
49
50 #ifdef BF537_FAMILY
51 # define BF537_GENERIC_ERROR_INT_DEMUX
52 #else
53 # undef BF537_GENERIC_ERROR_INT_DEMUX
54 #endif
55
56 /*
57 * NOTES:
58 * - we have separated the physical Hardware interrupt from the
59 * levels that the LINUX kernel sees (see the description in irq.h)
60 * -
61 */
62
63 #ifndef CONFIG_SMP
64 /* Initialize this to an actual value to force it into the .data
65 * section so that we know it is properly initialized at entry into
66 * the kernel but before bss is initialized to zero (which is where
67 * it would live otherwise). The 0x1f magic represents the IRQs we
68 * cannot actually mask out in hardware.
69 */
70 unsigned long bfin_irq_flags = 0x1f;
71 EXPORT_SYMBOL(bfin_irq_flags);
72 #endif
73
74 /* The number of spurious interrupts */
75 atomic_t num_spurious;
76
77 #ifdef CONFIG_PM
78 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
79 unsigned vr_wakeup;
80 #endif
81
82 struct ivgx {
83 /* irq number for request_irq, available in mach-bf5xx/irq.h */
84 unsigned int irqno;
85 /* corresponding bit in the SIC_ISR register */
86 unsigned int isrflag;
87 } ivg_table[NR_PERI_INTS];
88
89 struct ivg_slice {
90 /* position of first irq in ivg_table for given ivg */
91 struct ivgx *ifirst;
92 struct ivgx *istop;
93 } ivg7_13[IVG13 - IVG7 + 1];
94
95
96 /*
97 * Search SIC_IAR and fill tables with the irqvalues
98 * and their positions in the SIC_ISR register.
99 */
100 static void __init search_IAR(void)
101 {
102 unsigned ivg, irq_pos = 0;
103 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
104 int irqn;
105
106 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
107
108 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
109 int iar_shift = (irqn & 7) * 4;
110 if (ivg == (0xf &
111 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
112 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
113 bfin_read32((unsigned long *)SIC_IAR0 +
114 ((irqn % 32) >> 3) + ((irqn / 32) *
115 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
116 #else
117 bfin_read32((unsigned long *)SIC_IAR0 +
118 (irqn >> 3)) >> iar_shift)) {
119 #endif
120 ivg_table[irq_pos].irqno = IVG7 + irqn;
121 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
122 ivg7_13[ivg].istop++;
123 irq_pos++;
124 }
125 }
126 }
127 }
128
129 /*
130 * This is for core internal IRQs
131 */
132
133 static void bfin_ack_noop(unsigned int irq)
134 {
135 /* Dummy function. */
136 }
137
138 static void bfin_core_mask_irq(unsigned int irq)
139 {
140 bfin_irq_flags &= ~(1 << irq);
141 if (!irqs_disabled_hw())
142 local_irq_enable_hw();
143 }
144
145 static void bfin_core_unmask_irq(unsigned int irq)
146 {
147 bfin_irq_flags |= 1 << irq;
148 /*
149 * If interrupts are enabled, IMASK must contain the same value
150 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
151 * are currently disabled we need not do anything; one of the
152 * callers will take care of setting IMASK to the proper value
153 * when reenabling interrupts.
154 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
155 * what we need.
156 */
157 if (!irqs_disabled_hw())
158 local_irq_enable_hw();
159 return;
160 }
161
162 static void bfin_internal_mask_irq(unsigned int irq)
163 {
164 #ifdef CONFIG_BF53x
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq)));
167 #else
168 unsigned mask_bank, mask_bit;
169 mask_bank = SIC_SYSIRQ(irq) / 32;
170 mask_bit = SIC_SYSIRQ(irq) % 32;
171 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
172 ~(1 << mask_bit));
173 #ifdef CONFIG_SMP
174 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
175 ~(1 << mask_bit));
176 #endif
177 #endif
178 }
179
180 static void bfin_internal_unmask_irq(unsigned int irq)
181 {
182 #ifdef CONFIG_BF53x
183 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
184 (1 << SIC_SYSIRQ(irq)));
185 #else
186 unsigned mask_bank, mask_bit;
187 mask_bank = SIC_SYSIRQ(irq) / 32;
188 mask_bit = SIC_SYSIRQ(irq) % 32;
189 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
190 (1 << mask_bit));
191 #ifdef CONFIG_SMP
192 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
193 (1 << mask_bit));
194 #endif
195 #endif
196 }
197
198 #ifdef CONFIG_PM
199 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
200 {
201 u32 bank, bit, wakeup = 0;
202 unsigned long flags;
203 bank = SIC_SYSIRQ(irq) / 32;
204 bit = SIC_SYSIRQ(irq) % 32;
205
206 switch (irq) {
207 #ifdef IRQ_RTC
208 case IRQ_RTC:
209 wakeup |= WAKE;
210 break;
211 #endif
212 #ifdef IRQ_CAN0_RX
213 case IRQ_CAN0_RX:
214 wakeup |= CANWE;
215 break;
216 #endif
217 #ifdef IRQ_CAN1_RX
218 case IRQ_CAN1_RX:
219 wakeup |= CANWE;
220 break;
221 #endif
222 #ifdef IRQ_USB_INT0
223 case IRQ_USB_INT0:
224 wakeup |= USBWE;
225 break;
226 #endif
227 #ifdef IRQ_KEY
228 case IRQ_KEY:
229 wakeup |= KPADWE;
230 break;
231 #endif
232 #ifdef CONFIG_BF54x
233 case IRQ_CNT:
234 wakeup |= ROTWE;
235 break;
236 #endif
237 default:
238 break;
239 }
240
241 local_irq_save_hw(flags);
242
243 if (state) {
244 bfin_sic_iwr[bank] |= (1 << bit);
245 vr_wakeup |= wakeup;
246
247 } else {
248 bfin_sic_iwr[bank] &= ~(1 << bit);
249 vr_wakeup &= ~wakeup;
250 }
251
252 local_irq_restore_hw(flags);
253
254 return 0;
255 }
256 #endif
257
258 static struct irq_chip bfin_core_irqchip = {
259 .name = "CORE",
260 .ack = bfin_ack_noop,
261 .mask = bfin_core_mask_irq,
262 .unmask = bfin_core_unmask_irq,
263 };
264
265 static struct irq_chip bfin_internal_irqchip = {
266 .name = "INTN",
267 .ack = bfin_ack_noop,
268 .mask = bfin_internal_mask_irq,
269 .unmask = bfin_internal_unmask_irq,
270 .mask_ack = bfin_internal_mask_irq,
271 .disable = bfin_internal_mask_irq,
272 .enable = bfin_internal_unmask_irq,
273 #ifdef CONFIG_PM
274 .set_wake = bfin_internal_set_wake,
275 #endif
276 };
277
278 static void bfin_handle_irq(unsigned irq)
279 {
280 #ifdef CONFIG_IPIPE
281 struct pt_regs regs; /* Contents not used. */
282 ipipe_trace_irq_entry(irq);
283 __ipipe_handle_irq(irq, &regs);
284 ipipe_trace_irq_exit(irq);
285 #else /* !CONFIG_IPIPE */
286 struct irq_desc *desc = irq_desc + irq;
287 desc->handle_irq(irq, desc);
288 #endif /* !CONFIG_IPIPE */
289 }
290
291 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
292 static int error_int_mask;
293
294 static void bfin_generic_error_mask_irq(unsigned int irq)
295 {
296 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
297
298 if (!error_int_mask)
299 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
300 }
301
302 static void bfin_generic_error_unmask_irq(unsigned int irq)
303 {
304 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
305 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
306 }
307
308 static struct irq_chip bfin_generic_error_irqchip = {
309 .name = "ERROR",
310 .ack = bfin_ack_noop,
311 .mask_ack = bfin_generic_error_mask_irq,
312 .mask = bfin_generic_error_mask_irq,
313 .unmask = bfin_generic_error_unmask_irq,
314 };
315
316 static void bfin_demux_error_irq(unsigned int int_err_irq,
317 struct irq_desc *inta_desc)
318 {
319 int irq = 0;
320
321 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
322 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
323 irq = IRQ_MAC_ERROR;
324 else
325 #endif
326 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
327 irq = IRQ_SPORT0_ERROR;
328 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
329 irq = IRQ_SPORT1_ERROR;
330 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
331 irq = IRQ_PPI_ERROR;
332 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
333 irq = IRQ_CAN_ERROR;
334 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
335 irq = IRQ_SPI_ERROR;
336 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
337 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
338 irq = IRQ_UART0_ERROR;
339 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
340 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
341 irq = IRQ_UART1_ERROR;
342
343 if (irq) {
344 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
345 bfin_handle_irq(irq);
346 else {
347
348 switch (irq) {
349 case IRQ_PPI_ERROR:
350 bfin_write_PPI_STATUS(PPI_ERR_MASK);
351 break;
352 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
353 case IRQ_MAC_ERROR:
354 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
355 break;
356 #endif
357 case IRQ_SPORT0_ERROR:
358 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
359 break;
360
361 case IRQ_SPORT1_ERROR:
362 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
363 break;
364
365 case IRQ_CAN_ERROR:
366 bfin_write_CAN_GIS(CAN_ERR_MASK);
367 break;
368
369 case IRQ_SPI_ERROR:
370 bfin_write_SPI_STAT(SPI_ERR_MASK);
371 break;
372
373 default:
374 break;
375 }
376
377 pr_debug("IRQ %d:"
378 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
379 irq);
380 }
381 } else
382 printk(KERN_ERR
383 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
384 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
385 __func__, __FILE__, __LINE__);
386
387 }
388 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
389
390 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
391 {
392 #ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq);
394 #else
395 struct irq_desc *desc = irq_desc + irq;
396 /* May not call generic set_irq_handler() due to spinlock
397 recursion. */
398 desc->handle_irq = handle;
399 #endif
400 }
401
402 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
403 extern void bfin_gpio_irq_prepare(unsigned gpio);
404
405 #if !defined(CONFIG_BF54x)
406
407 static void bfin_gpio_ack_irq(unsigned int irq)
408 {
409 /* AFAIK ack_irq in case mask_ack is provided
410 * get's only called for edge sense irqs
411 */
412 set_gpio_data(irq_to_gpio(irq), 0);
413 }
414
415 static void bfin_gpio_mask_ack_irq(unsigned int irq)
416 {
417 struct irq_desc *desc = irq_desc + irq;
418 u32 gpionr = irq_to_gpio(irq);
419
420 if (desc->handle_irq == handle_edge_irq)
421 set_gpio_data(gpionr, 0);
422
423 set_gpio_maska(gpionr, 0);
424 }
425
426 static void bfin_gpio_mask_irq(unsigned int irq)
427 {
428 set_gpio_maska(irq_to_gpio(irq), 0);
429 }
430
431 static void bfin_gpio_unmask_irq(unsigned int irq)
432 {
433 set_gpio_maska(irq_to_gpio(irq), 1);
434 }
435
436 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
437 {
438 u32 gpionr = irq_to_gpio(irq);
439
440 if (__test_and_set_bit(gpionr, gpio_enabled))
441 bfin_gpio_irq_prepare(gpionr);
442
443 bfin_gpio_unmask_irq(irq);
444
445 return 0;
446 }
447
448 static void bfin_gpio_irq_shutdown(unsigned int irq)
449 {
450 u32 gpionr = irq_to_gpio(irq);
451
452 bfin_gpio_mask_irq(irq);
453 __clear_bit(gpionr, gpio_enabled);
454 bfin_gpio_irq_free(gpionr);
455 }
456
457 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
458 {
459 int ret;
460 char buf[16];
461 u32 gpionr = irq_to_gpio(irq);
462
463 if (type == IRQ_TYPE_PROBE) {
464 /* only probe unenabled GPIO interrupt lines */
465 if (__test_bit(gpionr, gpio_enabled))
466 return 0;
467 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
468 }
469
470 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
471 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
472
473 snprintf(buf, 16, "gpio-irq%d", irq);
474 ret = bfin_gpio_irq_request(gpionr, buf);
475 if (ret)
476 return ret;
477
478 if (__test_and_set_bit(gpionr, gpio_enabled))
479 bfin_gpio_irq_prepare(gpionr);
480
481 } else {
482 __clear_bit(gpionr, gpio_enabled);
483 return 0;
484 }
485
486 set_gpio_inen(gpionr, 0);
487 set_gpio_dir(gpionr, 0);
488
489 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
490 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
491 set_gpio_both(gpionr, 1);
492 else
493 set_gpio_both(gpionr, 0);
494
495 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
496 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
497 else
498 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
499
500 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
501 set_gpio_edge(gpionr, 1);
502 set_gpio_inen(gpionr, 1);
503 set_gpio_data(gpionr, 0);
504
505 } else {
506 set_gpio_edge(gpionr, 0);
507 set_gpio_inen(gpionr, 1);
508 }
509
510 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
511 bfin_set_irq_handler(irq, handle_edge_irq);
512 else
513 bfin_set_irq_handler(irq, handle_level_irq);
514
515 return 0;
516 }
517
518 #ifdef CONFIG_PM
519 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
520 {
521 unsigned gpio = irq_to_gpio(irq);
522
523 if (state)
524 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
525 else
526 gpio_pm_wakeup_free(gpio);
527
528 return 0;
529 }
530 #endif
531
532 static void bfin_demux_gpio_irq(unsigned int inta_irq,
533 struct irq_desc *desc)
534 {
535 unsigned int i, gpio, mask, irq, search = 0;
536
537 switch (inta_irq) {
538 #if defined(CONFIG_BF53x)
539 case IRQ_PROG_INTA:
540 irq = IRQ_PF0;
541 search = 1;
542 break;
543 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
544 case IRQ_MAC_RX:
545 irq = IRQ_PH0;
546 break;
547 # endif
548 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
549 case IRQ_PORTF_INTA:
550 irq = IRQ_PF0;
551 break;
552 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
553 case IRQ_PORTF_INTA:
554 irq = IRQ_PF0;
555 break;
556 case IRQ_PORTG_INTA:
557 irq = IRQ_PG0;
558 break;
559 case IRQ_PORTH_INTA:
560 irq = IRQ_PH0;
561 break;
562 #elif defined(CONFIG_BF561)
563 case IRQ_PROG0_INTA:
564 irq = IRQ_PF0;
565 break;
566 case IRQ_PROG1_INTA:
567 irq = IRQ_PF16;
568 break;
569 case IRQ_PROG2_INTA:
570 irq = IRQ_PF32;
571 break;
572 #endif
573 default:
574 BUG();
575 return;
576 }
577
578 if (search) {
579 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
580 irq += i;
581
582 mask = get_gpiop_data(i) & get_gpiop_maska(i);
583
584 while (mask) {
585 if (mask & 1)
586 bfin_handle_irq(irq);
587 irq++;
588 mask >>= 1;
589 }
590 }
591 } else {
592 gpio = irq_to_gpio(irq);
593 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
594
595 do {
596 if (mask & 1)
597 bfin_handle_irq(irq);
598 irq++;
599 mask >>= 1;
600 } while (mask);
601 }
602
603 }
604
605 #else /* CONFIG_BF54x */
606
607 #define NR_PINT_SYS_IRQS 4
608 #define NR_PINT_BITS 32
609 #define NR_PINTS 160
610 #define IRQ_NOT_AVAIL 0xFF
611
612 #define PINT_2_BANK(x) ((x) >> 5)
613 #define PINT_2_BIT(x) ((x) & 0x1F)
614 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
615
616 static unsigned char irq2pint_lut[NR_PINTS];
617 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
618
619 struct pin_int_t {
620 unsigned int mask_set;
621 unsigned int mask_clear;
622 unsigned int request;
623 unsigned int assign;
624 unsigned int edge_set;
625 unsigned int edge_clear;
626 unsigned int invert_set;
627 unsigned int invert_clear;
628 unsigned int pinstate;
629 unsigned int latch;
630 };
631
632 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
633 (struct pin_int_t *)PINT0_MASK_SET,
634 (struct pin_int_t *)PINT1_MASK_SET,
635 (struct pin_int_t *)PINT2_MASK_SET,
636 (struct pin_int_t *)PINT3_MASK_SET,
637 };
638
639 inline unsigned int get_irq_base(u32 bank, u8 bmap)
640 {
641 unsigned int irq_base;
642
643 if (bank < 2) { /*PA-PB */
644 irq_base = IRQ_PA0 + bmap * 16;
645 } else { /*PC-PJ */
646 irq_base = IRQ_PC0 + bmap * 16;
647 }
648
649 return irq_base;
650 }
651
652 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
653 void init_pint_lut(void)
654 {
655 u16 bank, bit, irq_base, bit_pos;
656 u32 pint_assign;
657 u8 bmap;
658
659 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
660
661 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
662
663 pint_assign = pint[bank]->assign;
664
665 for (bit = 0; bit < NR_PINT_BITS; bit++) {
666
667 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
668
669 irq_base = get_irq_base(bank, bmap);
670
671 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
672 bit_pos = bit + bank * NR_PINT_BITS;
673
674 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
675 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
676 }
677 }
678 }
679
680 static void bfin_gpio_ack_irq(unsigned int irq)
681 {
682 struct irq_desc *desc = irq_desc + irq;
683 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
684 u32 pintbit = PINT_BIT(pint_val);
685 u32 bank = PINT_2_BANK(pint_val);
686
687 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
688 if (pint[bank]->invert_set & pintbit)
689 pint[bank]->invert_clear = pintbit;
690 else
691 pint[bank]->invert_set = pintbit;
692 }
693 pint[bank]->request = pintbit;
694
695 }
696
697 static void bfin_gpio_mask_ack_irq(unsigned int irq)
698 {
699 struct irq_desc *desc = irq_desc + irq;
700 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
701 u32 pintbit = PINT_BIT(pint_val);
702 u32 bank = PINT_2_BANK(pint_val);
703
704 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
705 if (pint[bank]->invert_set & pintbit)
706 pint[bank]->invert_clear = pintbit;
707 else
708 pint[bank]->invert_set = pintbit;
709 }
710
711 pint[bank]->request = pintbit;
712 pint[bank]->mask_clear = pintbit;
713 }
714
715 static void bfin_gpio_mask_irq(unsigned int irq)
716 {
717 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
718
719 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
720 }
721
722 static void bfin_gpio_unmask_irq(unsigned int irq)
723 {
724 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
725 u32 pintbit = PINT_BIT(pint_val);
726 u32 bank = PINT_2_BANK(pint_val);
727
728 pint[bank]->request = pintbit;
729 pint[bank]->mask_set = pintbit;
730 }
731
732 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
733 {
734 u32 gpionr = irq_to_gpio(irq);
735 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
736
737 if (pint_val == IRQ_NOT_AVAIL) {
738 printk(KERN_ERR
739 "GPIO IRQ %d :Not in PINT Assign table "
740 "Reconfigure Interrupt to Port Assignemt\n", irq);
741 return -ENODEV;
742 }
743
744 if (__test_and_set_bit(gpionr, gpio_enabled))
745 bfin_gpio_irq_prepare(gpionr);
746
747 bfin_gpio_unmask_irq(irq);
748
749 return 0;
750 }
751
752 static void bfin_gpio_irq_shutdown(unsigned int irq)
753 {
754 u32 gpionr = irq_to_gpio(irq);
755
756 bfin_gpio_mask_irq(irq);
757 __clear_bit(gpionr, gpio_enabled);
758 bfin_gpio_irq_free(gpionr);
759 }
760
761 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
762 {
763 int ret;
764 char buf[16];
765 u32 gpionr = irq_to_gpio(irq);
766 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
767 u32 pintbit = PINT_BIT(pint_val);
768 u32 bank = PINT_2_BANK(pint_val);
769
770 if (pint_val == IRQ_NOT_AVAIL)
771 return -ENODEV;
772
773 if (type == IRQ_TYPE_PROBE) {
774 /* only probe unenabled GPIO interrupt lines */
775 if (__test_bit(gpionr, gpio_enabled))
776 return 0;
777 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
778 }
779
780 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
781 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
782
783 snprintf(buf, 16, "gpio-irq%d", irq);
784 ret = bfin_gpio_irq_request(gpionr, buf);
785 if (ret)
786 return ret;
787
788 if (__test_and_set_bit(gpionr, gpio_enabled))
789 bfin_gpio_irq_prepare(gpionr);
790
791 } else {
792 __clear_bit(gpionr, gpio_enabled);
793 return 0;
794 }
795
796 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
797 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
798 else
799 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
800
801 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
802 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
803 if (gpio_get_value(gpionr))
804 pint[bank]->invert_set = pintbit;
805 else
806 pint[bank]->invert_clear = pintbit;
807 }
808
809 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
810 pint[bank]->edge_set = pintbit;
811 bfin_set_irq_handler(irq, handle_edge_irq);
812 } else {
813 pint[bank]->edge_clear = pintbit;
814 bfin_set_irq_handler(irq, handle_level_irq);
815 }
816
817 return 0;
818 }
819
820 #ifdef CONFIG_PM
821 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
822 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
823
824 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
825 {
826 u32 pint_irq;
827 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
828 u32 bank = PINT_2_BANK(pint_val);
829 u32 pintbit = PINT_BIT(pint_val);
830
831 switch (bank) {
832 case 0:
833 pint_irq = IRQ_PINT0;
834 break;
835 case 2:
836 pint_irq = IRQ_PINT2;
837 break;
838 case 3:
839 pint_irq = IRQ_PINT3;
840 break;
841 case 1:
842 pint_irq = IRQ_PINT1;
843 break;
844 default:
845 return -EINVAL;
846 }
847
848 bfin_internal_set_wake(pint_irq, state);
849
850 if (state)
851 pint_wakeup_masks[bank] |= pintbit;
852 else
853 pint_wakeup_masks[bank] &= ~pintbit;
854
855 return 0;
856 }
857
858 u32 bfin_pm_setup(void)
859 {
860 u32 val, i;
861
862 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
863 val = pint[i]->mask_clear;
864 pint_saved_masks[i] = val;
865 if (val ^ pint_wakeup_masks[i]) {
866 pint[i]->mask_clear = val;
867 pint[i]->mask_set = pint_wakeup_masks[i];
868 }
869 }
870
871 return 0;
872 }
873
874 void bfin_pm_restore(void)
875 {
876 u32 i, val;
877
878 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
879 val = pint_saved_masks[i];
880 if (val ^ pint_wakeup_masks[i]) {
881 pint[i]->mask_clear = pint[i]->mask_clear;
882 pint[i]->mask_set = val;
883 }
884 }
885 }
886 #endif
887
888 static void bfin_demux_gpio_irq(unsigned int inta_irq,
889 struct irq_desc *desc)
890 {
891 u32 bank, pint_val;
892 u32 request, irq;
893
894 switch (inta_irq) {
895 case IRQ_PINT0:
896 bank = 0;
897 break;
898 case IRQ_PINT2:
899 bank = 2;
900 break;
901 case IRQ_PINT3:
902 bank = 3;
903 break;
904 case IRQ_PINT1:
905 bank = 1;
906 break;
907 default:
908 return;
909 }
910
911 pint_val = bank * NR_PINT_BITS;
912
913 request = pint[bank]->request;
914
915 while (request) {
916 if (request & 1) {
917 irq = pint2irq_lut[pint_val] + SYS_IRQS;
918 bfin_handle_irq(irq);
919 }
920 pint_val++;
921 request >>= 1;
922 }
923
924 }
925 #endif
926
927 static struct irq_chip bfin_gpio_irqchip = {
928 .name = "GPIO",
929 .ack = bfin_gpio_ack_irq,
930 .mask = bfin_gpio_mask_irq,
931 .mask_ack = bfin_gpio_mask_ack_irq,
932 .unmask = bfin_gpio_unmask_irq,
933 .disable = bfin_gpio_mask_irq,
934 .enable = bfin_gpio_unmask_irq,
935 .set_type = bfin_gpio_irq_type,
936 .startup = bfin_gpio_irq_startup,
937 .shutdown = bfin_gpio_irq_shutdown,
938 #ifdef CONFIG_PM
939 .set_wake = bfin_gpio_set_wake,
940 #endif
941 };
942
943 void __cpuinit init_exception_vectors(void)
944 {
945 /* cannot program in software:
946 * evt0 - emulation (jtag)
947 * evt1 - reset
948 */
949 bfin_write_EVT2(evt_nmi);
950 bfin_write_EVT3(trap);
951 bfin_write_EVT5(evt_ivhw);
952 bfin_write_EVT6(evt_timer);
953 bfin_write_EVT7(evt_evt7);
954 bfin_write_EVT8(evt_evt8);
955 bfin_write_EVT9(evt_evt9);
956 bfin_write_EVT10(evt_evt10);
957 bfin_write_EVT11(evt_evt11);
958 bfin_write_EVT12(evt_evt12);
959 bfin_write_EVT13(evt_evt13);
960 bfin_write_EVT14(evt14_softirq);
961 bfin_write_EVT15(evt_system_call);
962 CSYNC();
963 }
964
965 /*
966 * This function should be called during kernel startup to initialize
967 * the BFin IRQ handling routines.
968 */
969
970 int __init init_arch_irq(void)
971 {
972 int irq;
973 unsigned long ilat = 0;
974 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
975 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
976 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
977 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
978 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
979 # ifdef CONFIG_BF54x
980 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
981 # endif
982 # ifdef CONFIG_SMP
983 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
984 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
985 # endif
986 #else
987 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
988 #endif
989
990 local_irq_disable();
991
992 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
993 /* Clear EMAC Interrupt Status bits so we can demux it later */
994 bfin_write_EMAC_SYSTAT(-1);
995 #endif
996
997 #ifdef CONFIG_BF54x
998 # ifdef CONFIG_PINTx_REASSIGN
999 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1000 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1001 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1002 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1003 # endif
1004 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1005 init_pint_lut();
1006 #endif
1007
1008 for (irq = 0; irq <= SYS_IRQS; irq++) {
1009 if (irq <= IRQ_CORETMR)
1010 set_irq_chip(irq, &bfin_core_irqchip);
1011 else
1012 set_irq_chip(irq, &bfin_internal_irqchip);
1013
1014 switch (irq) {
1015 #if defined(CONFIG_BF53x)
1016 case IRQ_PROG_INTA:
1017 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1018 case IRQ_MAC_RX:
1019 # endif
1020 #elif defined(CONFIG_BF54x)
1021 case IRQ_PINT0:
1022 case IRQ_PINT1:
1023 case IRQ_PINT2:
1024 case IRQ_PINT3:
1025 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1026 case IRQ_PORTF_INTA:
1027 case IRQ_PORTG_INTA:
1028 case IRQ_PORTH_INTA:
1029 #elif defined(CONFIG_BF561)
1030 case IRQ_PROG0_INTA:
1031 case IRQ_PROG1_INTA:
1032 case IRQ_PROG2_INTA:
1033 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1034 case IRQ_PORTF_INTA:
1035 #endif
1036
1037 set_irq_chained_handler(irq,
1038 bfin_demux_gpio_irq);
1039 break;
1040 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1041 case IRQ_GENERIC_ERROR:
1042 set_irq_chained_handler(irq, bfin_demux_error_irq);
1043 break;
1044 #endif
1045 #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
1046 case IRQ_TIMER0:
1047 set_irq_handler(irq, handle_percpu_irq);
1048 break;
1049 #endif
1050 #ifdef CONFIG_SMP
1051 case IRQ_SUPPLE_0:
1052 case IRQ_SUPPLE_1:
1053 set_irq_handler(irq, handle_percpu_irq);
1054 break;
1055 #endif
1056 default:
1057 #ifdef CONFIG_IPIPE
1058 /*
1059 * We want internal interrupt sources to be masked, because
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but
1061 * interrupts are _not_ masked at CPU level. So let's handle
1062 * them as level interrupts.
1063 */
1064 set_irq_handler(irq, handle_level_irq);
1065 #else /* !CONFIG_IPIPE */
1066 set_irq_handler(irq, handle_simple_irq);
1067 #endif /* !CONFIG_IPIPE */
1068 break;
1069 }
1070 }
1071
1072 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1073 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1074 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1075 handle_level_irq);
1076 #endif
1077
1078 /* if configured as edge, then will be changed to do_edge_IRQ */
1079 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1080 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1081 handle_level_irq);
1082
1083
1084 bfin_write_IMASK(0);
1085 CSYNC();
1086 ilat = bfin_read_ILAT();
1087 CSYNC();
1088 bfin_write_ILAT(ilat);
1089 CSYNC();
1090
1091 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1092 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1093 * local_irq_enable()
1094 */
1095 program_IAR();
1096 /* Therefore it's better to setup IARs before interrupts enabled */
1097 search_IAR();
1098
1099 /* Enable interrupts IVG7-15 */
1100 bfin_irq_flags |= IMASK_IVG15 |
1101 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1102 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1103
1104 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1105 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1106 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1107 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1108 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1109 * will screw up the bootrom as it relies on MDMA0/1 waking it
1110 * up from IDLE instructions. See this report for more info:
1111 * http://blackfin.uclinux.org/gf/tracker/4323
1112 */
1113 if (ANOMALY_05000435)
1114 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1115 else
1116 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1117 #else
1118 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1119 #endif
1120 # ifdef CONFIG_BF54x
1121 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1122 # endif
1123 #else
1124 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1125 #endif
1126
1127 #ifdef CONFIG_IPIPE
1128 for (irq = 0; irq < NR_IRQS; irq++) {
1129 struct irq_desc *desc = irq_desc + irq;
1130 desc->ic_prio = __ipipe_get_irq_priority(irq);
1131 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1132 }
1133 #endif /* CONFIG_IPIPE */
1134
1135 return 0;
1136 }
1137
1138 #ifdef CONFIG_DO_IRQ_L1
1139 __attribute__((l1_text))
1140 #endif
1141 void do_irq(int vec, struct pt_regs *fp)
1142 {
1143 if (vec == EVT_IVTMR_P) {
1144 vec = IRQ_CORETMR;
1145 } else {
1146 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1147 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1148 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1149 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1150 unsigned long sic_status[3];
1151
1152 if (smp_processor_id()) {
1153 #ifdef CONFIG_SMP
1154 /* This will be optimized out in UP mode. */
1155 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1156 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1157 #endif
1158 } else {
1159 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1160 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1161 }
1162 #ifdef CONFIG_BF54x
1163 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1164 #endif
1165 for (;; ivg++) {
1166 if (ivg >= ivg_stop) {
1167 atomic_inc(&num_spurious);
1168 return;
1169 }
1170 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1171 break;
1172 }
1173 #else
1174 unsigned long sic_status;
1175
1176 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1177
1178 for (;; ivg++) {
1179 if (ivg >= ivg_stop) {
1180 atomic_inc(&num_spurious);
1181 return;
1182 } else if (sic_status & ivg->isrflag)
1183 break;
1184 }
1185 #endif
1186 vec = ivg->irqno;
1187 }
1188 asm_do_IRQ(vec, fp);
1189 }
1190
1191 #ifdef CONFIG_IPIPE
1192
1193 int __ipipe_get_irq_priority(unsigned irq)
1194 {
1195 int ient, prio;
1196
1197 if (irq <= IRQ_CORETMR)
1198 return irq;
1199
1200 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1201 struct ivgx *ivg = ivg_table + ient;
1202 if (ivg->irqno == irq) {
1203 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1204 if (ivg7_13[prio].ifirst <= ivg &&
1205 ivg7_13[prio].istop > ivg)
1206 return IVG7 + prio;
1207 }
1208 }
1209 }
1210
1211 return IVG15;
1212 }
1213
1214 int __ipipe_get_irqthread_priority(unsigned irq)
1215 {
1216 int ient, prio;
1217 int demux_irq;
1218
1219 /* The returned priority value is rescaled to [0..IVG13+1]
1220 * with 0 being the lowest effective priority level. */
1221
1222 if (irq <= IRQ_CORETMR)
1223 return IVG13 - irq + 1;
1224
1225 /* GPIO IRQs are given the priority of the demux
1226 * interrupt. */
1227 if (IS_GPIOIRQ(irq)) {
1228 #if defined(CONFIG_BF54x)
1229 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1230 demux_irq = (bank == 0 ? IRQ_PINT0 :
1231 bank == 1 ? IRQ_PINT1 :
1232 bank == 2 ? IRQ_PINT2 :
1233 IRQ_PINT3);
1234 #elif defined(CONFIG_BF561)
1235 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1236 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1237 IRQ_PROG0_INTA);
1238 #elif defined(CONFIG_BF52x)
1239 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1240 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1241 IRQ_PORTF_INTA);
1242 #else
1243 demux_irq = irq;
1244 #endif
1245 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1246 }
1247
1248 /* The GPIO demux interrupt is given a lower priority
1249 * than the GPIO IRQs, so that its threaded handler
1250 * unmasks the interrupt line after the decoded IRQs
1251 * have been processed. */
1252 prio = PRIO_GPIODEMUX(irq);
1253 /* demux irq? */
1254 if (prio != -1)
1255 return IVG13 - prio;
1256
1257 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1258 struct ivgx *ivg = ivg_table + ient;
1259 if (ivg->irqno == irq) {
1260 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1261 if (ivg7_13[prio].ifirst <= ivg &&
1262 ivg7_13[prio].istop > ivg)
1263 return IVG7 - prio;
1264 }
1265 }
1266 }
1267
1268 return 0;
1269 }
1270
1271 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1272 #ifdef CONFIG_DO_IRQ_L1
1273 __attribute__((l1_text))
1274 #endif
1275 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1276 {
1277 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1278 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1279 int irq;
1280
1281 if (likely(vec == EVT_IVTMR_P)) {
1282 irq = IRQ_CORETMR;
1283 goto handle_irq;
1284 }
1285
1286 SSYNC();
1287
1288 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1289 {
1290 unsigned long sic_status[3];
1291
1292 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1293 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1294 #ifdef CONFIG_BF54x
1295 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1296 #endif
1297 for (;; ivg++) {
1298 if (ivg >= ivg_stop) {
1299 atomic_inc(&num_spurious);
1300 return 0;
1301 }
1302 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1303 break;
1304 }
1305 }
1306 #else
1307 {
1308 unsigned long sic_status;
1309
1310 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1311
1312 for (;; ivg++) {
1313 if (ivg >= ivg_stop) {
1314 atomic_inc(&num_spurious);
1315 return 0;
1316 } else if (sic_status & ivg->isrflag)
1317 break;
1318 }
1319 }
1320 #endif
1321
1322 irq = ivg->irqno;
1323
1324 if (irq == IRQ_SYSTMR) {
1325 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1326 /* This is basically what we need from the register frame. */
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1328 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1329 if (!ipipe_root_domain_p)
1330 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1331 else
1332 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1333 }
1334
1335 handle_irq:
1336
1337 ipipe_trace_irq_entry(irq);
1338 __ipipe_handle_irq(irq, regs);
1339 ipipe_trace_irq_exit(irq);
1340
1341 if (ipipe_root_domain_p)
1342 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
1343
1344 return 0;
1345 }
1346
1347 #endif /* CONFIG_IPIPE */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree