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KVM: x86: Move TSC reset out of vmcb_init
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob6a2321136f28d6edf1ed1e4af19d857ca1e50288
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/tlbflush.h>
31 #include <asm/desc.h>
32
33 #include <asm/virtext.h>
34 #include "trace.h"
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
43
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
46
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50
51 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
57 /* Turn on to get debugging output*/
58 /* #define NESTED_DEBUG */
59
60 #ifdef NESTED_DEBUG
61 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
62 #else
63 #define nsvm_printk(fmt, args...) do {} while(0)
64 #endif
65
66 static bool erratum_383_found __read_mostly;
67
68 static const u32 host_save_user_msrs[] = {
69 #ifdef CONFIG_X86_64
70 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
71 MSR_FS_BASE,
72 #endif
73 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
74 };
75
76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77
78 struct kvm_vcpu;
79
80 struct nested_state {
81 struct vmcb *hsave;
82 u64 hsave_msr;
83 u64 vmcb;
84
85 /* These are the merged vectors */
86 u32 *msrpm;
87
88 /* gpa pointers to the real vectors */
89 u64 vmcb_msrpm;
90
91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
99 };
100
101 struct vcpu_svm {
102 struct kvm_vcpu vcpu;
103 struct vmcb *vmcb;
104 unsigned long vmcb_pa;
105 struct svm_cpu_data *svm_data;
106 uint64_t asid_generation;
107 uint64_t sysenter_esp;
108 uint64_t sysenter_eip;
109
110 u64 next_rip;
111
112 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
113 u64 host_gs_base;
114
115 u32 *msrpm;
116
117 struct nested_state nested;
118 };
119
120 /* enable NPT for AMD64 and X86 with PAE */
121 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
122 static bool npt_enabled = true;
123 #else
124 static bool npt_enabled = false;
125 #endif
126 static int npt = 1;
127
128 module_param(npt, int, S_IRUGO);
129
130 static int nested = 1;
131 module_param(nested, int, S_IRUGO);
132
133 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
134 static void svm_complete_interrupts(struct vcpu_svm *svm);
135
136 static int nested_svm_exit_handled(struct vcpu_svm *svm);
137 static int nested_svm_vmexit(struct vcpu_svm *svm);
138 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
139 bool has_error_code, u32 error_code);
140
141 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
142 {
143 return container_of(vcpu, struct vcpu_svm, vcpu);
144 }
145
146 static inline bool is_nested(struct vcpu_svm *svm)
147 {
148 return svm->nested.vmcb;
149 }
150
151 static inline void enable_gif(struct vcpu_svm *svm)
152 {
153 svm->vcpu.arch.hflags |= HF_GIF_MASK;
154 }
155
156 static inline void disable_gif(struct vcpu_svm *svm)
157 {
158 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
159 }
160
161 static inline bool gif_set(struct vcpu_svm *svm)
162 {
163 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
164 }
165
166 static unsigned long iopm_base;
167
168 struct kvm_ldttss_desc {
169 u16 limit0;
170 u16 base0;
171 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
172 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
173 u32 base3;
174 u32 zero1;
175 } __attribute__((packed));
176
177 struct svm_cpu_data {
178 int cpu;
179
180 u64 asid_generation;
181 u32 max_asid;
182 u32 next_asid;
183 struct kvm_ldttss_desc *tss_desc;
184
185 struct page *save_area;
186 };
187
188 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
189 static uint32_t svm_features;
190
191 struct svm_init_data {
192 int cpu;
193 int r;
194 };
195
196 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
197
198 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
199 #define MSRS_RANGE_SIZE 2048
200 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
201
202 #define MAX_INST_SIZE 15
203
204 static inline u32 svm_has(u32 feat)
205 {
206 return svm_features & feat;
207 }
208
209 static inline void clgi(void)
210 {
211 asm volatile (__ex(SVM_CLGI));
212 }
213
214 static inline void stgi(void)
215 {
216 asm volatile (__ex(SVM_STGI));
217 }
218
219 static inline void invlpga(unsigned long addr, u32 asid)
220 {
221 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
222 }
223
224 static inline void force_new_asid(struct kvm_vcpu *vcpu)
225 {
226 to_svm(vcpu)->asid_generation--;
227 }
228
229 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
230 {
231 force_new_asid(vcpu);
232 }
233
234 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
235 {
236 if (!npt_enabled && !(efer & EFER_LMA))
237 efer &= ~EFER_LME;
238
239 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
240 vcpu->arch.shadow_efer = efer;
241 }
242
243 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
244 bool has_error_code, u32 error_code)
245 {
246 struct vcpu_svm *svm = to_svm(vcpu);
247
248 /* If we are within a nested VM we'd better #VMEXIT and let the
249 guest handle the exception */
250 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
251 return;
252
253 svm->vmcb->control.event_inj = nr
254 | SVM_EVTINJ_VALID
255 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
256 | SVM_EVTINJ_TYPE_EXEPT;
257 svm->vmcb->control.event_inj_err = error_code;
258 }
259
260 static int is_external_interrupt(u32 info)
261 {
262 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
263 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
264 }
265
266 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
267 {
268 struct vcpu_svm *svm = to_svm(vcpu);
269 u32 ret = 0;
270
271 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
272 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
273 return ret & mask;
274 }
275
276 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
277 {
278 struct vcpu_svm *svm = to_svm(vcpu);
279
280 if (mask == 0)
281 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
282 else
283 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
284
285 }
286
287 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
288 {
289 struct vcpu_svm *svm = to_svm(vcpu);
290
291 if (!svm->next_rip) {
292 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
293 EMULATE_DONE)
294 printk(KERN_DEBUG "%s: NOP\n", __func__);
295 return;
296 }
297 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
298 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
299 __func__, kvm_rip_read(vcpu), svm->next_rip);
300
301 kvm_rip_write(vcpu, svm->next_rip);
302 svm_set_interrupt_shadow(vcpu, 0);
303 }
304
305 static void svm_init_erratum_383(void)
306 {
307 u32 low, high;
308 int err;
309 u64 val;
310
311 /* Only Fam10h is affected */
312 if (boot_cpu_data.x86 != 0x10)
313 return;
314
315 /* Use _safe variants to not break nested virtualization */
316 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
317 if (err)
318 return;
319
320 val |= (1ULL << 47);
321
322 low = lower_32_bits(val);
323 high = upper_32_bits(val);
324
325 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
326
327 erratum_383_found = true;
328 }
329
330 static int has_svm(void)
331 {
332 const char *msg;
333
334 if (!cpu_has_svm(&msg)) {
335 printk(KERN_INFO "has_svm: %s\n", msg);
336 return 0;
337 }
338
339 return 1;
340 }
341
342 static void svm_hardware_disable(void *garbage)
343 {
344 cpu_svm_disable();
345 }
346
347 static void svm_hardware_enable(void *garbage)
348 {
349 struct svm_cpu_data *svm_data;
350 uint64_t efer;
351 struct descriptor_table gdt_descr;
352 struct desc_struct *gdt;
353 int me = raw_smp_processor_id();
354
355 if (!has_svm()) {
356 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
357 return;
358 }
359 svm_data = per_cpu(svm_data, me);
360
361 if (!svm_data) {
362 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
363 me);
364 return;
365 }
366
367 svm_data->asid_generation = 1;
368 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
369 svm_data->next_asid = svm_data->max_asid + 1;
370
371 kvm_get_gdt(&gdt_descr);
372 gdt = (struct desc_struct *)gdt_descr.base;
373 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
374
375 rdmsrl(MSR_EFER, efer);
376 wrmsrl(MSR_EFER, efer | EFER_SVME);
377
378 wrmsrl(MSR_VM_HSAVE_PA,
379 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
380
381 svm_init_erratum_383();
382
383 return;
384 }
385
386 static void svm_cpu_uninit(int cpu)
387 {
388 struct svm_cpu_data *svm_data
389 = per_cpu(svm_data, raw_smp_processor_id());
390
391 if (!svm_data)
392 return;
393
394 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
395 __free_page(svm_data->save_area);
396 kfree(svm_data);
397 }
398
399 static int svm_cpu_init(int cpu)
400 {
401 struct svm_cpu_data *svm_data;
402 int r;
403
404 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
405 if (!svm_data)
406 return -ENOMEM;
407 svm_data->cpu = cpu;
408 svm_data->save_area = alloc_page(GFP_KERNEL);
409 r = -ENOMEM;
410 if (!svm_data->save_area)
411 goto err_1;
412
413 per_cpu(svm_data, cpu) = svm_data;
414
415 return 0;
416
417 err_1:
418 kfree(svm_data);
419 return r;
420
421 }
422
423 static void set_msr_interception(u32 *msrpm, unsigned msr,
424 int read, int write)
425 {
426 int i;
427
428 for (i = 0; i < NUM_MSR_MAPS; i++) {
429 if (msr >= msrpm_ranges[i] &&
430 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
431 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
432 msrpm_ranges[i]) * 2;
433
434 u32 *base = msrpm + (msr_offset / 32);
435 u32 msr_shift = msr_offset % 32;
436 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
437 *base = (*base & ~(0x3 << msr_shift)) |
438 (mask << msr_shift);
439 return;
440 }
441 }
442 BUG();
443 }
444
445 static void svm_vcpu_init_msrpm(u32 *msrpm)
446 {
447 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
448
449 #ifdef CONFIG_X86_64
450 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
451 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
452 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
453 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
454 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
455 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
456 #endif
457 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
458 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
459 }
460
461 static void svm_enable_lbrv(struct vcpu_svm *svm)
462 {
463 u32 *msrpm = svm->msrpm;
464
465 svm->vmcb->control.lbr_ctl = 1;
466 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
467 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
468 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
469 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
470 }
471
472 static void svm_disable_lbrv(struct vcpu_svm *svm)
473 {
474 u32 *msrpm = svm->msrpm;
475
476 svm->vmcb->control.lbr_ctl = 0;
477 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
478 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
479 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
480 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
481 }
482
483 static __init int svm_hardware_setup(void)
484 {
485 int cpu;
486 struct page *iopm_pages;
487 void *iopm_va;
488 int r;
489
490 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
491
492 if (!iopm_pages)
493 return -ENOMEM;
494
495 iopm_va = page_address(iopm_pages);
496 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
497 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
498
499 if (boot_cpu_has(X86_FEATURE_NX))
500 kvm_enable_efer_bits(EFER_NX);
501
502 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
503 kvm_enable_efer_bits(EFER_FFXSR);
504
505 if (nested) {
506 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
507 kvm_enable_efer_bits(EFER_SVME);
508 }
509
510 for_each_online_cpu(cpu) {
511 r = svm_cpu_init(cpu);
512 if (r)
513 goto err;
514 }
515
516 svm_features = cpuid_edx(SVM_CPUID_FUNC);
517
518 if (!svm_has(SVM_FEATURE_NPT))
519 npt_enabled = false;
520
521 if (npt_enabled && !npt) {
522 printk(KERN_INFO "kvm: Nested Paging disabled\n");
523 npt_enabled = false;
524 }
525
526 if (npt_enabled) {
527 printk(KERN_INFO "kvm: Nested Paging enabled\n");
528 kvm_enable_tdp();
529 } else
530 kvm_disable_tdp();
531
532 return 0;
533
534 err:
535 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
536 iopm_base = 0;
537 return r;
538 }
539
540 static __exit void svm_hardware_unsetup(void)
541 {
542 int cpu;
543
544 for_each_online_cpu(cpu)
545 svm_cpu_uninit(cpu);
546
547 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
548 iopm_base = 0;
549 }
550
551 static void init_seg(struct vmcb_seg *seg)
552 {
553 seg->selector = 0;
554 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
555 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
556 seg->limit = 0xffff;
557 seg->base = 0;
558 }
559
560 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
561 {
562 seg->selector = 0;
563 seg->attrib = SVM_SELECTOR_P_MASK | type;
564 seg->limit = 0xffff;
565 seg->base = 0;
566 }
567
568 static void init_vmcb(struct vcpu_svm *svm)
569 {
570 struct vmcb_control_area *control = &svm->vmcb->control;
571 struct vmcb_save_area *save = &svm->vmcb->save;
572
573 control->intercept_cr_read = INTERCEPT_CR0_MASK |
574 INTERCEPT_CR3_MASK |
575 INTERCEPT_CR4_MASK;
576
577 control->intercept_cr_write = INTERCEPT_CR0_MASK |
578 INTERCEPT_CR3_MASK |
579 INTERCEPT_CR4_MASK |
580 INTERCEPT_CR8_MASK;
581
582 control->intercept_dr_read = INTERCEPT_DR0_MASK |
583 INTERCEPT_DR1_MASK |
584 INTERCEPT_DR2_MASK |
585 INTERCEPT_DR3_MASK;
586
587 control->intercept_dr_write = INTERCEPT_DR0_MASK |
588 INTERCEPT_DR1_MASK |
589 INTERCEPT_DR2_MASK |
590 INTERCEPT_DR3_MASK |
591 INTERCEPT_DR5_MASK |
592 INTERCEPT_DR7_MASK;
593
594 control->intercept_exceptions = (1 << PF_VECTOR) |
595 (1 << UD_VECTOR) |
596 (1 << MC_VECTOR);
597
598
599 control->intercept = (1ULL << INTERCEPT_INTR) |
600 (1ULL << INTERCEPT_NMI) |
601 (1ULL << INTERCEPT_SMI) |
602 (1ULL << INTERCEPT_CPUID) |
603 (1ULL << INTERCEPT_INVD) |
604 (1ULL << INTERCEPT_HLT) |
605 (1ULL << INTERCEPT_INVLPG) |
606 (1ULL << INTERCEPT_INVLPGA) |
607 (1ULL << INTERCEPT_IOIO_PROT) |
608 (1ULL << INTERCEPT_MSR_PROT) |
609 (1ULL << INTERCEPT_TASK_SWITCH) |
610 (1ULL << INTERCEPT_SHUTDOWN) |
611 (1ULL << INTERCEPT_VMRUN) |
612 (1ULL << INTERCEPT_VMMCALL) |
613 (1ULL << INTERCEPT_VMLOAD) |
614 (1ULL << INTERCEPT_VMSAVE) |
615 (1ULL << INTERCEPT_STGI) |
616 (1ULL << INTERCEPT_CLGI) |
617 (1ULL << INTERCEPT_SKINIT) |
618 (1ULL << INTERCEPT_WBINVD) |
619 (1ULL << INTERCEPT_MONITOR) |
620 (1ULL << INTERCEPT_MWAIT);
621
622 control->iopm_base_pa = iopm_base;
623 control->msrpm_base_pa = __pa(svm->msrpm);
624 control->int_ctl = V_INTR_MASKING_MASK;
625
626 init_seg(&save->es);
627 init_seg(&save->ss);
628 init_seg(&save->ds);
629 init_seg(&save->fs);
630 init_seg(&save->gs);
631
632 save->cs.selector = 0xf000;
633 /* Executable/Readable Code Segment */
634 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
635 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
636 save->cs.limit = 0xffff;
637 /*
638 * cs.base should really be 0xffff0000, but vmx can't handle that, so
639 * be consistent with it.
640 *
641 * Replace when we have real mode working for vmx.
642 */
643 save->cs.base = 0xf0000;
644
645 save->gdtr.limit = 0xffff;
646 save->idtr.limit = 0xffff;
647
648 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
649 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
650
651 save->efer = EFER_SVME;
652 save->dr6 = 0xffff0ff0;
653 save->dr7 = 0x400;
654 save->rflags = 2;
655 save->rip = 0x0000fff0;
656 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
657
658 /* This is the guest-visible cr0 value.
659 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
660 */
661 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
662 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
663
664 save->cr4 = X86_CR4_PAE;
665 /* rdx = ?? */
666
667 if (npt_enabled) {
668 /* Setup VMCB for Nested Paging */
669 control->nested_ctl = 1;
670 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
671 (1ULL << INTERCEPT_INVLPG));
672 control->intercept_exceptions &= ~(1 << PF_VECTOR);
673 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
674 INTERCEPT_CR3_MASK);
675 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
676 INTERCEPT_CR3_MASK);
677 save->g_pat = 0x0007040600070406ULL;
678 /* enable caching because the QEMU Bios doesn't enable it */
679 save->cr0 = X86_CR0_ET;
680 save->cr3 = 0;
681 save->cr4 = 0;
682 }
683 force_new_asid(&svm->vcpu);
684
685 svm->nested.vmcb = 0;
686 svm->vcpu.arch.hflags = 0;
687
688 enable_gif(svm);
689 }
690
691 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
692 {
693 struct vcpu_svm *svm = to_svm(vcpu);
694
695 init_vmcb(svm);
696
697 if (!kvm_vcpu_is_bsp(vcpu)) {
698 kvm_rip_write(vcpu, 0);
699 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
700 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
701 }
702 vcpu->arch.regs_avail = ~0;
703 vcpu->arch.regs_dirty = ~0;
704
705 return 0;
706 }
707
708 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
709 {
710 struct vcpu_svm *svm;
711 struct page *page;
712 struct page *msrpm_pages;
713 struct page *hsave_page;
714 struct page *nested_msrpm_pages;
715 int err;
716
717 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
718 if (!svm) {
719 err = -ENOMEM;
720 goto out;
721 }
722
723 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
724 if (err)
725 goto free_svm;
726
727 err = -ENOMEM;
728 page = alloc_page(GFP_KERNEL);
729 if (!page)
730 goto uninit;
731
732 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
733 if (!msrpm_pages)
734 goto free_page1;
735
736 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
737 if (!nested_msrpm_pages)
738 goto free_page2;
739
740 hsave_page = alloc_page(GFP_KERNEL);
741 if (!hsave_page)
742 goto free_page3;
743
744 svm->nested.hsave = page_address(hsave_page);
745
746 svm->msrpm = page_address(msrpm_pages);
747 svm_vcpu_init_msrpm(svm->msrpm);
748
749 svm->nested.msrpm = page_address(nested_msrpm_pages);
750
751 svm->vmcb = page_address(page);
752 clear_page(svm->vmcb);
753 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
754 svm->asid_generation = 0;
755 init_vmcb(svm);
756 svm->vmcb->control.tsc_offset = 0-native_read_tsc();
757
758 fx_init(&svm->vcpu);
759 svm->vcpu.fpu_active = 1;
760 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
761 if (kvm_vcpu_is_bsp(&svm->vcpu))
762 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
763
764 return &svm->vcpu;
765
766 free_page3:
767 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
768 free_page2:
769 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
770 free_page1:
771 __free_page(page);
772 uninit:
773 kvm_vcpu_uninit(&svm->vcpu);
774 free_svm:
775 kmem_cache_free(kvm_vcpu_cache, svm);
776 out:
777 return ERR_PTR(err);
778 }
779
780 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
781 {
782 struct vcpu_svm *svm = to_svm(vcpu);
783
784 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
785 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
786 __free_page(virt_to_page(svm->nested.hsave));
787 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
788 kvm_vcpu_uninit(vcpu);
789 kmem_cache_free(kvm_vcpu_cache, svm);
790 }
791
792 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
793 {
794 struct vcpu_svm *svm = to_svm(vcpu);
795 int i;
796
797 if (unlikely(cpu != vcpu->cpu)) {
798 u64 delta;
799
800 if (check_tsc_unstable()) {
801 /*
802 * Make sure that the guest sees a monotonically
803 * increasing TSC.
804 */
805 delta = vcpu->arch.host_tsc - native_read_tsc();
806 svm->vmcb->control.tsc_offset += delta;
807 if (is_nested(svm))
808 svm->nested.hsave->control.tsc_offset += delta;
809 }
810 vcpu->cpu = cpu;
811 kvm_migrate_timers(vcpu);
812 svm->asid_generation = 0;
813 }
814
815 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
816 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
817 }
818
819 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
820 {
821 struct vcpu_svm *svm = to_svm(vcpu);
822 int i;
823
824 ++vcpu->stat.host_state_reload;
825 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
826 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
827
828 rdtscll(vcpu->arch.host_tsc);
829 }
830
831 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
832 {
833 return to_svm(vcpu)->vmcb->save.rflags;
834 }
835
836 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
837 {
838 to_svm(vcpu)->vmcb->save.rflags = rflags;
839 }
840
841 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
842 {
843 switch (reg) {
844 case VCPU_EXREG_PDPTR:
845 BUG_ON(!npt_enabled);
846 load_pdptrs(vcpu, vcpu->arch.cr3);
847 break;
848 default:
849 BUG();
850 }
851 }
852
853 static void svm_set_vintr(struct vcpu_svm *svm)
854 {
855 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
856 }
857
858 static void svm_clear_vintr(struct vcpu_svm *svm)
859 {
860 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
861 }
862
863 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
864 {
865 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
866
867 switch (seg) {
868 case VCPU_SREG_CS: return &save->cs;
869 case VCPU_SREG_DS: return &save->ds;
870 case VCPU_SREG_ES: return &save->es;
871 case VCPU_SREG_FS: return &save->fs;
872 case VCPU_SREG_GS: return &save->gs;
873 case VCPU_SREG_SS: return &save->ss;
874 case VCPU_SREG_TR: return &save->tr;
875 case VCPU_SREG_LDTR: return &save->ldtr;
876 }
877 BUG();
878 return NULL;
879 }
880
881 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
882 {
883 struct vmcb_seg *s = svm_seg(vcpu, seg);
884
885 return s->base;
886 }
887
888 static void svm_get_segment(struct kvm_vcpu *vcpu,
889 struct kvm_segment *var, int seg)
890 {
891 struct vmcb_seg *s = svm_seg(vcpu, seg);
892
893 var->base = s->base;
894 var->limit = s->limit;
895 var->selector = s->selector;
896 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
897 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
898 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
899 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
900 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
901 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
902 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
903 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
904
905 /* AMD's VMCB does not have an explicit unusable field, so emulate it
906 * for cross vendor migration purposes by "not present"
907 */
908 var->unusable = !var->present || (var->type == 0);
909
910 switch (seg) {
911 case VCPU_SREG_CS:
912 /*
913 * SVM always stores 0 for the 'G' bit in the CS selector in
914 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
915 * Intel's VMENTRY has a check on the 'G' bit.
916 */
917 var->g = s->limit > 0xfffff;
918 break;
919 case VCPU_SREG_TR:
920 /*
921 * Work around a bug where the busy flag in the tr selector
922 * isn't exposed
923 */
924 var->type |= 0x2;
925 break;
926 case VCPU_SREG_DS:
927 case VCPU_SREG_ES:
928 case VCPU_SREG_FS:
929 case VCPU_SREG_GS:
930 /*
931 * The accessed bit must always be set in the segment
932 * descriptor cache, although it can be cleared in the
933 * descriptor, the cached bit always remains at 1. Since
934 * Intel has a check on this, set it here to support
935 * cross-vendor migration.
936 */
937 if (!var->unusable)
938 var->type |= 0x1;
939 break;
940 case VCPU_SREG_SS:
941 /* On AMD CPUs sometimes the DB bit in the segment
942 * descriptor is left as 1, although the whole segment has
943 * been made unusable. Clear it here to pass an Intel VMX
944 * entry check when cross vendor migrating.
945 */
946 if (var->unusable)
947 var->db = 0;
948 break;
949 }
950 }
951
952 static int svm_get_cpl(struct kvm_vcpu *vcpu)
953 {
954 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
955
956 return save->cpl;
957 }
958
959 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
960 {
961 struct vcpu_svm *svm = to_svm(vcpu);
962
963 dt->limit = svm->vmcb->save.idtr.limit;
964 dt->base = svm->vmcb->save.idtr.base;
965 }
966
967 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
968 {
969 struct vcpu_svm *svm = to_svm(vcpu);
970
971 svm->vmcb->save.idtr.limit = dt->limit;
972 svm->vmcb->save.idtr.base = dt->base ;
973 }
974
975 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
976 {
977 struct vcpu_svm *svm = to_svm(vcpu);
978
979 dt->limit = svm->vmcb->save.gdtr.limit;
980 dt->base = svm->vmcb->save.gdtr.base;
981 }
982
983 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
984 {
985 struct vcpu_svm *svm = to_svm(vcpu);
986
987 svm->vmcb->save.gdtr.limit = dt->limit;
988 svm->vmcb->save.gdtr.base = dt->base ;
989 }
990
991 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
992 {
993 }
994
995 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
996 {
997 struct vcpu_svm *svm = to_svm(vcpu);
998
999 #ifdef CONFIG_X86_64
1000 if (vcpu->arch.shadow_efer & EFER_LME) {
1001 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1002 vcpu->arch.shadow_efer |= EFER_LMA;
1003 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1004 }
1005
1006 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1007 vcpu->arch.shadow_efer &= ~EFER_LMA;
1008 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1009 }
1010 }
1011 #endif
1012 if (npt_enabled)
1013 goto set;
1014
1015 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
1016 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1017 vcpu->fpu_active = 1;
1018 }
1019
1020 vcpu->arch.cr0 = cr0;
1021 cr0 |= X86_CR0_PG | X86_CR0_WP;
1022 if (!vcpu->fpu_active) {
1023 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1024 cr0 |= X86_CR0_TS;
1025 }
1026 set:
1027 /*
1028 * re-enable caching here because the QEMU bios
1029 * does not do it - this results in some delay at
1030 * reboot
1031 */
1032 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1033 svm->vmcb->save.cr0 = cr0;
1034 }
1035
1036 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1037 {
1038 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1039 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1040
1041 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1042 force_new_asid(vcpu);
1043
1044 vcpu->arch.cr4 = cr4;
1045 if (!npt_enabled)
1046 cr4 |= X86_CR4_PAE;
1047 cr4 |= host_cr4_mce;
1048 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1049 }
1050
1051 static void svm_set_segment(struct kvm_vcpu *vcpu,
1052 struct kvm_segment *var, int seg)
1053 {
1054 struct vcpu_svm *svm = to_svm(vcpu);
1055 struct vmcb_seg *s = svm_seg(vcpu, seg);
1056
1057 s->base = var->base;
1058 s->limit = var->limit;
1059 s->selector = var->selector;
1060 if (var->unusable)
1061 s->attrib = 0;
1062 else {
1063 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1064 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1065 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1066 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1067 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1068 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1069 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1070 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1071 }
1072 if (seg == VCPU_SREG_CS)
1073 svm->vmcb->save.cpl
1074 = (svm->vmcb->save.cs.attrib
1075 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1076
1077 }
1078
1079 static void update_db_intercept(struct kvm_vcpu *vcpu)
1080 {
1081 struct vcpu_svm *svm = to_svm(vcpu);
1082
1083 svm->vmcb->control.intercept_exceptions &=
1084 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1085
1086 if (vcpu->arch.singlestep)
1087 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1088
1089 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1090 if (vcpu->guest_debug &
1091 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1092 svm->vmcb->control.intercept_exceptions |=
1093 1 << DB_VECTOR;
1094 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1095 svm->vmcb->control.intercept_exceptions |=
1096 1 << BP_VECTOR;
1097 } else
1098 vcpu->guest_debug = 0;
1099 }
1100
1101 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1102 {
1103 int old_debug = vcpu->guest_debug;
1104 struct vcpu_svm *svm = to_svm(vcpu);
1105
1106 vcpu->guest_debug = dbg->control;
1107
1108 update_db_intercept(vcpu);
1109
1110 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1111 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1112 else
1113 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1114
1115 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1116 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1117 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1118 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1119
1120 return 0;
1121 }
1122
1123 static void load_host_msrs(struct kvm_vcpu *vcpu)
1124 {
1125 #ifdef CONFIG_X86_64
1126 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1127 #endif
1128 }
1129
1130 static void save_host_msrs(struct kvm_vcpu *vcpu)
1131 {
1132 #ifdef CONFIG_X86_64
1133 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1134 #endif
1135 }
1136
1137 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1138 {
1139 if (svm_data->next_asid > svm_data->max_asid) {
1140 ++svm_data->asid_generation;
1141 svm_data->next_asid = 1;
1142 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1143 }
1144
1145 svm->asid_generation = svm_data->asid_generation;
1146 svm->vmcb->control.asid = svm_data->next_asid++;
1147 }
1148
1149 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1150 {
1151 struct vcpu_svm *svm = to_svm(vcpu);
1152 unsigned long val;
1153
1154 switch (dr) {
1155 case 0 ... 3:
1156 val = vcpu->arch.db[dr];
1157 break;
1158 case 6:
1159 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1160 val = vcpu->arch.dr6;
1161 else
1162 val = svm->vmcb->save.dr6;
1163 break;
1164 case 7:
1165 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1166 val = vcpu->arch.dr7;
1167 else
1168 val = svm->vmcb->save.dr7;
1169 break;
1170 default:
1171 val = 0;
1172 }
1173
1174 return val;
1175 }
1176
1177 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1178 int *exception)
1179 {
1180 struct vcpu_svm *svm = to_svm(vcpu);
1181
1182 *exception = 0;
1183
1184 switch (dr) {
1185 case 0 ... 3:
1186 vcpu->arch.db[dr] = value;
1187 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1188 vcpu->arch.eff_db[dr] = value;
1189 return;
1190 case 4 ... 5:
1191 if (vcpu->arch.cr4 & X86_CR4_DE)
1192 *exception = UD_VECTOR;
1193 return;
1194 case 6:
1195 if (value & 0xffffffff00000000ULL) {
1196 *exception = GP_VECTOR;
1197 return;
1198 }
1199 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1200 return;
1201 case 7:
1202 if (value & 0xffffffff00000000ULL) {
1203 *exception = GP_VECTOR;
1204 return;
1205 }
1206 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1207 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1208 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1209 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1210 }
1211 return;
1212 default:
1213 /* FIXME: Possible case? */
1214 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1215 __func__, dr);
1216 *exception = UD_VECTOR;
1217 return;
1218 }
1219 }
1220
1221 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1222 {
1223 u64 fault_address;
1224 u32 error_code;
1225
1226 fault_address = svm->vmcb->control.exit_info_2;
1227 error_code = svm->vmcb->control.exit_info_1;
1228
1229 trace_kvm_page_fault(fault_address, error_code);
1230 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1231 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1232 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1233 }
1234
1235 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1236 {
1237 if (!(svm->vcpu.guest_debug &
1238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1239 !svm->vcpu.arch.singlestep) {
1240 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1241 return 1;
1242 }
1243
1244 if (svm->vcpu.arch.singlestep) {
1245 svm->vcpu.arch.singlestep = false;
1246 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1247 svm->vmcb->save.rflags &=
1248 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1249 update_db_intercept(&svm->vcpu);
1250 }
1251
1252 if (svm->vcpu.guest_debug &
1253 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1254 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1255 kvm_run->debug.arch.pc =
1256 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1257 kvm_run->debug.arch.exception = DB_VECTOR;
1258 return 0;
1259 }
1260
1261 return 1;
1262 }
1263
1264 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1265 {
1266 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1267 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1268 kvm_run->debug.arch.exception = BP_VECTOR;
1269 return 0;
1270 }
1271
1272 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1273 {
1274 int er;
1275
1276 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1277 if (er != EMULATE_DONE)
1278 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1279 return 1;
1280 }
1281
1282 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1283 {
1284 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1285 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1286 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1287 svm->vcpu.fpu_active = 1;
1288
1289 return 1;
1290 }
1291
1292 static bool is_erratum_383(void)
1293 {
1294 int err, i;
1295 u64 value;
1296
1297 if (!erratum_383_found)
1298 return false;
1299
1300 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1301 if (err)
1302 return false;
1303
1304 /* Bit 62 may or may not be set for this mce */
1305 value &= ~(1ULL << 62);
1306
1307 if (value != 0xb600000000010015ULL)
1308 return false;
1309
1310 /* Clear MCi_STATUS registers */
1311 for (i = 0; i < 6; ++i)
1312 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1313
1314 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1315 if (!err) {
1316 u32 low, high;
1317
1318 value &= ~(1ULL << 2);
1319 low = lower_32_bits(value);
1320 high = upper_32_bits(value);
1321
1322 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1323 }
1324
1325 /* Flush tlb to evict multi-match entries */
1326 __flush_tlb_all();
1327
1328 return true;
1329 }
1330
1331 static void svm_handle_mce(struct vcpu_svm *svm)
1332 {
1333 if (is_erratum_383()) {
1334 /*
1335 * Erratum 383 triggered. Guest state is corrupt so kill the
1336 * guest.
1337 */
1338 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1339
1340 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1341
1342 return;
1343 }
1344
1345 /*
1346 * On an #MC intercept the MCE handler is not called automatically in
1347 * the host. So do it by hand here.
1348 */
1349 asm volatile (
1350 "int $0x12\n");
1351 /* not sure if we ever come back to this point */
1352
1353 return;
1354 }
1355
1356 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1357 {
1358 return 1;
1359 }
1360
1361 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1362 {
1363 /*
1364 * VMCB is undefined after a SHUTDOWN intercept
1365 * so reinitialize it.
1366 */
1367 clear_page(svm->vmcb);
1368 init_vmcb(svm);
1369
1370 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1371 return 0;
1372 }
1373
1374 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1375 {
1376 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1377 int size, in, string;
1378 unsigned port;
1379
1380 ++svm->vcpu.stat.io_exits;
1381
1382 svm->next_rip = svm->vmcb->control.exit_info_2;
1383
1384 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1385
1386 if (string) {
1387 if (emulate_instruction(&svm->vcpu,
1388 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1389 return 0;
1390 return 1;
1391 }
1392
1393 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1394 port = io_info >> 16;
1395 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1396
1397 skip_emulated_instruction(&svm->vcpu);
1398 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1399 }
1400
1401 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1402 {
1403 return 1;
1404 }
1405
1406 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1407 {
1408 ++svm->vcpu.stat.irq_exits;
1409 return 1;
1410 }
1411
1412 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1413 {
1414 return 1;
1415 }
1416
1417 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1418 {
1419 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1420 skip_emulated_instruction(&svm->vcpu);
1421 return kvm_emulate_halt(&svm->vcpu);
1422 }
1423
1424 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1425 {
1426 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1427 skip_emulated_instruction(&svm->vcpu);
1428 kvm_emulate_hypercall(&svm->vcpu);
1429 return 1;
1430 }
1431
1432 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1433 {
1434 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1435 || !is_paging(&svm->vcpu)) {
1436 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1437 return 1;
1438 }
1439
1440 if (svm->vmcb->save.cpl) {
1441 kvm_inject_gp(&svm->vcpu, 0);
1442 return 1;
1443 }
1444
1445 return 0;
1446 }
1447
1448 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1449 bool has_error_code, u32 error_code)
1450 {
1451 if (!is_nested(svm))
1452 return 0;
1453
1454 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1455 svm->vmcb->control.exit_code_hi = 0;
1456 svm->vmcb->control.exit_info_1 = error_code;
1457 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1458
1459 return nested_svm_exit_handled(svm);
1460 }
1461
1462 static inline int nested_svm_intr(struct vcpu_svm *svm)
1463 {
1464 if (!is_nested(svm))
1465 return 0;
1466
1467 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1468 return 0;
1469
1470 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1471 return 0;
1472
1473 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1474
1475 if (nested_svm_exit_handled(svm)) {
1476 nsvm_printk("VMexit -> INTR\n");
1477 return 1;
1478 }
1479
1480 return 0;
1481 }
1482
1483 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1484 {
1485 struct page *page;
1486
1487 down_read(&current->mm->mmap_sem);
1488 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1489 up_read(&current->mm->mmap_sem);
1490
1491 if (is_error_page(page))
1492 goto error;
1493
1494 return kmap_atomic(page, idx);
1495
1496 error:
1497 kvm_release_page_clean(page);
1498 kvm_inject_gp(&svm->vcpu, 0);
1499
1500 return NULL;
1501 }
1502
1503 static void nested_svm_unmap(void *addr, enum km_type idx)
1504 {
1505 struct page *page;
1506
1507 if (!addr)
1508 return;
1509
1510 page = kmap_atomic_to_page(addr);
1511
1512 kunmap_atomic(addr, idx);
1513 kvm_release_page_dirty(page);
1514 }
1515
1516 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1517 {
1518 u32 param = svm->vmcb->control.exit_info_1 & 1;
1519 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1520 bool ret = false;
1521 u32 t0, t1;
1522 u8 *msrpm;
1523
1524 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1525 return false;
1526
1527 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1528
1529 if (!msrpm)
1530 goto out;
1531
1532 switch (msr) {
1533 case 0 ... 0x1fff:
1534 t0 = (msr * 2) % 8;
1535 t1 = msr / 8;
1536 break;
1537 case 0xc0000000 ... 0xc0001fff:
1538 t0 = (8192 + msr - 0xc0000000) * 2;
1539 t1 = (t0 / 8);
1540 t0 %= 8;
1541 break;
1542 case 0xc0010000 ... 0xc0011fff:
1543 t0 = (16384 + msr - 0xc0010000) * 2;
1544 t1 = (t0 / 8);
1545 t0 %= 8;
1546 break;
1547 default:
1548 ret = true;
1549 goto out;
1550 }
1551
1552 ret = msrpm[t1] & ((1 << param) << t0);
1553
1554 out:
1555 nested_svm_unmap(msrpm, KM_USER0);
1556
1557 return ret;
1558 }
1559
1560 static int nested_svm_exit_special(struct vcpu_svm *svm)
1561 {
1562 u32 exit_code = svm->vmcb->control.exit_code;
1563
1564 switch (exit_code) {
1565 case SVM_EXIT_INTR:
1566 case SVM_EXIT_NMI:
1567 return NESTED_EXIT_HOST;
1568 /* For now we are always handling NPFs when using them */
1569 case SVM_EXIT_NPF:
1570 if (npt_enabled)
1571 return NESTED_EXIT_HOST;
1572 break;
1573 /* When we're shadowing, trap PFs */
1574 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1575 if (!npt_enabled)
1576 return NESTED_EXIT_HOST;
1577 break;
1578 default:
1579 break;
1580 }
1581
1582 return NESTED_EXIT_CONTINUE;
1583 }
1584
1585 /*
1586 * If this function returns true, this #vmexit was already handled
1587 */
1588 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1589 {
1590 u32 exit_code = svm->vmcb->control.exit_code;
1591 int vmexit = NESTED_EXIT_HOST;
1592
1593 switch (exit_code) {
1594 case SVM_EXIT_MSR:
1595 vmexit = nested_svm_exit_handled_msr(svm);
1596 break;
1597 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1598 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1599 if (svm->nested.intercept_cr_read & cr_bits)
1600 vmexit = NESTED_EXIT_DONE;
1601 break;
1602 }
1603 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1604 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1605 if (svm->nested.intercept_cr_write & cr_bits)
1606 vmexit = NESTED_EXIT_DONE;
1607 break;
1608 }
1609 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1610 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1611 if (svm->nested.intercept_dr_read & dr_bits)
1612 vmexit = NESTED_EXIT_DONE;
1613 break;
1614 }
1615 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1616 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1617 if (svm->nested.intercept_dr_write & dr_bits)
1618 vmexit = NESTED_EXIT_DONE;
1619 break;
1620 }
1621 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1622 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1623 if (svm->nested.intercept_exceptions & excp_bits)
1624 vmexit = NESTED_EXIT_DONE;
1625 break;
1626 }
1627 default: {
1628 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1629 nsvm_printk("exit code: 0x%x\n", exit_code);
1630 if (svm->nested.intercept & exit_bits)
1631 vmexit = NESTED_EXIT_DONE;
1632 }
1633 }
1634
1635 if (vmexit == NESTED_EXIT_DONE) {
1636 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1637 nested_svm_vmexit(svm);
1638 }
1639
1640 return vmexit;
1641 }
1642
1643 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1644 {
1645 struct vmcb_control_area *dst = &dst_vmcb->control;
1646 struct vmcb_control_area *from = &from_vmcb->control;
1647
1648 dst->intercept_cr_read = from->intercept_cr_read;
1649 dst->intercept_cr_write = from->intercept_cr_write;
1650 dst->intercept_dr_read = from->intercept_dr_read;
1651 dst->intercept_dr_write = from->intercept_dr_write;
1652 dst->intercept_exceptions = from->intercept_exceptions;
1653 dst->intercept = from->intercept;
1654 dst->iopm_base_pa = from->iopm_base_pa;
1655 dst->msrpm_base_pa = from->msrpm_base_pa;
1656 dst->tsc_offset = from->tsc_offset;
1657 dst->asid = from->asid;
1658 dst->tlb_ctl = from->tlb_ctl;
1659 dst->int_ctl = from->int_ctl;
1660 dst->int_vector = from->int_vector;
1661 dst->int_state = from->int_state;
1662 dst->exit_code = from->exit_code;
1663 dst->exit_code_hi = from->exit_code_hi;
1664 dst->exit_info_1 = from->exit_info_1;
1665 dst->exit_info_2 = from->exit_info_2;
1666 dst->exit_int_info = from->exit_int_info;
1667 dst->exit_int_info_err = from->exit_int_info_err;
1668 dst->nested_ctl = from->nested_ctl;
1669 dst->event_inj = from->event_inj;
1670 dst->event_inj_err = from->event_inj_err;
1671 dst->nested_cr3 = from->nested_cr3;
1672 dst->lbr_ctl = from->lbr_ctl;
1673 }
1674
1675 static int nested_svm_vmexit(struct vcpu_svm *svm)
1676 {
1677 struct vmcb *nested_vmcb;
1678 struct vmcb *hsave = svm->nested.hsave;
1679 struct vmcb *vmcb = svm->vmcb;
1680
1681 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1682 if (!nested_vmcb)
1683 return 1;
1684
1685 /* Give the current vmcb to the guest */
1686 disable_gif(svm);
1687
1688 nested_vmcb->save.es = vmcb->save.es;
1689 nested_vmcb->save.cs = vmcb->save.cs;
1690 nested_vmcb->save.ss = vmcb->save.ss;
1691 nested_vmcb->save.ds = vmcb->save.ds;
1692 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1693 nested_vmcb->save.idtr = vmcb->save.idtr;
1694 if (npt_enabled)
1695 nested_vmcb->save.cr3 = vmcb->save.cr3;
1696 nested_vmcb->save.cr2 = vmcb->save.cr2;
1697 nested_vmcb->save.rflags = vmcb->save.rflags;
1698 nested_vmcb->save.rip = vmcb->save.rip;
1699 nested_vmcb->save.rsp = vmcb->save.rsp;
1700 nested_vmcb->save.rax = vmcb->save.rax;
1701 nested_vmcb->save.dr7 = vmcb->save.dr7;
1702 nested_vmcb->save.dr6 = vmcb->save.dr6;
1703 nested_vmcb->save.cpl = vmcb->save.cpl;
1704
1705 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1706 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1707 nested_vmcb->control.int_state = vmcb->control.int_state;
1708 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1709 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1710 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1711 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1712 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1713 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1714 nested_vmcb->control.tlb_ctl = 0;
1715 nested_vmcb->control.event_inj = 0;
1716 nested_vmcb->control.event_inj_err = 0;
1717
1718 /* We always set V_INTR_MASKING and remember the old value in hflags */
1719 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1720 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1721
1722 /* Restore the original control entries */
1723 copy_vmcb_control_area(vmcb, hsave);
1724
1725 /* Kill any pending exceptions */
1726 if (svm->vcpu.arch.exception.pending == true)
1727 nsvm_printk("WARNING: Pending Exception\n");
1728
1729 kvm_clear_exception_queue(&svm->vcpu);
1730 kvm_clear_interrupt_queue(&svm->vcpu);
1731
1732 /* Restore selected save entries */
1733 svm->vmcb->save.es = hsave->save.es;
1734 svm->vmcb->save.cs = hsave->save.cs;
1735 svm->vmcb->save.ss = hsave->save.ss;
1736 svm->vmcb->save.ds = hsave->save.ds;
1737 svm->vmcb->save.gdtr = hsave->save.gdtr;
1738 svm->vmcb->save.idtr = hsave->save.idtr;
1739 svm->vmcb->save.rflags = hsave->save.rflags;
1740 svm_set_efer(&svm->vcpu, hsave->save.efer);
1741 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1742 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1743 if (npt_enabled) {
1744 svm->vmcb->save.cr3 = hsave->save.cr3;
1745 svm->vcpu.arch.cr3 = hsave->save.cr3;
1746 } else {
1747 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1748 }
1749 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1750 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1751 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1752 svm->vmcb->save.dr7 = 0;
1753 svm->vmcb->save.cpl = 0;
1754 svm->vmcb->control.exit_int_info = 0;
1755
1756 /* Exit nested SVM mode */
1757 svm->nested.vmcb = 0;
1758
1759 nested_svm_unmap(nested_vmcb, KM_USER0);
1760
1761 kvm_mmu_reset_context(&svm->vcpu);
1762 kvm_mmu_load(&svm->vcpu);
1763
1764 return 0;
1765 }
1766
1767 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1768 {
1769 u32 *nested_msrpm;
1770 int i;
1771
1772 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1773 if (!nested_msrpm)
1774 return false;
1775
1776 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1777 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1778
1779 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1780
1781 nested_svm_unmap(nested_msrpm, KM_USER0);
1782
1783 return true;
1784 }
1785
1786 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1787 {
1788 struct vmcb *nested_vmcb;
1789 struct vmcb *hsave = svm->nested.hsave;
1790 struct vmcb *vmcb = svm->vmcb;
1791
1792 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1793 if (!nested_vmcb)
1794 return false;
1795
1796 /* nested_vmcb is our indicator if nested SVM is activated */
1797 svm->nested.vmcb = svm->vmcb->save.rax;
1798
1799 /* Clear internal status */
1800 kvm_clear_exception_queue(&svm->vcpu);
1801 kvm_clear_interrupt_queue(&svm->vcpu);
1802
1803 /* Save the old vmcb, so we don't need to pick what we save, but
1804 can restore everything when a VMEXIT occurs */
1805 hsave->save.es = vmcb->save.es;
1806 hsave->save.cs = vmcb->save.cs;
1807 hsave->save.ss = vmcb->save.ss;
1808 hsave->save.ds = vmcb->save.ds;
1809 hsave->save.gdtr = vmcb->save.gdtr;
1810 hsave->save.idtr = vmcb->save.idtr;
1811 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1812 hsave->save.cr0 = svm->vcpu.arch.cr0;
1813 hsave->save.cr4 = svm->vcpu.arch.cr4;
1814 hsave->save.rflags = vmcb->save.rflags;
1815 hsave->save.rip = svm->next_rip;
1816 hsave->save.rsp = vmcb->save.rsp;
1817 hsave->save.rax = vmcb->save.rax;
1818 if (npt_enabled)
1819 hsave->save.cr3 = vmcb->save.cr3;
1820 else
1821 hsave->save.cr3 = svm->vcpu.arch.cr3;
1822
1823 copy_vmcb_control_area(hsave, vmcb);
1824
1825 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1826 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1827 else
1828 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1829
1830 /* Load the nested guest state */
1831 svm->vmcb->save.es = nested_vmcb->save.es;
1832 svm->vmcb->save.cs = nested_vmcb->save.cs;
1833 svm->vmcb->save.ss = nested_vmcb->save.ss;
1834 svm->vmcb->save.ds = nested_vmcb->save.ds;
1835 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1836 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1837 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1838 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1839 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1840 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1841 if (npt_enabled) {
1842 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1843 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1844 } else {
1845 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1846 kvm_mmu_reset_context(&svm->vcpu);
1847 }
1848 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1849 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1850 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1851 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1852 /* In case we don't even reach vcpu_run, the fields are not updated */
1853 svm->vmcb->save.rax = nested_vmcb->save.rax;
1854 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1855 svm->vmcb->save.rip = nested_vmcb->save.rip;
1856 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1857 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1858 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1859
1860 /* We don't want a nested guest to be more powerful than the guest,
1861 so all intercepts are ORed */
1862 svm->vmcb->control.intercept_cr_read |=
1863 nested_vmcb->control.intercept_cr_read;
1864 svm->vmcb->control.intercept_cr_write |=
1865 nested_vmcb->control.intercept_cr_write;
1866 svm->vmcb->control.intercept_dr_read |=
1867 nested_vmcb->control.intercept_dr_read;
1868 svm->vmcb->control.intercept_dr_write |=
1869 nested_vmcb->control.intercept_dr_write;
1870 svm->vmcb->control.intercept_exceptions |=
1871 nested_vmcb->control.intercept_exceptions;
1872
1873 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1874
1875 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1876
1877 /* cache intercepts */
1878 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1879 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1880 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1881 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1882 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1883 svm->nested.intercept = nested_vmcb->control.intercept;
1884
1885 force_new_asid(&svm->vcpu);
1886 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1887 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1888 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1889 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1890 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1891 nested_vmcb->control.int_ctl);
1892 }
1893 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1894 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1895 else
1896 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1897
1898 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1899 nested_vmcb->control.exit_int_info,
1900 nested_vmcb->control.int_state);
1901
1902 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1903 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1904 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1905 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1906 nsvm_printk("Injecting Event: 0x%x\n",
1907 nested_vmcb->control.event_inj);
1908 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1909 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1910
1911 nested_svm_unmap(nested_vmcb, KM_USER0);
1912
1913 enable_gif(svm);
1914
1915 return true;
1916 }
1917
1918 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1919 {
1920 to_vmcb->save.fs = from_vmcb->save.fs;
1921 to_vmcb->save.gs = from_vmcb->save.gs;
1922 to_vmcb->save.tr = from_vmcb->save.tr;
1923 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1924 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1925 to_vmcb->save.star = from_vmcb->save.star;
1926 to_vmcb->save.lstar = from_vmcb->save.lstar;
1927 to_vmcb->save.cstar = from_vmcb->save.cstar;
1928 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1929 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1930 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1931 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1932 }
1933
1934 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1935 {
1936 struct vmcb *nested_vmcb;
1937
1938 if (nested_svm_check_permissions(svm))
1939 return 1;
1940
1941 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1942 skip_emulated_instruction(&svm->vcpu);
1943
1944 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1945 if (!nested_vmcb)
1946 return 1;
1947
1948 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1949 nested_svm_unmap(nested_vmcb, KM_USER0);
1950
1951 return 1;
1952 }
1953
1954 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1955 {
1956 struct vmcb *nested_vmcb;
1957
1958 if (nested_svm_check_permissions(svm))
1959 return 1;
1960
1961 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1962 skip_emulated_instruction(&svm->vcpu);
1963
1964 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1965 if (!nested_vmcb)
1966 return 1;
1967
1968 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1969 nested_svm_unmap(nested_vmcb, KM_USER0);
1970
1971 return 1;
1972 }
1973
1974 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1975 {
1976 nsvm_printk("VMrun\n");
1977
1978 if (nested_svm_check_permissions(svm))
1979 return 1;
1980
1981 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1982 skip_emulated_instruction(&svm->vcpu);
1983
1984 if (!nested_svm_vmrun(svm))
1985 return 1;
1986
1987 if (!nested_svm_vmrun_msrpm(svm))
1988 goto failed;
1989
1990 return 1;
1991
1992 failed:
1993
1994 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1995 svm->vmcb->control.exit_code_hi = 0;
1996 svm->vmcb->control.exit_info_1 = 0;
1997 svm->vmcb->control.exit_info_2 = 0;
1998
1999 nested_svm_vmexit(svm);
2000
2001 return 1;
2002 }
2003
2004 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2005 {
2006 if (nested_svm_check_permissions(svm))
2007 return 1;
2008
2009 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2010 skip_emulated_instruction(&svm->vcpu);
2011
2012 enable_gif(svm);
2013
2014 return 1;
2015 }
2016
2017 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2018 {
2019 if (nested_svm_check_permissions(svm))
2020 return 1;
2021
2022 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2023 skip_emulated_instruction(&svm->vcpu);
2024
2025 disable_gif(svm);
2026
2027 /* After a CLGI no interrupts should come */
2028 svm_clear_vintr(svm);
2029 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2030
2031 return 1;
2032 }
2033
2034 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2035 {
2036 struct kvm_vcpu *vcpu = &svm->vcpu;
2037 nsvm_printk("INVLPGA\n");
2038
2039 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2040 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2041
2042 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2043 skip_emulated_instruction(&svm->vcpu);
2044 return 1;
2045 }
2046
2047 static int invalid_op_interception(struct vcpu_svm *svm,
2048 struct kvm_run *kvm_run)
2049 {
2050 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2051 return 1;
2052 }
2053
2054 static int task_switch_interception(struct vcpu_svm *svm,
2055 struct kvm_run *kvm_run)
2056 {
2057 u16 tss_selector;
2058 int reason;
2059 int int_type = svm->vmcb->control.exit_int_info &
2060 SVM_EXITINTINFO_TYPE_MASK;
2061 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2062 uint32_t type =
2063 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2064 uint32_t idt_v =
2065 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2066
2067 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2068
2069 if (svm->vmcb->control.exit_info_2 &
2070 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2071 reason = TASK_SWITCH_IRET;
2072 else if (svm->vmcb->control.exit_info_2 &
2073 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2074 reason = TASK_SWITCH_JMP;
2075 else if (idt_v)
2076 reason = TASK_SWITCH_GATE;
2077 else
2078 reason = TASK_SWITCH_CALL;
2079
2080 if (reason == TASK_SWITCH_GATE) {
2081 switch (type) {
2082 case SVM_EXITINTINFO_TYPE_NMI:
2083 svm->vcpu.arch.nmi_injected = false;
2084 break;
2085 case SVM_EXITINTINFO_TYPE_EXEPT:
2086 kvm_clear_exception_queue(&svm->vcpu);
2087 break;
2088 case SVM_EXITINTINFO_TYPE_INTR:
2089 kvm_clear_interrupt_queue(&svm->vcpu);
2090 break;
2091 default:
2092 break;
2093 }
2094 }
2095
2096 if (reason != TASK_SWITCH_GATE ||
2097 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2098 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2099 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2100 skip_emulated_instruction(&svm->vcpu);
2101
2102 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2103 }
2104
2105 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2106 {
2107 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2108 kvm_emulate_cpuid(&svm->vcpu);
2109 return 1;
2110 }
2111
2112 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2113 {
2114 ++svm->vcpu.stat.nmi_window_exits;
2115 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2116 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2117 return 1;
2118 }
2119
2120 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2121 {
2122 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2123 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2124 return 1;
2125 }
2126
2127 static int emulate_on_interception(struct vcpu_svm *svm,
2128 struct kvm_run *kvm_run)
2129 {
2130 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2131 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2132 return 1;
2133 }
2134
2135 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2136 {
2137 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2138 /* instruction emulation calls kvm_set_cr8() */
2139 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2140 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2141 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2142 return 1;
2143 }
2144 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2145 return 1;
2146 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2147 return 0;
2148 }
2149
2150 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2151 {
2152 struct vcpu_svm *svm = to_svm(vcpu);
2153
2154 switch (ecx) {
2155 case MSR_IA32_TSC: {
2156 u64 tsc_offset;
2157
2158 if (is_nested(svm))
2159 tsc_offset = svm->nested.hsave->control.tsc_offset;
2160 else
2161 tsc_offset = svm->vmcb->control.tsc_offset;
2162
2163 *data = tsc_offset + native_read_tsc();
2164 break;
2165 }
2166 case MSR_K6_STAR:
2167 *data = svm->vmcb->save.star;
2168 break;
2169 #ifdef CONFIG_X86_64
2170 case MSR_LSTAR:
2171 *data = svm->vmcb->save.lstar;
2172 break;
2173 case MSR_CSTAR:
2174 *data = svm->vmcb->save.cstar;
2175 break;
2176 case MSR_KERNEL_GS_BASE:
2177 *data = svm->vmcb->save.kernel_gs_base;
2178 break;
2179 case MSR_SYSCALL_MASK:
2180 *data = svm->vmcb->save.sfmask;
2181 break;
2182 #endif
2183 case MSR_IA32_SYSENTER_CS:
2184 *data = svm->vmcb->save.sysenter_cs;
2185 break;
2186 case MSR_IA32_SYSENTER_EIP:
2187 *data = svm->sysenter_eip;
2188 break;
2189 case MSR_IA32_SYSENTER_ESP:
2190 *data = svm->sysenter_esp;
2191 break;
2192 /* Nobody will change the following 5 values in the VMCB so
2193 we can safely return them on rdmsr. They will always be 0
2194 until LBRV is implemented. */
2195 case MSR_IA32_DEBUGCTLMSR:
2196 *data = svm->vmcb->save.dbgctl;
2197 break;
2198 case MSR_IA32_LASTBRANCHFROMIP:
2199 *data = svm->vmcb->save.br_from;
2200 break;
2201 case MSR_IA32_LASTBRANCHTOIP:
2202 *data = svm->vmcb->save.br_to;
2203 break;
2204 case MSR_IA32_LASTINTFROMIP:
2205 *data = svm->vmcb->save.last_excp_from;
2206 break;
2207 case MSR_IA32_LASTINTTOIP:
2208 *data = svm->vmcb->save.last_excp_to;
2209 break;
2210 case MSR_VM_HSAVE_PA:
2211 *data = svm->nested.hsave_msr;
2212 break;
2213 case MSR_VM_CR:
2214 *data = 0;
2215 break;
2216 case MSR_IA32_UCODE_REV:
2217 *data = 0x01000065;
2218 break;
2219 default:
2220 return kvm_get_msr_common(vcpu, ecx, data);
2221 }
2222 return 0;
2223 }
2224
2225 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2226 {
2227 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2228 u64 data;
2229
2230 if (svm_get_msr(&svm->vcpu, ecx, &data))
2231 kvm_inject_gp(&svm->vcpu, 0);
2232 else {
2233 trace_kvm_msr_read(ecx, data);
2234
2235 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2236 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2237 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2238 skip_emulated_instruction(&svm->vcpu);
2239 }
2240 return 1;
2241 }
2242
2243 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2244 {
2245 struct vcpu_svm *svm = to_svm(vcpu);
2246
2247 switch (ecx) {
2248 case MSR_IA32_TSC: {
2249 u64 tsc_offset = data - native_read_tsc();
2250 u64 g_tsc_offset = 0;
2251
2252 if (is_nested(svm)) {
2253 g_tsc_offset = svm->vmcb->control.tsc_offset -
2254 svm->nested.hsave->control.tsc_offset;
2255 svm->nested.hsave->control.tsc_offset = tsc_offset;
2256 }
2257
2258 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2259
2260 break;
2261 }
2262 case MSR_K6_STAR:
2263 svm->vmcb->save.star = data;
2264 break;
2265 #ifdef CONFIG_X86_64
2266 case MSR_LSTAR:
2267 svm->vmcb->save.lstar = data;
2268 break;
2269 case MSR_CSTAR:
2270 svm->vmcb->save.cstar = data;
2271 break;
2272 case MSR_KERNEL_GS_BASE:
2273 svm->vmcb->save.kernel_gs_base = data;
2274 break;
2275 case MSR_SYSCALL_MASK:
2276 svm->vmcb->save.sfmask = data;
2277 break;
2278 #endif
2279 case MSR_IA32_SYSENTER_CS:
2280 svm->vmcb->save.sysenter_cs = data;
2281 break;
2282 case MSR_IA32_SYSENTER_EIP:
2283 svm->sysenter_eip = data;
2284 svm->vmcb->save.sysenter_eip = data;
2285 break;
2286 case MSR_IA32_SYSENTER_ESP:
2287 svm->sysenter_esp = data;
2288 svm->vmcb->save.sysenter_esp = data;
2289 break;
2290 case MSR_IA32_DEBUGCTLMSR:
2291 if (!svm_has(SVM_FEATURE_LBRV)) {
2292 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2293 __func__, data);
2294 break;
2295 }
2296 if (data & DEBUGCTL_RESERVED_BITS)
2297 return 1;
2298
2299 svm->vmcb->save.dbgctl = data;
2300 if (data & (1ULL<<0))
2301 svm_enable_lbrv(svm);
2302 else
2303 svm_disable_lbrv(svm);
2304 break;
2305 case MSR_VM_HSAVE_PA:
2306 svm->nested.hsave_msr = data;
2307 break;
2308 case MSR_VM_CR:
2309 case MSR_VM_IGNNE:
2310 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2311 break;
2312 default:
2313 return kvm_set_msr_common(vcpu, ecx, data);
2314 }
2315 return 0;
2316 }
2317
2318 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2319 {
2320 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2321 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2322 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2323
2324 trace_kvm_msr_write(ecx, data);
2325
2326 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2327 if (svm_set_msr(&svm->vcpu, ecx, data))
2328 kvm_inject_gp(&svm->vcpu, 0);
2329 else
2330 skip_emulated_instruction(&svm->vcpu);
2331 return 1;
2332 }
2333
2334 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2335 {
2336 if (svm->vmcb->control.exit_info_1)
2337 return wrmsr_interception(svm, kvm_run);
2338 else
2339 return rdmsr_interception(svm, kvm_run);
2340 }
2341
2342 static int interrupt_window_interception(struct vcpu_svm *svm,
2343 struct kvm_run *kvm_run)
2344 {
2345 svm_clear_vintr(svm);
2346 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2347 /*
2348 * If the user space waits to inject interrupts, exit as soon as
2349 * possible
2350 */
2351 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2352 kvm_run->request_interrupt_window &&
2353 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2354 ++svm->vcpu.stat.irq_window_exits;
2355 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2356 return 0;
2357 }
2358
2359 return 1;
2360 }
2361
2362 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2363 struct kvm_run *kvm_run) = {
2364 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2365 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2366 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2367 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2368 /* for now: */
2369 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2370 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2371 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2372 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2373 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2374 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2375 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2376 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2377 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2378 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2379 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2380 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2381 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2382 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2383 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2384 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2385 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2386 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2387 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2388 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2389 [SVM_EXIT_INTR] = intr_interception,
2390 [SVM_EXIT_NMI] = nmi_interception,
2391 [SVM_EXIT_SMI] = nop_on_interception,
2392 [SVM_EXIT_INIT] = nop_on_interception,
2393 [SVM_EXIT_VINTR] = interrupt_window_interception,
2394 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2395 [SVM_EXIT_CPUID] = cpuid_interception,
2396 [SVM_EXIT_IRET] = iret_interception,
2397 [SVM_EXIT_INVD] = emulate_on_interception,
2398 [SVM_EXIT_HLT] = halt_interception,
2399 [SVM_EXIT_INVLPG] = invlpg_interception,
2400 [SVM_EXIT_INVLPGA] = invlpga_interception,
2401 [SVM_EXIT_IOIO] = io_interception,
2402 [SVM_EXIT_MSR] = msr_interception,
2403 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2404 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2405 [SVM_EXIT_VMRUN] = vmrun_interception,
2406 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2407 [SVM_EXIT_VMLOAD] = vmload_interception,
2408 [SVM_EXIT_VMSAVE] = vmsave_interception,
2409 [SVM_EXIT_STGI] = stgi_interception,
2410 [SVM_EXIT_CLGI] = clgi_interception,
2411 [SVM_EXIT_SKINIT] = invalid_op_interception,
2412 [SVM_EXIT_WBINVD] = emulate_on_interception,
2413 [SVM_EXIT_MONITOR] = invalid_op_interception,
2414 [SVM_EXIT_MWAIT] = invalid_op_interception,
2415 [SVM_EXIT_NPF] = pf_interception,
2416 };
2417
2418 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2419 {
2420 struct vcpu_svm *svm = to_svm(vcpu);
2421 u32 exit_code = svm->vmcb->control.exit_code;
2422
2423 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2424
2425 if (is_nested(svm)) {
2426 int vmexit;
2427
2428 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2429 exit_code, svm->vmcb->control.exit_info_1,
2430 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2431
2432 vmexit = nested_svm_exit_special(svm);
2433
2434 if (vmexit == NESTED_EXIT_CONTINUE)
2435 vmexit = nested_svm_exit_handled(svm);
2436
2437 if (vmexit == NESTED_EXIT_DONE)
2438 return 1;
2439 }
2440
2441 svm_complete_interrupts(svm);
2442
2443 if (npt_enabled) {
2444 int mmu_reload = 0;
2445 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2446 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2447 mmu_reload = 1;
2448 }
2449 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2450 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2451 if (mmu_reload) {
2452 kvm_mmu_reset_context(vcpu);
2453 kvm_mmu_load(vcpu);
2454 }
2455 }
2456
2457
2458 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2459 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2460 kvm_run->fail_entry.hardware_entry_failure_reason
2461 = svm->vmcb->control.exit_code;
2462 return 0;
2463 }
2464
2465 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2466 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2467 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2468 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2469 "exit_code 0x%x\n",
2470 __func__, svm->vmcb->control.exit_int_info,
2471 exit_code);
2472
2473 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2474 || !svm_exit_handlers[exit_code]) {
2475 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2476 kvm_run->hw.hardware_exit_reason = exit_code;
2477 return 0;
2478 }
2479
2480 return svm_exit_handlers[exit_code](svm, kvm_run);
2481 }
2482
2483 static void reload_tss(struct kvm_vcpu *vcpu)
2484 {
2485 int cpu = raw_smp_processor_id();
2486
2487 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2488 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2489 load_TR_desc();
2490 }
2491
2492 static void pre_svm_run(struct vcpu_svm *svm)
2493 {
2494 int cpu = raw_smp_processor_id();
2495
2496 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2497
2498 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2499 /* FIXME: handle wraparound of asid_generation */
2500 if (svm->asid_generation != svm_data->asid_generation)
2501 new_asid(svm, svm_data);
2502 }
2503
2504 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2505 {
2506 struct vcpu_svm *svm = to_svm(vcpu);
2507
2508 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2509 vcpu->arch.hflags |= HF_NMI_MASK;
2510 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2511 ++vcpu->stat.nmi_injections;
2512 }
2513
2514 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2515 {
2516 struct vmcb_control_area *control;
2517
2518 trace_kvm_inj_virq(irq);
2519
2520 ++svm->vcpu.stat.irq_injections;
2521 control = &svm->vmcb->control;
2522 control->int_vector = irq;
2523 control->int_ctl &= ~V_INTR_PRIO_MASK;
2524 control->int_ctl |= V_IRQ_MASK |
2525 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2526 }
2527
2528 static void svm_set_irq(struct kvm_vcpu *vcpu)
2529 {
2530 struct vcpu_svm *svm = to_svm(vcpu);
2531
2532 BUG_ON(!(gif_set(svm)));
2533
2534 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2535 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2536 }
2537
2538 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2539 {
2540 struct vcpu_svm *svm = to_svm(vcpu);
2541
2542 if (irr == -1)
2543 return;
2544
2545 if (tpr >= irr)
2546 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2547 }
2548
2549 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2550 {
2551 struct vcpu_svm *svm = to_svm(vcpu);
2552 struct vmcb *vmcb = svm->vmcb;
2553 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2554 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2555 }
2556
2557 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2558 {
2559 struct vcpu_svm *svm = to_svm(vcpu);
2560 struct vmcb *vmcb = svm->vmcb;
2561 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2562 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2563 gif_set(svm) &&
2564 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
2565 }
2566
2567 static void enable_irq_window(struct kvm_vcpu *vcpu)
2568 {
2569 struct vcpu_svm *svm = to_svm(vcpu);
2570 nsvm_printk("Trying to open IRQ window\n");
2571
2572 nested_svm_intr(svm);
2573
2574 /* In case GIF=0 we can't rely on the CPU to tell us when
2575 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2576 * The next time we get that intercept, this function will be
2577 * called again though and we'll get the vintr intercept. */
2578 if (gif_set(svm)) {
2579 svm_set_vintr(svm);
2580 svm_inject_irq(svm, 0x0);
2581 }
2582 }
2583
2584 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2585 {
2586 struct vcpu_svm *svm = to_svm(vcpu);
2587
2588 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2589 == HF_NMI_MASK)
2590 return; /* IRET will cause a vm exit */
2591
2592 /* Something prevents NMI from been injected. Single step over
2593 possible problem (IRET or exception injection or interrupt
2594 shadow) */
2595 vcpu->arch.singlestep = true;
2596 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2597 update_db_intercept(vcpu);
2598 }
2599
2600 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2601 {
2602 return 0;
2603 }
2604
2605 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2606 {
2607 force_new_asid(vcpu);
2608 }
2609
2610 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2611 {
2612 }
2613
2614 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2615 {
2616 struct vcpu_svm *svm = to_svm(vcpu);
2617
2618 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2619 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2620 kvm_set_cr8(vcpu, cr8);
2621 }
2622 }
2623
2624 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2625 {
2626 struct vcpu_svm *svm = to_svm(vcpu);
2627 u64 cr8;
2628
2629 cr8 = kvm_get_cr8(vcpu);
2630 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2631 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2632 }
2633
2634 static void svm_complete_interrupts(struct vcpu_svm *svm)
2635 {
2636 u8 vector;
2637 int type;
2638 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2639
2640 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2641 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2642
2643 svm->vcpu.arch.nmi_injected = false;
2644 kvm_clear_exception_queue(&svm->vcpu);
2645 kvm_clear_interrupt_queue(&svm->vcpu);
2646
2647 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2648 return;
2649
2650 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2651 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2652
2653 switch (type) {
2654 case SVM_EXITINTINFO_TYPE_NMI:
2655 svm->vcpu.arch.nmi_injected = true;
2656 break;
2657 case SVM_EXITINTINFO_TYPE_EXEPT:
2658 /* In case of software exception do not reinject an exception
2659 vector, but re-execute and instruction instead */
2660 if (is_nested(svm))
2661 break;
2662 if (kvm_exception_is_soft(vector))
2663 break;
2664 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2665 u32 err = svm->vmcb->control.exit_int_info_err;
2666 kvm_queue_exception_e(&svm->vcpu, vector, err);
2667
2668 } else
2669 kvm_queue_exception(&svm->vcpu, vector);
2670 break;
2671 case SVM_EXITINTINFO_TYPE_INTR:
2672 kvm_queue_interrupt(&svm->vcpu, vector, false);
2673 break;
2674 default:
2675 break;
2676 }
2677 }
2678
2679 #ifdef CONFIG_X86_64
2680 #define R "r"
2681 #else
2682 #define R "e"
2683 #endif
2684
2685 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2686 {
2687 struct vcpu_svm *svm = to_svm(vcpu);
2688 u16 fs_selector;
2689 u16 gs_selector;
2690 u16 ldt_selector;
2691
2692 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2693 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2694 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2695
2696 pre_svm_run(svm);
2697
2698 sync_lapic_to_cr8(vcpu);
2699
2700 save_host_msrs(vcpu);
2701 fs_selector = kvm_read_fs();
2702 gs_selector = kvm_read_gs();
2703 ldt_selector = kvm_read_ldt();
2704 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2705 /* required for live migration with NPT */
2706 if (npt_enabled)
2707 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2708
2709 clgi();
2710
2711 local_irq_enable();
2712
2713 asm volatile (
2714 "push %%"R"bp; \n\t"
2715 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2716 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2717 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2718 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2719 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2720 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2721 #ifdef CONFIG_X86_64
2722 "mov %c[r8](%[svm]), %%r8 \n\t"
2723 "mov %c[r9](%[svm]), %%r9 \n\t"
2724 "mov %c[r10](%[svm]), %%r10 \n\t"
2725 "mov %c[r11](%[svm]), %%r11 \n\t"
2726 "mov %c[r12](%[svm]), %%r12 \n\t"
2727 "mov %c[r13](%[svm]), %%r13 \n\t"
2728 "mov %c[r14](%[svm]), %%r14 \n\t"
2729 "mov %c[r15](%[svm]), %%r15 \n\t"
2730 #endif
2731
2732 /* Enter guest mode */
2733 "push %%"R"ax \n\t"
2734 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2735 __ex(SVM_VMLOAD) "\n\t"
2736 __ex(SVM_VMRUN) "\n\t"
2737 __ex(SVM_VMSAVE) "\n\t"
2738 "pop %%"R"ax \n\t"
2739
2740 /* Save guest registers, load host registers */
2741 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2742 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2743 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2744 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2745 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2746 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2747 #ifdef CONFIG_X86_64
2748 "mov %%r8, %c[r8](%[svm]) \n\t"
2749 "mov %%r9, %c[r9](%[svm]) \n\t"
2750 "mov %%r10, %c[r10](%[svm]) \n\t"
2751 "mov %%r11, %c[r11](%[svm]) \n\t"
2752 "mov %%r12, %c[r12](%[svm]) \n\t"
2753 "mov %%r13, %c[r13](%[svm]) \n\t"
2754 "mov %%r14, %c[r14](%[svm]) \n\t"
2755 "mov %%r15, %c[r15](%[svm]) \n\t"
2756 #endif
2757 "pop %%"R"bp"
2758 :
2759 : [svm]"a"(svm),
2760 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2761 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2762 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2763 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2764 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2765 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2766 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2767 #ifdef CONFIG_X86_64
2768 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2769 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2770 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2771 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2772 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2773 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2774 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2775 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2776 #endif
2777 : "cc", "memory"
2778 , R"bx", R"cx", R"dx", R"si", R"di"
2779 #ifdef CONFIG_X86_64
2780 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2781 #endif
2782 );
2783
2784 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2785 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2786 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2787 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2788
2789 kvm_load_fs(fs_selector);
2790 kvm_load_gs(gs_selector);
2791 kvm_load_ldt(ldt_selector);
2792 load_host_msrs(vcpu);
2793
2794 reload_tss(vcpu);
2795
2796 local_irq_disable();
2797
2798 stgi();
2799
2800 sync_cr8_to_lapic(vcpu);
2801
2802 svm->next_rip = 0;
2803
2804 if (npt_enabled) {
2805 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2806 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2807 }
2808
2809 /*
2810 * We need to handle MC intercepts here before the vcpu has a chance to
2811 * change the physical cpu
2812 */
2813 if (unlikely(svm->vmcb->control.exit_code ==
2814 SVM_EXIT_EXCP_BASE + MC_VECTOR))
2815 svm_handle_mce(svm);
2816 }
2817
2818 #undef R
2819
2820 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2821 {
2822 struct vcpu_svm *svm = to_svm(vcpu);
2823
2824 if (npt_enabled) {
2825 svm->vmcb->control.nested_cr3 = root;
2826 force_new_asid(vcpu);
2827 return;
2828 }
2829
2830 svm->vmcb->save.cr3 = root;
2831 force_new_asid(vcpu);
2832
2833 if (vcpu->fpu_active) {
2834 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2835 svm->vmcb->save.cr0 |= X86_CR0_TS;
2836 vcpu->fpu_active = 0;
2837 }
2838 }
2839
2840 static int is_disabled(void)
2841 {
2842 u64 vm_cr;
2843
2844 rdmsrl(MSR_VM_CR, vm_cr);
2845 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2846 return 1;
2847
2848 return 0;
2849 }
2850
2851 static void
2852 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2853 {
2854 /*
2855 * Patch in the VMMCALL instruction:
2856 */
2857 hypercall[0] = 0x0f;
2858 hypercall[1] = 0x01;
2859 hypercall[2] = 0xd9;
2860 }
2861
2862 static void svm_check_processor_compat(void *rtn)
2863 {
2864 *(int *)rtn = 0;
2865 }
2866
2867 static bool svm_cpu_has_accelerated_tpr(void)
2868 {
2869 return false;
2870 }
2871
2872 static int get_npt_level(void)
2873 {
2874 #ifdef CONFIG_X86_64
2875 return PT64_ROOT_LEVEL;
2876 #else
2877 return PT32E_ROOT_LEVEL;
2878 #endif
2879 }
2880
2881 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2882 {
2883 return 0;
2884 }
2885
2886 static const struct trace_print_flags svm_exit_reasons_str[] = {
2887 { SVM_EXIT_READ_CR0, "read_cr0" },
2888 { SVM_EXIT_READ_CR3, "read_cr3" },
2889 { SVM_EXIT_READ_CR4, "read_cr4" },
2890 { SVM_EXIT_READ_CR8, "read_cr8" },
2891 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2892 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2893 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2894 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2895 { SVM_EXIT_READ_DR0, "read_dr0" },
2896 { SVM_EXIT_READ_DR1, "read_dr1" },
2897 { SVM_EXIT_READ_DR2, "read_dr2" },
2898 { SVM_EXIT_READ_DR3, "read_dr3" },
2899 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2900 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2901 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2902 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2903 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2904 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2905 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2906 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2907 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2908 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2909 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2910 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2911 { SVM_EXIT_INTR, "interrupt" },
2912 { SVM_EXIT_NMI, "nmi" },
2913 { SVM_EXIT_SMI, "smi" },
2914 { SVM_EXIT_INIT, "init" },
2915 { SVM_EXIT_VINTR, "vintr" },
2916 { SVM_EXIT_CPUID, "cpuid" },
2917 { SVM_EXIT_INVD, "invd" },
2918 { SVM_EXIT_HLT, "hlt" },
2919 { SVM_EXIT_INVLPG, "invlpg" },
2920 { SVM_EXIT_INVLPGA, "invlpga" },
2921 { SVM_EXIT_IOIO, "io" },
2922 { SVM_EXIT_MSR, "msr" },
2923 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2924 { SVM_EXIT_SHUTDOWN, "shutdown" },
2925 { SVM_EXIT_VMRUN, "vmrun" },
2926 { SVM_EXIT_VMMCALL, "hypercall" },
2927 { SVM_EXIT_VMLOAD, "vmload" },
2928 { SVM_EXIT_VMSAVE, "vmsave" },
2929 { SVM_EXIT_STGI, "stgi" },
2930 { SVM_EXIT_CLGI, "clgi" },
2931 { SVM_EXIT_SKINIT, "skinit" },
2932 { SVM_EXIT_WBINVD, "wbinvd" },
2933 { SVM_EXIT_MONITOR, "monitor" },
2934 { SVM_EXIT_MWAIT, "mwait" },
2935 { SVM_EXIT_NPF, "npf" },
2936 { -1, NULL }
2937 };
2938
2939 static bool svm_gb_page_enable(void)
2940 {
2941 return true;
2942 }
2943
2944 static struct kvm_x86_ops svm_x86_ops = {
2945 .cpu_has_kvm_support = has_svm,
2946 .disabled_by_bios = is_disabled,
2947 .hardware_setup = svm_hardware_setup,
2948 .hardware_unsetup = svm_hardware_unsetup,
2949 .check_processor_compatibility = svm_check_processor_compat,
2950 .hardware_enable = svm_hardware_enable,
2951 .hardware_disable = svm_hardware_disable,
2952 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2953
2954 .vcpu_create = svm_create_vcpu,
2955 .vcpu_free = svm_free_vcpu,
2956 .vcpu_reset = svm_vcpu_reset,
2957
2958 .prepare_guest_switch = svm_prepare_guest_switch,
2959 .vcpu_load = svm_vcpu_load,
2960 .vcpu_put = svm_vcpu_put,
2961
2962 .set_guest_debug = svm_guest_debug,
2963 .get_msr = svm_get_msr,
2964 .set_msr = svm_set_msr,
2965 .get_segment_base = svm_get_segment_base,
2966 .get_segment = svm_get_segment,
2967 .set_segment = svm_set_segment,
2968 .get_cpl = svm_get_cpl,
2969 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2970 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2971 .set_cr0 = svm_set_cr0,
2972 .set_cr3 = svm_set_cr3,
2973 .set_cr4 = svm_set_cr4,
2974 .set_efer = svm_set_efer,
2975 .get_idt = svm_get_idt,
2976 .set_idt = svm_set_idt,
2977 .get_gdt = svm_get_gdt,
2978 .set_gdt = svm_set_gdt,
2979 .get_dr = svm_get_dr,
2980 .set_dr = svm_set_dr,
2981 .cache_reg = svm_cache_reg,
2982 .get_rflags = svm_get_rflags,
2983 .set_rflags = svm_set_rflags,
2984
2985 .tlb_flush = svm_flush_tlb,
2986
2987 .run = svm_vcpu_run,
2988 .handle_exit = handle_exit,
2989 .skip_emulated_instruction = skip_emulated_instruction,
2990 .set_interrupt_shadow = svm_set_interrupt_shadow,
2991 .get_interrupt_shadow = svm_get_interrupt_shadow,
2992 .patch_hypercall = svm_patch_hypercall,
2993 .set_irq = svm_set_irq,
2994 .set_nmi = svm_inject_nmi,
2995 .queue_exception = svm_queue_exception,
2996 .interrupt_allowed = svm_interrupt_allowed,
2997 .nmi_allowed = svm_nmi_allowed,
2998 .enable_nmi_window = enable_nmi_window,
2999 .enable_irq_window = enable_irq_window,
3000 .update_cr8_intercept = update_cr8_intercept,
3001
3002 .set_tss_addr = svm_set_tss_addr,
3003 .get_tdp_level = get_npt_level,
3004 .get_mt_mask = svm_get_mt_mask,
3005
3006 .exit_reasons_str = svm_exit_reasons_str,
3007 .gb_page_enable = svm_gb_page_enable,
3008 };
3009
3010 static int __init svm_init(void)
3011 {
3012 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3013 THIS_MODULE);
3014 }
3015
3016 static void __exit svm_exit(void)
3017 {
3018 kvm_exit();
3019 }
3020
3021 module_init(svm_init)
3022 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree