?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] 4189/1: AT91: MACB Ethernet clock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.h
blob6ed1d47dbbd3452bfa0460fb6b92df67c8370f5f
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
8
9 /* PCI config registers */
10 enum {
11 PCI_DEV_REG1 = 0x40,
12 PCI_DEV_REG2 = 0x44,
13 PCI_DEV_STATUS = 0x7c,
14 PCI_DEV_REG3 = 0x80,
15 PCI_DEV_REG4 = 0x84,
16 PCI_DEV_REG5 = 0x88,
17 };
18
19 enum {
20 PEX_DEV_CAP = 0xe4,
21 PEX_DEV_CTRL = 0xe8,
22 PEX_DEV_STA = 0xea,
23 PEX_LNK_STAT = 0xf2,
24 PEX_UNC_ERR_STAT= 0x104,
25 };
26
27 /* Yukon-2 */
28 enum pci_dev_reg_1 {
29 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
30 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
31 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
32 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
33 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
34 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
35 };
36
37 enum pci_dev_reg_2 {
38 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
39 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
40 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
41
42 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
43 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
44 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
45 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
46
47 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
48 };
49
50 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
51 enum pci_dev_reg_4 {
52 /* (Link Training & Status State Machine) */
53 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
54 /* (Active State Power Management) */
55 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
56 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
57 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
58 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
59
60 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
61 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
62 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
63 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
64 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
65 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
66 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
67 };
68
69
70 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
71 PCI_STATUS_SIG_SYSTEM_ERROR | \
72 PCI_STATUS_REC_MASTER_ABORT | \
73 PCI_STATUS_REC_TARGET_ABORT | \
74 PCI_STATUS_PARITY)
75
76 enum pex_dev_ctrl {
77 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
78 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
79 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
80 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
81 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
82 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
83 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
84 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
85 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
86 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
87 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
88 };
89 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
90
91 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
92 enum pex_err {
93 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
94
95 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
96
97 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
98
99 PEX_COMP_TO = 1<<14, /* Completion Timeout */
100 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
101 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
102
103 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
104 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
105 };
106
107
108 enum csr_regs {
109 B0_RAP = 0x0000,
110 B0_CTST = 0x0004,
111 B0_Y2LED = 0x0005,
112 B0_POWER_CTRL = 0x0007,
113 B0_ISRC = 0x0008,
114 B0_IMSK = 0x000c,
115 B0_HWE_ISRC = 0x0010,
116 B0_HWE_IMSK = 0x0014,
117
118 /* Special ISR registers (Yukon-2 only) */
119 B0_Y2_SP_ISRC2 = 0x001c,
120 B0_Y2_SP_ISRC3 = 0x0020,
121 B0_Y2_SP_EISR = 0x0024,
122 B0_Y2_SP_LISR = 0x0028,
123 B0_Y2_SP_ICR = 0x002c,
124
125 B2_MAC_1 = 0x0100,
126 B2_MAC_2 = 0x0108,
127 B2_MAC_3 = 0x0110,
128 B2_CONN_TYP = 0x0118,
129 B2_PMD_TYP = 0x0119,
130 B2_MAC_CFG = 0x011a,
131 B2_CHIP_ID = 0x011b,
132 B2_E_0 = 0x011c,
133
134 B2_Y2_CLK_GATE = 0x011d,
135 B2_Y2_HW_RES = 0x011e,
136 B2_E_3 = 0x011f,
137 B2_Y2_CLK_CTRL = 0x0120,
138
139 B2_TI_INI = 0x0130,
140 B2_TI_VAL = 0x0134,
141 B2_TI_CTRL = 0x0138,
142 B2_TI_TEST = 0x0139,
143
144 B2_TST_CTRL1 = 0x0158,
145 B2_TST_CTRL2 = 0x0159,
146 B2_GP_IO = 0x015c,
147
148 B2_I2C_CTRL = 0x0160,
149 B2_I2C_DATA = 0x0164,
150 B2_I2C_IRQ = 0x0168,
151 B2_I2C_SW = 0x016c,
152
153 B3_RAM_ADDR = 0x0180,
154 B3_RAM_DATA_LO = 0x0184,
155 B3_RAM_DATA_HI = 0x0188,
156
157 /* RAM Interface Registers */
158 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
159 /*
160 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
161 * not usable in SW. Please notice these are NOT real timeouts, these are
162 * the number of qWords transferred continuously.
163 */
164 #define RAM_BUFFER(port, reg) (reg | (port <<6))
165
166 B3_RI_WTO_R1 = 0x0190,
167 B3_RI_WTO_XA1 = 0x0191,
168 B3_RI_WTO_XS1 = 0x0192,
169 B3_RI_RTO_R1 = 0x0193,
170 B3_RI_RTO_XA1 = 0x0194,
171 B3_RI_RTO_XS1 = 0x0195,
172 B3_RI_WTO_R2 = 0x0196,
173 B3_RI_WTO_XA2 = 0x0197,
174 B3_RI_WTO_XS2 = 0x0198,
175 B3_RI_RTO_R2 = 0x0199,
176 B3_RI_RTO_XA2 = 0x019a,
177 B3_RI_RTO_XS2 = 0x019b,
178 B3_RI_TO_VAL = 0x019c,
179 B3_RI_CTRL = 0x01a0,
180 B3_RI_TEST = 0x01a2,
181 B3_MA_TOINI_RX1 = 0x01b0,
182 B3_MA_TOINI_RX2 = 0x01b1,
183 B3_MA_TOINI_TX1 = 0x01b2,
184 B3_MA_TOINI_TX2 = 0x01b3,
185 B3_MA_TOVAL_RX1 = 0x01b4,
186 B3_MA_TOVAL_RX2 = 0x01b5,
187 B3_MA_TOVAL_TX1 = 0x01b6,
188 B3_MA_TOVAL_TX2 = 0x01b7,
189 B3_MA_TO_CTRL = 0x01b8,
190 B3_MA_TO_TEST = 0x01ba,
191 B3_MA_RCINI_RX1 = 0x01c0,
192 B3_MA_RCINI_RX2 = 0x01c1,
193 B3_MA_RCINI_TX1 = 0x01c2,
194 B3_MA_RCINI_TX2 = 0x01c3,
195 B3_MA_RCVAL_RX1 = 0x01c4,
196 B3_MA_RCVAL_RX2 = 0x01c5,
197 B3_MA_RCVAL_TX1 = 0x01c6,
198 B3_MA_RCVAL_TX2 = 0x01c7,
199 B3_MA_RC_CTRL = 0x01c8,
200 B3_MA_RC_TEST = 0x01ca,
201 B3_PA_TOINI_RX1 = 0x01d0,
202 B3_PA_TOINI_RX2 = 0x01d4,
203 B3_PA_TOINI_TX1 = 0x01d8,
204 B3_PA_TOINI_TX2 = 0x01dc,
205 B3_PA_TOVAL_RX1 = 0x01e0,
206 B3_PA_TOVAL_RX2 = 0x01e4,
207 B3_PA_TOVAL_TX1 = 0x01e8,
208 B3_PA_TOVAL_TX2 = 0x01ec,
209 B3_PA_CTRL = 0x01f0,
210 B3_PA_TEST = 0x01f2,
211
212 Y2_CFG_SPC = 0x1c00,
213 };
214
215 /* B0_CTST 16 bit Control/Status register */
216 enum {
217 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
218 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
219 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
220 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
221 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
222 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
223 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
224 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
225 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
226 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
227
228 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
229 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
230 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
231 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
232 CS_MRST_CLR = 1<<3, /* Clear Master reset */
233 CS_MRST_SET = 1<<2, /* Set Master reset */
234 CS_RST_CLR = 1<<1, /* Clear Software reset */
235 CS_RST_SET = 1, /* Set Software reset */
236 };
237
238 /* B0_LED 8 Bit LED register */
239 enum {
240 /* Bit 7.. 2: reserved */
241 LED_STAT_ON = 1<<1, /* Status LED on */
242 LED_STAT_OFF = 1, /* Status LED off */
243 };
244
245 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
246 enum {
247 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
248 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
249 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
250 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
251 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
252 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
253 PC_VCC_ON = 1<<1, /* Switch VCC On */
254 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
255 };
256
257 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
258
259 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
260 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
261 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
262 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
263 enum {
264 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
265 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
266 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
267
268 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
269 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
270 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
271 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
272
273 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
274 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
275 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
276 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
277 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
278
279 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
280 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
281 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
282 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
283 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
284
285 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
286 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
287 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
288 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
289 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
290 };
291
292 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
293 enum {
294 IS_ERR_MSK = 0x00003fff,/* All Error bits */
295
296 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
297 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
298 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
299 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
300 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
301 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
302 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
303 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
304 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
305 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
306 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
307 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
308 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
309 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
310 };
311
312 /* Hardware error interrupt mask for Yukon 2 */
313 enum {
314 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
315 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
316 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
317 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
318 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
319 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
320 /* Link 2 */
321 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
322 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
323 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
324 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
325 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
326 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
327 /* Link 1 */
328 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
329 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
330 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
331 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
332 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
333 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
334
335 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
336 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
337 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
338 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
339
340 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
341 Y2_IS_PCI_EXP |
342 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
343 };
344
345 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
346 enum {
347 DPT_START = 1<<1,
348 DPT_STOP = 1<<0,
349 };
350
351 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
352 enum {
353 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
354 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
355 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
356 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
357 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
358 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
359 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
360 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
361 };
362
363 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
364 enum {
365 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
366 /* Bit 3.. 2: reserved */
367 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
368 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
369 };
370
371 /* B2_CHIP_ID 8 bit Chip Identification Number */
372 enum {
373 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
374 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
375 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
376 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
377 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
378 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
379 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
380 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
381
382 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
383 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
384 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
385
386 CHIP_REV_YU_EC_U_A0 = 1,
387 CHIP_REV_YU_EC_U_A1 = 2,
388 CHIP_REV_YU_EC_U_B0 = 3,
389
390 CHIP_REV_YU_FE_A1 = 1,
391 CHIP_REV_YU_FE_A2 = 2,
392
393 };
394
395 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
396 enum {
397 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
398 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
399 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
400 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
401 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
402 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
403 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
404 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
405 };
406
407 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
408 enum {
409 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
410 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
411 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
412 };
413 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
414 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
415
416
417 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
418 enum {
419 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
420 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
421 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
422 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
423 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
424 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
425 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
426 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
427 };
428
429 /* B2_TI_CTRL 8 bit Timer control */
430 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
431 enum {
432 TIM_START = 1<<2, /* Start Timer */
433 TIM_STOP = 1<<1, /* Stop Timer */
434 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
435 };
436
437 /* B2_TI_TEST 8 Bit Timer Test */
438 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
439 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
440 enum {
441 TIM_T_ON = 1<<2, /* Test mode on */
442 TIM_T_OFF = 1<<1, /* Test mode off */
443 TIM_T_STEP = 1<<0, /* Test step */
444 };
445
446 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
447 /* Bit 31..19: reserved */
448 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
449 /* RAM Interface Registers */
450
451 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
452 enum {
453 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
454 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
455
456 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
457 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
458 };
459
460 #define SK_RI_TO_53 36 /* RAM interface timeout */
461
462
463 /* Port related registers FIFO, and Arbiter */
464 #define SK_REG(port,reg) (((port)<<7)+(reg))
465
466 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
467 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
468 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
469 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
470 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
471
472 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
473
474 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
475 enum {
476 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
477 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
478 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
479 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
480 TXA_START_RC = 1<<3, /* Start sync Rate Control */
481 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
482 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
483 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
484 };
485
486 /*
487 * Bank 4 - 5
488 */
489 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
490 enum {
491 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
492 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
493 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
494 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
495 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
496 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
497 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
498 };
499
500
501 enum {
502 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
503 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
504 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
505 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
506 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
507 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
508 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
509 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
510 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
511 };
512
513 /* Queue Register Offsets, use Q_ADDR() to access */
514 enum {
515 B8_Q_REGS = 0x0400, /* base of Queue registers */
516 Q_D = 0x00, /* 8*32 bit Current Descriptor */
517 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
518 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
519 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
520 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
521 Q_BC = 0x30, /* 32 bit Current Byte Counter */
522 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
523 Q_F = 0x38, /* 32 bit Flag Register */
524 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
525 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
526 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
527 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
528 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
529 Q_T2 = 0x40, /* 32 bit Test Register 2 */
530 Q_T3 = 0x44, /* 32 bit Test Register 3 */
531
532 /* Yukon-2 */
533 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
534 Q_WM = 0x40, /* 16 bit FIFO Watermark */
535 Q_AL = 0x42, /* 8 bit FIFO Alignment */
536 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
537 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
538 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
539 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
540 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
541 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
542 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
543 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
544 };
545 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
546
547 /* Q_F 32 bit Flag Register */
548 enum {
549 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
550 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
551 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
552 F_WM_REACHED = 1<<25, /* Watermark reached */
553 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
554 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
555 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
556 };
557
558 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
559 enum {
560 Y2_B8_PREF_REGS = 0x0450,
561
562 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
563 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
564 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
565 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
566 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
567 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
568 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
569 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
570 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
571 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
572
573 PREF_UNIT_MASK_IDX = 0x0fff,
574 };
575 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
576
577 /* RAM Buffer Register Offsets */
578 enum {
579
580 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
581 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
582 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
583 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
584 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
585 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
586 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
587 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
588 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
589 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
590 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
591 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
592 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
593 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
594 };
595
596 /* Receive and Transmit Queues */
597 enum {
598 Q_R1 = 0x0000, /* Receive Queue 1 */
599 Q_R2 = 0x0080, /* Receive Queue 2 */
600 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
601 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
602 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
603 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
604 };
605
606 /* Different PHY Types */
607 enum {
608 PHY_ADDR_MARV = 0,
609 };
610
611 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
612
613
614 enum {
615 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
616 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
617 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
618 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
619
620 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
621
622 /* Receive GMAC FIFO (YUKON and Yukon-2) */
623
624 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
625 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
626 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
627 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
628 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
629 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
630 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
631 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
632 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
633 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
634
635 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
636
637 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
638
639 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
640 };
641
642
643 /* Q_BC 32 bit Current Byte Counter */
644
645 /* BMU Control Status Registers */
646 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
647 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
648 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
649 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
650 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
651 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
652 /* Q_CSR 32 bit BMU Control/Status Register */
653
654 /* Rx BMU Control / Status Registers (Yukon-2) */
655 enum {
656 BMU_IDLE = 1<<31, /* BMU Idle State */
657 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
658 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
659
660 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
661 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
662 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
663 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
664 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
665 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
666 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
667 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
668 BMU_START = 1<<8, /* Start Rx/Tx Queue */
669 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
670 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
671 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
672 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
673 BMU_OP_ON = 1<<3, /* BMU Operational On */
674 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
675 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
676 BMU_RST_SET = 1<<0, /* Set BMU Reset */
677
678 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
679 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
680 BMU_FIFO_ENA | BMU_OP_ON,
681
682 BMU_WM_DEFAULT = 0x600,
683 BMU_WM_PEX = 0x80,
684 };
685
686 /* Tx BMU Control / Status Registers (Yukon-2) */
687 /* Bit 31: same as for Rx */
688 enum {
689 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
690 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
691 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
692 };
693
694 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
695 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
696 enum {
697 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
698 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
699 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
700 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
701 };
702
703 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
704 /* RB_START 32 bit RAM Buffer Start Address */
705 /* RB_END 32 bit RAM Buffer End Address */
706 /* RB_WP 32 bit RAM Buffer Write Pointer */
707 /* RB_RP 32 bit RAM Buffer Read Pointer */
708 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
709 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
710 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
711 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
712 /* RB_PC 32 bit RAM Buffer Packet Counter */
713 /* RB_LEV 32 bit RAM Buffer Level Register */
714
715 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
716 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
717 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
718
719 /* RB_CTRL 8 bit RAM Buffer Control Register */
720 enum {
721 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
722 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
723 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
724 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
725 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
726 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
727 };
728
729
730 /* Transmit GMAC FIFO (YUKON only) */
731 enum {
732 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
733 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
734 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
735
736 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
737 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
738 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
739
740 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
741 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
742 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
743 };
744
745 /* Descriptor Poll Timer Registers */
746 enum {
747 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
748 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
749 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
750
751 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
752 };
753
754 /* Time Stamp Timer Registers (YUKON only) */
755 enum {
756 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
757 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
758 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
759 };
760
761 /* Polling Unit Registers (Yukon-2 only) */
762 enum {
763 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
764 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
765
766 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
767 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
768 };
769
770 /* ASF Subsystem Registers (Yukon-2 only) */
771 enum {
772 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
773 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
774 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
775
776 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
777 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
778 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
779 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
780 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
781 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
782 };
783
784 /* Status BMU Registers (Yukon-2 only)*/
785 enum {
786 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
787 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
788
789 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
790 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
791 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
792 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
793 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
794 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
795 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
796 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
797
798 /* FIFO Control/Status Registers (Yukon-2 only)*/
799 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
800 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
801 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
802 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
803 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
804 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
805 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
806
807 /* Level and ISR Timer Registers (Yukon-2 only)*/
808 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
809 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
810 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
811 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
812 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
813 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
814 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
815 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
816 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
817 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
818 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
819 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
820 };
821
822 enum {
823 LINKLED_OFF = 0x01,
824 LINKLED_ON = 0x02,
825 LINKLED_LINKSYNC_OFF = 0x04,
826 LINKLED_LINKSYNC_ON = 0x08,
827 LINKLED_BLINK_OFF = 0x10,
828 LINKLED_BLINK_ON = 0x20,
829 };
830
831 /* GMAC and GPHY Control Registers (YUKON only) */
832 enum {
833 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
834 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
835 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
836 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
837 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
838
839 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
840
841 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
842
843 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
844 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
845 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
846 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
847 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
848 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
849 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
850
851 /* WOL Pattern Length Registers (YUKON only) */
852
853 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
854 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
855
856 /* WOL Pattern Counter Registers (YUKON only) */
857
858
859 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
860 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
861 };
862
863 enum {
864 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
865 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
866 };
867
868 enum {
869 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
870 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
871 };
872
873 /*
874 * Marvel-PHY Registers, indirect addressed over GMAC
875 */
876 enum {
877 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
878 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
879 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
880 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
881 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
882 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
883 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
884 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
885 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
886 /* Marvel-specific registers */
887 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
888 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
889 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
890 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
891 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
892 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
893 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
894 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
895 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
896 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
897 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
898 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
899 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
900 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
901 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
902 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
903 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
904 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
905
906 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
907 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
908 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
909 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
910 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
911 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
912 };
913
914 enum {
915 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
916 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
917 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
918 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
919 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
920 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
921 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
922 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
923 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
924 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
925 };
926
927 enum {
928 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
929 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
930 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
931 };
932
933 enum {
934 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
935
936 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
937 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
938 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
939 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
940 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
941 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
942 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
943 };
944
945 enum {
946 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
947 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
948 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
949 };
950
951 /* different Marvell PHY Ids */
952 enum {
953 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
954
955 PHY_BCOM_ID1_A1 = 0x6041,
956 PHY_BCOM_ID1_B2 = 0x6043,
957 PHY_BCOM_ID1_C0 = 0x6044,
958 PHY_BCOM_ID1_C5 = 0x6047,
959
960 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
961 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
962 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
963 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
964 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
965 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
966 };
967
968 /* Advertisement register bits */
969 enum {
970 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
971 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
972 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
973
974 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
975 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
976 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
977 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
978 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
979 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
980 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
981 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
982 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
983 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
984 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
985 PHY_AN_100HALF | PHY_AN_100FULL,
986 };
987
988 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
989 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
990 enum {
991 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
992 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
993 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
994 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
995 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
996 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
997 /* Bit 9..8: reserved */
998 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
999 };
1000
1001 /** Marvell-Specific */
1002 enum {
1003 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1004 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1005 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1006
1007 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1008 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1009 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1010 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1011 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1012 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1013 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1014 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1015 };
1016
1017 /* special defines for FIBER (88E1011S only) */
1018 enum {
1019 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1020 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1021 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1022 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1023 };
1024
1025 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1026 enum {
1027 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1028 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1029 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1030 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1031 };
1032
1033 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1034 enum {
1035 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1036 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1037 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1038 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1039 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1040 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1041 };
1042
1043 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1044 enum {
1045 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1046 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1047 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1048 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1049 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1050 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1051 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1052 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1053 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1054 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1055 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1056 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1057 };
1058
1059 enum {
1060 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1061 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1062 };
1063
1064 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1065
1066 enum {
1067 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1068 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1069 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1070 };
1071
1072 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1073 enum {
1074 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1075 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1076 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1077 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1078 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1079
1080 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1081 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1082
1083 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1084 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1085 };
1086
1087 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1088 enum {
1089 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1090 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1091 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1092 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1093 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1094 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1095 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1096 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1097 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1098 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1099 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1100 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1101 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1102 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1103 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1104 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1105 };
1106
1107 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1108
1109 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1110 enum {
1111 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1112 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1113 };
1114
1115 enum {
1116 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1117 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1118 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1119 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1120 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1121 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1122 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1123 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1124 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1125 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1126 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1127 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1128
1129 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1130 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1131 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1132
1133 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1134 | PHY_M_IS_FIFO_ERROR,
1135 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1136 };
1137
1138
1139 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1140 enum {
1141 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1142 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1143
1144 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1145 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1146 /* (88E1011 only) */
1147 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1148 /* (88E1011 only) */
1149 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1150 /* (88E1111 only) */
1151 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1152 /* !!! Errata in spec. (1 = disable) */
1153 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1154 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1155 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1156 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1157 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1158 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1159
1160 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1161 /* 00=1x; 01=2x; 10=3x; 11=4x */
1162 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1163 /* 00=dis; 01=1x; 10=2x; 11=3x */
1164 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1165 /* 000=1x; 001=2x; 010=3x; 011=4x */
1166 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1167 /* 01X=0; 110=2.5; 111=25 (MHz) */
1168
1169 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1170 enum {
1171 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1172 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1173 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1174 };
1175 /* !!! Errata in spec. (1 = disable) */
1176
1177 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1178 /* 100=5x; 101=6x; 110=7x; 111=8x */
1179 enum {
1180 MAC_TX_CLK_0_MHZ = 2,
1181 MAC_TX_CLK_2_5_MHZ = 6,
1182 MAC_TX_CLK_25_MHZ = 7,
1183 };
1184
1185 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1186 enum {
1187 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1188 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1189 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1190 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1191 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1192 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1193 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1194 /* (88E1111 only) */
1195 };
1196
1197 enum {
1198 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1199 /* (88E1011 only) */
1200 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1201 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1202 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1203 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1204 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1205 };
1206
1207 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1208
1209 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1210 enum {
1211 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1212 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1213 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1214 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1215 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1216 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1217 };
1218
1219 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1220 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1221 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1222 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1223 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1224 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1225
1226 enum {
1227 PULS_NO_STR = 0,/* no pulse stretching */
1228 PULS_21MS = 1,/* 21 ms to 42 ms */
1229 PULS_42MS = 2,/* 42 ms to 84 ms */
1230 PULS_84MS = 3,/* 84 ms to 170 ms */
1231 PULS_170MS = 4,/* 170 ms to 340 ms */
1232 PULS_340MS = 5,/* 340 ms to 670 ms */
1233 PULS_670MS = 6,/* 670 ms to 1.3 s */
1234 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1235 };
1236
1237 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1238
1239 enum {
1240 BLINK_42MS = 0,/* 42 ms */
1241 BLINK_84MS = 1,/* 84 ms */
1242 BLINK_170MS = 2,/* 170 ms */
1243 BLINK_340MS = 3,/* 340 ms */
1244 BLINK_670MS = 4,/* 670 ms */
1245 };
1246
1247 /**** PHY_MARV_LED_OVER 16 bit r/w LED control */
1248 enum {
1249 PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */
1250 PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */
1251 PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */
1252 PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */
1253 PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */
1254 PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */
1255
1256 PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10
1257 | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000
1258 | PHY_M_LED_MO_RX,
1259 };
1260
1261 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1262 enum {
1263 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1264 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1265 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1266 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1267 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1268 };
1269
1270 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1271 enum {
1272 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1273 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1274 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1275 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1276 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1277 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1278 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1279 /* (88E1111 only) */
1280
1281 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1282 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1283 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1284 };
1285
1286 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1287 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1288 /* Bit 15..12: reserved (used internally) */
1289 enum {
1290 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1291 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1292 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1293 };
1294
1295 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1296 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1297 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1298
1299 enum {
1300 LED_PAR_CTRL_COLX = 0x00,
1301 LED_PAR_CTRL_ERROR = 0x01,
1302 LED_PAR_CTRL_DUPLEX = 0x02,
1303 LED_PAR_CTRL_DP_COL = 0x03,
1304 LED_PAR_CTRL_SPEED = 0x04,
1305 LED_PAR_CTRL_LINK = 0x05,
1306 LED_PAR_CTRL_TX = 0x06,
1307 LED_PAR_CTRL_RX = 0x07,
1308 LED_PAR_CTRL_ACT = 0x08,
1309 LED_PAR_CTRL_LNK_RX = 0x09,
1310 LED_PAR_CTRL_LNK_AC = 0x0a,
1311 LED_PAR_CTRL_ACT_BL = 0x0b,
1312 LED_PAR_CTRL_TX_BL = 0x0c,
1313 LED_PAR_CTRL_RX_BL = 0x0d,
1314 LED_PAR_CTRL_COL_BL = 0x0e,
1315 LED_PAR_CTRL_INACT = 0x0f
1316 };
1317
1318 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1319 enum {
1320 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1321 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1322 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1323 };
1324
1325 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1326 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1327 enum {
1328 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1329 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1330 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1331 };
1332
1333 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1334 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1335 enum {
1336 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1337 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1338 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1339 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1340 };
1341 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1342
1343 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1344 enum {
1345 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1346 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1347 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1348 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1349 };
1350
1351 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1352 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1353 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1354 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1355
1356 /* GMAC registers */
1357 /* Port Registers */
1358 enum {
1359 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1360 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1361 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1362 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1363 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1364 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1365 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1366 /* Source Address Registers */
1367 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1368 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1369 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1370 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1371 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1372 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1373
1374 /* Multicast Address Hash Registers */
1375 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1376 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1377 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1378 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1379
1380 /* Interrupt Source Registers */
1381 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1382 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1383 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1384
1385 /* Interrupt Mask Registers */
1386 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1387 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1388 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1389
1390 /* Serial Management Interface (SMI) Registers */
1391 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1392 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1393 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1394 /* MIB Counters */
1395 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1396 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1397 };
1398
1399
1400 /*
1401 * MIB Counters base address definitions (low word) -
1402 * use offset 4 for access to high word (32 bit r/o)
1403 */
1404 enum {
1405 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1406 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1407 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1408 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1409 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1410
1411 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1412 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1413 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1414 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1415 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1416 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1417 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1418 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1419 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1420 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1421 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1422 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1423 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1424 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1425 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1426
1427 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1428 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1429 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1430 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1431 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1432 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1433 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1434 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1435 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1436 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1437 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1438 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1439 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1440 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1441
1442 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1443 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1444 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1445 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1446 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1447 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1448 };
1449
1450 /* GMAC Bit Definitions */
1451 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1452 enum {
1453 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1454 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1455 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1456 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1457 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1458 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1459 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1460 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1461
1462 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1463 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1464 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1465 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1466 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1467 };
1468
1469 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1470 enum {
1471 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1472 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1473 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1474 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1475 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1476 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1477 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1478 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1479 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1480 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1481 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1482 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1483 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1484 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1485 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1486 };
1487
1488 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1489 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1490
1491 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1492 enum {
1493 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1494 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1495 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1496 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1497 };
1498
1499 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1500 #define TX_COL_DEF 0x04
1501
1502 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1503 enum {
1504 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1505 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1506 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1507 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1508 };
1509
1510 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1511 enum {
1512 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1513 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1514 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1515 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1516
1517 TX_JAM_LEN_DEF = 0x03,
1518 TX_JAM_IPG_DEF = 0x0b,
1519 TX_IPG_JAM_DEF = 0x1c,
1520 TX_BOF_LIM_DEF = 0x04,
1521 };
1522
1523 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1524 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1525 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1526 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1527
1528
1529 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1530 enum {
1531 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1532 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1533 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1534 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1535 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1536 };
1537
1538 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1539 #define DATA_BLIND_DEF 0x04
1540
1541 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1542 #define IPG_DATA_DEF 0x1e
1543
1544 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1545 enum {
1546 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1547 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1548 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1549 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1550 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1551 };
1552
1553 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1554 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1555
1556 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1557 enum {
1558 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1559 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1560 };
1561
1562 /* Receive Frame Status Encoding */
1563 enum {
1564 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1565 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1566 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1567 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1568 GMR_FS_MC = 1<<10, /* Multicast Packet */
1569 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1570 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1571 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1572 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1573 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1574 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1575 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1576
1577 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1578 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1579
1580 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1581 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1582 GMR_FS_MII_ERR | GMR_FS_GOOD_FC | GMR_FS_BAD_FC |
1583 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1584 };
1585
1586 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1587 enum {
1588 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1589 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1590 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1591 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1592
1593 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1594 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1595 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1596
1597 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1598 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1599 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1600 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1601 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1602 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1603 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1604
1605 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1606 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1607 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1608 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1609
1610 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1611
1612 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1613 };
1614
1615
1616 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1617 enum {
1618 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1619 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1620
1621 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1622 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1623
1624 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1625 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1626 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1627
1628 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1629 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1630 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1631 };
1632
1633 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1634 enum {
1635 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1636 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1637 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1638 };
1639
1640 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1641 enum {
1642 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1643 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1644 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1645 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1646 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1647
1648 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1649 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1650 };
1651
1652 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1653 enum {
1654 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1655 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1656 };
1657
1658 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1659 enum {
1660 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1661 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1662 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1663 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1664 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1665 };
1666
1667 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1668 enum {
1669 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1670 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1671 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1672 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1673 GMC_PAUSE_ON = 1<<3, /* Pause On */
1674 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1675 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1676 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1677 };
1678
1679 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1680 enum {
1681 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1682 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1683 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1684 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1685 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1686 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1687 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1688 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1689 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1690 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1691 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1692 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1693 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1694 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1695 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1696 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1697 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1698 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1699 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1700 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1701 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1702 /* Bits 7..2: reserved */
1703 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1704 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1705 };
1706
1707 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1708 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1709 enum {
1710 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1711 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1712 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1713 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1714 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1715 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1716
1717 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1718
1719 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1720 /* Bits 15.. 2: reserved */
1721 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1722 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1723
1724
1725 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1726 WOL_CTL_LINK_CHG_OCC = 1<<15,
1727 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1728 WOL_CTL_PATTERN_OCC = 1<<13,
1729 WOL_CTL_CLEAR_RESULT = 1<<12,
1730 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1731 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1732 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1733 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1734 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1735 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1736 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1737 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1738 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1739 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1740 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1741 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1742 };
1743
1744 #define WOL_CTL_DEFAULT \
1745 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1746 WOL_CTL_DIS_PME_ON_PATTERN | \
1747 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1748 WOL_CTL_DIS_LINK_CHG_UNIT | \
1749 WOL_CTL_DIS_PATTERN_UNIT | \
1750 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1751
1752 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1753 #define WOL_CTL_PATT_ENA(x) (1 << (x))
1754
1755
1756 /* Control flags */
1757 enum {
1758 UDPTCP = 1<<0,
1759 CALSUM = 1<<1,
1760 WR_SUM = 1<<2,
1761 INIT_SUM= 1<<3,
1762 LOCK_SUM= 1<<4,
1763 INS_VLAN= 1<<5,
1764 EOP = 1<<7,
1765 };
1766
1767 enum {
1768 HW_OWNER = 1<<7,
1769 OP_TCPWRITE = 0x11,
1770 OP_TCPSTART = 0x12,
1771 OP_TCPINIT = 0x14,
1772 OP_TCPLCK = 0x18,
1773 OP_TCPCHKSUM = OP_TCPSTART,
1774 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1775 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1776 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1777 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1778
1779 OP_ADDR64 = 0x21,
1780 OP_VLAN = 0x22,
1781 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1782 OP_LRGLEN = 0x24,
1783 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1784 OP_BUFFER = 0x40,
1785 OP_PACKET = 0x41,
1786 OP_LARGESEND = 0x43,
1787
1788 /* YUKON-2 STATUS opcodes defines */
1789 OP_RXSTAT = 0x60,
1790 OP_RXTIMESTAMP = 0x61,
1791 OP_RXVLAN = 0x62,
1792 OP_RXCHKS = 0x64,
1793 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1794 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1795 OP_RSS_HASH = 0x65,
1796 OP_TXINDEXLE = 0x68,
1797 };
1798
1799 /* Yukon 2 hardware interface */
1800 struct sky2_tx_le {
1801 __le32 addr;
1802 __le16 length; /* also vlan tag or checksum start */
1803 u8 ctrl;
1804 u8 opcode;
1805 } __attribute((packed));
1806
1807 struct sky2_rx_le {
1808 __le32 addr;
1809 __le16 length;
1810 u8 ctrl;
1811 u8 opcode;
1812 } __attribute((packed));
1813
1814 struct sky2_status_le {
1815 __le32 status; /* also checksum */
1816 __le16 length; /* also vlan tag */
1817 u8 link;
1818 u8 opcode;
1819 } __attribute((packed));
1820
1821 struct tx_ring_info {
1822 struct sk_buff *skb;
1823 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1824 DECLARE_PCI_UNMAP_ADDR(maplen);
1825 };
1826
1827 struct rx_ring_info {
1828 struct sk_buff *skb;
1829 dma_addr_t data_addr;
1830 DECLARE_PCI_UNMAP_ADDR(data_size);
1831 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
1832 };
1833
1834 enum flow_control {
1835 FC_NONE = 0,
1836 FC_TX = 1,
1837 FC_RX = 2,
1838 FC_BOTH = 3,
1839 };
1840
1841 struct sky2_port {
1842 struct sky2_hw *hw;
1843 struct net_device *netdev;
1844 unsigned port;
1845 u32 msg_enable;
1846 spinlock_t phy_lock;
1847
1848 struct tx_ring_info *tx_ring;
1849 struct sky2_tx_le *tx_le;
1850 u16 tx_cons; /* next le to check */
1851 u16 tx_prod; /* next le to use */
1852 u32 tx_addr64;
1853 u16 tx_pending;
1854 u16 tx_last_mss;
1855 u32 tx_tcpsum;
1856
1857 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
1858 struct sky2_rx_le *rx_le;
1859 u32 rx_addr64;
1860 u16 rx_next; /* next re to check */
1861 u16 rx_put; /* next le index to use */
1862 u16 rx_pending;
1863 u16 rx_data_size;
1864 u16 rx_nfrags;
1865
1866 #ifdef SKY2_VLAN_TAG_USED
1867 u16 rx_tag;
1868 struct vlan_group *vlgrp;
1869 #endif
1870
1871 dma_addr_t rx_le_map;
1872 dma_addr_t tx_le_map;
1873 u16 advertising; /* ADVERTISED_ bits */
1874 u16 speed; /* SPEED_1000, SPEED_100, ... */
1875 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1876 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1877 u8 rx_csum;
1878 enum flow_control flow_mode;
1879 enum flow_control flow_status;
1880
1881 struct net_device_stats net_stats;
1882
1883 };
1884
1885 struct sky2_hw {
1886 void __iomem *regs;
1887 struct pci_dev *pdev;
1888 struct net_device *dev[2];
1889
1890 int pm_cap;
1891 u8 chip_id;
1892 u8 chip_rev;
1893 u8 pmd_type;
1894 u8 ports;
1895
1896 struct sky2_status_le *st_le;
1897 u32 st_idx;
1898 dma_addr_t st_dma;
1899
1900 struct timer_list idle_timer;
1901 int msi;
1902 wait_queue_head_t msi_wait;
1903 };
1904
1905 static inline int sky2_is_copper(const struct sky2_hw *hw)
1906 {
1907 return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P');
1908 }
1909
1910 /* Register accessor for memory mapped device */
1911 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1912 {
1913 return readl(hw->regs + reg);
1914 }
1915
1916 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1917 {
1918 return readw(hw->regs + reg);
1919 }
1920
1921 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1922 {
1923 return readb(hw->regs + reg);
1924 }
1925
1926 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1927 {
1928 writel(val, hw->regs + reg);
1929 }
1930
1931 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1932 {
1933 writew(val, hw->regs + reg);
1934 }
1935
1936 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1937 {
1938 writeb(val, hw->regs + reg);
1939 }
1940
1941 /* Yukon PHY related registers */
1942 #define SK_GMAC_REG(port,reg) \
1943 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1944 #define GM_PHY_RETRIES 100
1945
1946 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1947 {
1948 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1949 }
1950
1951 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1952 {
1953 unsigned base = SK_GMAC_REG(port, reg);
1954 return (u32) sky2_read16(hw, base)
1955 | (u32) sky2_read16(hw, base+4) << 16;
1956 }
1957
1958 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1959 {
1960 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1961 }
1962
1963 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1964 const u8 *addr)
1965 {
1966 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1967 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1968 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1969 }
1970
1971 /* PCI config space access */
1972 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
1973 {
1974 return sky2_read32(hw, Y2_CFG_SPC + reg);
1975 }
1976
1977 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
1978 {
1979 return sky2_read16(hw, Y2_CFG_SPC + reg);
1980 }
1981
1982 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
1983 {
1984 sky2_write32(hw, Y2_CFG_SPC + reg, val);
1985 }
1986
1987 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
1988 {
1989 sky2_write16(hw, Y2_CFG_SPC + reg, val);
1990 }
1991 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree