drivers/ata/pata_cs5520.c

   1 /*
   2  *      IDE tuning and bus mastering support for the CS5510/CS5520
   3  *      chipsets
   4  *
   5  *      The CS5510/CS5520 are slightly unusual devices. Unlike the
   6  *      typical IDE controllers they do bus mastering with the drive in
   7  *      PIO mode and smarter silicon.
   8  *
   9  *      The practical upshot of this is that we must always tune the
  10  *      drive for the right PIO mode. We must also ignore all the blacklists
  11  *      and the drive bus mastering DMA information. Also to confuse matters
  12  *      further we can do DMA on PIO only drives.
  13  *
  14  *      DMA on the 5510 also requires we disable_hlt() during DMA on early
  15  *      revisions.
  16  *
  17  *      *** This driver is strictly experimental ***
  18  *
  19  *      (c) Copyright Red Hat Inc 2002
  20  *
  21  * This program is free software; you can redistribute it and/or modify it
  22  * under the terms of the GNU General Public License as published by the
  23  * Free Software Foundation; either version 2, or (at your option) any
  24  * later version.
  25  *
  26  * This program is distributed in the hope that it will be useful, but
  27  * WITHOUT ANY WARRANTY; without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  29  * General Public License for more details.
  30  *
  31  * Documentation:
  32  *      Not publically available.
  33  */
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <linux/init.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/delay.h>
  40 #include <scsi/scsi_host.h>
  41 #include <linux/libata.h>
  42
  43 #define DRV_NAME        "pata_cs5520"
  44 #define DRV_VERSION     "0.6.3"
  45
  46 struct pio_clocks
  47 {
  48         int address;
  49         int assert;
  50         int recovery;
  51 };
  52
  53 static const struct pio_clocks cs5520_pio_clocks[]={
  54         {3, 6, 11},
  55         {2, 5, 6},
  56         {1, 4, 3},
  57         {1, 3, 2},
  58         {1, 2, 1}
  59 };
  60
  61 /**
  62  *      cs5520_set_timings      -       program PIO timings
  63  *      @ap: ATA port
  64  *      @adev: ATA device
  65  *
  66  *      Program the PIO mode timings for the controller according to the pio
  67  *      clocking table.
  68  */
  69
  70 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
  71 {
  72         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  73         int slave = adev->devno;
  74
  75         pio -= XFER_PIO_0;
  76
  77         /* Channel command timing */
  78         pci_write_config_byte(pdev, 0x62 + ap->port_no,
  79                                 (cs5520_pio_clocks[pio].recovery << 4) |
  80                                 (cs5520_pio_clocks[pio].assert));
  81         /* FIXME: should these use address ? */
  82         /* Read command timing */
  83         pci_write_config_byte(pdev, 0x64 +  4*ap->port_no + slave,
  84                                 (cs5520_pio_clocks[pio].recovery << 4) |
  85                                 (cs5520_pio_clocks[pio].assert));
  86         /* Write command timing */
  87         pci_write_config_byte(pdev, 0x66 +  4*ap->port_no + slave,
  88                                 (cs5520_pio_clocks[pio].recovery << 4) |
  89                                 (cs5520_pio_clocks[pio].assert));
  90 }
  91
  92 /**
  93  *      cs5520_enable_dma       -       turn on DMA bits
  94  *
  95  *      Turn on the DMA bits for this disk. Needed because the BIOS probably
  96  *      has not done the work for us. Belongs in the core SATA code.
  97  */
  98
  99 static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
 100 {
 101         /* Set the DMA enable/disable flag */
 102         u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02);
 103         reg |= 1<<(adev->devno + 5);
 104         outb(reg, ap->ioaddr.bmdma_addr + 0x02);
 105 }
 106
 107 /**
 108  *      cs5520_set_dmamode      -       program DMA timings
 109  *      @ap: ATA port
 110  *      @adev: ATA device
 111  *
 112  *      Program the DMA mode timings for the controller according to the pio
 113  *      clocking table. Note that this device sets the DMA timings to PIO
 114  *      mode values. This may seem bizarre but the 5520 architecture talks
 115  *      PIO mode to the disk and DMA mode to the controller so the underlying
 116  *      transfers are PIO timed.
 117  */
 118
 119 static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 120 {
 121         static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
 122         cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
 123         cs5520_enable_dma(ap, adev);
 124 }
 125
 126 /**
 127  *      cs5520_set_piomode      -       program PIO timings
 128  *      @ap: ATA port
 129  *      @adev: ATA device
 130  *
 131  *      Program the PIO mode timings for the controller according to the pio
 132  *      clocking table. We know pio_mode will equal dma_mode because of the
 133  *      CS5520 architecture. At least once we turned DMA on and wrote a
 134  *      mode setter.
 135  */
 136
 137 static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
 138 {
 139         cs5520_set_timings(ap, adev, adev->pio_mode);
 140 }
 141
 142
 143 static int cs5520_pre_reset(struct ata_port *ap)
 144 {
 145         ap->cbl = ATA_CBL_PATA40;
 146         return ata_std_prereset(ap);
 147 }
 148
 149 static void cs5520_error_handler(struct ata_port *ap)
 150 {
 151         return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
 152 }
 153
 154 static struct scsi_host_template cs5520_sht = {
 155         .module                 = THIS_MODULE,
 156         .name                   = DRV_NAME,
 157         .ioctl                  = ata_scsi_ioctl,
 158         .queuecommand           = ata_scsi_queuecmd,
 159         .can_queue              = ATA_DEF_QUEUE,
 160         .this_id                = ATA_SHT_THIS_ID,
 161         .sg_tablesize           = LIBATA_MAX_PRD,
 162         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 163         .emulated               = ATA_SHT_EMULATED,
 164         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 165         .proc_name              = DRV_NAME,
 166         .dma_boundary           = ATA_DMA_BOUNDARY,
 167         .slave_configure        = ata_scsi_slave_config,
 168         .slave_destroy          = ata_scsi_slave_destroy,
 169         .bios_param             = ata_std_bios_param,
 170         .resume                 = ata_scsi_device_resume,
 171         .suspend                = ata_scsi_device_suspend,
 172 };
 173
 174 static struct ata_port_operations cs5520_port_ops = {
 175         .port_disable           = ata_port_disable,
 176         .set_piomode            = cs5520_set_piomode,
 177         .set_dmamode            = cs5520_set_dmamode,
 178
 179         .tf_load                = ata_tf_load,
 180         .tf_read                = ata_tf_read,
 181         .check_status           = ata_check_status,
 182         .exec_command           = ata_exec_command,
 183         .dev_select             = ata_std_dev_select,
 184
 185         .freeze                 = ata_bmdma_freeze,
 186         .thaw                   = ata_bmdma_thaw,
 187         .error_handler          = cs5520_error_handler,
 188         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 189
 190         .bmdma_setup            = ata_bmdma_setup,
 191         .bmdma_start            = ata_bmdma_start,
 192         .bmdma_stop             = ata_bmdma_stop,
 193         .bmdma_status           = ata_bmdma_status,
 194         .qc_prep                = ata_qc_prep,
 195         .qc_issue               = ata_qc_issue_prot,
 196         .data_xfer              = ata_pio_data_xfer,
 197
 198         .irq_handler            = ata_interrupt,
 199         .irq_clear              = ata_bmdma_irq_clear,
 200
 201         .port_start             = ata_port_start,
 202         .port_stop              = ata_port_stop,
 203         .host_stop              = ata_host_stop,
 204 };
 205
 206 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 207 {
 208         u8 pcicfg;
 209         static struct ata_probe_ent probe[2];
 210         int ports = 0;
 211
 212         /* IDE port enable bits */
 213         pci_read_config_byte(dev, 0x60, &pcicfg);
 214
 215         /* Check if the ATA ports are enabled */
 216         if ((pcicfg & 3) == 0)
 217                 return -ENODEV;
 218
 219         if ((pcicfg & 0x40) == 0) {
 220                 printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n");
 221                 pci_write_config_byte(dev, 0x60, pcicfg | 0x40);
 222         }
 223
 224         /* Perform set up for DMA */
 225         if (pci_enable_device_bars(dev, 1<<2)) {
 226                 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
 227                 return -ENODEV;
 228         }
 229         pci_set_master(dev);
 230         if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
 231                 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
 232                 return -ENODEV;
 233         }
 234         if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
 235                 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
 236                 return -ENODEV;
 237         }
 238
 239         /* We have to do our own plumbing as the PCI setup for this
 240            chipset is non-standard so we can't punt to the libata code */
 241
 242         INIT_LIST_HEAD(&probe[0].node);
 243         probe[0].dev = pci_dev_to_dev(dev);
 244         probe[0].port_ops = &cs5520_port_ops;
 245         probe[0].sht = &cs5520_sht;
 246         probe[0].pio_mask = 0x1F;
 247         probe[0].mwdma_mask = id->driver_data;
 248         probe[0].irq = 14;
 249         probe[0].irq_flags = 0;
 250         probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
 251         probe[0].n_ports = 1;
 252         probe[0].port[0].cmd_addr = 0x1F0;
 253         probe[0].port[0].ctl_addr = 0x3F6;
 254         probe[0].port[0].altstatus_addr = 0x3F6;
 255         probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2);
 256
 257         /* The secondary lurks at different addresses but is otherwise
 258            the same beastie */
 259
 260         probe[1] = probe[0];
 261         INIT_LIST_HEAD(&probe[1].node);
 262         probe[1].irq = 15;
 263         probe[1].port[0].cmd_addr = 0x170;
 264         probe[1].port[0].ctl_addr = 0x376;
 265         probe[1].port[0].altstatus_addr = 0x376;
 266         probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8;
 267
 268         /* Let libata fill in the port details */
 269         ata_std_ports(&probe[0].port[0]);
 270         ata_std_ports(&probe[1].port[0]);
 271
 272         /* Now add the ports that are active */
 273         if (pcicfg & 1)
 274                 ports += ata_device_add(&probe[0]);
 275         if (pcicfg & 2)
 276                 ports += ata_device_add(&probe[1]);
 277         if (ports)
 278                 return 0;
 279         return -ENODEV;
 280 }
 281
 282 /**
 283  *      cs5520_remove_one       -       device unload
 284  *      @pdev: PCI device being removed
 285  *
 286  *      Handle an unplug/unload event for a PCI device. Unload the
 287  *      PCI driver but do not use the default handler as we manage
 288  *      resources ourself and *MUST NOT* disable the device as it has
 289  *      other functions.
 290  */
 291
 292 static void __devexit cs5520_remove_one(struct pci_dev *pdev)
 293 {
 294         struct device *dev = pci_dev_to_dev(pdev);
 295         struct ata_host *host = dev_get_drvdata(dev);
 296
 297         ata_host_remove(host);
 298         dev_set_drvdata(dev, NULL);
 299 }
 300
 301 /**
 302  *      cs5520_reinit_one       -       device resume
 303  *      @pdev: PCI device
 304  *
 305  *      Do any reconfiguration work needed by a resume from RAM. We need
 306  *      to restore DMA mode support on BIOSen which disabled it
 307  */
 308
 309 static int cs5520_reinit_one(struct pci_dev *pdev)
 310 {
 311         u8 pcicfg;
 312         pci_read_config_byte(pdev, 0x60, &pcicfg);
 313         if ((pcicfg & 0x40) == 0)
 314                 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
 315         return ata_pci_device_resume(pdev);
 316 }
 317 /* For now keep DMA off. We can set it for all but A rev CS5510 once the
 318    core ATA code can handle it */
 319
 320 static const struct pci_device_id pata_cs5520[] = {
 321         { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
 322         { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
 323
 324         { },
 325 };
 326
 327 static struct pci_driver cs5520_pci_driver = {
 328         .name           = DRV_NAME,
 329         .id_table       = pata_cs5520,
 330         .probe          = cs5520_init_one,
 331         .remove         = cs5520_remove_one,
 332         .suspend        = ata_pci_device_suspend,
 333         .resume         = cs5520_reinit_one,
 334 };
 335
 336 static int __init cs5520_init(void)
 337 {
 338         return pci_register_driver(&cs5520_pci_driver);
 339 }
 340
 341 static void __exit cs5520_exit(void)
 342 {
 343         pci_unregister_driver(&cs5520_pci_driver);
 344 }
 345
 346 MODULE_AUTHOR("Alan Cox");
 347 MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
 348 MODULE_LICENSE("GPL");
 349 MODULE_DEVICE_TABLE(pci, pata_cs5520);
 350 MODULE_VERSION(DRV_VERSION);
 351
 352 module_init(cs5520_init);
 353 module_exit(cs5520_exit);
 354