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[ARM] 4189/1: AT91: MACB Ethernet clock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / pata_cmd64x.c
blob449162cbf93ef13477bbecaff90e23fdbf8df585
1 /*
2 * pata_cmd64x.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based upon
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
8 *
9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10 * Note, this driver is not used at all on other systems because
11 * there the "BIOS" has done all of the following already.
12 * Due to massive hardware bugs, UltraDMA is only supported
13 * on the 646U2 and not on the 646U.
14 *
15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
16 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
17 *
18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
19 *
20 * TODO
21 * Testing work
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <scsi/scsi_host.h>
31 #include <linux/libata.h>
32
33 #define DRV_NAME "pata_cmd64x"
34 #define DRV_VERSION "0.2.2"
35
36 /*
37 * CMD64x specific registers definition.
38 */
39
40 enum {
41 CFR = 0x50,
42 CFR_INTR_CH0 = 0x02,
43 CNTRL = 0x51,
44 CNTRL_DIS_RA0 = 0x40,
45 CNTRL_DIS_RA1 = 0x80,
46 CNTRL_ENA_2ND = 0x08,
47 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
56 ARTTIM2 = 0x57,
57 ARTTIM3 = 0x57,
58 DRWTIM23 = 0x58,
59 DRWTIM2 = 0x58,
60 BRST = 0x59,
61 DRWTIM3 = 0x5b,
62 BMIDECR0 = 0x70,
63 MRDMODE = 0x71,
64 MRDMODE_INTR_CH0 = 0x04,
65 MRDMODE_INTR_CH1 = 0x08,
66 MRDMODE_BLK_CH0 = 0x10,
67 MRDMODE_BLK_CH1 = 0x20,
68 BMIDESR0 = 0x72,
69 UDIDETCR0 = 0x73,
70 DTPR0 = 0x74,
71 BMIDECR1 = 0x78,
72 BMIDECSR = 0x79,
73 BMIDESR1 = 0x7A,
74 UDIDETCR1 = 0x7B,
75 DTPR1 = 0x7C
76 };
77
78 static int cmd64x_pre_reset(struct ata_port *ap)
79 {
80 ap->cbl = ATA_CBL_PATA40;
81 return ata_std_prereset(ap);
82 }
83
84 static int cmd648_pre_reset(struct ata_port *ap)
85 {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87 u8 r;
88
89 /* Check cable detect bits */
90 pci_read_config_byte(pdev, BMIDECSR, &r);
91 if (r & (1 << ap->port_no))
92 ap->cbl = ATA_CBL_PATA80;
93 else
94 ap->cbl = ATA_CBL_PATA40;
95
96 return ata_std_prereset(ap);
97 }
98
99 static void cmd64x_error_handler(struct ata_port *ap)
100 {
101 return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
102 }
103
104 static void cmd648_error_handler(struct ata_port *ap)
105 {
106 ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
107 }
108
109 /**
110 * cmd64x_set_piomode - set initial PIO mode data
111 * @ap: ATA interface
112 * @adev: ATA device
113 *
114 * Called to do the PIO mode setup.
115 */
116
117 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
118 {
119 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
120 struct ata_timing t;
121 const unsigned long T = 1000000 / 33;
122 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
123
124 u8 reg;
125
126 /* Port layout is not logical so use a table */
127 const u8 arttim_port[2][2] = {
128 { ARTTIM0, ARTTIM1 },
129 { ARTTIM23, ARTTIM23 }
130 };
131 const u8 drwtim_port[2][2] = {
132 { DRWTIM0, DRWTIM1 },
133 { DRWTIM2, DRWTIM3 }
134 };
135
136 int arttim = arttim_port[ap->port_no][adev->devno];
137 int drwtim = drwtim_port[ap->port_no][adev->devno];
138
139
140 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
141 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
142 return;
143 }
144 if (ap->port_no) {
145 /* Slave has shared address setup */
146 struct ata_device *pair = ata_dev_pair(adev);
147
148 if (pair) {
149 struct ata_timing tp;
150 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
151 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
152 }
153 }
154
155 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
156 t.active, t.recover, t.setup);
157 if (t.recover > 16) {
158 t.active += t.recover - 16;
159 t.recover = 16;
160 }
161 if (t.active > 16)
162 t.active = 16;
163
164 /* Now convert the clocks into values we can actually stuff into
165 the chip */
166
167 if (t.recover > 1)
168 t.recover--;
169 else
170 t.recover = 15;
171
172 if (t.setup > 4)
173 t.setup = 0xC0;
174 else
175 t.setup = setup_data[t.setup];
176
177 t.active &= 0x0F; /* 0 = 16 */
178
179 /* Load setup timing */
180 pci_read_config_byte(pdev, arttim, &reg);
181 reg &= 0x3F;
182 reg |= t.setup;
183 pci_write_config_byte(pdev, arttim, reg);
184
185 /* Load active/recovery */
186 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
187 }
188
189 /**
190 * cmd64x_set_dmamode - set initial DMA mode data
191 * @ap: ATA interface
192 * @adev: ATA device
193 *
194 * Called to do the DMA mode setup.
195 */
196
197 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
198 {
199 static const u8 udma_data[] = {
200 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
201 };
202 static const u8 mwdma_data[] = {
203 0x30, 0x20, 0x10
204 };
205
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
207 u8 regU, regD;
208
209 int pciU = UDIDETCR0 + 8 * ap->port_no;
210 int pciD = BMIDESR0 + 8 * ap->port_no;
211 int shift = 2 * adev->devno;
212
213 pci_read_config_byte(pdev, pciD, &regD);
214 pci_read_config_byte(pdev, pciU, &regU);
215
216 /* DMA bits off */
217 regD &= ~(0x20 << adev->devno);
218 /* DMA control bits */
219 regU &= ~(0x30 << shift);
220 /* DMA timing bits */
221 regU &= ~(0x05 << adev->devno);
222
223 if (adev->dma_mode >= XFER_UDMA_0) {
224 /* Merge thge timing value */
225 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
226 /* Merge the control bits */
227 regU |= 1 << adev->devno; /* UDMA on */
228 if (adev->dma_mode > 2) /* 15nS timing */
229 regU |= 4 << adev->devno;
230 } else
231 regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
232
233 regD |= 0x20 << adev->devno;
234
235 pci_write_config_byte(pdev, pciU, regU);
236 pci_write_config_byte(pdev, pciD, regD);
237 }
238
239 /**
240 * cmd648_dma_stop - DMA stop callback
241 * @qc: Command in progress
242 *
243 * DMA has completed.
244 */
245
246 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
247 {
248 struct ata_port *ap = qc->ap;
249 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
250 u8 dma_intr;
251 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
252 int dma_reg = ap->port_no ? ARTTIM2 : CFR;
253
254 ata_bmdma_stop(qc);
255
256 pci_read_config_byte(pdev, dma_reg, &dma_intr);
257 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
258 }
259
260 /**
261 * cmd646r1_dma_stop - DMA stop callback
262 * @qc: Command in progress
263 *
264 * Stub for now while investigating the r1 quirk in the old driver.
265 */
266
267 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
268 {
269 ata_bmdma_stop(qc);
270 }
271
272 static struct scsi_host_template cmd64x_sht = {
273 .module = THIS_MODULE,
274 .name = DRV_NAME,
275 .ioctl = ata_scsi_ioctl,
276 .queuecommand = ata_scsi_queuecmd,
277 .can_queue = ATA_DEF_QUEUE,
278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = LIBATA_MAX_PRD,
280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = ATA_SHT_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = ATA_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
286 .slave_destroy = ata_scsi_slave_destroy,
287 .bios_param = ata_std_bios_param,
288 .resume = ata_scsi_device_resume,
289 .suspend = ata_scsi_device_suspend,
290 };
291
292 static struct ata_port_operations cmd64x_port_ops = {
293 .port_disable = ata_port_disable,
294 .set_piomode = cmd64x_set_piomode,
295 .set_dmamode = cmd64x_set_dmamode,
296 .mode_filter = ata_pci_default_filter,
297 .tf_load = ata_tf_load,
298 .tf_read = ata_tf_read,
299 .check_status = ata_check_status,
300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
302
303 .freeze = ata_bmdma_freeze,
304 .thaw = ata_bmdma_thaw,
305 .error_handler = cmd64x_error_handler,
306 .post_internal_cmd = ata_bmdma_post_internal_cmd,
307
308 .bmdma_setup = ata_bmdma_setup,
309 .bmdma_start = ata_bmdma_start,
310 .bmdma_stop = ata_bmdma_stop,
311 .bmdma_status = ata_bmdma_status,
312
313 .qc_prep = ata_qc_prep,
314 .qc_issue = ata_qc_issue_prot,
315
316 .data_xfer = ata_pio_data_xfer,
317
318 .irq_handler = ata_interrupt,
319 .irq_clear = ata_bmdma_irq_clear,
320
321 .port_start = ata_port_start,
322 .port_stop = ata_port_stop,
323 .host_stop = ata_host_stop
324 };
325
326 static struct ata_port_operations cmd646r1_port_ops = {
327 .port_disable = ata_port_disable,
328 .set_piomode = cmd64x_set_piomode,
329 .set_dmamode = cmd64x_set_dmamode,
330 .mode_filter = ata_pci_default_filter,
331 .tf_load = ata_tf_load,
332 .tf_read = ata_tf_read,
333 .check_status = ata_check_status,
334 .exec_command = ata_exec_command,
335 .dev_select = ata_std_dev_select,
336
337 .freeze = ata_bmdma_freeze,
338 .thaw = ata_bmdma_thaw,
339 .error_handler = cmd64x_error_handler,
340 .post_internal_cmd = ata_bmdma_post_internal_cmd,
341
342 .bmdma_setup = ata_bmdma_setup,
343 .bmdma_start = ata_bmdma_start,
344 .bmdma_stop = cmd646r1_bmdma_stop,
345 .bmdma_status = ata_bmdma_status,
346
347 .qc_prep = ata_qc_prep,
348 .qc_issue = ata_qc_issue_prot,
349
350 .data_xfer = ata_pio_data_xfer,
351
352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear,
354
355 .port_start = ata_port_start,
356 .port_stop = ata_port_stop,
357 .host_stop = ata_host_stop
358 };
359
360 static struct ata_port_operations cmd648_port_ops = {
361 .port_disable = ata_port_disable,
362 .set_piomode = cmd64x_set_piomode,
363 .set_dmamode = cmd64x_set_dmamode,
364 .mode_filter = ata_pci_default_filter,
365 .tf_load = ata_tf_load,
366 .tf_read = ata_tf_read,
367 .check_status = ata_check_status,
368 .exec_command = ata_exec_command,
369 .dev_select = ata_std_dev_select,
370
371 .freeze = ata_bmdma_freeze,
372 .thaw = ata_bmdma_thaw,
373 .error_handler = cmd648_error_handler,
374 .post_internal_cmd = ata_bmdma_post_internal_cmd,
375
376 .bmdma_setup = ata_bmdma_setup,
377 .bmdma_start = ata_bmdma_start,
378 .bmdma_stop = cmd648_bmdma_stop,
379 .bmdma_status = ata_bmdma_status,
380
381 .qc_prep = ata_qc_prep,
382 .qc_issue = ata_qc_issue_prot,
383
384 .data_xfer = ata_pio_data_xfer,
385
386 .irq_handler = ata_interrupt,
387 .irq_clear = ata_bmdma_irq_clear,
388
389 .port_start = ata_port_start,
390 .port_stop = ata_port_stop,
391 .host_stop = ata_host_stop
392 };
393
394 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
395 {
396 u32 class_rev;
397
398 static struct ata_port_info cmd_info[6] = {
399 { /* CMD 643 - no UDMA */
400 .sht = &cmd64x_sht,
401 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
402 .pio_mask = 0x1f,
403 .mwdma_mask = 0x07,
404 .port_ops = &cmd64x_port_ops
405 },
406 { /* CMD 646 with broken UDMA */
407 .sht = &cmd64x_sht,
408 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
409 .pio_mask = 0x1f,
410 .mwdma_mask = 0x07,
411 .port_ops = &cmd64x_port_ops
412 },
413 { /* CMD 646 with working UDMA */
414 .sht = &cmd64x_sht,
415 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
416 .pio_mask = 0x1f,
417 .mwdma_mask = 0x07,
418 .udma_mask = ATA_UDMA1,
419 .port_ops = &cmd64x_port_ops
420 },
421 { /* CMD 646 rev 1 */
422 .sht = &cmd64x_sht,
423 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
424 .pio_mask = 0x1f,
425 .mwdma_mask = 0x07,
426 .port_ops = &cmd646r1_port_ops
427 },
428 { /* CMD 648 */
429 .sht = &cmd64x_sht,
430 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
431 .pio_mask = 0x1f,
432 .mwdma_mask = 0x07,
433 .udma_mask = ATA_UDMA2,
434 .port_ops = &cmd648_port_ops
435 },
436 { /* CMD 649 */
437 .sht = &cmd64x_sht,
438 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
439 .pio_mask = 0x1f,
440 .mwdma_mask = 0x07,
441 .udma_mask = ATA_UDMA3,
442 .port_ops = &cmd648_port_ops
443 }
444 };
445 static struct ata_port_info *port_info[2], *info;
446 u8 mrdmode;
447
448 info = &cmd_info[id->driver_data];
449
450 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
451 class_rev &= 0xFF;
452
453 if (id->driver_data == 0) /* 643 */
454 ata_pci_clear_simplex(pdev);
455
456 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
457 /* Does UDMA work ? */
458 if (class_rev > 4)
459 info = &cmd_info[2];
460 /* Early rev with other problems ? */
461 else if (class_rev == 1)
462 info = &cmd_info[3];
463 }
464
465 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
466 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
467 mrdmode &= ~ 0x30; /* IRQ set up */
468 mrdmode |= 0x02; /* Memory read line enable */
469 pci_write_config_byte(pdev, MRDMODE, mrdmode);
470
471 /* Force PIO 0 here.. */
472
473 /* PPC specific fixup copied from old driver */
474 #ifdef CONFIG_PPC
475 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
476 #endif
477
478 port_info[0] = port_info[1] = info;
479 return ata_pci_init_one(pdev, port_info, 2);
480 }
481
482 static int cmd64x_reinit_one(struct pci_dev *pdev)
483 {
484 u8 mrdmode;
485 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
486 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
487 mrdmode &= ~ 0x30; /* IRQ set up */
488 mrdmode |= 0x02; /* Memory read line enable */
489 pci_write_config_byte(pdev, MRDMODE, mrdmode);
490 #ifdef CONFIG_PPC
491 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
492 #endif
493 return ata_pci_device_resume(pdev);
494 }
495
496 static const struct pci_device_id cmd64x[] = {
497 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
498 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
499 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
501
502 { },
503 };
504
505 static struct pci_driver cmd64x_pci_driver = {
506 .name = DRV_NAME,
507 .id_table = cmd64x,
508 .probe = cmd64x_init_one,
509 .remove = ata_pci_remove_one,
510 .suspend = ata_pci_device_suspend,
511 .resume = cmd64x_reinit_one,
512 };
513
514 static int __init cmd64x_init(void)
515 {
516 return pci_register_driver(&cmd64x_pci_driver);
517 }
518
519 static void __exit cmd64x_exit(void)
520 {
521 pci_unregister_driver(&cmd64x_pci_driver);
522 }
523
524 MODULE_AUTHOR("Alan Cox");
525 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
526 MODULE_LICENSE("GPL");
527 MODULE_DEVICE_TABLE(pci, cmd64x);
528 MODULE_VERSION(DRV_VERSION);
529
530 module_init(cmd64x_init);
531 module_exit(cmd64x_exit);
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