3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
25 static int pci_msi_enable
= 1;
29 #ifndef arch_msi_check_device
30 int arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
36 #ifndef arch_setup_msi_irqs
37 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
39 struct msi_desc
*entry
;
43 * If an architecture wants to support multiple MSI, it needs to
44 * override arch_setup_msi_irqs()
46 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
49 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
50 ret
= arch_setup_msi_irq(dev
, entry
);
61 #ifndef arch_teardown_msi_irqs
62 void arch_teardown_msi_irqs(struct pci_dev
*dev
)
64 struct msi_desc
*entry
;
66 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
70 nvec
= 1 << entry
->msi_attrib
.multiple
;
71 for (i
= 0; i
< nvec
; i
++)
72 arch_teardown_msi_irq(entry
->irq
+ i
);
77 static void msi_set_enable(struct pci_dev
*dev
, int pos
, int enable
)
83 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
84 control
&= ~PCI_MSI_FLAGS_ENABLE
;
86 control
|= PCI_MSI_FLAGS_ENABLE
;
87 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
90 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
95 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
97 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
98 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
100 control
|= PCI_MSIX_FLAGS_ENABLE
;
101 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
105 static inline __attribute_const__ u32
msi_mask(unsigned x
)
107 /* Don't shift by >= width of type */
110 return (1 << (1 << x
)) - 1;
113 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
115 return msi_mask((control
>> 1) & 7);
118 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
120 return msi_mask((control
>> 4) & 7);
124 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
125 * mask all MSI interrupts by clearing the MSI enable bit does not work
126 * reliably as devices without an INTx disable bit will then generate a
127 * level IRQ which will never be cleared.
129 static u32
__msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
131 u32 mask_bits
= desc
->masked
;
133 if (!desc
->msi_attrib
.maskbit
)
138 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
143 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
145 desc
->masked
= __msi_mask_irq(desc
, mask
, flag
);
149 * This internal function does not flush PCI writes to the device.
150 * All users must ensure that they read from the device before either
151 * assuming that the device state is up to date, or returning out of this
152 * file. This saves a few milliseconds when initialising devices with lots
153 * of MSI-X interrupts.
155 static u32
__msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
157 u32 mask_bits
= desc
->masked
;
158 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
159 PCI_MSIX_ENTRY_VECTOR_CTRL
;
162 writel(mask_bits
, desc
->mask_base
+ offset
);
167 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
169 desc
->masked
= __msix_mask_irq(desc
, flag
);
172 static void msi_set_mask_bit(unsigned irq
, u32 flag
)
174 struct msi_desc
*desc
= get_irq_msi(irq
);
176 if (desc
->msi_attrib
.is_msix
) {
177 msix_mask_irq(desc
, flag
);
178 readl(desc
->mask_base
); /* Flush write to device */
180 unsigned offset
= irq
- desc
->dev
->irq
;
181 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
185 void mask_msi_irq(unsigned int irq
)
187 msi_set_mask_bit(irq
, 1);
190 void unmask_msi_irq(unsigned int irq
)
192 msi_set_mask_bit(irq
, 0);
195 void read_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
197 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
199 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
201 if (entry
->msi_attrib
.is_msix
) {
202 void __iomem
*base
= entry
->mask_base
+
203 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
205 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
206 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
207 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
209 struct pci_dev
*dev
= entry
->dev
;
210 int pos
= entry
->msi_attrib
.pos
;
213 pci_read_config_dword(dev
, msi_lower_address_reg(pos
),
215 if (entry
->msi_attrib
.is_64
) {
216 pci_read_config_dword(dev
, msi_upper_address_reg(pos
),
218 pci_read_config_word(dev
, msi_data_reg(pos
, 1), &data
);
221 pci_read_config_word(dev
, msi_data_reg(pos
, 0), &data
);
227 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
229 struct irq_desc
*desc
= irq_to_desc(irq
);
231 read_msi_msg_desc(desc
, msg
);
234 void get_cached_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
236 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
238 /* Assert that the cache is valid, assuming that
239 * valid messages are not all-zeroes. */
240 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
246 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
248 struct irq_desc
*desc
= irq_to_desc(irq
);
250 get_cached_msi_msg_desc(desc
, msg
);
253 void write_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
255 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
257 if (entry
->dev
->current_state
!= PCI_D0
) {
258 /* Don't touch the hardware now */
259 } else if (entry
->msi_attrib
.is_msix
) {
261 base
= entry
->mask_base
+
262 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
264 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
265 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
266 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
268 struct pci_dev
*dev
= entry
->dev
;
269 int pos
= entry
->msi_attrib
.pos
;
272 pci_read_config_word(dev
, msi_control_reg(pos
), &msgctl
);
273 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
274 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
275 pci_write_config_word(dev
, msi_control_reg(pos
), msgctl
);
277 pci_write_config_dword(dev
, msi_lower_address_reg(pos
),
279 if (entry
->msi_attrib
.is_64
) {
280 pci_write_config_dword(dev
, msi_upper_address_reg(pos
),
282 pci_write_config_word(dev
, msi_data_reg(pos
, 1),
285 pci_write_config_word(dev
, msi_data_reg(pos
, 0),
292 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
294 struct irq_desc
*desc
= irq_to_desc(irq
);
296 write_msi_msg_desc(desc
, msg
);
299 static void free_msi_irqs(struct pci_dev
*dev
)
301 struct msi_desc
*entry
, *tmp
;
303 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
307 nvec
= 1 << entry
->msi_attrib
.multiple
;
308 for (i
= 0; i
< nvec
; i
++)
309 BUG_ON(irq_has_action(entry
->irq
+ i
));
312 arch_teardown_msi_irqs(dev
);
314 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
315 if (entry
->msi_attrib
.is_msix
) {
316 if (list_is_last(&entry
->list
, &dev
->msi_list
))
317 iounmap(entry
->mask_base
);
319 list_del(&entry
->list
);
324 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
326 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
330 INIT_LIST_HEAD(&desc
->list
);
336 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
338 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
339 pci_intx(dev
, enable
);
342 static void __pci_restore_msi_state(struct pci_dev
*dev
)
346 struct msi_desc
*entry
;
348 if (!dev
->msi_enabled
)
351 entry
= get_irq_msi(dev
->irq
);
352 pos
= entry
->msi_attrib
.pos
;
354 pci_intx_for_msi(dev
, 0);
355 msi_set_enable(dev
, pos
, 0);
356 write_msi_msg(dev
->irq
, &entry
->msg
);
358 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
359 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
360 control
&= ~PCI_MSI_FLAGS_QSIZE
;
361 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
362 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
365 static void __pci_restore_msix_state(struct pci_dev
*dev
)
368 struct msi_desc
*entry
;
371 if (!dev
->msix_enabled
)
373 BUG_ON(list_empty(&dev
->msi_list
));
374 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
375 pos
= entry
->msi_attrib
.pos
;
376 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
378 /* route the table */
379 pci_intx_for_msi(dev
, 0);
380 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
381 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
383 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
384 write_msi_msg(entry
->irq
, &entry
->msg
);
385 msix_mask_irq(entry
, entry
->masked
);
388 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
389 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
392 void pci_restore_msi_state(struct pci_dev
*dev
)
394 __pci_restore_msi_state(dev
);
395 __pci_restore_msix_state(dev
);
397 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
400 * msi_capability_init - configure device's MSI capability structure
401 * @dev: pointer to the pci_dev data structure of MSI device function
402 * @nvec: number of interrupts to allocate
404 * Setup the MSI capability structure of the device with the requested
405 * number of interrupts. A return value of zero indicates the successful
406 * setup of an entry with the new MSI irq. A negative return value indicates
407 * an error, and a positive return value indicates the number of interrupts
408 * which could have been allocated.
410 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
412 struct msi_desc
*entry
;
417 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
418 msi_set_enable(dev
, pos
, 0); /* Disable MSI during set up */
420 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
421 /* MSI Entry Initialization */
422 entry
= alloc_msi_entry(dev
);
426 entry
->msi_attrib
.is_msix
= 0;
427 entry
->msi_attrib
.is_64
= is_64bit_address(control
);
428 entry
->msi_attrib
.entry_nr
= 0;
429 entry
->msi_attrib
.maskbit
= is_mask_bit_support(control
);
430 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
431 entry
->msi_attrib
.pos
= pos
;
433 entry
->mask_pos
= msi_mask_reg(pos
, entry
->msi_attrib
.is_64
);
434 /* All MSIs are unmasked by default, Mask them all */
435 if (entry
->msi_attrib
.maskbit
)
436 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
437 mask
= msi_capable_mask(control
);
438 msi_mask_irq(entry
, mask
, mask
);
440 list_add_tail(&entry
->list
, &dev
->msi_list
);
442 /* Configure MSI capability structure */
443 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
445 msi_mask_irq(entry
, mask
, ~mask
);
450 /* Set MSI enabled bits */
451 pci_intx_for_msi(dev
, 0);
452 msi_set_enable(dev
, pos
, 1);
453 dev
->msi_enabled
= 1;
455 dev
->irq
= entry
->irq
;
459 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned pos
,
462 unsigned long phys_addr
;
466 pci_read_config_dword(dev
, msix_table_offset_reg(pos
), &table_offset
);
467 bir
= (u8
)(table_offset
& PCI_MSIX_FLAGS_BIRMASK
);
468 table_offset
&= ~PCI_MSIX_FLAGS_BIRMASK
;
469 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
471 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
474 static int msix_setup_entries(struct pci_dev
*dev
, unsigned pos
,
475 void __iomem
*base
, struct msix_entry
*entries
,
478 struct msi_desc
*entry
;
481 for (i
= 0; i
< nvec
; i
++) {
482 entry
= alloc_msi_entry(dev
);
488 /* No enough memory. Don't try again */
492 entry
->msi_attrib
.is_msix
= 1;
493 entry
->msi_attrib
.is_64
= 1;
494 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
495 entry
->msi_attrib
.default_irq
= dev
->irq
;
496 entry
->msi_attrib
.pos
= pos
;
497 entry
->mask_base
= base
;
499 list_add_tail(&entry
->list
, &dev
->msi_list
);
505 static void msix_program_entries(struct pci_dev
*dev
,
506 struct msix_entry
*entries
)
508 struct msi_desc
*entry
;
511 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
512 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
513 PCI_MSIX_ENTRY_VECTOR_CTRL
;
515 entries
[i
].vector
= entry
->irq
;
516 set_irq_msi(entry
->irq
, entry
);
517 entry
->masked
= readl(entry
->mask_base
+ offset
);
518 msix_mask_irq(entry
, 1);
524 * msix_capability_init - configure device's MSI-X capability
525 * @dev: pointer to the pci_dev data structure of MSI-X device function
526 * @entries: pointer to an array of struct msix_entry entries
527 * @nvec: number of @entries
529 * Setup the MSI-X capability structure of device function with a
530 * single MSI-X irq. A return of zero indicates the successful setup of
531 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
533 static int msix_capability_init(struct pci_dev
*dev
,
534 struct msix_entry
*entries
, int nvec
)
540 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
541 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
543 /* Ensure MSI-X is disabled while it is set up */
544 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
545 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
547 /* Request & Map MSI-X table region */
548 base
= msix_map_region(dev
, pos
, multi_msix_capable(control
));
552 ret
= msix_setup_entries(dev
, pos
, base
, entries
, nvec
);
556 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
561 * Some devices require MSI-X to be enabled before we can touch the
562 * MSI-X registers. We need to mask all the vectors to prevent
563 * interrupts coming in before they're fully set up.
565 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
566 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
568 msix_program_entries(dev
, entries
);
570 /* Set MSI-X enabled bits and unmask the function */
571 pci_intx_for_msi(dev
, 0);
572 dev
->msix_enabled
= 1;
574 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
575 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
582 * If we had some success, report the number of irqs
583 * we succeeded in setting up.
585 struct msi_desc
*entry
;
588 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
602 * pci_msi_check_device - check whether MSI may be enabled on a device
603 * @dev: pointer to the pci_dev data structure of MSI device function
604 * @nvec: how many MSIs have been requested ?
605 * @type: are we checking for MSI or MSI-X ?
607 * Look at global flags, the device itself, and its parent busses
608 * to determine if MSI/-X are supported for the device. If MSI/-X is
609 * supported return 0, else return an error code.
611 static int pci_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
616 /* MSI must be globally enabled and supported by the device */
617 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
621 * You can't ask to have 0 or less MSIs configured.
623 * b) the list manipulation code assumes nvec >= 1.
629 * Any bridge which does NOT route MSI transactions from its
630 * secondary bus to its primary bus must set NO_MSI flag on
631 * the secondary pci_bus.
632 * We expect only arch-specific PCI host bus controller driver
633 * or quirks for specific PCI bridges to be setting NO_MSI.
635 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
636 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
639 ret
= arch_msi_check_device(dev
, nvec
, type
);
643 if (!pci_find_capability(dev
, type
))
650 * pci_enable_msi_block - configure device's MSI capability structure
651 * @dev: device to configure
652 * @nvec: number of interrupts to configure
654 * Allocate IRQs for a device with the MSI capability.
655 * This function returns a negative errno if an error occurs. If it
656 * is unable to allocate the number of interrupts requested, it returns
657 * the number of interrupts it might be able to allocate. If it successfully
658 * allocates at least the number of interrupts requested, it returns 0 and
659 * updates the @dev's irq member to the lowest new interrupt number; the
660 * other interrupt numbers allocated to this device are consecutive.
662 int pci_enable_msi_block(struct pci_dev
*dev
, unsigned int nvec
)
664 int status
, pos
, maxvec
;
667 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
670 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
671 maxvec
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
675 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
679 WARN_ON(!!dev
->msi_enabled
);
681 /* Check whether driver already requested MSI-X irqs */
682 if (dev
->msix_enabled
) {
683 dev_info(&dev
->dev
, "can't enable MSI "
684 "(MSI-X already enabled)\n");
688 status
= msi_capability_init(dev
, nvec
);
691 EXPORT_SYMBOL(pci_enable_msi_block
);
693 void pci_msi_shutdown(struct pci_dev
*dev
)
695 struct msi_desc
*desc
;
700 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
703 BUG_ON(list_empty(&dev
->msi_list
));
704 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
705 pos
= desc
->msi_attrib
.pos
;
707 msi_set_enable(dev
, pos
, 0);
708 pci_intx_for_msi(dev
, 1);
709 dev
->msi_enabled
= 0;
711 /* Return the device with MSI unmasked as initial states */
712 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &ctrl
);
713 mask
= msi_capable_mask(ctrl
);
714 /* Keep cached state to be restored */
715 __msi_mask_irq(desc
, mask
, ~mask
);
717 /* Restore dev->irq to its default pin-assertion irq */
718 dev
->irq
= desc
->msi_attrib
.default_irq
;
721 void pci_disable_msi(struct pci_dev
*dev
)
723 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
726 pci_msi_shutdown(dev
);
729 EXPORT_SYMBOL(pci_disable_msi
);
732 * pci_msix_table_size - return the number of device's MSI-X table entries
733 * @dev: pointer to the pci_dev data structure of MSI-X device function
735 int pci_msix_table_size(struct pci_dev
*dev
)
740 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
744 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
745 return multi_msix_capable(control
);
749 * pci_enable_msix - configure device's MSI-X capability structure
750 * @dev: pointer to the pci_dev data structure of MSI-X device function
751 * @entries: pointer to an array of MSI-X entries
752 * @nvec: number of MSI-X irqs requested for allocation by device driver
754 * Setup the MSI-X capability structure of device function with the number
755 * of requested irqs upon its software driver call to request for
756 * MSI-X mode enabled on its hardware device function. A return of zero
757 * indicates the successful configuration of MSI-X capability structure
758 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
759 * Or a return of > 0 indicates that driver request is exceeding the number
760 * of irqs or MSI-X vectors available. Driver should use the returned value to
761 * re-send its request.
763 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
765 int status
, nr_entries
;
771 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
775 nr_entries
= pci_msix_table_size(dev
);
776 if (nvec
> nr_entries
)
779 /* Check for any invalid entries */
780 for (i
= 0; i
< nvec
; i
++) {
781 if (entries
[i
].entry
>= nr_entries
)
782 return -EINVAL
; /* invalid entry */
783 for (j
= i
+ 1; j
< nvec
; j
++) {
784 if (entries
[i
].entry
== entries
[j
].entry
)
785 return -EINVAL
; /* duplicate entry */
788 WARN_ON(!!dev
->msix_enabled
);
790 /* Check whether driver already requested for MSI irq */
791 if (dev
->msi_enabled
) {
792 dev_info(&dev
->dev
, "can't enable MSI-X "
793 "(MSI IRQ already assigned)\n");
796 status
= msix_capability_init(dev
, entries
, nvec
);
799 EXPORT_SYMBOL(pci_enable_msix
);
801 void pci_msix_shutdown(struct pci_dev
*dev
)
803 struct msi_desc
*entry
;
805 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
808 /* Return the device with MSI-X masked as initial states */
809 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
810 /* Keep cached states to be restored */
811 __msix_mask_irq(entry
, 1);
814 msix_set_enable(dev
, 0);
815 pci_intx_for_msi(dev
, 1);
816 dev
->msix_enabled
= 0;
819 void pci_disable_msix(struct pci_dev
*dev
)
821 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
824 pci_msix_shutdown(dev
);
827 EXPORT_SYMBOL(pci_disable_msix
);
830 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
831 * @dev: pointer to the pci_dev data structure of MSI(X) device function
833 * Being called during hotplug remove, from which the device function
834 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
835 * allocated for this device function, are reclaimed to unused state,
836 * which may be used later on.
838 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
840 if (!pci_msi_enable
|| !dev
)
843 if (dev
->msi_enabled
|| dev
->msix_enabled
)
847 void pci_no_msi(void)
853 * pci_msi_enabled - is MSI enabled?
855 * Returns true if MSI has not been disabled by the command-line option
858 int pci_msi_enabled(void)
860 return pci_msi_enable
;
862 EXPORT_SYMBOL(pci_msi_enabled
);
864 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
866 INIT_LIST_HEAD(&dev
->msi_list
);