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KVM: VMX: Update instruction length on intercepted BP
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / vmx.c
blob85904fa41f03b5845358395f4a970ec64dc7e22b
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
30 #include "x86.h"
31
32 #include <asm/io.h>
33 #include <asm/desc.h>
34 #include <asm/vmx.h>
35 #include <asm/virtext.h>
36 #include <asm/mce.h>
37
38 #include "trace.h"
39
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
44
45 static int __read_mostly bypass_guest_pf = 1;
46 module_param(bypass_guest_pf, bool, S_IRUGO);
47
48 static int __read_mostly enable_vpid = 1;
49 module_param_named(vpid, enable_vpid, bool, 0444);
50
51 static int __read_mostly flexpriority_enabled = 1;
52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
53
54 static int __read_mostly enable_ept = 1;
55 module_param_named(ept, enable_ept, bool, S_IRUGO);
56
57 static int __read_mostly enable_unrestricted_guest = 1;
58 module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
61 static int __read_mostly emulate_invalid_guest_state = 0;
62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
63
64 /*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75 #define KVM_VMX_DEFAULT_PLE_GAP 41
76 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78 module_param(ple_gap, int, S_IRUGO);
79
80 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81 module_param(ple_window, int, S_IRUGO);
82
83 struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87 };
88
89 struct shared_msr_entry {
90 unsigned index;
91 u64 data;
92 u64 mask;
93 };
94
95 struct vcpu_vmx {
96 struct kvm_vcpu vcpu;
97 struct list_head local_vcpus_link;
98 unsigned long host_rsp;
99 int launched;
100 u8 fail;
101 u32 idt_vectoring_info;
102 struct shared_msr_entry *guest_msrs;
103 int nmsrs;
104 int save_nmsrs;
105 #ifdef CONFIG_X86_64
106 u64 msr_host_kernel_gs_base;
107 u64 msr_guest_kernel_gs_base;
108 #endif
109 struct vmcs *vmcs;
110 struct {
111 int loaded;
112 u16 fs_sel, gs_sel, ldt_sel;
113 int gs_ldt_reload_needed;
114 int fs_reload_needed;
115 } host_state;
116 struct {
117 int vm86_active;
118 u8 save_iopl;
119 struct kvm_save_segment {
120 u16 selector;
121 unsigned long base;
122 u32 limit;
123 u32 ar;
124 } tr, es, ds, fs, gs;
125 struct {
126 bool pending;
127 u8 vector;
128 unsigned rip;
129 } irq;
130 } rmode;
131 int vpid;
132 bool emulation_required;
133
134 /* Support for vnmi-less CPUs */
135 int soft_vnmi_blocked;
136 ktime_t entry_time;
137 s64 vnmi_blocked_time;
138 u32 exit_reason;
139 };
140
141 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
142 {
143 return container_of(vcpu, struct vcpu_vmx, vcpu);
144 }
145
146 static int init_rmode(struct kvm *kvm);
147 static u64 construct_eptp(unsigned long root_hpa);
148
149 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
150 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
151 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
152
153 static unsigned long *vmx_io_bitmap_a;
154 static unsigned long *vmx_io_bitmap_b;
155 static unsigned long *vmx_msr_bitmap_legacy;
156 static unsigned long *vmx_msr_bitmap_longmode;
157
158 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
159 static DEFINE_SPINLOCK(vmx_vpid_lock);
160
161 static struct vmcs_config {
162 int size;
163 int order;
164 u32 revision_id;
165 u32 pin_based_exec_ctrl;
166 u32 cpu_based_exec_ctrl;
167 u32 cpu_based_2nd_exec_ctrl;
168 u32 vmexit_ctrl;
169 u32 vmentry_ctrl;
170 } vmcs_config;
171
172 static struct vmx_capability {
173 u32 ept;
174 u32 vpid;
175 } vmx_capability;
176
177 #define VMX_SEGMENT_FIELD(seg) \
178 [VCPU_SREG_##seg] = { \
179 .selector = GUEST_##seg##_SELECTOR, \
180 .base = GUEST_##seg##_BASE, \
181 .limit = GUEST_##seg##_LIMIT, \
182 .ar_bytes = GUEST_##seg##_AR_BYTES, \
183 }
184
185 static struct kvm_vmx_segment_field {
186 unsigned selector;
187 unsigned base;
188 unsigned limit;
189 unsigned ar_bytes;
190 } kvm_vmx_segment_fields[] = {
191 VMX_SEGMENT_FIELD(CS),
192 VMX_SEGMENT_FIELD(DS),
193 VMX_SEGMENT_FIELD(ES),
194 VMX_SEGMENT_FIELD(FS),
195 VMX_SEGMENT_FIELD(GS),
196 VMX_SEGMENT_FIELD(SS),
197 VMX_SEGMENT_FIELD(TR),
198 VMX_SEGMENT_FIELD(LDTR),
199 };
200
201 static u64 host_efer;
202
203 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
204
205 /*
206 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
207 * away by decrementing the array size.
208 */
209 static const u32 vmx_msr_index[] = {
210 #ifdef CONFIG_X86_64
211 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
212 #endif
213 MSR_EFER, MSR_K6_STAR,
214 };
215 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
216
217 static inline int is_page_fault(u32 intr_info)
218 {
219 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
220 INTR_INFO_VALID_MASK)) ==
221 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
222 }
223
224 static inline int is_no_device(u32 intr_info)
225 {
226 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
227 INTR_INFO_VALID_MASK)) ==
228 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
229 }
230
231 static inline int is_invalid_opcode(u32 intr_info)
232 {
233 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
234 INTR_INFO_VALID_MASK)) ==
235 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
236 }
237
238 static inline int is_external_interrupt(u32 intr_info)
239 {
240 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
241 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
242 }
243
244 static inline int is_machine_check(u32 intr_info)
245 {
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
248 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
249 }
250
251 static inline int cpu_has_vmx_msr_bitmap(void)
252 {
253 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
254 }
255
256 static inline int cpu_has_vmx_tpr_shadow(void)
257 {
258 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
259 }
260
261 static inline int vm_need_tpr_shadow(struct kvm *kvm)
262 {
263 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
264 }
265
266 static inline int cpu_has_secondary_exec_ctrls(void)
267 {
268 return vmcs_config.cpu_based_exec_ctrl &
269 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
270 }
271
272 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
273 {
274 return vmcs_config.cpu_based_2nd_exec_ctrl &
275 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
276 }
277
278 static inline bool cpu_has_vmx_flexpriority(void)
279 {
280 return cpu_has_vmx_tpr_shadow() &&
281 cpu_has_vmx_virtualize_apic_accesses();
282 }
283
284 static inline bool cpu_has_vmx_ept_execute_only(void)
285 {
286 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
287 }
288
289 static inline bool cpu_has_vmx_eptp_uncacheable(void)
290 {
291 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
292 }
293
294 static inline bool cpu_has_vmx_eptp_writeback(void)
295 {
296 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
297 }
298
299 static inline bool cpu_has_vmx_ept_2m_page(void)
300 {
301 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
302 }
303
304 static inline int cpu_has_vmx_invept_individual_addr(void)
305 {
306 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
307 }
308
309 static inline int cpu_has_vmx_invept_context(void)
310 {
311 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
312 }
313
314 static inline int cpu_has_vmx_invept_global(void)
315 {
316 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
317 }
318
319 static inline int cpu_has_vmx_ept(void)
320 {
321 return vmcs_config.cpu_based_2nd_exec_ctrl &
322 SECONDARY_EXEC_ENABLE_EPT;
323 }
324
325 static inline int cpu_has_vmx_unrestricted_guest(void)
326 {
327 return vmcs_config.cpu_based_2nd_exec_ctrl &
328 SECONDARY_EXEC_UNRESTRICTED_GUEST;
329 }
330
331 static inline int cpu_has_vmx_ple(void)
332 {
333 return vmcs_config.cpu_based_2nd_exec_ctrl &
334 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
335 }
336
337 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
338 {
339 return flexpriority_enabled &&
340 (cpu_has_vmx_virtualize_apic_accesses()) &&
341 (irqchip_in_kernel(kvm));
342 }
343
344 static inline int cpu_has_vmx_vpid(void)
345 {
346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_VPID;
348 }
349
350 static inline int cpu_has_virtual_nmis(void)
351 {
352 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
353 }
354
355 static inline bool report_flexpriority(void)
356 {
357 return flexpriority_enabled;
358 }
359
360 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
361 {
362 int i;
363
364 for (i = 0; i < vmx->nmsrs; ++i)
365 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
366 return i;
367 return -1;
368 }
369
370 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
371 {
372 struct {
373 u64 vpid : 16;
374 u64 rsvd : 48;
375 u64 gva;
376 } operand = { vpid, 0, gva };
377
378 asm volatile (__ex(ASM_VMX_INVVPID)
379 /* CF==1 or ZF==1 --> rc = -1 */
380 "; ja 1f ; ud2 ; 1:"
381 : : "a"(&operand), "c"(ext) : "cc", "memory");
382 }
383
384 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
385 {
386 struct {
387 u64 eptp, gpa;
388 } operand = {eptp, gpa};
389
390 asm volatile (__ex(ASM_VMX_INVEPT)
391 /* CF==1 or ZF==1 --> rc = -1 */
392 "; ja 1f ; ud2 ; 1:\n"
393 : : "a" (&operand), "c" (ext) : "cc", "memory");
394 }
395
396 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
397 {
398 int i;
399
400 i = __find_msr_index(vmx, msr);
401 if (i >= 0)
402 return &vmx->guest_msrs[i];
403 return NULL;
404 }
405
406 static void vmcs_clear(struct vmcs *vmcs)
407 {
408 u64 phys_addr = __pa(vmcs);
409 u8 error;
410
411 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
412 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
413 : "cc", "memory");
414 if (error)
415 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
416 vmcs, phys_addr);
417 }
418
419 static void __vcpu_clear(void *arg)
420 {
421 struct vcpu_vmx *vmx = arg;
422 int cpu = raw_smp_processor_id();
423
424 if (vmx->vcpu.cpu == cpu)
425 vmcs_clear(vmx->vmcs);
426 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
427 per_cpu(current_vmcs, cpu) = NULL;
428 rdtscll(vmx->vcpu.arch.host_tsc);
429 list_del(&vmx->local_vcpus_link);
430 vmx->vcpu.cpu = -1;
431 vmx->launched = 0;
432 }
433
434 static void vcpu_clear(struct vcpu_vmx *vmx)
435 {
436 if (vmx->vcpu.cpu == -1)
437 return;
438 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
439 }
440
441 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
442 {
443 if (vmx->vpid == 0)
444 return;
445
446 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
447 }
448
449 static inline void ept_sync_global(void)
450 {
451 if (cpu_has_vmx_invept_global())
452 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
453 }
454
455 static inline void ept_sync_context(u64 eptp)
456 {
457 if (enable_ept) {
458 if (cpu_has_vmx_invept_context())
459 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
460 else
461 ept_sync_global();
462 }
463 }
464
465 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
466 {
467 if (enable_ept) {
468 if (cpu_has_vmx_invept_individual_addr())
469 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
470 eptp, gpa);
471 else
472 ept_sync_context(eptp);
473 }
474 }
475
476 static unsigned long vmcs_readl(unsigned long field)
477 {
478 unsigned long value;
479
480 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
481 : "=a"(value) : "d"(field) : "cc");
482 return value;
483 }
484
485 static u16 vmcs_read16(unsigned long field)
486 {
487 return vmcs_readl(field);
488 }
489
490 static u32 vmcs_read32(unsigned long field)
491 {
492 return vmcs_readl(field);
493 }
494
495 static u64 vmcs_read64(unsigned long field)
496 {
497 #ifdef CONFIG_X86_64
498 return vmcs_readl(field);
499 #else
500 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
501 #endif
502 }
503
504 static noinline void vmwrite_error(unsigned long field, unsigned long value)
505 {
506 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
507 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
508 dump_stack();
509 }
510
511 static void vmcs_writel(unsigned long field, unsigned long value)
512 {
513 u8 error;
514
515 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
516 : "=q"(error) : "a"(value), "d"(field) : "cc");
517 if (unlikely(error))
518 vmwrite_error(field, value);
519 }
520
521 static void vmcs_write16(unsigned long field, u16 value)
522 {
523 vmcs_writel(field, value);
524 }
525
526 static void vmcs_write32(unsigned long field, u32 value)
527 {
528 vmcs_writel(field, value);
529 }
530
531 static void vmcs_write64(unsigned long field, u64 value)
532 {
533 vmcs_writel(field, value);
534 #ifndef CONFIG_X86_64
535 asm volatile ("");
536 vmcs_writel(field+1, value >> 32);
537 #endif
538 }
539
540 static void vmcs_clear_bits(unsigned long field, u32 mask)
541 {
542 vmcs_writel(field, vmcs_readl(field) & ~mask);
543 }
544
545 static void vmcs_set_bits(unsigned long field, u32 mask)
546 {
547 vmcs_writel(field, vmcs_readl(field) | mask);
548 }
549
550 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
551 {
552 u32 eb;
553
554 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
555 if (!vcpu->fpu_active)
556 eb |= 1u << NM_VECTOR;
557 /*
558 * Unconditionally intercept #DB so we can maintain dr6 without
559 * reading it every exit.
560 */
561 eb |= 1u << DB_VECTOR;
562 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
563 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
564 eb |= 1u << BP_VECTOR;
565 }
566 if (to_vmx(vcpu)->rmode.vm86_active)
567 eb = ~0;
568 if (enable_ept)
569 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
570 vmcs_write32(EXCEPTION_BITMAP, eb);
571 }
572
573 static void reload_tss(void)
574 {
575 /*
576 * VT restores TR but not its size. Useless.
577 */
578 struct descriptor_table gdt;
579 struct desc_struct *descs;
580
581 kvm_get_gdt(&gdt);
582 descs = (void *)gdt.base;
583 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
584 load_TR_desc();
585 }
586
587 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
588 {
589 u64 guest_efer;
590 u64 ignore_bits;
591
592 guest_efer = vmx->vcpu.arch.shadow_efer;
593
594 /*
595 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
596 * outside long mode
597 */
598 ignore_bits = EFER_NX | EFER_SCE;
599 #ifdef CONFIG_X86_64
600 ignore_bits |= EFER_LMA | EFER_LME;
601 /* SCE is meaningful only in long mode on Intel */
602 if (guest_efer & EFER_LMA)
603 ignore_bits &= ~(u64)EFER_SCE;
604 #endif
605 guest_efer &= ~ignore_bits;
606 guest_efer |= host_efer & ignore_bits;
607 vmx->guest_msrs[efer_offset].data = guest_efer;
608 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
609 return true;
610 }
611
612 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
613 {
614 struct vcpu_vmx *vmx = to_vmx(vcpu);
615 int i;
616
617 if (vmx->host_state.loaded)
618 return;
619
620 vmx->host_state.loaded = 1;
621 /*
622 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
623 * allow segment selectors with cpl > 0 or ti == 1.
624 */
625 vmx->host_state.ldt_sel = kvm_read_ldt();
626 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
627 vmx->host_state.fs_sel = kvm_read_fs();
628 if (!(vmx->host_state.fs_sel & 7)) {
629 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
630 vmx->host_state.fs_reload_needed = 0;
631 } else {
632 vmcs_write16(HOST_FS_SELECTOR, 0);
633 vmx->host_state.fs_reload_needed = 1;
634 }
635 vmx->host_state.gs_sel = kvm_read_gs();
636 if (!(vmx->host_state.gs_sel & 7))
637 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
638 else {
639 vmcs_write16(HOST_GS_SELECTOR, 0);
640 vmx->host_state.gs_ldt_reload_needed = 1;
641 }
642
643 #ifdef CONFIG_X86_64
644 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
645 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
646 #else
647 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
648 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
649 #endif
650
651 #ifdef CONFIG_X86_64
652 if (is_long_mode(&vmx->vcpu)) {
653 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
654 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
655 }
656 #endif
657 for (i = 0; i < vmx->save_nmsrs; ++i)
658 kvm_set_shared_msr(vmx->guest_msrs[i].index,
659 vmx->guest_msrs[i].data,
660 vmx->guest_msrs[i].mask);
661 }
662
663 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
664 {
665 unsigned long flags;
666
667 if (!vmx->host_state.loaded)
668 return;
669
670 ++vmx->vcpu.stat.host_state_reload;
671 vmx->host_state.loaded = 0;
672 if (vmx->host_state.fs_reload_needed)
673 kvm_load_fs(vmx->host_state.fs_sel);
674 if (vmx->host_state.gs_ldt_reload_needed) {
675 kvm_load_ldt(vmx->host_state.ldt_sel);
676 /*
677 * If we have to reload gs, we must take care to
678 * preserve our gs base.
679 */
680 local_irq_save(flags);
681 kvm_load_gs(vmx->host_state.gs_sel);
682 #ifdef CONFIG_X86_64
683 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
684 #endif
685 local_irq_restore(flags);
686 }
687 reload_tss();
688 #ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
691 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
692 }
693 #endif
694 }
695
696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
697 {
698 preempt_disable();
699 __vmx_load_host_state(vmx);
700 preempt_enable();
701 }
702
703 /*
704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
705 * vcpu mutex is already taken.
706 */
707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
708 {
709 struct vcpu_vmx *vmx = to_vmx(vcpu);
710 u64 phys_addr = __pa(vmx->vmcs);
711 u64 tsc_this, delta, new_offset;
712
713 if (vcpu->cpu != cpu) {
714 vcpu_clear(vmx);
715 kvm_migrate_timers(vcpu);
716 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
717 local_irq_disable();
718 list_add(&vmx->local_vcpus_link,
719 &per_cpu(vcpus_on_cpu, cpu));
720 local_irq_enable();
721 }
722
723 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
724 u8 error;
725
726 per_cpu(current_vmcs, cpu) = vmx->vmcs;
727 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
728 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
729 : "cc");
730 if (error)
731 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
732 vmx->vmcs, phys_addr);
733 }
734
735 if (vcpu->cpu != cpu) {
736 struct descriptor_table dt;
737 unsigned long sysenter_esp;
738
739 vcpu->cpu = cpu;
740 /*
741 * Linux uses per-cpu TSS and GDT, so set these when switching
742 * processors.
743 */
744 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
745 kvm_get_gdt(&dt);
746 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
747
748 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
749 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
750
751 /*
752 * Make sure the time stamp counter is monotonous.
753 */
754 rdtscll(tsc_this);
755 if (tsc_this < vcpu->arch.host_tsc) {
756 delta = vcpu->arch.host_tsc - tsc_this;
757 new_offset = vmcs_read64(TSC_OFFSET) + delta;
758 vmcs_write64(TSC_OFFSET, new_offset);
759 }
760 }
761 }
762
763 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
764 {
765 __vmx_load_host_state(to_vmx(vcpu));
766 }
767
768 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
769 {
770 if (vcpu->fpu_active)
771 return;
772 vcpu->fpu_active = 1;
773 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
774 if (vcpu->arch.cr0 & X86_CR0_TS)
775 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
776 update_exception_bitmap(vcpu);
777 }
778
779 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
780 {
781 if (!vcpu->fpu_active)
782 return;
783 vcpu->fpu_active = 0;
784 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
785 update_exception_bitmap(vcpu);
786 }
787
788 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
789 {
790 unsigned long rflags;
791
792 rflags = vmcs_readl(GUEST_RFLAGS);
793 if (to_vmx(vcpu)->rmode.vm86_active)
794 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
795 return rflags;
796 }
797
798 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799 {
800 if (to_vmx(vcpu)->rmode.vm86_active)
801 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
802 vmcs_writel(GUEST_RFLAGS, rflags);
803 }
804
805 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
806 {
807 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
808 int ret = 0;
809
810 if (interruptibility & GUEST_INTR_STATE_STI)
811 ret |= X86_SHADOW_INT_STI;
812 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
813 ret |= X86_SHADOW_INT_MOV_SS;
814
815 return ret & mask;
816 }
817
818 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819 {
820 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 u32 interruptibility = interruptibility_old;
822
823 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
824
825 if (mask & X86_SHADOW_INT_MOV_SS)
826 interruptibility |= GUEST_INTR_STATE_MOV_SS;
827 if (mask & X86_SHADOW_INT_STI)
828 interruptibility |= GUEST_INTR_STATE_STI;
829
830 if ((interruptibility != interruptibility_old))
831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
832 }
833
834 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
835 {
836 unsigned long rip;
837
838 rip = kvm_rip_read(vcpu);
839 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
840 kvm_rip_write(vcpu, rip);
841
842 /* skipping an emulated instruction also counts */
843 vmx_set_interrupt_shadow(vcpu, 0);
844 }
845
846 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
847 bool has_error_code, u32 error_code)
848 {
849 struct vcpu_vmx *vmx = to_vmx(vcpu);
850 u32 intr_info = nr | INTR_INFO_VALID_MASK;
851
852 if (has_error_code) {
853 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
854 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
855 }
856
857 if (vmx->rmode.vm86_active) {
858 vmx->rmode.irq.pending = true;
859 vmx->rmode.irq.vector = nr;
860 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
861 if (kvm_exception_is_soft(nr))
862 vmx->rmode.irq.rip +=
863 vmx->vcpu.arch.event_exit_inst_len;
864 intr_info |= INTR_TYPE_SOFT_INTR;
865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
868 return;
869 }
870
871 if (kvm_exception_is_soft(nr)) {
872 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
873 vmx->vcpu.arch.event_exit_inst_len);
874 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
875 } else
876 intr_info |= INTR_TYPE_HARD_EXCEPTION;
877
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
879 }
880
881 /*
882 * Swap MSR entry in host/guest MSR entry array.
883 */
884 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
885 {
886 struct shared_msr_entry tmp;
887
888 tmp = vmx->guest_msrs[to];
889 vmx->guest_msrs[to] = vmx->guest_msrs[from];
890 vmx->guest_msrs[from] = tmp;
891 }
892
893 /*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
898 static void setup_msrs(struct vcpu_vmx *vmx)
899 {
900 int save_nmsrs, index;
901 unsigned long *msr_bitmap;
902
903 vmx_load_host_state(vmx);
904 save_nmsrs = 0;
905 #ifdef CONFIG_X86_64
906 if (is_long_mode(&vmx->vcpu)) {
907 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
908 if (index >= 0)
909 move_msr_up(vmx, index, save_nmsrs++);
910 index = __find_msr_index(vmx, MSR_LSTAR);
911 if (index >= 0)
912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_CSTAR);
914 if (index >= 0)
915 move_msr_up(vmx, index, save_nmsrs++);
916 /*
917 * MSR_K6_STAR is only needed on long mode guests, and only
918 * if efer.sce is enabled.
919 */
920 index = __find_msr_index(vmx, MSR_K6_STAR);
921 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
922 move_msr_up(vmx, index, save_nmsrs++);
923 }
924 #endif
925 index = __find_msr_index(vmx, MSR_EFER);
926 if (index >= 0 && update_transition_efer(vmx, index))
927 move_msr_up(vmx, index, save_nmsrs++);
928
929 vmx->save_nmsrs = save_nmsrs;
930
931 if (cpu_has_vmx_msr_bitmap()) {
932 if (is_long_mode(&vmx->vcpu))
933 msr_bitmap = vmx_msr_bitmap_longmode;
934 else
935 msr_bitmap = vmx_msr_bitmap_legacy;
936
937 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
938 }
939 }
940
941 /*
942 * reads and returns guest's timestamp counter "register"
943 * guest_tsc = host_tsc + tsc_offset -- 21.3
944 */
945 static u64 guest_read_tsc(void)
946 {
947 u64 host_tsc, tsc_offset;
948
949 rdtscll(host_tsc);
950 tsc_offset = vmcs_read64(TSC_OFFSET);
951 return host_tsc + tsc_offset;
952 }
953
954 /*
955 * writes 'guest_tsc' into guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
957 */
958 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
959 {
960 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
961 }
962
963 /*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969 {
970 u64 data;
971 struct shared_msr_entry *msr;
972
973 if (!pdata) {
974 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
975 return -EINVAL;
976 }
977
978 switch (msr_index) {
979 #ifdef CONFIG_X86_64
980 case MSR_FS_BASE:
981 data = vmcs_readl(GUEST_FS_BASE);
982 break;
983 case MSR_GS_BASE:
984 data = vmcs_readl(GUEST_GS_BASE);
985 break;
986 case MSR_KERNEL_GS_BASE:
987 vmx_load_host_state(to_vmx(vcpu));
988 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
989 break;
990 #endif
991 case MSR_EFER:
992 return kvm_get_msr_common(vcpu, msr_index, pdata);
993 case MSR_IA32_TSC:
994 data = guest_read_tsc();
995 break;
996 case MSR_IA32_SYSENTER_CS:
997 data = vmcs_read32(GUEST_SYSENTER_CS);
998 break;
999 case MSR_IA32_SYSENTER_EIP:
1000 data = vmcs_readl(GUEST_SYSENTER_EIP);
1001 break;
1002 case MSR_IA32_SYSENTER_ESP:
1003 data = vmcs_readl(GUEST_SYSENTER_ESP);
1004 break;
1005 default:
1006 vmx_load_host_state(to_vmx(vcpu));
1007 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1008 if (msr) {
1009 vmx_load_host_state(to_vmx(vcpu));
1010 data = msr->data;
1011 break;
1012 }
1013 return kvm_get_msr_common(vcpu, msr_index, pdata);
1014 }
1015
1016 *pdata = data;
1017 return 0;
1018 }
1019
1020 /*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
1025 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026 {
1027 struct vcpu_vmx *vmx = to_vmx(vcpu);
1028 struct shared_msr_entry *msr;
1029 u64 host_tsc;
1030 int ret = 0;
1031
1032 switch (msr_index) {
1033 case MSR_EFER:
1034 vmx_load_host_state(vmx);
1035 ret = kvm_set_msr_common(vcpu, msr_index, data);
1036 break;
1037 #ifdef CONFIG_X86_64
1038 case MSR_FS_BASE:
1039 vmcs_writel(GUEST_FS_BASE, data);
1040 break;
1041 case MSR_GS_BASE:
1042 vmcs_writel(GUEST_GS_BASE, data);
1043 break;
1044 case MSR_KERNEL_GS_BASE:
1045 vmx_load_host_state(vmx);
1046 vmx->msr_guest_kernel_gs_base = data;
1047 break;
1048 #endif
1049 case MSR_IA32_SYSENTER_CS:
1050 vmcs_write32(GUEST_SYSENTER_CS, data);
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
1053 vmcs_writel(GUEST_SYSENTER_EIP, data);
1054 break;
1055 case MSR_IA32_SYSENTER_ESP:
1056 vmcs_writel(GUEST_SYSENTER_ESP, data);
1057 break;
1058 case MSR_IA32_TSC:
1059 rdtscll(host_tsc);
1060 guest_write_tsc(data, host_tsc);
1061 break;
1062 case MSR_IA32_CR_PAT:
1063 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064 vmcs_write64(GUEST_IA32_PAT, data);
1065 vcpu->arch.pat = data;
1066 break;
1067 }
1068 /* Otherwise falls through to kvm_set_msr_common */
1069 default:
1070 msr = find_msr_entry(vmx, msr_index);
1071 if (msr) {
1072 vmx_load_host_state(vmx);
1073 msr->data = data;
1074 break;
1075 }
1076 ret = kvm_set_msr_common(vcpu, msr_index, data);
1077 }
1078
1079 return ret;
1080 }
1081
1082 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1083 {
1084 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085 switch (reg) {
1086 case VCPU_REGS_RSP:
1087 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088 break;
1089 case VCPU_REGS_RIP:
1090 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091 break;
1092 case VCPU_EXREG_PDPTR:
1093 if (enable_ept)
1094 ept_save_pdptrs(vcpu);
1095 break;
1096 default:
1097 break;
1098 }
1099 }
1100
1101 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1102 {
1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105 else
1106 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
1108 update_exception_bitmap(vcpu);
1109 }
1110
1111 static __init int cpu_has_kvm_support(void)
1112 {
1113 return cpu_has_vmx();
1114 }
1115
1116 static __init int vmx_disabled_by_bios(void)
1117 {
1118 u64 msr;
1119
1120 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1121 return (msr & (FEATURE_CONTROL_LOCKED |
1122 FEATURE_CONTROL_VMXON_ENABLED))
1123 == FEATURE_CONTROL_LOCKED;
1124 /* locked but not enabled */
1125 }
1126
1127 static int hardware_enable(void *garbage)
1128 {
1129 int cpu = raw_smp_processor_id();
1130 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131 u64 old;
1132
1133 if (read_cr4() & X86_CR4_VMXE)
1134 return -EBUSY;
1135
1136 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1138 if ((old & (FEATURE_CONTROL_LOCKED |
1139 FEATURE_CONTROL_VMXON_ENABLED))
1140 != (FEATURE_CONTROL_LOCKED |
1141 FEATURE_CONTROL_VMXON_ENABLED))
1142 /* enable and lock */
1143 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1144 FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED);
1146 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1147 asm volatile (ASM_VMX_VMXON_RAX
1148 : : "a"(&phys_addr), "m"(phys_addr)
1149 : "memory", "cc");
1150
1151 ept_sync_global();
1152
1153 return 0;
1154 }
1155
1156 static void vmclear_local_vcpus(void)
1157 {
1158 int cpu = raw_smp_processor_id();
1159 struct vcpu_vmx *vmx, *n;
1160
1161 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162 local_vcpus_link)
1163 __vcpu_clear(vmx);
1164 }
1165
1166
1167 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168 * tricks.
1169 */
1170 static void kvm_cpu_vmxoff(void)
1171 {
1172 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1173 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1174 }
1175
1176 static void hardware_disable(void *garbage)
1177 {
1178 vmclear_local_vcpus();
1179 kvm_cpu_vmxoff();
1180 }
1181
1182 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1183 u32 msr, u32 *result)
1184 {
1185 u32 vmx_msr_low, vmx_msr_high;
1186 u32 ctl = ctl_min | ctl_opt;
1187
1188 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1192
1193 /* Ensure minimum (required) set of control bits are supported. */
1194 if (ctl_min & ~ctl)
1195 return -EIO;
1196
1197 *result = ctl;
1198 return 0;
1199 }
1200
1201 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1202 {
1203 u32 vmx_msr_low, vmx_msr_high;
1204 u32 min, opt, min2, opt2;
1205 u32 _pin_based_exec_control = 0;
1206 u32 _cpu_based_exec_control = 0;
1207 u32 _cpu_based_2nd_exec_control = 0;
1208 u32 _vmexit_control = 0;
1209 u32 _vmentry_control = 0;
1210
1211 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1212 opt = PIN_BASED_VIRTUAL_NMIS;
1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214 &_pin_based_exec_control) < 0)
1215 return -EIO;
1216
1217 min = CPU_BASED_HLT_EXITING |
1218 #ifdef CONFIG_X86_64
1219 CPU_BASED_CR8_LOAD_EXITING |
1220 CPU_BASED_CR8_STORE_EXITING |
1221 #endif
1222 CPU_BASED_CR3_LOAD_EXITING |
1223 CPU_BASED_CR3_STORE_EXITING |
1224 CPU_BASED_USE_IO_BITMAPS |
1225 CPU_BASED_MOV_DR_EXITING |
1226 CPU_BASED_USE_TSC_OFFSETING |
1227 CPU_BASED_MWAIT_EXITING |
1228 CPU_BASED_MONITOR_EXITING |
1229 CPU_BASED_INVLPG_EXITING;
1230 opt = CPU_BASED_TPR_SHADOW |
1231 CPU_BASED_USE_MSR_BITMAPS |
1232 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1233 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1234 &_cpu_based_exec_control) < 0)
1235 return -EIO;
1236 #ifdef CONFIG_X86_64
1237 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1238 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1239 ~CPU_BASED_CR8_STORE_EXITING;
1240 #endif
1241 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1242 min2 = 0;
1243 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1244 SECONDARY_EXEC_WBINVD_EXITING |
1245 SECONDARY_EXEC_ENABLE_VPID |
1246 SECONDARY_EXEC_ENABLE_EPT |
1247 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1248 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1249 if (adjust_vmx_controls(min2, opt2,
1250 MSR_IA32_VMX_PROCBASED_CTLS2,
1251 &_cpu_based_2nd_exec_control) < 0)
1252 return -EIO;
1253 }
1254 #ifndef CONFIG_X86_64
1255 if (!(_cpu_based_2nd_exec_control &
1256 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1257 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1258 #endif
1259 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1260 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1261 enabled */
1262 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1263 CPU_BASED_CR3_STORE_EXITING |
1264 CPU_BASED_INVLPG_EXITING);
1265 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1266 vmx_capability.ept, vmx_capability.vpid);
1267 }
1268
1269 min = 0;
1270 #ifdef CONFIG_X86_64
1271 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1272 #endif
1273 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1274 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1275 &_vmexit_control) < 0)
1276 return -EIO;
1277
1278 min = 0;
1279 opt = VM_ENTRY_LOAD_IA32_PAT;
1280 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1281 &_vmentry_control) < 0)
1282 return -EIO;
1283
1284 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1285
1286 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1287 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1288 return -EIO;
1289
1290 #ifdef CONFIG_X86_64
1291 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1292 if (vmx_msr_high & (1u<<16))
1293 return -EIO;
1294 #endif
1295
1296 /* Require Write-Back (WB) memory type for VMCS accesses. */
1297 if (((vmx_msr_high >> 18) & 15) != 6)
1298 return -EIO;
1299
1300 vmcs_conf->size = vmx_msr_high & 0x1fff;
1301 vmcs_conf->order = get_order(vmcs_config.size);
1302 vmcs_conf->revision_id = vmx_msr_low;
1303
1304 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1305 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1306 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1307 vmcs_conf->vmexit_ctrl = _vmexit_control;
1308 vmcs_conf->vmentry_ctrl = _vmentry_control;
1309
1310 return 0;
1311 }
1312
1313 static struct vmcs *alloc_vmcs_cpu(int cpu)
1314 {
1315 int node = cpu_to_node(cpu);
1316 struct page *pages;
1317 struct vmcs *vmcs;
1318
1319 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1320 if (!pages)
1321 return NULL;
1322 vmcs = page_address(pages);
1323 memset(vmcs, 0, vmcs_config.size);
1324 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1325 return vmcs;
1326 }
1327
1328 static struct vmcs *alloc_vmcs(void)
1329 {
1330 return alloc_vmcs_cpu(raw_smp_processor_id());
1331 }
1332
1333 static void free_vmcs(struct vmcs *vmcs)
1334 {
1335 free_pages((unsigned long)vmcs, vmcs_config.order);
1336 }
1337
1338 static void free_kvm_area(void)
1339 {
1340 int cpu;
1341
1342 for_each_possible_cpu(cpu) {
1343 free_vmcs(per_cpu(vmxarea, cpu));
1344 per_cpu(vmxarea, cpu) = NULL;
1345 }
1346 }
1347
1348 static __init int alloc_kvm_area(void)
1349 {
1350 int cpu;
1351
1352 for_each_possible_cpu(cpu) {
1353 struct vmcs *vmcs;
1354
1355 vmcs = alloc_vmcs_cpu(cpu);
1356 if (!vmcs) {
1357 free_kvm_area();
1358 return -ENOMEM;
1359 }
1360
1361 per_cpu(vmxarea, cpu) = vmcs;
1362 }
1363 return 0;
1364 }
1365
1366 static __init int hardware_setup(void)
1367 {
1368 if (setup_vmcs_config(&vmcs_config) < 0)
1369 return -EIO;
1370
1371 if (boot_cpu_has(X86_FEATURE_NX))
1372 kvm_enable_efer_bits(EFER_NX);
1373
1374 if (!cpu_has_vmx_vpid())
1375 enable_vpid = 0;
1376
1377 if (!cpu_has_vmx_ept()) {
1378 enable_ept = 0;
1379 enable_unrestricted_guest = 0;
1380 }
1381
1382 if (!cpu_has_vmx_unrestricted_guest())
1383 enable_unrestricted_guest = 0;
1384
1385 if (!cpu_has_vmx_flexpriority())
1386 flexpriority_enabled = 0;
1387
1388 if (!cpu_has_vmx_tpr_shadow())
1389 kvm_x86_ops->update_cr8_intercept = NULL;
1390
1391 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1392 kvm_disable_largepages();
1393
1394 if (!cpu_has_vmx_ple())
1395 ple_gap = 0;
1396
1397 return alloc_kvm_area();
1398 }
1399
1400 static __exit void hardware_unsetup(void)
1401 {
1402 free_kvm_area();
1403 }
1404
1405 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1406 {
1407 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1408
1409 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1410 vmcs_write16(sf->selector, save->selector);
1411 vmcs_writel(sf->base, save->base);
1412 vmcs_write32(sf->limit, save->limit);
1413 vmcs_write32(sf->ar_bytes, save->ar);
1414 } else {
1415 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1416 << AR_DPL_SHIFT;
1417 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1418 }
1419 }
1420
1421 static void enter_pmode(struct kvm_vcpu *vcpu)
1422 {
1423 unsigned long flags;
1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
1425
1426 vmx->emulation_required = 1;
1427 vmx->rmode.vm86_active = 0;
1428
1429 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1430 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1431 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1432
1433 flags = vmcs_readl(GUEST_RFLAGS);
1434 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1435 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1436 vmcs_writel(GUEST_RFLAGS, flags);
1437
1438 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1439 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1440
1441 update_exception_bitmap(vcpu);
1442
1443 if (emulate_invalid_guest_state)
1444 return;
1445
1446 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1447 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1448 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1449 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1450
1451 vmcs_write16(GUEST_SS_SELECTOR, 0);
1452 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1453
1454 vmcs_write16(GUEST_CS_SELECTOR,
1455 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1456 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1457 }
1458
1459 static gva_t rmode_tss_base(struct kvm *kvm)
1460 {
1461 if (!kvm->arch.tss_addr) {
1462 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1463 kvm->memslots[0].npages - 3;
1464 return base_gfn << PAGE_SHIFT;
1465 }
1466 return kvm->arch.tss_addr;
1467 }
1468
1469 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1470 {
1471 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1472
1473 save->selector = vmcs_read16(sf->selector);
1474 save->base = vmcs_readl(sf->base);
1475 save->limit = vmcs_read32(sf->limit);
1476 save->ar = vmcs_read32(sf->ar_bytes);
1477 vmcs_write16(sf->selector, save->base >> 4);
1478 vmcs_write32(sf->base, save->base & 0xfffff);
1479 vmcs_write32(sf->limit, 0xffff);
1480 vmcs_write32(sf->ar_bytes, 0xf3);
1481 }
1482
1483 static void enter_rmode(struct kvm_vcpu *vcpu)
1484 {
1485 unsigned long flags;
1486 struct vcpu_vmx *vmx = to_vmx(vcpu);
1487
1488 if (enable_unrestricted_guest)
1489 return;
1490
1491 vmx->emulation_required = 1;
1492 vmx->rmode.vm86_active = 1;
1493
1494 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1495 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1496
1497 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1498 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1499
1500 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1501 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1502
1503 flags = vmcs_readl(GUEST_RFLAGS);
1504 vmx->rmode.save_iopl
1505 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1506
1507 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1508
1509 vmcs_writel(GUEST_RFLAGS, flags);
1510 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1511 update_exception_bitmap(vcpu);
1512
1513 if (emulate_invalid_guest_state)
1514 goto continue_rmode;
1515
1516 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1517 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1518 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1519
1520 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1521 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1522 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1523 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1524 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1525
1526 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1527 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1528 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1529 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1530
1531 continue_rmode:
1532 kvm_mmu_reset_context(vcpu);
1533 init_rmode(vcpu->kvm);
1534 }
1535
1536 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1537 {
1538 struct vcpu_vmx *vmx = to_vmx(vcpu);
1539 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1540
1541 if (!msr)
1542 return;
1543
1544 /*
1545 * Force kernel_gs_base reloading before EFER changes, as control
1546 * of this msr depends on is_long_mode().
1547 */
1548 vmx_load_host_state(to_vmx(vcpu));
1549 vcpu->arch.shadow_efer = efer;
1550 if (!msr)
1551 return;
1552 if (efer & EFER_LMA) {
1553 vmcs_write32(VM_ENTRY_CONTROLS,
1554 vmcs_read32(VM_ENTRY_CONTROLS) |
1555 VM_ENTRY_IA32E_MODE);
1556 msr->data = efer;
1557 } else {
1558 vmcs_write32(VM_ENTRY_CONTROLS,
1559 vmcs_read32(VM_ENTRY_CONTROLS) &
1560 ~VM_ENTRY_IA32E_MODE);
1561
1562 msr->data = efer & ~EFER_LME;
1563 }
1564 setup_msrs(vmx);
1565 }
1566
1567 #ifdef CONFIG_X86_64
1568
1569 static void enter_lmode(struct kvm_vcpu *vcpu)
1570 {
1571 u32 guest_tr_ar;
1572
1573 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1574 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1575 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1576 __func__);
1577 vmcs_write32(GUEST_TR_AR_BYTES,
1578 (guest_tr_ar & ~AR_TYPE_MASK)
1579 | AR_TYPE_BUSY_64_TSS);
1580 }
1581 vcpu->arch.shadow_efer |= EFER_LMA;
1582 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1583 }
1584
1585 static void exit_lmode(struct kvm_vcpu *vcpu)
1586 {
1587 vcpu->arch.shadow_efer &= ~EFER_LMA;
1588
1589 vmcs_write32(VM_ENTRY_CONTROLS,
1590 vmcs_read32(VM_ENTRY_CONTROLS)
1591 & ~VM_ENTRY_IA32E_MODE);
1592 }
1593
1594 #endif
1595
1596 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1597 {
1598 vpid_sync_vcpu_all(to_vmx(vcpu));
1599 if (enable_ept)
1600 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1601 }
1602
1603 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1604 {
1605 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1606 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1607 }
1608
1609 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1610 {
1611 if (!test_bit(VCPU_EXREG_PDPTR,
1612 (unsigned long *)&vcpu->arch.regs_dirty))
1613 return;
1614
1615 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1616 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1617 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1618 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1619 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1620 }
1621 }
1622
1623 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1624 {
1625 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1626 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1627 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1628 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1629 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1630 }
1631
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_avail);
1634 __set_bit(VCPU_EXREG_PDPTR,
1635 (unsigned long *)&vcpu->arch.regs_dirty);
1636 }
1637
1638 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1639
1640 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1641 unsigned long cr0,
1642 struct kvm_vcpu *vcpu)
1643 {
1644 if (!(cr0 & X86_CR0_PG)) {
1645 /* From paging/starting to nonpaging */
1646 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1647 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1648 (CPU_BASED_CR3_LOAD_EXITING |
1649 CPU_BASED_CR3_STORE_EXITING));
1650 vcpu->arch.cr0 = cr0;
1651 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1652 } else if (!is_paging(vcpu)) {
1653 /* From nonpaging to paging */
1654 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1655 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1656 ~(CPU_BASED_CR3_LOAD_EXITING |
1657 CPU_BASED_CR3_STORE_EXITING));
1658 vcpu->arch.cr0 = cr0;
1659 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1660 }
1661
1662 if (!(cr0 & X86_CR0_WP))
1663 *hw_cr0 &= ~X86_CR0_WP;
1664 }
1665
1666 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1667 struct kvm_vcpu *vcpu)
1668 {
1669 if (!is_paging(vcpu)) {
1670 *hw_cr4 &= ~X86_CR4_PAE;
1671 *hw_cr4 |= X86_CR4_PSE;
1672 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1673 *hw_cr4 &= ~X86_CR4_PAE;
1674 }
1675
1676 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1677 {
1678 struct vcpu_vmx *vmx = to_vmx(vcpu);
1679 unsigned long hw_cr0;
1680
1681 if (enable_unrestricted_guest)
1682 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1683 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1684 else
1685 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1686
1687 vmx_fpu_deactivate(vcpu);
1688
1689 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1690 enter_pmode(vcpu);
1691
1692 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1693 enter_rmode(vcpu);
1694
1695 #ifdef CONFIG_X86_64
1696 if (vcpu->arch.shadow_efer & EFER_LME) {
1697 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1698 enter_lmode(vcpu);
1699 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1700 exit_lmode(vcpu);
1701 }
1702 #endif
1703
1704 if (enable_ept)
1705 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1706
1707 vmcs_writel(CR0_READ_SHADOW, cr0);
1708 vmcs_writel(GUEST_CR0, hw_cr0);
1709 vcpu->arch.cr0 = cr0;
1710
1711 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1712 vmx_fpu_activate(vcpu);
1713 }
1714
1715 static u64 construct_eptp(unsigned long root_hpa)
1716 {
1717 u64 eptp;
1718
1719 /* TODO write the value reading from MSR */
1720 eptp = VMX_EPT_DEFAULT_MT |
1721 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1722 eptp |= (root_hpa & PAGE_MASK);
1723
1724 return eptp;
1725 }
1726
1727 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1728 {
1729 unsigned long guest_cr3;
1730 u64 eptp;
1731
1732 guest_cr3 = cr3;
1733 if (enable_ept) {
1734 eptp = construct_eptp(cr3);
1735 vmcs_write64(EPT_POINTER, eptp);
1736 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1737 vcpu->kvm->arch.ept_identity_map_addr;
1738 ept_load_pdptrs(vcpu);
1739 }
1740
1741 vmx_flush_tlb(vcpu);
1742 vmcs_writel(GUEST_CR3, guest_cr3);
1743 if (vcpu->arch.cr0 & X86_CR0_PE)
1744 vmx_fpu_deactivate(vcpu);
1745 }
1746
1747 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1748 {
1749 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1750 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1751
1752 vcpu->arch.cr4 = cr4;
1753 if (enable_ept)
1754 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1755
1756 vmcs_writel(CR4_READ_SHADOW, cr4);
1757 vmcs_writel(GUEST_CR4, hw_cr4);
1758 }
1759
1760 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1761 {
1762 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1763
1764 return vmcs_readl(sf->base);
1765 }
1766
1767 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1768 struct kvm_segment *var, int seg)
1769 {
1770 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1771 u32 ar;
1772
1773 var->base = vmcs_readl(sf->base);
1774 var->limit = vmcs_read32(sf->limit);
1775 var->selector = vmcs_read16(sf->selector);
1776 ar = vmcs_read32(sf->ar_bytes);
1777 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1778 ar = 0;
1779 var->type = ar & 15;
1780 var->s = (ar >> 4) & 1;
1781 var->dpl = (ar >> 5) & 3;
1782 var->present = (ar >> 7) & 1;
1783 var->avl = (ar >> 12) & 1;
1784 var->l = (ar >> 13) & 1;
1785 var->db = (ar >> 14) & 1;
1786 var->g = (ar >> 15) & 1;
1787 var->unusable = (ar >> 16) & 1;
1788 }
1789
1790 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1791 {
1792 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1793 return 0;
1794
1795 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1796 return 3;
1797
1798 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1799 }
1800
1801 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1802 {
1803 u32 ar;
1804
1805 if (var->unusable)
1806 ar = 1 << 16;
1807 else {
1808 ar = var->type & 15;
1809 ar |= (var->s & 1) << 4;
1810 ar |= (var->dpl & 3) << 5;
1811 ar |= (var->present & 1) << 7;
1812 ar |= (var->avl & 1) << 12;
1813 ar |= (var->l & 1) << 13;
1814 ar |= (var->db & 1) << 14;
1815 ar |= (var->g & 1) << 15;
1816 }
1817 if (ar == 0) /* a 0 value means unusable */
1818 ar = AR_UNUSABLE_MASK;
1819
1820 return ar;
1821 }
1822
1823 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1824 struct kvm_segment *var, int seg)
1825 {
1826 struct vcpu_vmx *vmx = to_vmx(vcpu);
1827 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1828 u32 ar;
1829
1830 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1831 vmx->rmode.tr.selector = var->selector;
1832 vmx->rmode.tr.base = var->base;
1833 vmx->rmode.tr.limit = var->limit;
1834 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1835 return;
1836 }
1837 vmcs_writel(sf->base, var->base);
1838 vmcs_write32(sf->limit, var->limit);
1839 vmcs_write16(sf->selector, var->selector);
1840 if (vmx->rmode.vm86_active && var->s) {
1841 /*
1842 * Hack real-mode segments into vm86 compatibility.
1843 */
1844 if (var->base == 0xffff0000 && var->selector == 0xf000)
1845 vmcs_writel(sf->base, 0xf0000);
1846 ar = 0xf3;
1847 } else
1848 ar = vmx_segment_access_rights(var);
1849
1850 /*
1851 * Fix the "Accessed" bit in AR field of segment registers for older
1852 * qemu binaries.
1853 * IA32 arch specifies that at the time of processor reset the
1854 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1855 * is setting it to 0 in the usedland code. This causes invalid guest
1856 * state vmexit when "unrestricted guest" mode is turned on.
1857 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1858 * tree. Newer qemu binaries with that qemu fix would not need this
1859 * kvm hack.
1860 */
1861 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1862 ar |= 0x1; /* Accessed */
1863
1864 vmcs_write32(sf->ar_bytes, ar);
1865 }
1866
1867 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1868 {
1869 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1870
1871 *db = (ar >> 14) & 1;
1872 *l = (ar >> 13) & 1;
1873 }
1874
1875 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1876 {
1877 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1878 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1879 }
1880
1881 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1882 {
1883 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1884 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1885 }
1886
1887 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1888 {
1889 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1890 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1891 }
1892
1893 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1894 {
1895 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1896 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1897 }
1898
1899 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1900 {
1901 struct kvm_segment var;
1902 u32 ar;
1903
1904 vmx_get_segment(vcpu, &var, seg);
1905 ar = vmx_segment_access_rights(&var);
1906
1907 if (var.base != (var.selector << 4))
1908 return false;
1909 if (var.limit != 0xffff)
1910 return false;
1911 if (ar != 0xf3)
1912 return false;
1913
1914 return true;
1915 }
1916
1917 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1918 {
1919 struct kvm_segment cs;
1920 unsigned int cs_rpl;
1921
1922 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1923 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1924
1925 if (cs.unusable)
1926 return false;
1927 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1928 return false;
1929 if (!cs.s)
1930 return false;
1931 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1932 if (cs.dpl > cs_rpl)
1933 return false;
1934 } else {
1935 if (cs.dpl != cs_rpl)
1936 return false;
1937 }
1938 if (!cs.present)
1939 return false;
1940
1941 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1942 return true;
1943 }
1944
1945 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1946 {
1947 struct kvm_segment ss;
1948 unsigned int ss_rpl;
1949
1950 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1951 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1952
1953 if (ss.unusable)
1954 return true;
1955 if (ss.type != 3 && ss.type != 7)
1956 return false;
1957 if (!ss.s)
1958 return false;
1959 if (ss.dpl != ss_rpl) /* DPL != RPL */
1960 return false;
1961 if (!ss.present)
1962 return false;
1963
1964 return true;
1965 }
1966
1967 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1968 {
1969 struct kvm_segment var;
1970 unsigned int rpl;
1971
1972 vmx_get_segment(vcpu, &var, seg);
1973 rpl = var.selector & SELECTOR_RPL_MASK;
1974
1975 if (var.unusable)
1976 return true;
1977 if (!var.s)
1978 return false;
1979 if (!var.present)
1980 return false;
1981 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1982 if (var.dpl < rpl) /* DPL < RPL */
1983 return false;
1984 }
1985
1986 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1987 * rights flags
1988 */
1989 return true;
1990 }
1991
1992 static bool tr_valid(struct kvm_vcpu *vcpu)
1993 {
1994 struct kvm_segment tr;
1995
1996 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1997
1998 if (tr.unusable)
1999 return false;
2000 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2001 return false;
2002 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2003 return false;
2004 if (!tr.present)
2005 return false;
2006
2007 return true;
2008 }
2009
2010 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2011 {
2012 struct kvm_segment ldtr;
2013
2014 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2015
2016 if (ldtr.unusable)
2017 return true;
2018 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2019 return false;
2020 if (ldtr.type != 2)
2021 return false;
2022 if (!ldtr.present)
2023 return false;
2024
2025 return true;
2026 }
2027
2028 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2029 {
2030 struct kvm_segment cs, ss;
2031
2032 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2033 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2034
2035 return ((cs.selector & SELECTOR_RPL_MASK) ==
2036 (ss.selector & SELECTOR_RPL_MASK));
2037 }
2038
2039 /*
2040 * Check if guest state is valid. Returns true if valid, false if
2041 * not.
2042 * We assume that registers are always usable
2043 */
2044 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2045 {
2046 /* real mode guest state checks */
2047 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2048 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2049 return false;
2050 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2051 return false;
2052 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2053 return false;
2054 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2055 return false;
2056 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2057 return false;
2058 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2059 return false;
2060 } else {
2061 /* protected mode guest state checks */
2062 if (!cs_ss_rpl_check(vcpu))
2063 return false;
2064 if (!code_segment_valid(vcpu))
2065 return false;
2066 if (!stack_segment_valid(vcpu))
2067 return false;
2068 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2069 return false;
2070 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2071 return false;
2072 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2073 return false;
2074 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2075 return false;
2076 if (!tr_valid(vcpu))
2077 return false;
2078 if (!ldtr_valid(vcpu))
2079 return false;
2080 }
2081 /* TODO:
2082 * - Add checks on RIP
2083 * - Add checks on RFLAGS
2084 */
2085
2086 return true;
2087 }
2088
2089 static int init_rmode_tss(struct kvm *kvm)
2090 {
2091 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2092 u16 data = 0;
2093 int ret = 0;
2094 int r;
2095
2096 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2097 if (r < 0)
2098 goto out;
2099 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2100 r = kvm_write_guest_page(kvm, fn++, &data,
2101 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2102 if (r < 0)
2103 goto out;
2104 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2105 if (r < 0)
2106 goto out;
2107 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2108 if (r < 0)
2109 goto out;
2110 data = ~0;
2111 r = kvm_write_guest_page(kvm, fn, &data,
2112 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2113 sizeof(u8));
2114 if (r < 0)
2115 goto out;
2116
2117 ret = 1;
2118 out:
2119 return ret;
2120 }
2121
2122 static int init_rmode_identity_map(struct kvm *kvm)
2123 {
2124 int i, r, ret;
2125 pfn_t identity_map_pfn;
2126 u32 tmp;
2127
2128 if (!enable_ept)
2129 return 1;
2130 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2131 printk(KERN_ERR "EPT: identity-mapping pagetable "
2132 "haven't been allocated!\n");
2133 return 0;
2134 }
2135 if (likely(kvm->arch.ept_identity_pagetable_done))
2136 return 1;
2137 ret = 0;
2138 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2139 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2140 if (r < 0)
2141 goto out;
2142 /* Set up identity-mapping pagetable for EPT in real mode */
2143 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2144 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2145 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2146 r = kvm_write_guest_page(kvm, identity_map_pfn,
2147 &tmp, i * sizeof(tmp), sizeof(tmp));
2148 if (r < 0)
2149 goto out;
2150 }
2151 kvm->arch.ept_identity_pagetable_done = true;
2152 ret = 1;
2153 out:
2154 return ret;
2155 }
2156
2157 static void seg_setup(int seg)
2158 {
2159 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2160 unsigned int ar;
2161
2162 vmcs_write16(sf->selector, 0);
2163 vmcs_writel(sf->base, 0);
2164 vmcs_write32(sf->limit, 0xffff);
2165 if (enable_unrestricted_guest) {
2166 ar = 0x93;
2167 if (seg == VCPU_SREG_CS)
2168 ar |= 0x08; /* code segment */
2169 } else
2170 ar = 0xf3;
2171
2172 vmcs_write32(sf->ar_bytes, ar);
2173 }
2174
2175 static int alloc_apic_access_page(struct kvm *kvm)
2176 {
2177 struct kvm_userspace_memory_region kvm_userspace_mem;
2178 int r = 0;
2179
2180 down_write(&kvm->slots_lock);
2181 if (kvm->arch.apic_access_page)
2182 goto out;
2183 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2184 kvm_userspace_mem.flags = 0;
2185 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2186 kvm_userspace_mem.memory_size = PAGE_SIZE;
2187 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2188 if (r)
2189 goto out;
2190
2191 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2192 out:
2193 up_write(&kvm->slots_lock);
2194 return r;
2195 }
2196
2197 static int alloc_identity_pagetable(struct kvm *kvm)
2198 {
2199 struct kvm_userspace_memory_region kvm_userspace_mem;
2200 int r = 0;
2201
2202 down_write(&kvm->slots_lock);
2203 if (kvm->arch.ept_identity_pagetable)
2204 goto out;
2205 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2206 kvm_userspace_mem.flags = 0;
2207 kvm_userspace_mem.guest_phys_addr =
2208 kvm->arch.ept_identity_map_addr;
2209 kvm_userspace_mem.memory_size = PAGE_SIZE;
2210 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2211 if (r)
2212 goto out;
2213
2214 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2215 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2216 out:
2217 up_write(&kvm->slots_lock);
2218 return r;
2219 }
2220
2221 static void allocate_vpid(struct vcpu_vmx *vmx)
2222 {
2223 int vpid;
2224
2225 vmx->vpid = 0;
2226 if (!enable_vpid)
2227 return;
2228 spin_lock(&vmx_vpid_lock);
2229 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2230 if (vpid < VMX_NR_VPIDS) {
2231 vmx->vpid = vpid;
2232 __set_bit(vpid, vmx_vpid_bitmap);
2233 }
2234 spin_unlock(&vmx_vpid_lock);
2235 }
2236
2237 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2238 {
2239 int f = sizeof(unsigned long);
2240
2241 if (!cpu_has_vmx_msr_bitmap())
2242 return;
2243
2244 /*
2245 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2246 * have the write-low and read-high bitmap offsets the wrong way round.
2247 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2248 */
2249 if (msr <= 0x1fff) {
2250 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2251 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2252 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2253 msr &= 0x1fff;
2254 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2255 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2256 }
2257 }
2258
2259 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2260 {
2261 if (!longmode_only)
2262 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2263 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2264 }
2265
2266 /*
2267 * Sets up the vmcs for emulated real mode.
2268 */
2269 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2270 {
2271 u32 host_sysenter_cs, msr_low, msr_high;
2272 u32 junk;
2273 u64 host_pat, tsc_this, tsc_base;
2274 unsigned long a;
2275 struct descriptor_table dt;
2276 int i;
2277 unsigned long kvm_vmx_return;
2278 u32 exec_control;
2279
2280 /* I/O */
2281 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2282 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2283
2284 if (cpu_has_vmx_msr_bitmap())
2285 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2286
2287 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2288
2289 /* Control */
2290 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2291 vmcs_config.pin_based_exec_ctrl);
2292
2293 exec_control = vmcs_config.cpu_based_exec_ctrl;
2294 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2295 exec_control &= ~CPU_BASED_TPR_SHADOW;
2296 #ifdef CONFIG_X86_64
2297 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2298 CPU_BASED_CR8_LOAD_EXITING;
2299 #endif
2300 }
2301 if (!enable_ept)
2302 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2303 CPU_BASED_CR3_LOAD_EXITING |
2304 CPU_BASED_INVLPG_EXITING;
2305 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2306
2307 if (cpu_has_secondary_exec_ctrls()) {
2308 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2309 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2310 exec_control &=
2311 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2312 if (vmx->vpid == 0)
2313 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2314 if (!enable_ept) {
2315 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2316 enable_unrestricted_guest = 0;
2317 }
2318 if (!enable_unrestricted_guest)
2319 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2320 if (!ple_gap)
2321 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2322 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2323 }
2324
2325 if (ple_gap) {
2326 vmcs_write32(PLE_GAP, ple_gap);
2327 vmcs_write32(PLE_WINDOW, ple_window);
2328 }
2329
2330 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2331 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2332 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2333
2334 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2335 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2336 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2337
2338 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2339 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2340 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2341 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2342 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2343 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2344 #ifdef CONFIG_X86_64
2345 rdmsrl(MSR_FS_BASE, a);
2346 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2347 rdmsrl(MSR_GS_BASE, a);
2348 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2349 #else
2350 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2351 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2352 #endif
2353
2354 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2355
2356 kvm_get_idt(&dt);
2357 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2358
2359 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2360 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2361 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2362 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2363 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2364
2365 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2366 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2367 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2368 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2369 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2370 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2371
2372 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2373 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2374 host_pat = msr_low | ((u64) msr_high << 32);
2375 vmcs_write64(HOST_IA32_PAT, host_pat);
2376 }
2377 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2378 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2379 host_pat = msr_low | ((u64) msr_high << 32);
2380 /* Write the default value follow host pat */
2381 vmcs_write64(GUEST_IA32_PAT, host_pat);
2382 /* Keep arch.pat sync with GUEST_IA32_PAT */
2383 vmx->vcpu.arch.pat = host_pat;
2384 }
2385
2386 for (i = 0; i < NR_VMX_MSR; ++i) {
2387 u32 index = vmx_msr_index[i];
2388 u32 data_low, data_high;
2389 u64 data;
2390 int j = vmx->nmsrs;
2391
2392 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2393 continue;
2394 if (wrmsr_safe(index, data_low, data_high) < 0)
2395 continue;
2396 data = data_low | ((u64)data_high << 32);
2397 vmx->guest_msrs[j].index = i;
2398 vmx->guest_msrs[j].data = 0;
2399 vmx->guest_msrs[j].mask = -1ull;
2400 ++vmx->nmsrs;
2401 }
2402
2403 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2404
2405 /* 22.2.1, 20.8.1 */
2406 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2407
2408 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2409 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2410
2411 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2412 rdtscll(tsc_this);
2413 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2414 tsc_base = tsc_this;
2415
2416 guest_write_tsc(0, tsc_base);
2417
2418 return 0;
2419 }
2420
2421 static int init_rmode(struct kvm *kvm)
2422 {
2423 if (!init_rmode_tss(kvm))
2424 return 0;
2425 if (!init_rmode_identity_map(kvm))
2426 return 0;
2427 return 1;
2428 }
2429
2430 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2431 {
2432 struct vcpu_vmx *vmx = to_vmx(vcpu);
2433 u64 msr;
2434 int ret;
2435
2436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2437 down_read(&vcpu->kvm->slots_lock);
2438 if (!init_rmode(vmx->vcpu.kvm)) {
2439 ret = -ENOMEM;
2440 goto out;
2441 }
2442
2443 vmx->rmode.vm86_active = 0;
2444
2445 vmx->soft_vnmi_blocked = 0;
2446
2447 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2448 kvm_set_cr8(&vmx->vcpu, 0);
2449 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2450 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2451 msr |= MSR_IA32_APICBASE_BSP;
2452 kvm_set_apic_base(&vmx->vcpu, msr);
2453
2454 fx_init(&vmx->vcpu);
2455
2456 seg_setup(VCPU_SREG_CS);
2457 /*
2458 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2459 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2460 */
2461 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2462 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2463 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2464 } else {
2465 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2466 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2467 }
2468
2469 seg_setup(VCPU_SREG_DS);
2470 seg_setup(VCPU_SREG_ES);
2471 seg_setup(VCPU_SREG_FS);
2472 seg_setup(VCPU_SREG_GS);
2473 seg_setup(VCPU_SREG_SS);
2474
2475 vmcs_write16(GUEST_TR_SELECTOR, 0);
2476 vmcs_writel(GUEST_TR_BASE, 0);
2477 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2478 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2479
2480 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2481 vmcs_writel(GUEST_LDTR_BASE, 0);
2482 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2483 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2484
2485 vmcs_write32(GUEST_SYSENTER_CS, 0);
2486 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2487 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2488
2489 vmcs_writel(GUEST_RFLAGS, 0x02);
2490 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2491 kvm_rip_write(vcpu, 0xfff0);
2492 else
2493 kvm_rip_write(vcpu, 0);
2494 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2495
2496 vmcs_writel(GUEST_DR7, 0x400);
2497
2498 vmcs_writel(GUEST_GDTR_BASE, 0);
2499 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2500
2501 vmcs_writel(GUEST_IDTR_BASE, 0);
2502 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2503
2504 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2506 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2507
2508 /* Special registers */
2509 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2510
2511 setup_msrs(vmx);
2512
2513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2514
2515 if (cpu_has_vmx_tpr_shadow()) {
2516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2517 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2518 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2519 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2520 vmcs_write32(TPR_THRESHOLD, 0);
2521 }
2522
2523 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2524 vmcs_write64(APIC_ACCESS_ADDR,
2525 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2526
2527 if (vmx->vpid != 0)
2528 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2529
2530 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2531 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2532 vmx_set_cr4(&vmx->vcpu, 0);
2533 vmx_set_efer(&vmx->vcpu, 0);
2534 vmx_fpu_activate(&vmx->vcpu);
2535 update_exception_bitmap(&vmx->vcpu);
2536
2537 vpid_sync_vcpu_all(vmx);
2538
2539 ret = 0;
2540
2541 /* HACK: Don't enable emulation on guest boot/reset */
2542 vmx->emulation_required = 0;
2543
2544 out:
2545 up_read(&vcpu->kvm->slots_lock);
2546 return ret;
2547 }
2548
2549 static void enable_irq_window(struct kvm_vcpu *vcpu)
2550 {
2551 u32 cpu_based_vm_exec_control;
2552
2553 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2554 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2555 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2556 }
2557
2558 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2559 {
2560 u32 cpu_based_vm_exec_control;
2561
2562 if (!cpu_has_virtual_nmis()) {
2563 enable_irq_window(vcpu);
2564 return;
2565 }
2566
2567 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2568 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2570 }
2571
2572 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2573 {
2574 struct vcpu_vmx *vmx = to_vmx(vcpu);
2575 uint32_t intr;
2576 int irq = vcpu->arch.interrupt.nr;
2577
2578 trace_kvm_inj_virq(irq);
2579
2580 ++vcpu->stat.irq_injections;
2581 if (vmx->rmode.vm86_active) {
2582 vmx->rmode.irq.pending = true;
2583 vmx->rmode.irq.vector = irq;
2584 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2585 if (vcpu->arch.interrupt.soft)
2586 vmx->rmode.irq.rip +=
2587 vmx->vcpu.arch.event_exit_inst_len;
2588 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2589 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2590 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2591 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2592 return;
2593 }
2594 intr = irq | INTR_INFO_VALID_MASK;
2595 if (vcpu->arch.interrupt.soft) {
2596 intr |= INTR_TYPE_SOFT_INTR;
2597 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2598 vmx->vcpu.arch.event_exit_inst_len);
2599 } else
2600 intr |= INTR_TYPE_EXT_INTR;
2601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2602 }
2603
2604 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2605 {
2606 struct vcpu_vmx *vmx = to_vmx(vcpu);
2607
2608 if (!cpu_has_virtual_nmis()) {
2609 /*
2610 * Tracking the NMI-blocked state in software is built upon
2611 * finding the next open IRQ window. This, in turn, depends on
2612 * well-behaving guests: They have to keep IRQs disabled at
2613 * least as long as the NMI handler runs. Otherwise we may
2614 * cause NMI nesting, maybe breaking the guest. But as this is
2615 * highly unlikely, we can live with the residual risk.
2616 */
2617 vmx->soft_vnmi_blocked = 1;
2618 vmx->vnmi_blocked_time = 0;
2619 }
2620
2621 ++vcpu->stat.nmi_injections;
2622 if (vmx->rmode.vm86_active) {
2623 vmx->rmode.irq.pending = true;
2624 vmx->rmode.irq.vector = NMI_VECTOR;
2625 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2626 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2627 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2628 INTR_INFO_VALID_MASK);
2629 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2630 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2631 return;
2632 }
2633 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2634 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2635 }
2636
2637 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2638 {
2639 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2640 return 0;
2641
2642 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2643 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2644 GUEST_INTR_STATE_NMI));
2645 }
2646
2647 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2648 {
2649 if (!cpu_has_virtual_nmis())
2650 return to_vmx(vcpu)->soft_vnmi_blocked;
2651 else
2652 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2653 GUEST_INTR_STATE_NMI);
2654 }
2655
2656 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2657 {
2658 struct vcpu_vmx *vmx = to_vmx(vcpu);
2659
2660 if (!cpu_has_virtual_nmis()) {
2661 if (vmx->soft_vnmi_blocked != masked) {
2662 vmx->soft_vnmi_blocked = masked;
2663 vmx->vnmi_blocked_time = 0;
2664 }
2665 } else {
2666 if (masked)
2667 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2668 GUEST_INTR_STATE_NMI);
2669 else
2670 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2671 GUEST_INTR_STATE_NMI);
2672 }
2673 }
2674
2675 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2676 {
2677 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2678 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2679 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2680 }
2681
2682 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2683 {
2684 int ret;
2685 struct kvm_userspace_memory_region tss_mem = {
2686 .slot = TSS_PRIVATE_MEMSLOT,
2687 .guest_phys_addr = addr,
2688 .memory_size = PAGE_SIZE * 3,
2689 .flags = 0,
2690 };
2691
2692 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2693 if (ret)
2694 return ret;
2695 kvm->arch.tss_addr = addr;
2696 return 0;
2697 }
2698
2699 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2700 int vec, u32 err_code)
2701 {
2702 /*
2703 * Instruction with address size override prefix opcode 0x67
2704 * Cause the #SS fault with 0 error code in VM86 mode.
2705 */
2706 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2707 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2708 return 1;
2709 /*
2710 * Forward all other exceptions that are valid in real mode.
2711 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2712 * the required debugging infrastructure rework.
2713 */
2714 switch (vec) {
2715 case DB_VECTOR:
2716 if (vcpu->guest_debug &
2717 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2718 return 0;
2719 kvm_queue_exception(vcpu, vec);
2720 return 1;
2721 case BP_VECTOR:
2722 /*
2723 * Update instruction length as we may reinject the exception
2724 * from user space while in guest debugging mode.
2725 */
2726 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2727 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2729 return 0;
2730 /* fall through */
2731 case DE_VECTOR:
2732 case OF_VECTOR:
2733 case BR_VECTOR:
2734 case UD_VECTOR:
2735 case DF_VECTOR:
2736 case SS_VECTOR:
2737 case GP_VECTOR:
2738 case MF_VECTOR:
2739 kvm_queue_exception(vcpu, vec);
2740 return 1;
2741 }
2742 return 0;
2743 }
2744
2745 /*
2746 * Trigger machine check on the host. We assume all the MSRs are already set up
2747 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2748 * We pass a fake environment to the machine check handler because we want
2749 * the guest to be always treated like user space, no matter what context
2750 * it used internally.
2751 */
2752 static void kvm_machine_check(void)
2753 {
2754 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2755 struct pt_regs regs = {
2756 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2757 .flags = X86_EFLAGS_IF,
2758 };
2759
2760 do_machine_check(&regs, 0);
2761 #endif
2762 }
2763
2764 static int handle_machine_check(struct kvm_vcpu *vcpu)
2765 {
2766 /* already handled by vcpu_run */
2767 return 1;
2768 }
2769
2770 static int handle_exception(struct kvm_vcpu *vcpu)
2771 {
2772 struct vcpu_vmx *vmx = to_vmx(vcpu);
2773 struct kvm_run *kvm_run = vcpu->run;
2774 u32 intr_info, ex_no, error_code;
2775 unsigned long cr2, rip, dr6;
2776 u32 vect_info;
2777 enum emulation_result er;
2778
2779 vect_info = vmx->idt_vectoring_info;
2780 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2781
2782 if (is_machine_check(intr_info))
2783 return handle_machine_check(vcpu);
2784
2785 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2786 !is_page_fault(intr_info)) {
2787 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2788 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2789 vcpu->run->internal.ndata = 2;
2790 vcpu->run->internal.data[0] = vect_info;
2791 vcpu->run->internal.data[1] = intr_info;
2792 return 0;
2793 }
2794
2795 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2796 return 1; /* already handled by vmx_vcpu_run() */
2797
2798 if (is_no_device(intr_info)) {
2799 vmx_fpu_activate(vcpu);
2800 return 1;
2801 }
2802
2803 if (is_invalid_opcode(intr_info)) {
2804 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2805 if (er != EMULATE_DONE)
2806 kvm_queue_exception(vcpu, UD_VECTOR);
2807 return 1;
2808 }
2809
2810 error_code = 0;
2811 rip = kvm_rip_read(vcpu);
2812 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2813 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2814 if (is_page_fault(intr_info)) {
2815 /* EPT won't cause page fault directly */
2816 if (enable_ept)
2817 BUG();
2818 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2819 trace_kvm_page_fault(cr2, error_code);
2820
2821 if (kvm_event_needs_reinjection(vcpu))
2822 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2823 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2824 }
2825
2826 if (vmx->rmode.vm86_active &&
2827 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2828 error_code)) {
2829 if (vcpu->arch.halt_request) {
2830 vcpu->arch.halt_request = 0;
2831 return kvm_emulate_halt(vcpu);
2832 }
2833 return 1;
2834 }
2835
2836 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2837 switch (ex_no) {
2838 case DB_VECTOR:
2839 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2840 if (!(vcpu->guest_debug &
2841 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2842 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2843 kvm_queue_exception(vcpu, DB_VECTOR);
2844 return 1;
2845 }
2846 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2847 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2848 /* fall through */
2849 case BP_VECTOR:
2850 /*
2851 * Update instruction length as we may reinject #BP from
2852 * user space while in guest debugging mode. Reading it for
2853 * #DB as well causes no harm, it is not used in that case.
2854 */
2855 vmx->vcpu.arch.event_exit_inst_len =
2856 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2857 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2858 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2859 kvm_run->debug.arch.exception = ex_no;
2860 break;
2861 default:
2862 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2863 kvm_run->ex.exception = ex_no;
2864 kvm_run->ex.error_code = error_code;
2865 break;
2866 }
2867 return 0;
2868 }
2869
2870 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2871 {
2872 ++vcpu->stat.irq_exits;
2873 return 1;
2874 }
2875
2876 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2877 {
2878 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2879 return 0;
2880 }
2881
2882 static int handle_io(struct kvm_vcpu *vcpu)
2883 {
2884 unsigned long exit_qualification;
2885 int size, in, string;
2886 unsigned port;
2887
2888 ++vcpu->stat.io_exits;
2889 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2890 string = (exit_qualification & 16) != 0;
2891
2892 if (string) {
2893 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2894 return 0;
2895 return 1;
2896 }
2897
2898 size = (exit_qualification & 7) + 1;
2899 in = (exit_qualification & 8) != 0;
2900 port = exit_qualification >> 16;
2901
2902 skip_emulated_instruction(vcpu);
2903 return kvm_emulate_pio(vcpu, in, size, port);
2904 }
2905
2906 static void
2907 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2908 {
2909 /*
2910 * Patch in the VMCALL instruction:
2911 */
2912 hypercall[0] = 0x0f;
2913 hypercall[1] = 0x01;
2914 hypercall[2] = 0xc1;
2915 }
2916
2917 static int handle_cr(struct kvm_vcpu *vcpu)
2918 {
2919 unsigned long exit_qualification, val;
2920 int cr;
2921 int reg;
2922
2923 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2924 cr = exit_qualification & 15;
2925 reg = (exit_qualification >> 8) & 15;
2926 switch ((exit_qualification >> 4) & 3) {
2927 case 0: /* mov to cr */
2928 val = kvm_register_read(vcpu, reg);
2929 trace_kvm_cr_write(cr, val);
2930 switch (cr) {
2931 case 0:
2932 kvm_set_cr0(vcpu, val);
2933 skip_emulated_instruction(vcpu);
2934 return 1;
2935 case 3:
2936 kvm_set_cr3(vcpu, val);
2937 skip_emulated_instruction(vcpu);
2938 return 1;
2939 case 4:
2940 kvm_set_cr4(vcpu, val);
2941 skip_emulated_instruction(vcpu);
2942 return 1;
2943 case 8: {
2944 u8 cr8_prev = kvm_get_cr8(vcpu);
2945 u8 cr8 = kvm_register_read(vcpu, reg);
2946 kvm_set_cr8(vcpu, cr8);
2947 skip_emulated_instruction(vcpu);
2948 if (irqchip_in_kernel(vcpu->kvm))
2949 return 1;
2950 if (cr8_prev <= cr8)
2951 return 1;
2952 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2953 return 0;
2954 }
2955 };
2956 break;
2957 case 2: /* clts */
2958 vmx_fpu_deactivate(vcpu);
2959 vcpu->arch.cr0 &= ~X86_CR0_TS;
2960 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2961 vmx_fpu_activate(vcpu);
2962 skip_emulated_instruction(vcpu);
2963 return 1;
2964 case 1: /*mov from cr*/
2965 switch (cr) {
2966 case 3:
2967 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2968 trace_kvm_cr_read(cr, vcpu->arch.cr3);
2969 skip_emulated_instruction(vcpu);
2970 return 1;
2971 case 8:
2972 val = kvm_get_cr8(vcpu);
2973 kvm_register_write(vcpu, reg, val);
2974 trace_kvm_cr_read(cr, val);
2975 skip_emulated_instruction(vcpu);
2976 return 1;
2977 }
2978 break;
2979 case 3: /* lmsw */
2980 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2981
2982 skip_emulated_instruction(vcpu);
2983 return 1;
2984 default:
2985 break;
2986 }
2987 vcpu->run->exit_reason = 0;
2988 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2989 (int)(exit_qualification >> 4) & 3, cr);
2990 return 0;
2991 }
2992
2993 static int handle_dr(struct kvm_vcpu *vcpu)
2994 {
2995 unsigned long exit_qualification;
2996 unsigned long val;
2997 int dr, reg;
2998
2999 if (!kvm_require_cpl(vcpu, 0))
3000 return 1;
3001 dr = vmcs_readl(GUEST_DR7);
3002 if (dr & DR7_GD) {
3003 /*
3004 * As the vm-exit takes precedence over the debug trap, we
3005 * need to emulate the latter, either for the host or the
3006 * guest debugging itself.
3007 */
3008 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3009 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3010 vcpu->run->debug.arch.dr7 = dr;
3011 vcpu->run->debug.arch.pc =
3012 vmcs_readl(GUEST_CS_BASE) +
3013 vmcs_readl(GUEST_RIP);
3014 vcpu->run->debug.arch.exception = DB_VECTOR;
3015 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3016 return 0;
3017 } else {
3018 vcpu->arch.dr7 &= ~DR7_GD;
3019 vcpu->arch.dr6 |= DR6_BD;
3020 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3021 kvm_queue_exception(vcpu, DB_VECTOR);
3022 return 1;
3023 }
3024 }
3025
3026 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3027 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3028 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3029 if (exit_qualification & TYPE_MOV_FROM_DR) {
3030 switch (dr) {
3031 case 0 ... 3:
3032 val = vcpu->arch.db[dr];
3033 break;
3034 case 6:
3035 val = vcpu->arch.dr6;
3036 break;
3037 case 7:
3038 val = vcpu->arch.dr7;
3039 break;
3040 default:
3041 val = 0;
3042 }
3043 kvm_register_write(vcpu, reg, val);
3044 } else {
3045 val = vcpu->arch.regs[reg];
3046 switch (dr) {
3047 case 0 ... 3:
3048 vcpu->arch.db[dr] = val;
3049 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3050 vcpu->arch.eff_db[dr] = val;
3051 break;
3052 case 4 ... 5:
3053 if (vcpu->arch.cr4 & X86_CR4_DE)
3054 kvm_queue_exception(vcpu, UD_VECTOR);
3055 break;
3056 case 6:
3057 if (val & 0xffffffff00000000ULL) {
3058 kvm_queue_exception(vcpu, GP_VECTOR);
3059 break;
3060 }
3061 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3062 break;
3063 case 7:
3064 if (val & 0xffffffff00000000ULL) {
3065 kvm_queue_exception(vcpu, GP_VECTOR);
3066 break;
3067 }
3068 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3069 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3070 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3071 vcpu->arch.switch_db_regs =
3072 (val & DR7_BP_EN_MASK);
3073 }
3074 break;
3075 }
3076 }
3077 skip_emulated_instruction(vcpu);
3078 return 1;
3079 }
3080
3081 static int handle_cpuid(struct kvm_vcpu *vcpu)
3082 {
3083 kvm_emulate_cpuid(vcpu);
3084 return 1;
3085 }
3086
3087 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3088 {
3089 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3090 u64 data;
3091
3092 if (vmx_get_msr(vcpu, ecx, &data)) {
3093 kvm_inject_gp(vcpu, 0);
3094 return 1;
3095 }
3096
3097 trace_kvm_msr_read(ecx, data);
3098
3099 /* FIXME: handling of bits 32:63 of rax, rdx */
3100 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3101 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3102 skip_emulated_instruction(vcpu);
3103 return 1;
3104 }
3105
3106 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3107 {
3108 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3109 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3110 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3111
3112 trace_kvm_msr_write(ecx, data);
3113
3114 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3115 kvm_inject_gp(vcpu, 0);
3116 return 1;
3117 }
3118
3119 skip_emulated_instruction(vcpu);
3120 return 1;
3121 }
3122
3123 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3124 {
3125 return 1;
3126 }
3127
3128 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3129 {
3130 u32 cpu_based_vm_exec_control;
3131
3132 /* clear pending irq */
3133 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3134 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3135 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3136
3137 ++vcpu->stat.irq_window_exits;
3138
3139 /*
3140 * If the user space waits to inject interrupts, exit as soon as
3141 * possible
3142 */
3143 if (!irqchip_in_kernel(vcpu->kvm) &&
3144 vcpu->run->request_interrupt_window &&
3145 !kvm_cpu_has_interrupt(vcpu)) {
3146 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3147 return 0;
3148 }
3149 return 1;
3150 }
3151
3152 static int handle_halt(struct kvm_vcpu *vcpu)
3153 {
3154 skip_emulated_instruction(vcpu);
3155 return kvm_emulate_halt(vcpu);
3156 }
3157
3158 static int handle_vmcall(struct kvm_vcpu *vcpu)
3159 {
3160 skip_emulated_instruction(vcpu);
3161 kvm_emulate_hypercall(vcpu);
3162 return 1;
3163 }
3164
3165 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3166 {
3167 kvm_queue_exception(vcpu, UD_VECTOR);
3168 return 1;
3169 }
3170
3171 static int handle_invlpg(struct kvm_vcpu *vcpu)
3172 {
3173 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3174
3175 kvm_mmu_invlpg(vcpu, exit_qualification);
3176 skip_emulated_instruction(vcpu);
3177 return 1;
3178 }
3179
3180 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3181 {
3182 skip_emulated_instruction(vcpu);
3183 /* TODO: Add support for VT-d/pass-through device */
3184 return 1;
3185 }
3186
3187 static int handle_apic_access(struct kvm_vcpu *vcpu)
3188 {
3189 unsigned long exit_qualification;
3190 enum emulation_result er;
3191 unsigned long offset;
3192
3193 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3194 offset = exit_qualification & 0xffful;
3195
3196 er = emulate_instruction(vcpu, 0, 0, 0);
3197
3198 if (er != EMULATE_DONE) {
3199 printk(KERN_ERR
3200 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3201 offset);
3202 return -ENOEXEC;
3203 }
3204 return 1;
3205 }
3206
3207 static int handle_task_switch(struct kvm_vcpu *vcpu)
3208 {
3209 struct vcpu_vmx *vmx = to_vmx(vcpu);
3210 unsigned long exit_qualification;
3211 u16 tss_selector;
3212 int reason, type, idt_v;
3213
3214 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3215 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3216
3217 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3218
3219 reason = (u32)exit_qualification >> 30;
3220 if (reason == TASK_SWITCH_GATE && idt_v) {
3221 switch (type) {
3222 case INTR_TYPE_NMI_INTR:
3223 vcpu->arch.nmi_injected = false;
3224 if (cpu_has_virtual_nmis())
3225 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3226 GUEST_INTR_STATE_NMI);
3227 break;
3228 case INTR_TYPE_EXT_INTR:
3229 case INTR_TYPE_SOFT_INTR:
3230 kvm_clear_interrupt_queue(vcpu);
3231 break;
3232 case INTR_TYPE_HARD_EXCEPTION:
3233 case INTR_TYPE_SOFT_EXCEPTION:
3234 kvm_clear_exception_queue(vcpu);
3235 break;
3236 default:
3237 break;
3238 }
3239 }
3240 tss_selector = exit_qualification;
3241
3242 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3243 type != INTR_TYPE_EXT_INTR &&
3244 type != INTR_TYPE_NMI_INTR))
3245 skip_emulated_instruction(vcpu);
3246
3247 if (!kvm_task_switch(vcpu, tss_selector, reason))
3248 return 0;
3249
3250 /* clear all local breakpoint enable flags */
3251 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3252
3253 /*
3254 * TODO: What about debug traps on tss switch?
3255 * Are we supposed to inject them and update dr6?
3256 */
3257
3258 return 1;
3259 }
3260
3261 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3262 {
3263 unsigned long exit_qualification;
3264 gpa_t gpa;
3265 int gla_validity;
3266
3267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3268
3269 if (exit_qualification & (1 << 6)) {
3270 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3271 return -EINVAL;
3272 }
3273
3274 gla_validity = (exit_qualification >> 7) & 0x3;
3275 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3276 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3277 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3278 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3279 vmcs_readl(GUEST_LINEAR_ADDRESS));
3280 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3281 (long unsigned int)exit_qualification);
3282 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3283 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3284 return 0;
3285 }
3286
3287 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3288 trace_kvm_page_fault(gpa, exit_qualification);
3289 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3290 }
3291
3292 static u64 ept_rsvd_mask(u64 spte, int level)
3293 {
3294 int i;
3295 u64 mask = 0;
3296
3297 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3298 mask |= (1ULL << i);
3299
3300 if (level > 2)
3301 /* bits 7:3 reserved */
3302 mask |= 0xf8;
3303 else if (level == 2) {
3304 if (spte & (1ULL << 7))
3305 /* 2MB ref, bits 20:12 reserved */
3306 mask |= 0x1ff000;
3307 else
3308 /* bits 6:3 reserved */
3309 mask |= 0x78;
3310 }
3311
3312 return mask;
3313 }
3314
3315 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3316 int level)
3317 {
3318 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3319
3320 /* 010b (write-only) */
3321 WARN_ON((spte & 0x7) == 0x2);
3322
3323 /* 110b (write/execute) */
3324 WARN_ON((spte & 0x7) == 0x6);
3325
3326 /* 100b (execute-only) and value not supported by logical processor */
3327 if (!cpu_has_vmx_ept_execute_only())
3328 WARN_ON((spte & 0x7) == 0x4);
3329
3330 /* not 000b */
3331 if ((spte & 0x7)) {
3332 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3333
3334 if (rsvd_bits != 0) {
3335 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3336 __func__, rsvd_bits);
3337 WARN_ON(1);
3338 }
3339
3340 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3341 u64 ept_mem_type = (spte & 0x38) >> 3;
3342
3343 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3344 ept_mem_type == 7) {
3345 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3346 __func__, ept_mem_type);
3347 WARN_ON(1);
3348 }
3349 }
3350 }
3351 }
3352
3353 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3354 {
3355 u64 sptes[4];
3356 int nr_sptes, i;
3357 gpa_t gpa;
3358
3359 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3360
3361 printk(KERN_ERR "EPT: Misconfiguration.\n");
3362 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3363
3364 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3365
3366 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3367 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3368
3369 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3370 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3371
3372 return 0;
3373 }
3374
3375 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3376 {
3377 u32 cpu_based_vm_exec_control;
3378
3379 /* clear pending NMI */
3380 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3381 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3382 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3383 ++vcpu->stat.nmi_window_exits;
3384
3385 return 1;
3386 }
3387
3388 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3389 {
3390 struct vcpu_vmx *vmx = to_vmx(vcpu);
3391 enum emulation_result err = EMULATE_DONE;
3392 int ret = 1;
3393
3394 while (!guest_state_valid(vcpu)) {
3395 err = emulate_instruction(vcpu, 0, 0, 0);
3396
3397 if (err == EMULATE_DO_MMIO) {
3398 ret = 0;
3399 goto out;
3400 }
3401
3402 if (err != EMULATE_DONE) {
3403 kvm_report_emulation_failure(vcpu, "emulation failure");
3404 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3405 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3406 vcpu->run->internal.ndata = 0;
3407 ret = 0;
3408 goto out;
3409 }
3410
3411 if (signal_pending(current))
3412 goto out;
3413 if (need_resched())
3414 schedule();
3415 }
3416
3417 vmx->emulation_required = 0;
3418 out:
3419 return ret;
3420 }
3421
3422 /*
3423 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3424 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3425 */
3426 static int handle_pause(struct kvm_vcpu *vcpu)
3427 {
3428 skip_emulated_instruction(vcpu);
3429 kvm_vcpu_on_spin(vcpu);
3430
3431 return 1;
3432 }
3433
3434 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3435 {
3436 kvm_queue_exception(vcpu, UD_VECTOR);
3437 return 1;
3438 }
3439
3440 /*
3441 * The exit handlers return 1 if the exit was handled fully and guest execution
3442 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3443 * to be done to userspace and return 0.
3444 */
3445 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3446 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3447 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3448 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3449 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3450 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3451 [EXIT_REASON_CR_ACCESS] = handle_cr,
3452 [EXIT_REASON_DR_ACCESS] = handle_dr,
3453 [EXIT_REASON_CPUID] = handle_cpuid,
3454 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3455 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3456 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3457 [EXIT_REASON_HLT] = handle_halt,
3458 [EXIT_REASON_INVLPG] = handle_invlpg,
3459 [EXIT_REASON_VMCALL] = handle_vmcall,
3460 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3461 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3462 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3463 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3464 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3465 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3466 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3467 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3468 [EXIT_REASON_VMON] = handle_vmx_insn,
3469 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3470 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3471 [EXIT_REASON_WBINVD] = handle_wbinvd,
3472 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3473 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3474 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3475 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3476 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3477 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3478 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3479 };
3480
3481 static const int kvm_vmx_max_exit_handlers =
3482 ARRAY_SIZE(kvm_vmx_exit_handlers);
3483
3484 /*
3485 * The guest has exited. See if we can fix it or if we need userspace
3486 * assistance.
3487 */
3488 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3489 {
3490 struct vcpu_vmx *vmx = to_vmx(vcpu);
3491 u32 exit_reason = vmx->exit_reason;
3492 u32 vectoring_info = vmx->idt_vectoring_info;
3493
3494 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3495
3496 /* If guest state is invalid, start emulating */
3497 if (vmx->emulation_required && emulate_invalid_guest_state)
3498 return handle_invalid_guest_state(vcpu);
3499
3500 /* Access CR3 don't cause VMExit in paging mode, so we need
3501 * to sync with guest real CR3. */
3502 if (enable_ept && is_paging(vcpu))
3503 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3504
3505 if (unlikely(vmx->fail)) {
3506 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3507 vcpu->run->fail_entry.hardware_entry_failure_reason
3508 = vmcs_read32(VM_INSTRUCTION_ERROR);
3509 return 0;
3510 }
3511
3512 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3513 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3514 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3515 exit_reason != EXIT_REASON_TASK_SWITCH))
3516 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3517 "(0x%x) and exit reason is 0x%x\n",
3518 __func__, vectoring_info, exit_reason);
3519
3520 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3521 if (vmx_interrupt_allowed(vcpu)) {
3522 vmx->soft_vnmi_blocked = 0;
3523 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3524 vcpu->arch.nmi_pending) {
3525 /*
3526 * This CPU don't support us in finding the end of an
3527 * NMI-blocked window if the guest runs with IRQs
3528 * disabled. So we pull the trigger after 1 s of
3529 * futile waiting, but inform the user about this.
3530 */
3531 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3532 "state on VCPU %d after 1 s timeout\n",
3533 __func__, vcpu->vcpu_id);
3534 vmx->soft_vnmi_blocked = 0;
3535 }
3536 }
3537
3538 if (exit_reason < kvm_vmx_max_exit_handlers
3539 && kvm_vmx_exit_handlers[exit_reason])
3540 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3541 else {
3542 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3543 vcpu->run->hw.hardware_exit_reason = exit_reason;
3544 }
3545 return 0;
3546 }
3547
3548 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3549 {
3550 if (irr == -1 || tpr < irr) {
3551 vmcs_write32(TPR_THRESHOLD, 0);
3552 return;
3553 }
3554
3555 vmcs_write32(TPR_THRESHOLD, irr);
3556 }
3557
3558 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3559 {
3560 u32 exit_intr_info;
3561 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3562 bool unblock_nmi;
3563 u8 vector;
3564 int type;
3565 bool idtv_info_valid;
3566
3567 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3568
3569 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3570
3571 /* Handle machine checks before interrupts are enabled */
3572 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3573 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3574 && is_machine_check(exit_intr_info)))
3575 kvm_machine_check();
3576
3577 /* We need to handle NMIs before interrupts are enabled */
3578 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3579 (exit_intr_info & INTR_INFO_VALID_MASK))
3580 asm("int $2");
3581
3582 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3583
3584 if (cpu_has_virtual_nmis()) {
3585 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3586 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3587 /*
3588 * SDM 3: 27.7.1.2 (September 2008)
3589 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3590 * a guest IRET fault.
3591 * SDM 3: 23.2.2 (September 2008)
3592 * Bit 12 is undefined in any of the following cases:
3593 * If the VM exit sets the valid bit in the IDT-vectoring
3594 * information field.
3595 * If the VM exit is due to a double fault.
3596 */
3597 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3598 vector != DF_VECTOR && !idtv_info_valid)
3599 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3600 GUEST_INTR_STATE_NMI);
3601 } else if (unlikely(vmx->soft_vnmi_blocked))
3602 vmx->vnmi_blocked_time +=
3603 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3604
3605 vmx->vcpu.arch.nmi_injected = false;
3606 kvm_clear_exception_queue(&vmx->vcpu);
3607 kvm_clear_interrupt_queue(&vmx->vcpu);
3608
3609 if (!idtv_info_valid)
3610 return;
3611
3612 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3613 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3614
3615 switch (type) {
3616 case INTR_TYPE_NMI_INTR:
3617 vmx->vcpu.arch.nmi_injected = true;
3618 /*
3619 * SDM 3: 27.7.1.2 (September 2008)
3620 * Clear bit "block by NMI" before VM entry if a NMI
3621 * delivery faulted.
3622 */
3623 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3624 GUEST_INTR_STATE_NMI);
3625 break;
3626 case INTR_TYPE_SOFT_EXCEPTION:
3627 vmx->vcpu.arch.event_exit_inst_len =
3628 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3629 /* fall through */
3630 case INTR_TYPE_HARD_EXCEPTION:
3631 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3632 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3633 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3634 } else
3635 kvm_queue_exception(&vmx->vcpu, vector);
3636 break;
3637 case INTR_TYPE_SOFT_INTR:
3638 vmx->vcpu.arch.event_exit_inst_len =
3639 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3640 /* fall through */
3641 case INTR_TYPE_EXT_INTR:
3642 kvm_queue_interrupt(&vmx->vcpu, vector,
3643 type == INTR_TYPE_SOFT_INTR);
3644 break;
3645 default:
3646 break;
3647 }
3648 }
3649
3650 /*
3651 * Failure to inject an interrupt should give us the information
3652 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3653 * when fetching the interrupt redirection bitmap in the real-mode
3654 * tss, this doesn't happen. So we do it ourselves.
3655 */
3656 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3657 {
3658 vmx->rmode.irq.pending = 0;
3659 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3660 return;
3661 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3662 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3663 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3664 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3665 return;
3666 }
3667 vmx->idt_vectoring_info =
3668 VECTORING_INFO_VALID_MASK
3669 | INTR_TYPE_EXT_INTR
3670 | vmx->rmode.irq.vector;
3671 }
3672
3673 #ifdef CONFIG_X86_64
3674 #define R "r"
3675 #define Q "q"
3676 #else
3677 #define R "e"
3678 #define Q "l"
3679 #endif
3680
3681 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3682 {
3683 struct vcpu_vmx *vmx = to_vmx(vcpu);
3684
3685 /* Record the guest's net vcpu time for enforced NMI injections. */
3686 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3687 vmx->entry_time = ktime_get();
3688
3689 /* Don't enter VMX if guest state is invalid, let the exit handler
3690 start emulation until we arrive back to a valid state */
3691 if (vmx->emulation_required && emulate_invalid_guest_state)
3692 return;
3693
3694 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3695 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3696 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3697 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3698
3699 /* When single-stepping over STI and MOV SS, we must clear the
3700 * corresponding interruptibility bits in the guest state. Otherwise
3701 * vmentry fails as it then expects bit 14 (BS) in pending debug
3702 * exceptions being set, but that's not correct for the guest debugging
3703 * case. */
3704 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3705 vmx_set_interrupt_shadow(vcpu, 0);
3706
3707 /*
3708 * Loading guest fpu may have cleared host cr0.ts
3709 */
3710 vmcs_writel(HOST_CR0, read_cr0());
3711
3712 if (vcpu->arch.switch_db_regs)
3713 set_debugreg(vcpu->arch.dr6, 6);
3714
3715 asm(
3716 /* Store host registers */
3717 "push %%"R"dx; push %%"R"bp;"
3718 "push %%"R"cx \n\t"
3719 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3720 "je 1f \n\t"
3721 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3722 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3723 "1: \n\t"
3724 /* Reload cr2 if changed */
3725 "mov %c[cr2](%0), %%"R"ax \n\t"
3726 "mov %%cr2, %%"R"dx \n\t"
3727 "cmp %%"R"ax, %%"R"dx \n\t"
3728 "je 2f \n\t"
3729 "mov %%"R"ax, %%cr2 \n\t"
3730 "2: \n\t"
3731 /* Check if vmlaunch of vmresume is needed */
3732 "cmpl $0, %c[launched](%0) \n\t"
3733 /* Load guest registers. Don't clobber flags. */
3734 "mov %c[rax](%0), %%"R"ax \n\t"
3735 "mov %c[rbx](%0), %%"R"bx \n\t"
3736 "mov %c[rdx](%0), %%"R"dx \n\t"
3737 "mov %c[rsi](%0), %%"R"si \n\t"
3738 "mov %c[rdi](%0), %%"R"di \n\t"
3739 "mov %c[rbp](%0), %%"R"bp \n\t"
3740 #ifdef CONFIG_X86_64
3741 "mov %c[r8](%0), %%r8 \n\t"
3742 "mov %c[r9](%0), %%r9 \n\t"
3743 "mov %c[r10](%0), %%r10 \n\t"
3744 "mov %c[r11](%0), %%r11 \n\t"
3745 "mov %c[r12](%0), %%r12 \n\t"
3746 "mov %c[r13](%0), %%r13 \n\t"
3747 "mov %c[r14](%0), %%r14 \n\t"
3748 "mov %c[r15](%0), %%r15 \n\t"
3749 #endif
3750 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3751
3752 /* Enter guest mode */
3753 "jne .Llaunched \n\t"
3754 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3755 "jmp .Lkvm_vmx_return \n\t"
3756 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3757 ".Lkvm_vmx_return: "
3758 /* Save guest registers, load host registers, keep flags */
3759 "xchg %0, (%%"R"sp) \n\t"
3760 "mov %%"R"ax, %c[rax](%0) \n\t"
3761 "mov %%"R"bx, %c[rbx](%0) \n\t"
3762 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3763 "mov %%"R"dx, %c[rdx](%0) \n\t"
3764 "mov %%"R"si, %c[rsi](%0) \n\t"
3765 "mov %%"R"di, %c[rdi](%0) \n\t"
3766 "mov %%"R"bp, %c[rbp](%0) \n\t"
3767 #ifdef CONFIG_X86_64
3768 "mov %%r8, %c[r8](%0) \n\t"
3769 "mov %%r9, %c[r9](%0) \n\t"
3770 "mov %%r10, %c[r10](%0) \n\t"
3771 "mov %%r11, %c[r11](%0) \n\t"
3772 "mov %%r12, %c[r12](%0) \n\t"
3773 "mov %%r13, %c[r13](%0) \n\t"
3774 "mov %%r14, %c[r14](%0) \n\t"
3775 "mov %%r15, %c[r15](%0) \n\t"
3776 #endif
3777 "mov %%cr2, %%"R"ax \n\t"
3778 "mov %%"R"ax, %c[cr2](%0) \n\t"
3779
3780 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3781 "setbe %c[fail](%0) \n\t"
3782 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3783 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3784 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3785 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3786 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3787 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3788 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3789 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3790 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3791 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3792 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3793 #ifdef CONFIG_X86_64
3794 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3795 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3796 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3797 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3798 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3799 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3800 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3801 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3802 #endif
3803 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3804 : "cc", "memory"
3805 , R"bx", R"di", R"si"
3806 #ifdef CONFIG_X86_64
3807 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3808 #endif
3809 );
3810
3811 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3812 | (1 << VCPU_EXREG_PDPTR));
3813 vcpu->arch.regs_dirty = 0;
3814
3815 if (vcpu->arch.switch_db_regs)
3816 get_debugreg(vcpu->arch.dr6, 6);
3817
3818 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3819 if (vmx->rmode.irq.pending)
3820 fixup_rmode_irq(vmx);
3821
3822 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3823 vmx->launched = 1;
3824
3825 vmx_complete_interrupts(vmx);
3826 }
3827
3828 #undef R
3829 #undef Q
3830
3831 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3832 {
3833 struct vcpu_vmx *vmx = to_vmx(vcpu);
3834
3835 if (vmx->vmcs) {
3836 vcpu_clear(vmx);
3837 free_vmcs(vmx->vmcs);
3838 vmx->vmcs = NULL;
3839 }
3840 }
3841
3842 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3843 {
3844 struct vcpu_vmx *vmx = to_vmx(vcpu);
3845
3846 spin_lock(&vmx_vpid_lock);
3847 if (vmx->vpid != 0)
3848 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3849 spin_unlock(&vmx_vpid_lock);
3850 vmx_free_vmcs(vcpu);
3851 kfree(vmx->guest_msrs);
3852 kvm_vcpu_uninit(vcpu);
3853 kmem_cache_free(kvm_vcpu_cache, vmx);
3854 }
3855
3856 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3857 {
3858 int err;
3859 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3860 int cpu;
3861
3862 if (!vmx)
3863 return ERR_PTR(-ENOMEM);
3864
3865 allocate_vpid(vmx);
3866
3867 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3868 if (err)
3869 goto free_vcpu;
3870
3871 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3872 if (!vmx->guest_msrs) {
3873 err = -ENOMEM;
3874 goto uninit_vcpu;
3875 }
3876
3877 vmx->vmcs = alloc_vmcs();
3878 if (!vmx->vmcs)
3879 goto free_msrs;
3880
3881 vmcs_clear(vmx->vmcs);
3882
3883 cpu = get_cpu();
3884 vmx_vcpu_load(&vmx->vcpu, cpu);
3885 err = vmx_vcpu_setup(vmx);
3886 vmx_vcpu_put(&vmx->vcpu);
3887 put_cpu();
3888 if (err)
3889 goto free_vmcs;
3890 if (vm_need_virtualize_apic_accesses(kvm))
3891 if (alloc_apic_access_page(kvm) != 0)
3892 goto free_vmcs;
3893
3894 if (enable_ept) {
3895 if (!kvm->arch.ept_identity_map_addr)
3896 kvm->arch.ept_identity_map_addr =
3897 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3898 if (alloc_identity_pagetable(kvm) != 0)
3899 goto free_vmcs;
3900 }
3901
3902 return &vmx->vcpu;
3903
3904 free_vmcs:
3905 free_vmcs(vmx->vmcs);
3906 free_msrs:
3907 kfree(vmx->guest_msrs);
3908 uninit_vcpu:
3909 kvm_vcpu_uninit(&vmx->vcpu);
3910 free_vcpu:
3911 kmem_cache_free(kvm_vcpu_cache, vmx);
3912 return ERR_PTR(err);
3913 }
3914
3915 static void __init vmx_check_processor_compat(void *rtn)
3916 {
3917 struct vmcs_config vmcs_conf;
3918
3919 *(int *)rtn = 0;
3920 if (setup_vmcs_config(&vmcs_conf) < 0)
3921 *(int *)rtn = -EIO;
3922 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3923 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3924 smp_processor_id());
3925 *(int *)rtn = -EIO;
3926 }
3927 }
3928
3929 static int get_ept_level(void)
3930 {
3931 return VMX_EPT_DEFAULT_GAW + 1;
3932 }
3933
3934 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3935 {
3936 u64 ret;
3937
3938 /* For VT-d and EPT combination
3939 * 1. MMIO: always map as UC
3940 * 2. EPT with VT-d:
3941 * a. VT-d without snooping control feature: can't guarantee the
3942 * result, try to trust guest.
3943 * b. VT-d with snooping control feature: snooping control feature of
3944 * VT-d engine can guarantee the cache correctness. Just set it
3945 * to WB to keep consistent with host. So the same as item 3.
3946 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3947 * consistent with host MTRR
3948 */
3949 if (is_mmio)
3950 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3951 else if (vcpu->kvm->arch.iommu_domain &&
3952 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3953 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3954 VMX_EPT_MT_EPTE_SHIFT;
3955 else
3956 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3957 | VMX_EPT_IGMT_BIT;
3958
3959 return ret;
3960 }
3961
3962 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3963 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3964 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3965 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3966 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3967 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3968 { EXIT_REASON_CR_ACCESS, "cr_access" },
3969 { EXIT_REASON_DR_ACCESS, "dr_access" },
3970 { EXIT_REASON_CPUID, "cpuid" },
3971 { EXIT_REASON_MSR_READ, "rdmsr" },
3972 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3973 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3974 { EXIT_REASON_HLT, "halt" },
3975 { EXIT_REASON_INVLPG, "invlpg" },
3976 { EXIT_REASON_VMCALL, "hypercall" },
3977 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3978 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3979 { EXIT_REASON_WBINVD, "wbinvd" },
3980 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3981 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3982 { -1, NULL }
3983 };
3984
3985 static bool vmx_gb_page_enable(void)
3986 {
3987 return false;
3988 }
3989
3990 static struct kvm_x86_ops vmx_x86_ops = {
3991 .cpu_has_kvm_support = cpu_has_kvm_support,
3992 .disabled_by_bios = vmx_disabled_by_bios,
3993 .hardware_setup = hardware_setup,
3994 .hardware_unsetup = hardware_unsetup,
3995 .check_processor_compatibility = vmx_check_processor_compat,
3996 .hardware_enable = hardware_enable,
3997 .hardware_disable = hardware_disable,
3998 .cpu_has_accelerated_tpr = report_flexpriority,
3999
4000 .vcpu_create = vmx_create_vcpu,
4001 .vcpu_free = vmx_free_vcpu,
4002 .vcpu_reset = vmx_vcpu_reset,
4003
4004 .prepare_guest_switch = vmx_save_host_state,
4005 .vcpu_load = vmx_vcpu_load,
4006 .vcpu_put = vmx_vcpu_put,
4007
4008 .set_guest_debug = set_guest_debug,
4009 .get_msr = vmx_get_msr,
4010 .set_msr = vmx_set_msr,
4011 .get_segment_base = vmx_get_segment_base,
4012 .get_segment = vmx_get_segment,
4013 .set_segment = vmx_set_segment,
4014 .get_cpl = vmx_get_cpl,
4015 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4016 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4017 .set_cr0 = vmx_set_cr0,
4018 .set_cr3 = vmx_set_cr3,
4019 .set_cr4 = vmx_set_cr4,
4020 .set_efer = vmx_set_efer,
4021 .get_idt = vmx_get_idt,
4022 .set_idt = vmx_set_idt,
4023 .get_gdt = vmx_get_gdt,
4024 .set_gdt = vmx_set_gdt,
4025 .cache_reg = vmx_cache_reg,
4026 .get_rflags = vmx_get_rflags,
4027 .set_rflags = vmx_set_rflags,
4028
4029 .tlb_flush = vmx_flush_tlb,
4030
4031 .run = vmx_vcpu_run,
4032 .handle_exit = vmx_handle_exit,
4033 .skip_emulated_instruction = skip_emulated_instruction,
4034 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4035 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4036 .patch_hypercall = vmx_patch_hypercall,
4037 .set_irq = vmx_inject_irq,
4038 .set_nmi = vmx_inject_nmi,
4039 .queue_exception = vmx_queue_exception,
4040 .interrupt_allowed = vmx_interrupt_allowed,
4041 .nmi_allowed = vmx_nmi_allowed,
4042 .get_nmi_mask = vmx_get_nmi_mask,
4043 .set_nmi_mask = vmx_set_nmi_mask,
4044 .enable_nmi_window = enable_nmi_window,
4045 .enable_irq_window = enable_irq_window,
4046 .update_cr8_intercept = update_cr8_intercept,
4047
4048 .set_tss_addr = vmx_set_tss_addr,
4049 .get_tdp_level = get_ept_level,
4050 .get_mt_mask = vmx_get_mt_mask,
4051
4052 .exit_reasons_str = vmx_exit_reasons_str,
4053 .gb_page_enable = vmx_gb_page_enable,
4054 };
4055
4056 static int __init vmx_init(void)
4057 {
4058 int r, i;
4059
4060 rdmsrl_safe(MSR_EFER, &host_efer);
4061
4062 for (i = 0; i < NR_VMX_MSR; ++i)
4063 kvm_define_shared_msr(i, vmx_msr_index[i]);
4064
4065 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4066 if (!vmx_io_bitmap_a)
4067 return -ENOMEM;
4068
4069 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4070 if (!vmx_io_bitmap_b) {
4071 r = -ENOMEM;
4072 goto out;
4073 }
4074
4075 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4076 if (!vmx_msr_bitmap_legacy) {
4077 r = -ENOMEM;
4078 goto out1;
4079 }
4080
4081 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4082 if (!vmx_msr_bitmap_longmode) {
4083 r = -ENOMEM;
4084 goto out2;
4085 }
4086
4087 /*
4088 * Allow direct access to the PC debug port (it is often used for I/O
4089 * delays, but the vmexits simply slow things down).
4090 */
4091 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4092 clear_bit(0x80, vmx_io_bitmap_a);
4093
4094 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4095
4096 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4097 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4098
4099 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4100
4101 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4102 if (r)
4103 goto out3;
4104
4105 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4106 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4107 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4108 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4109 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4110 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4111
4112 if (enable_ept) {
4113 bypass_guest_pf = 0;
4114 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4115 VMX_EPT_WRITABLE_MASK);
4116 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4117 VMX_EPT_EXECUTABLE_MASK);
4118 kvm_enable_tdp();
4119 } else
4120 kvm_disable_tdp();
4121
4122 if (bypass_guest_pf)
4123 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4124
4125 return 0;
4126
4127 out3:
4128 free_page((unsigned long)vmx_msr_bitmap_longmode);
4129 out2:
4130 free_page((unsigned long)vmx_msr_bitmap_legacy);
4131 out1:
4132 free_page((unsigned long)vmx_io_bitmap_b);
4133 out:
4134 free_page((unsigned long)vmx_io_bitmap_a);
4135 return r;
4136 }
4137
4138 static void __exit vmx_exit(void)
4139 {
4140 free_page((unsigned long)vmx_msr_bitmap_legacy);
4141 free_page((unsigned long)vmx_msr_bitmap_longmode);
4142 free_page((unsigned long)vmx_io_bitmap_b);
4143 free_page((unsigned long)vmx_io_bitmap_a);
4144
4145 kvm_exit();
4146 }
4147
4148 module_init(vmx_init)
4149 module_exit(vmx_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree