drivers/gpu/drm/nouveau/nouveau_channel.c

   1 /*
   2  * Copyright 2005-2006 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drv.h"
  28 #include "nouveau_drm.h"
  29 #include "nouveau_dma.h"
  30 #include "nouveau_ramht.h"
  31
  32 static int
  33 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
  34 {
  35         u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
  36         struct drm_device *dev = chan->dev;
  37         struct drm_nouveau_private *dev_priv = dev->dev_private;
  38         int ret;
  39
  40         /* allocate buffer object */
  41         ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, &chan->pushbuf_bo);
  42         if (ret)
  43                 goto out;
  44
  45         ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
  46         if (ret)
  47                 goto out;
  48
  49         ret = nouveau_bo_map(chan->pushbuf_bo);
  50         if (ret)
  51                 goto out;
  52
  53         /* create DMA object covering the entire memtype where the push
  54          * buffer resides, userspace can submit its own push buffers from
  55          * anywhere within the same memtype.
  56          */
  57         chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
  58         if (dev_priv->card_type >= NV_50) {
  59                 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
  60                                          &chan->pushbuf_vma);
  61                 if (ret)
  62                         goto out;
  63
  64                 if (dev_priv->card_type < NV_C0) {
  65                         ret = nouveau_gpuobj_dma_new(chan,
  66                                                      NV_CLASS_DMA_IN_MEMORY, 0,
  67                                                      (1ULL << 40),
  68                                                      NV_MEM_ACCESS_RO,
  69                                                      NV_MEM_TARGET_VM,
  70                                                      &chan->pushbuf);
  71                 }
  72                 chan->pushbuf_base = chan->pushbuf_vma.offset;
  73         } else
  74         if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
  75                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  76                                              dev_priv->gart_info.aper_size,
  77                                              NV_MEM_ACCESS_RO,
  78                                              NV_MEM_TARGET_GART,
  79                                              &chan->pushbuf);
  80         } else
  81         if (dev_priv->card_type != NV_04) {
  82                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  83                                              dev_priv->fb_available_size,
  84                                              NV_MEM_ACCESS_RO,
  85                                              NV_MEM_TARGET_VRAM,
  86                                              &chan->pushbuf);
  87         } else {
  88                 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
  89                  * exact reason for existing :)  PCI access to cmdbuf in
  90                  * VRAM.
  91                  */
  92                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  93                                              pci_resource_start(dev->pdev, 1),
  94                                              dev_priv->fb_available_size,
  95                                              NV_MEM_ACCESS_RO,
  96                                              NV_MEM_TARGET_PCI,
  97                                              &chan->pushbuf);
  98         }
  99
 100 out:
 101         if (ret) {
 102                 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
 103                 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
 104                 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
 105                 if (chan->pushbuf_bo) {
 106                         nouveau_bo_unmap(chan->pushbuf_bo);
 107                         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
 108                 }
 109         }
 110
 111         return 0;
 112 }
 113
 114 /* allocates and initializes a fifo for user space consumption */
 115 int
 116 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
 117                       struct drm_file *file_priv,
 118                       uint32_t vram_handle, uint32_t gart_handle)
 119 {
 120         struct drm_nouveau_private *dev_priv = dev->dev_private;
 121         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 122         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 123         struct nouveau_channel *chan;
 124         unsigned long flags;
 125         int ret;
 126
 127         /* allocate and lock channel structure */
 128         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
 129         if (!chan)
 130                 return -ENOMEM;
 131         chan->dev = dev;
 132         chan->file_priv = file_priv;
 133         chan->vram_handle = vram_handle;
 134         chan->gart_handle = gart_handle;
 135
 136         kref_init(&chan->ref);
 137         atomic_set(&chan->users, 1);
 138         mutex_init(&chan->mutex);
 139         mutex_lock(&chan->mutex);
 140
 141         /* allocate hw channel id */
 142         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 143         for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
 144                 if (!dev_priv->channels.ptr[chan->id]) {
 145                         nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
 146                         break;
 147                 }
 148         }
 149         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 150
 151         if (chan->id == pfifo->channels) {
 152                 mutex_unlock(&chan->mutex);
 153                 kfree(chan);
 154                 return -ENODEV;
 155         }
 156
 157         NV_DEBUG(dev, "initialising channel %d\n", chan->id);
 158         INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
 159         INIT_LIST_HEAD(&chan->nvsw.flip);
 160         INIT_LIST_HEAD(&chan->fence.pending);
 161         spin_lock_init(&chan->fence.lock);
 162
 163         /* setup channel's memory and vm */
 164         ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
 165         if (ret) {
 166                 NV_ERROR(dev, "gpuobj %d\n", ret);
 167                 nouveau_channel_put(&chan);
 168                 return ret;
 169         }
 170
 171         /* Allocate space for per-channel fixed notifier memory */
 172         ret = nouveau_notifier_init_channel(chan);
 173         if (ret) {
 174                 NV_ERROR(dev, "ntfy %d\n", ret);
 175                 nouveau_channel_put(&chan);
 176                 return ret;
 177         }
 178
 179         /* Allocate DMA push buffer */
 180         ret = nouveau_channel_pushbuf_init(chan);
 181         if (ret) {
 182                 NV_ERROR(dev, "pushbuf %d\n", ret);
 183                 nouveau_channel_put(&chan);
 184                 return ret;
 185         }
 186
 187         nouveau_dma_pre_init(chan);
 188         chan->user_put = 0x40;
 189         chan->user_get = 0x44;
 190
 191         /* disable the fifo caches */
 192         pfifo->reassign(dev, false);
 193
 194         /* Construct initial RAMFC for new channel */
 195         ret = pfifo->create_context(chan);
 196         if (ret) {
 197                 nouveau_channel_put(&chan);
 198                 return ret;
 199         }
 200
 201         pfifo->reassign(dev, true);
 202
 203         ret = nouveau_dma_init(chan);
 204         if (!ret)
 205                 ret = nouveau_fence_channel_init(chan);
 206         if (ret) {
 207                 nouveau_channel_put(&chan);
 208                 return ret;
 209         }
 210
 211         nouveau_debugfs_channel_init(chan);
 212
 213         NV_DEBUG(dev, "channel %d initialised\n", chan->id);
 214         if (fpriv) {
 215                 spin_lock(&fpriv->lock);
 216                 list_add(&chan->list, &fpriv->channels);
 217                 spin_unlock(&fpriv->lock);
 218         }
 219         *chan_ret = chan;
 220         return 0;
 221 }
 222
 223 struct nouveau_channel *
 224 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
 225 {
 226         struct nouveau_channel *chan = NULL;
 227
 228         if (likely(ref && atomic_inc_not_zero(&ref->users)))
 229                 nouveau_channel_ref(ref, &chan);
 230
 231         return chan;
 232 }
 233
 234 struct nouveau_channel *
 235 nouveau_channel_get(struct drm_file *file_priv, int id)
 236 {
 237         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 238         struct nouveau_channel *chan;
 239
 240         spin_lock(&fpriv->lock);
 241         list_for_each_entry(chan, &fpriv->channels, list) {
 242                 if (chan->id == id) {
 243                         chan = nouveau_channel_get_unlocked(chan);
 244                         spin_unlock(&fpriv->lock);
 245                         mutex_lock(&chan->mutex);
 246                         return chan;
 247                 }
 248         }
 249         spin_unlock(&fpriv->lock);
 250
 251         return ERR_PTR(-EINVAL);
 252 }
 253
 254 void
 255 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
 256 {
 257         struct nouveau_channel *chan = *pchan;
 258         struct drm_device *dev = chan->dev;
 259         struct drm_nouveau_private *dev_priv = dev->dev_private;
 260         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 261         unsigned long flags;
 262         int i;
 263
 264         /* decrement the refcount, and we're done if there's still refs */
 265         if (likely(!atomic_dec_and_test(&chan->users))) {
 266                 nouveau_channel_ref(NULL, pchan);
 267                 return;
 268         }
 269
 270         /* no one wants the channel anymore */
 271         NV_DEBUG(dev, "freeing channel %d\n", chan->id);
 272         nouveau_debugfs_channel_fini(chan);
 273
 274         /* give it chance to idle */
 275         nouveau_channel_idle(chan);
 276
 277         /* ensure all outstanding fences are signaled.  they should be if the
 278          * above attempts at idling were OK, but if we failed this'll tell TTM
 279          * we're done with the buffers.
 280          */
 281         nouveau_fence_channel_fini(chan);
 282
 283         /* boot it off the hardware */
 284         pfifo->reassign(dev, false);
 285
 286         /* destroy the engine specific contexts */
 287         pfifo->destroy_context(chan);
 288         for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
 289                 if (chan->engctx[i])
 290                         dev_priv->eng[i]->context_del(chan, i);
 291         }
 292
 293         pfifo->reassign(dev, true);
 294
 295         /* aside from its resources, the channel should now be dead,
 296          * remove it from the channel list
 297          */
 298         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 299         nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
 300         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 301
 302         /* destroy any resources the channel owned */
 303         nouveau_gpuobj_ref(NULL, &chan->pushbuf);
 304         if (chan->pushbuf_bo) {
 305                 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
 306                 nouveau_bo_unmap(chan->pushbuf_bo);
 307                 nouveau_bo_unpin(chan->pushbuf_bo);
 308                 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
 309         }
 310         nouveau_ramht_ref(NULL, &chan->ramht, chan);
 311         nouveau_notifier_takedown_channel(chan);
 312         nouveau_gpuobj_channel_takedown(chan);
 313
 314         nouveau_channel_ref(NULL, pchan);
 315 }
 316
 317 void
 318 nouveau_channel_put(struct nouveau_channel **pchan)
 319 {
 320         mutex_unlock(&(*pchan)->mutex);
 321         nouveau_channel_put_unlocked(pchan);
 322 }
 323
 324 static void
 325 nouveau_channel_del(struct kref *ref)
 326 {
 327         struct nouveau_channel *chan =
 328                 container_of(ref, struct nouveau_channel, ref);
 329
 330         kfree(chan);
 331 }
 332
 333 void
 334 nouveau_channel_ref(struct nouveau_channel *chan,
 335                     struct nouveau_channel **pchan)
 336 {
 337         if (chan)
 338                 kref_get(&chan->ref);
 339
 340         if (*pchan)
 341                 kref_put(&(*pchan)->ref, nouveau_channel_del);
 342
 343         *pchan = chan;
 344 }
 345
 346 void
 347 nouveau_channel_idle(struct nouveau_channel *chan)
 348 {
 349         struct drm_device *dev = chan->dev;
 350         struct nouveau_fence *fence = NULL;
 351         int ret;
 352
 353         nouveau_fence_update(chan);
 354
 355         if (chan->fence.sequence != chan->fence.sequence_ack) {
 356                 ret = nouveau_fence_new(chan, &fence, true);
 357                 if (!ret) {
 358                         ret = nouveau_fence_wait(fence, false, false);
 359                         nouveau_fence_unref(&fence);
 360                 }
 361
 362                 if (ret)
 363                         NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
 364         }
 365 }
 366
 367 /* cleans up all the fifos from file_priv */
 368 void
 369 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
 370 {
 371         struct drm_nouveau_private *dev_priv = dev->dev_private;
 372         struct nouveau_engine *engine = &dev_priv->engine;
 373         struct nouveau_channel *chan;
 374         int i;
 375
 376         NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
 377         for (i = 0; i < engine->fifo.channels; i++) {
 378                 chan = nouveau_channel_get(file_priv, i);
 379                 if (IS_ERR(chan))
 380                         continue;
 381
 382                 list_del(&chan->list);
 383                 atomic_dec(&chan->users);
 384                 nouveau_channel_put(&chan);
 385         }
 386 }
 387
 388
 389 /***********************************
 390  * ioctls wrapping the functions
 391  ***********************************/
 392
 393 static int
 394 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
 395                          struct drm_file *file_priv)
 396 {
 397         struct drm_nouveau_private *dev_priv = dev->dev_private;
 398         struct drm_nouveau_channel_alloc *init = data;
 399         struct nouveau_channel *chan;
 400         int ret;
 401
 402         if (!dev_priv->eng[NVOBJ_ENGINE_GR])
 403                 return -ENODEV;
 404
 405         if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
 406                 return -EINVAL;
 407
 408         ret = nouveau_channel_alloc(dev, &chan, file_priv,
 409                                     init->fb_ctxdma_handle,
 410                                     init->tt_ctxdma_handle);
 411         if (ret)
 412                 return ret;
 413         init->channel  = chan->id;
 414
 415         if (chan->dma.ib_max)
 416                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
 417                                         NOUVEAU_GEM_DOMAIN_GART;
 418         else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
 419                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
 420         else
 421                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
 422
 423         if (dev_priv->card_type < NV_C0) {
 424                 init->subchan[0].handle = NvM2MF;
 425                 if (dev_priv->card_type < NV_50)
 426                         init->subchan[0].grclass = 0x0039;
 427                 else
 428                         init->subchan[0].grclass = 0x5039;
 429                 init->subchan[1].handle = NvSw;
 430                 init->subchan[1].grclass = NV_SW;
 431                 init->nr_subchan = 2;
 432         } else {
 433                 init->subchan[0].handle  = 0x9039;
 434                 init->subchan[0].grclass = 0x9039;
 435                 init->nr_subchan = 1;
 436         }
 437
 438         /* Named memory object area */
 439         ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
 440                                     &init->notifier_handle);
 441
 442         if (ret == 0)
 443                 atomic_inc(&chan->users); /* userspace reference */
 444         nouveau_channel_put(&chan);
 445         return ret;
 446 }
 447
 448 static int
 449 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
 450                         struct drm_file *file_priv)
 451 {
 452         struct drm_nouveau_channel_free *req = data;
 453         struct nouveau_channel *chan;
 454
 455         chan = nouveau_channel_get(file_priv, req->channel);
 456         if (IS_ERR(chan))
 457                 return PTR_ERR(chan);
 458
 459         list_del(&chan->list);
 460         atomic_dec(&chan->users);
 461         nouveau_channel_put(&chan);
 462         return 0;
 463 }
 464
 465 /***********************************
 466  * finally, the ioctl table
 467  ***********************************/
 468
 469 struct drm_ioctl_desc nouveau_ioctls[] = {
 470         DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
 471         DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 472         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
 473         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
 474         DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
 475         DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
 476         DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
 477         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
 478         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
 479         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
 480         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
 481         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
 482 };
 483
 484 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);