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davinci: DA850/OMAP-L138: add frequency scaling support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / da850.c
blob49dcc71168c7b97491cb57c47ed29eb8575a2c07
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/cpufreq.h>
19
20 #include <asm/mach/map.h>
21
22 #include <mach/clock.h>
23 #include <mach/psc.h>
24 #include <mach/mux.h>
25 #include <mach/irqs.h>
26 #include <mach/cputype.h>
27 #include <mach/common.h>
28 #include <mach/time.h>
29 #include <mach/da8xx.h>
30 #include <mach/cpufreq.h>
31
32 #include "clock.h"
33 #include "mux.h"
34
35 /* SoC specific clock flags */
36 #define DA850_CLK_ASYNC3 BIT(16)
37
38 #define DA850_PLL1_BASE 0x01e1a000
39 #define DA850_TIMER64P2_BASE 0x01f0c000
40 #define DA850_TIMER64P3_BASE 0x01f0d000
41
42 #define DA850_REF_FREQ 24000000
43
44 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
45 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
46
47 static int da850_set_armrate(struct clk *clk, unsigned long rate);
48 static int da850_round_armrate(struct clk *clk, unsigned long rate);
49 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
50
51 static struct pll_data pll0_data = {
52 .num = 1,
53 .phys_base = DA8XX_PLL0_BASE,
54 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
55 };
56
57 static struct clk ref_clk = {
58 .name = "ref_clk",
59 .rate = DA850_REF_FREQ,
60 };
61
62 static struct clk pll0_clk = {
63 .name = "pll0",
64 .parent = &ref_clk,
65 .pll_data = &pll0_data,
66 .flags = CLK_PLL,
67 .set_rate = da850_set_pll0rate,
68 };
69
70 static struct clk pll0_aux_clk = {
71 .name = "pll0_aux_clk",
72 .parent = &pll0_clk,
73 .flags = CLK_PLL | PRE_PLL,
74 };
75
76 static struct clk pll0_sysclk2 = {
77 .name = "pll0_sysclk2",
78 .parent = &pll0_clk,
79 .flags = CLK_PLL,
80 .div_reg = PLLDIV2,
81 };
82
83 static struct clk pll0_sysclk3 = {
84 .name = "pll0_sysclk3",
85 .parent = &pll0_clk,
86 .flags = CLK_PLL,
87 .div_reg = PLLDIV3,
88 };
89
90 static struct clk pll0_sysclk4 = {
91 .name = "pll0_sysclk4",
92 .parent = &pll0_clk,
93 .flags = CLK_PLL,
94 .div_reg = PLLDIV4,
95 };
96
97 static struct clk pll0_sysclk5 = {
98 .name = "pll0_sysclk5",
99 .parent = &pll0_clk,
100 .flags = CLK_PLL,
101 .div_reg = PLLDIV5,
102 };
103
104 static struct clk pll0_sysclk6 = {
105 .name = "pll0_sysclk6",
106 .parent = &pll0_clk,
107 .flags = CLK_PLL,
108 .div_reg = PLLDIV6,
109 };
110
111 static struct clk pll0_sysclk7 = {
112 .name = "pll0_sysclk7",
113 .parent = &pll0_clk,
114 .flags = CLK_PLL,
115 .div_reg = PLLDIV7,
116 };
117
118 static struct pll_data pll1_data = {
119 .num = 2,
120 .phys_base = DA850_PLL1_BASE,
121 .flags = PLL_HAS_POSTDIV,
122 };
123
124 static struct clk pll1_clk = {
125 .name = "pll1",
126 .parent = &ref_clk,
127 .pll_data = &pll1_data,
128 .flags = CLK_PLL,
129 };
130
131 static struct clk pll1_aux_clk = {
132 .name = "pll1_aux_clk",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL | PRE_PLL,
135 };
136
137 static struct clk pll1_sysclk2 = {
138 .name = "pll1_sysclk2",
139 .parent = &pll1_clk,
140 .flags = CLK_PLL,
141 .div_reg = PLLDIV2,
142 };
143
144 static struct clk pll1_sysclk3 = {
145 .name = "pll1_sysclk3",
146 .parent = &pll1_clk,
147 .flags = CLK_PLL,
148 .div_reg = PLLDIV3,
149 };
150
151 static struct clk pll1_sysclk4 = {
152 .name = "pll1_sysclk4",
153 .parent = &pll1_clk,
154 .flags = CLK_PLL,
155 .div_reg = PLLDIV4,
156 };
157
158 static struct clk pll1_sysclk5 = {
159 .name = "pll1_sysclk5",
160 .parent = &pll1_clk,
161 .flags = CLK_PLL,
162 .div_reg = PLLDIV5,
163 };
164
165 static struct clk pll1_sysclk6 = {
166 .name = "pll0_sysclk6",
167 .parent = &pll0_clk,
168 .flags = CLK_PLL,
169 .div_reg = PLLDIV6,
170 };
171
172 static struct clk pll1_sysclk7 = {
173 .name = "pll1_sysclk7",
174 .parent = &pll1_clk,
175 .flags = CLK_PLL,
176 .div_reg = PLLDIV7,
177 };
178
179 static struct clk i2c0_clk = {
180 .name = "i2c0",
181 .parent = &pll0_aux_clk,
182 };
183
184 static struct clk timerp64_0_clk = {
185 .name = "timer0",
186 .parent = &pll0_aux_clk,
187 };
188
189 static struct clk timerp64_1_clk = {
190 .name = "timer1",
191 .parent = &pll0_aux_clk,
192 };
193
194 static struct clk arm_rom_clk = {
195 .name = "arm_rom",
196 .parent = &pll0_sysclk2,
197 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
198 .flags = ALWAYS_ENABLED,
199 };
200
201 static struct clk tpcc0_clk = {
202 .name = "tpcc0",
203 .parent = &pll0_sysclk2,
204 .lpsc = DA8XX_LPSC0_TPCC,
205 .flags = ALWAYS_ENABLED | CLK_PSC,
206 };
207
208 static struct clk tptc0_clk = {
209 .name = "tptc0",
210 .parent = &pll0_sysclk2,
211 .lpsc = DA8XX_LPSC0_TPTC0,
212 .flags = ALWAYS_ENABLED,
213 };
214
215 static struct clk tptc1_clk = {
216 .name = "tptc1",
217 .parent = &pll0_sysclk2,
218 .lpsc = DA8XX_LPSC0_TPTC1,
219 .flags = ALWAYS_ENABLED,
220 };
221
222 static struct clk tpcc1_clk = {
223 .name = "tpcc1",
224 .parent = &pll0_sysclk2,
225 .lpsc = DA850_LPSC1_TPCC1,
226 .flags = CLK_PSC | ALWAYS_ENABLED,
227 .psc_ctlr = 1,
228 };
229
230 static struct clk tptc2_clk = {
231 .name = "tptc2",
232 .parent = &pll0_sysclk2,
233 .lpsc = DA850_LPSC1_TPTC2,
234 .flags = ALWAYS_ENABLED,
235 .psc_ctlr = 1,
236 };
237
238 static struct clk uart0_clk = {
239 .name = "uart0",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC0_UART0,
242 };
243
244 static struct clk uart1_clk = {
245 .name = "uart1",
246 .parent = &pll0_sysclk2,
247 .lpsc = DA8XX_LPSC1_UART1,
248 .flags = DA850_CLK_ASYNC3,
249 .psc_ctlr = 1,
250 };
251
252 static struct clk uart2_clk = {
253 .name = "uart2",
254 .parent = &pll0_sysclk2,
255 .lpsc = DA8XX_LPSC1_UART2,
256 .flags = DA850_CLK_ASYNC3,
257 .psc_ctlr = 1,
258 };
259
260 static struct clk aintc_clk = {
261 .name = "aintc",
262 .parent = &pll0_sysclk4,
263 .lpsc = DA8XX_LPSC0_AINTC,
264 .flags = ALWAYS_ENABLED,
265 };
266
267 static struct clk gpio_clk = {
268 .name = "gpio",
269 .parent = &pll0_sysclk4,
270 .lpsc = DA8XX_LPSC1_GPIO,
271 .psc_ctlr = 1,
272 };
273
274 static struct clk i2c1_clk = {
275 .name = "i2c1",
276 .parent = &pll0_sysclk4,
277 .lpsc = DA8XX_LPSC1_I2C,
278 .psc_ctlr = 1,
279 };
280
281 static struct clk emif3_clk = {
282 .name = "emif3",
283 .parent = &pll0_sysclk5,
284 .lpsc = DA8XX_LPSC1_EMIF3C,
285 .flags = ALWAYS_ENABLED,
286 .psc_ctlr = 1,
287 };
288
289 static struct clk arm_clk = {
290 .name = "arm",
291 .parent = &pll0_sysclk6,
292 .lpsc = DA8XX_LPSC0_ARM,
293 .flags = ALWAYS_ENABLED,
294 .set_rate = da850_set_armrate,
295 .round_rate = da850_round_armrate,
296 };
297
298 static struct clk rmii_clk = {
299 .name = "rmii",
300 .parent = &pll0_sysclk7,
301 };
302
303 static struct clk emac_clk = {
304 .name = "emac",
305 .parent = &pll0_sysclk4,
306 .lpsc = DA8XX_LPSC1_CPGMAC,
307 .psc_ctlr = 1,
308 };
309
310 static struct clk mcasp_clk = {
311 .name = "mcasp",
312 .parent = &pll0_sysclk2,
313 .lpsc = DA8XX_LPSC1_McASP0,
314 .psc_ctlr = 1,
315 };
316
317 static struct clk lcdc_clk = {
318 .name = "lcdc",
319 .parent = &pll0_sysclk2,
320 .lpsc = DA8XX_LPSC1_LCDC,
321 .psc_ctlr = 1,
322 };
323
324 static struct clk mmcsd_clk = {
325 .name = "mmcsd",
326 .parent = &pll0_sysclk2,
327 .lpsc = DA8XX_LPSC0_MMC_SD,
328 };
329
330 static struct clk aemif_clk = {
331 .name = "aemif",
332 .parent = &pll0_sysclk3,
333 .lpsc = DA8XX_LPSC0_EMIF25,
334 .flags = ALWAYS_ENABLED,
335 };
336
337 static struct davinci_clk da850_clks[] = {
338 CLK(NULL, "ref", &ref_clk),
339 CLK(NULL, "pll0", &pll0_clk),
340 CLK(NULL, "pll0_aux", &pll0_aux_clk),
341 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
342 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
343 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
344 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
345 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
346 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
347 CLK(NULL, "pll1", &pll1_clk),
348 CLK(NULL, "pll1_aux", &pll1_aux_clk),
349 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
350 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
351 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
352 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
353 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
354 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
355 CLK("i2c_davinci.1", NULL, &i2c0_clk),
356 CLK(NULL, "timer0", &timerp64_0_clk),
357 CLK("watchdog", NULL, &timerp64_1_clk),
358 CLK(NULL, "arm_rom", &arm_rom_clk),
359 CLK(NULL, "tpcc0", &tpcc0_clk),
360 CLK(NULL, "tptc0", &tptc0_clk),
361 CLK(NULL, "tptc1", &tptc1_clk),
362 CLK(NULL, "tpcc1", &tpcc1_clk),
363 CLK(NULL, "tptc2", &tptc2_clk),
364 CLK(NULL, "uart0", &uart0_clk),
365 CLK(NULL, "uart1", &uart1_clk),
366 CLK(NULL, "uart2", &uart2_clk),
367 CLK(NULL, "aintc", &aintc_clk),
368 CLK(NULL, "gpio", &gpio_clk),
369 CLK("i2c_davinci.2", NULL, &i2c1_clk),
370 CLK(NULL, "emif3", &emif3_clk),
371 CLK(NULL, "arm", &arm_clk),
372 CLK(NULL, "rmii", &rmii_clk),
373 CLK("davinci_emac.1", NULL, &emac_clk),
374 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
375 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
376 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
377 CLK(NULL, "aemif", &aemif_clk),
378 CLK(NULL, NULL, NULL),
379 };
380
381 /*
382 * Device specific mux setup
383 *
384 * soc description mux mode mode mux dbg
385 * reg offset mask mode
386 */
387 static const struct mux_config da850_pins[] = {
388 #ifdef CONFIG_DAVINCI_MUX
389 /* UART0 function */
390 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
391 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
392 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
393 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
394 /* UART1 function */
395 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
396 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
397 /* UART2 function */
398 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
399 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
400 /* I2C1 function */
401 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
402 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
403 /* I2C0 function */
404 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
405 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
406 /* EMAC function */
407 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
408 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
409 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
410 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
411 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
412 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
413 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
414 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
415 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
416 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
417 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
418 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
419 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
420 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
421 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
422 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
423 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
424 /* McASP function */
425 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
426 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
427 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
428 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
429 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
430 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
431 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
432 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
433 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
434 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
435 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
436 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
437 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
438 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
439 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
440 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
441 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
442 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
443 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
444 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
445 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
446 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
447 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
448 /* LCD function */
449 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
450 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
451 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
452 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
453 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
454 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
455 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
456 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
457 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
458 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
465 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
466 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
467 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
468 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
469 /* MMC/SD0 function */
470 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
471 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
472 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
473 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
474 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
475 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
476 /* EMIF2.5/EMIFA function */
477 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
478 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
479 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
480 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
481 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
482 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
483 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
484 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
485 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
486 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
487 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
488 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
489 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
490 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
491 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
492 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
493 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
494 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
495 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
496 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
497 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
498 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
499 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
513 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
514 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
515 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
516 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
517 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
518 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
519 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
521 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
522 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
523 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
524 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
525 /* GPIO function */
526 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
527 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
528 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
529 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
530 #endif
531 };
532
533 const short da850_uart0_pins[] __initdata = {
534 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
535 -1
536 };
537
538 const short da850_uart1_pins[] __initdata = {
539 DA850_UART1_RXD, DA850_UART1_TXD,
540 -1
541 };
542
543 const short da850_uart2_pins[] __initdata = {
544 DA850_UART2_RXD, DA850_UART2_TXD,
545 -1
546 };
547
548 const short da850_i2c0_pins[] __initdata = {
549 DA850_I2C0_SDA, DA850_I2C0_SCL,
550 -1
551 };
552
553 const short da850_i2c1_pins[] __initdata = {
554 DA850_I2C1_SCL, DA850_I2C1_SDA,
555 -1
556 };
557
558 const short da850_cpgmac_pins[] __initdata = {
559 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
560 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
561 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
562 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
563 DA850_MDIO_D,
564 -1
565 };
566
567 const short da850_mcasp_pins[] __initdata = {
568 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
569 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
570 DA850_AXR_11, DA850_AXR_12,
571 -1
572 };
573
574 const short da850_lcdcntl_pins[] __initdata = {
575 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
576 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
577 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
578 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
579 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
580 -1
581 };
582
583 const short da850_mmcsd0_pins[] __initdata = {
584 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
585 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
586 DA850_GPIO4_0, DA850_GPIO4_1,
587 -1
588 };
589
590 const short da850_nand_pins[] __initdata = {
591 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
592 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
593 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
594 DA850_NEMA_WE, DA850_NEMA_OE,
595 -1
596 };
597
598 const short da850_nor_pins[] __initdata = {
599 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
600 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
601 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
602 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
603 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
604 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
605 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
606 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
607 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
608 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
609 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
610 DA850_EMA_A_22, DA850_EMA_A_23,
611 -1
612 };
613
614 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
615 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
616 [IRQ_DA8XX_COMMTX] = 7,
617 [IRQ_DA8XX_COMMRX] = 7,
618 [IRQ_DA8XX_NINT] = 7,
619 [IRQ_DA8XX_EVTOUT0] = 7,
620 [IRQ_DA8XX_EVTOUT1] = 7,
621 [IRQ_DA8XX_EVTOUT2] = 7,
622 [IRQ_DA8XX_EVTOUT3] = 7,
623 [IRQ_DA8XX_EVTOUT4] = 7,
624 [IRQ_DA8XX_EVTOUT5] = 7,
625 [IRQ_DA8XX_EVTOUT6] = 7,
626 [IRQ_DA8XX_EVTOUT6] = 7,
627 [IRQ_DA8XX_EVTOUT7] = 7,
628 [IRQ_DA8XX_CCINT0] = 7,
629 [IRQ_DA8XX_CCERRINT] = 7,
630 [IRQ_DA8XX_TCERRINT0] = 7,
631 [IRQ_DA8XX_AEMIFINT] = 7,
632 [IRQ_DA8XX_I2CINT0] = 7,
633 [IRQ_DA8XX_MMCSDINT0] = 7,
634 [IRQ_DA8XX_MMCSDINT1] = 7,
635 [IRQ_DA8XX_ALLINT0] = 7,
636 [IRQ_DA8XX_RTC] = 7,
637 [IRQ_DA8XX_SPINT0] = 7,
638 [IRQ_DA8XX_TINT12_0] = 7,
639 [IRQ_DA8XX_TINT34_0] = 7,
640 [IRQ_DA8XX_TINT12_1] = 7,
641 [IRQ_DA8XX_TINT34_1] = 7,
642 [IRQ_DA8XX_UARTINT0] = 7,
643 [IRQ_DA8XX_KEYMGRINT] = 7,
644 [IRQ_DA8XX_SECINT] = 7,
645 [IRQ_DA8XX_SECKEYERR] = 7,
646 [IRQ_DA850_MPUADDRERR0] = 7,
647 [IRQ_DA850_MPUPROTERR0] = 7,
648 [IRQ_DA850_IOPUADDRERR0] = 7,
649 [IRQ_DA850_IOPUPROTERR0] = 7,
650 [IRQ_DA850_IOPUADDRERR1] = 7,
651 [IRQ_DA850_IOPUPROTERR1] = 7,
652 [IRQ_DA850_IOPUADDRERR2] = 7,
653 [IRQ_DA850_IOPUPROTERR2] = 7,
654 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
655 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
656 [IRQ_DA850_MPUADDRERR1] = 7,
657 [IRQ_DA850_MPUPROTERR1] = 7,
658 [IRQ_DA850_IOPUADDRERR3] = 7,
659 [IRQ_DA850_IOPUPROTERR3] = 7,
660 [IRQ_DA850_IOPUADDRERR4] = 7,
661 [IRQ_DA850_IOPUPROTERR4] = 7,
662 [IRQ_DA850_IOPUADDRERR5] = 7,
663 [IRQ_DA850_IOPUPROTERR5] = 7,
664 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
665 [IRQ_DA8XX_CHIPINT0] = 7,
666 [IRQ_DA8XX_CHIPINT1] = 7,
667 [IRQ_DA8XX_CHIPINT2] = 7,
668 [IRQ_DA8XX_CHIPINT3] = 7,
669 [IRQ_DA8XX_TCERRINT1] = 7,
670 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
671 [IRQ_DA8XX_C0_RX_PULSE] = 7,
672 [IRQ_DA8XX_C0_TX_PULSE] = 7,
673 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
674 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
675 [IRQ_DA8XX_C1_RX_PULSE] = 7,
676 [IRQ_DA8XX_C1_TX_PULSE] = 7,
677 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
678 [IRQ_DA8XX_MEMERR] = 7,
679 [IRQ_DA8XX_GPIO0] = 7,
680 [IRQ_DA8XX_GPIO1] = 7,
681 [IRQ_DA8XX_GPIO2] = 7,
682 [IRQ_DA8XX_GPIO3] = 7,
683 [IRQ_DA8XX_GPIO4] = 7,
684 [IRQ_DA8XX_GPIO5] = 7,
685 [IRQ_DA8XX_GPIO6] = 7,
686 [IRQ_DA8XX_GPIO7] = 7,
687 [IRQ_DA8XX_GPIO8] = 7,
688 [IRQ_DA8XX_I2CINT1] = 7,
689 [IRQ_DA8XX_LCDINT] = 7,
690 [IRQ_DA8XX_UARTINT1] = 7,
691 [IRQ_DA8XX_MCASPINT] = 7,
692 [IRQ_DA8XX_ALLINT1] = 7,
693 [IRQ_DA8XX_SPINT1] = 7,
694 [IRQ_DA8XX_UHPI_INT1] = 7,
695 [IRQ_DA8XX_USB_INT] = 7,
696 [IRQ_DA8XX_IRQN] = 7,
697 [IRQ_DA8XX_RWAKEUP] = 7,
698 [IRQ_DA8XX_UARTINT2] = 7,
699 [IRQ_DA8XX_DFTSSINT] = 7,
700 [IRQ_DA8XX_EHRPWM0] = 7,
701 [IRQ_DA8XX_EHRPWM0TZ] = 7,
702 [IRQ_DA8XX_EHRPWM1] = 7,
703 [IRQ_DA8XX_EHRPWM1TZ] = 7,
704 [IRQ_DA850_SATAINT] = 7,
705 [IRQ_DA850_TINT12_2] = 7,
706 [IRQ_DA850_TINT34_2] = 7,
707 [IRQ_DA850_TINTALL_2] = 7,
708 [IRQ_DA8XX_ECAP0] = 7,
709 [IRQ_DA8XX_ECAP1] = 7,
710 [IRQ_DA8XX_ECAP2] = 7,
711 [IRQ_DA850_MMCSDINT0_1] = 7,
712 [IRQ_DA850_MMCSDINT1_1] = 7,
713 [IRQ_DA850_T12CMPINT0_2] = 7,
714 [IRQ_DA850_T12CMPINT1_2] = 7,
715 [IRQ_DA850_T12CMPINT2_2] = 7,
716 [IRQ_DA850_T12CMPINT3_2] = 7,
717 [IRQ_DA850_T12CMPINT4_2] = 7,
718 [IRQ_DA850_T12CMPINT5_2] = 7,
719 [IRQ_DA850_T12CMPINT6_2] = 7,
720 [IRQ_DA850_T12CMPINT7_2] = 7,
721 [IRQ_DA850_T12CMPINT0_3] = 7,
722 [IRQ_DA850_T12CMPINT1_3] = 7,
723 [IRQ_DA850_T12CMPINT2_3] = 7,
724 [IRQ_DA850_T12CMPINT3_3] = 7,
725 [IRQ_DA850_T12CMPINT4_3] = 7,
726 [IRQ_DA850_T12CMPINT5_3] = 7,
727 [IRQ_DA850_T12CMPINT6_3] = 7,
728 [IRQ_DA850_T12CMPINT7_3] = 7,
729 [IRQ_DA850_RPIINT] = 7,
730 [IRQ_DA850_VPIFINT] = 7,
731 [IRQ_DA850_CCINT1] = 7,
732 [IRQ_DA850_CCERRINT1] = 7,
733 [IRQ_DA850_TCERRINT2] = 7,
734 [IRQ_DA850_TINT12_3] = 7,
735 [IRQ_DA850_TINT34_3] = 7,
736 [IRQ_DA850_TINTALL_3] = 7,
737 [IRQ_DA850_MCBSP0RINT] = 7,
738 [IRQ_DA850_MCBSP0XINT] = 7,
739 [IRQ_DA850_MCBSP1RINT] = 7,
740 [IRQ_DA850_MCBSP1XINT] = 7,
741 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
742 };
743
744 static struct map_desc da850_io_desc[] = {
745 {
746 .virtual = IO_VIRT,
747 .pfn = __phys_to_pfn(IO_PHYS),
748 .length = IO_SIZE,
749 .type = MT_DEVICE
750 },
751 {
752 .virtual = DA8XX_CP_INTC_VIRT,
753 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
754 .length = DA8XX_CP_INTC_SIZE,
755 .type = MT_DEVICE
756 },
757 };
758
759 static void __iomem *da850_psc_bases[] = {
760 IO_ADDRESS(DA8XX_PSC0_BASE),
761 IO_ADDRESS(DA8XX_PSC1_BASE),
762 };
763
764 /* Contents of JTAG ID register used to identify exact cpu type */
765 static struct davinci_id da850_ids[] = {
766 {
767 .variant = 0x0,
768 .part_no = 0xb7d1,
769 .manufacturer = 0x017, /* 0x02f >> 1 */
770 .cpu_id = DAVINCI_CPU_ID_DA850,
771 .name = "da850/omap-l138",
772 },
773 };
774
775 static struct davinci_timer_instance da850_timer_instance[4] = {
776 {
777 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
778 .bottom_irq = IRQ_DA8XX_TINT12_0,
779 .top_irq = IRQ_DA8XX_TINT34_0,
780 },
781 {
782 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
783 .bottom_irq = IRQ_DA8XX_TINT12_1,
784 .top_irq = IRQ_DA8XX_TINT34_1,
785 },
786 {
787 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
788 .bottom_irq = IRQ_DA850_TINT12_2,
789 .top_irq = IRQ_DA850_TINT34_2,
790 },
791 {
792 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
793 .bottom_irq = IRQ_DA850_TINT12_3,
794 .top_irq = IRQ_DA850_TINT34_3,
795 },
796 };
797
798 /*
799 * T0_BOT: Timer 0, bottom : Used for clock_event
800 * T0_TOP: Timer 0, top : Used for clocksource
801 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
802 */
803 static struct davinci_timer_info da850_timer_info = {
804 .timers = da850_timer_instance,
805 .clockevent_id = T0_BOT,
806 .clocksource_id = T0_TOP,
807 };
808
809 static void da850_set_async3_src(int pllnum)
810 {
811 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
812 struct davinci_clk *c;
813 unsigned int v;
814 int ret;
815
816 for (c = da850_clks; c->lk.clk; c++) {
817 clk = c->lk.clk;
818 if (clk->flags & DA850_CLK_ASYNC3) {
819 ret = clk_set_parent(clk, newparent);
820 WARN(ret, "DA850: unable to re-parent clock %s",
821 clk->name);
822 }
823 }
824
825 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
826 if (pllnum)
827 v |= CFGCHIP3_ASYNC3_CLKSRC;
828 else
829 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
830 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
831 }
832
833 #ifdef CONFIG_CPU_FREQ
834 /*
835 * Notes:
836 * According to the TRM, minimum PLLM results in maximum power savings.
837 * The OPP definitions below should keep the PLLM as low as possible.
838 *
839 * The output of the PLLM must be between 400 to 600 MHz.
840 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
841 */
842 struct da850_opp {
843 unsigned int freq; /* in KHz */
844 unsigned int prediv;
845 unsigned int mult;
846 unsigned int postdiv;
847 };
848
849 static const struct da850_opp da850_opp_300 = {
850 .freq = 300000,
851 .prediv = 1,
852 .mult = 25,
853 .postdiv = 2,
854 };
855
856 static const struct da850_opp da850_opp_200 = {
857 .freq = 200000,
858 .prediv = 1,
859 .mult = 25,
860 .postdiv = 3,
861 };
862
863 static const struct da850_opp da850_opp_96 = {
864 .freq = 96000,
865 .prediv = 1,
866 .mult = 20,
867 .postdiv = 5,
868 };
869
870 #define OPP(freq) \
871 { \
872 .index = (unsigned int) &da850_opp_##freq, \
873 .frequency = freq * 1000, \
874 }
875
876 static struct cpufreq_frequency_table da850_freq_table[] = {
877 OPP(300),
878 OPP(200),
879 OPP(96),
880 {
881 .index = 0,
882 .frequency = CPUFREQ_TABLE_END,
883 },
884 };
885
886 static struct davinci_cpufreq_config cpufreq_info = {
887 .freq_table = &da850_freq_table[0],
888 };
889
890 static struct platform_device da850_cpufreq_device = {
891 .name = "cpufreq-davinci",
892 .dev = {
893 .platform_data = &cpufreq_info,
894 },
895 };
896
897 int __init da850_register_cpufreq(void)
898 {
899 return platform_device_register(&da850_cpufreq_device);
900 }
901
902 static int da850_round_armrate(struct clk *clk, unsigned long rate)
903 {
904 int i, ret = 0, diff;
905 unsigned int best = (unsigned int) -1;
906
907 rate /= 1000; /* convert to kHz */
908
909 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
910 diff = da850_freq_table[i].frequency - rate;
911 if (diff < 0)
912 diff = -diff;
913
914 if (diff < best) {
915 best = diff;
916 ret = da850_freq_table[i].frequency;
917 }
918 }
919
920 return ret * 1000;
921 }
922
923 static int da850_set_armrate(struct clk *clk, unsigned long index)
924 {
925 struct clk *pllclk = &pll0_clk;
926
927 return clk_set_rate(pllclk, index);
928 }
929
930 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
931 {
932 unsigned int prediv, mult, postdiv;
933 struct da850_opp *opp;
934 struct pll_data *pll = clk->pll_data;
935 unsigned int v;
936 int ret;
937
938 opp = (struct da850_opp *) da850_freq_table[index].index;
939 prediv = opp->prediv;
940 mult = opp->mult;
941 postdiv = opp->postdiv;
942
943 /* Unlock writing to PLL registers */
944 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
945 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
946 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
947
948 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
949 if (WARN_ON(ret))
950 return ret;
951
952 return 0;
953 }
954 #else
955 int __init da850_register_cpufreq(void)
956 {
957 return 0;
958 }
959
960 static int da850_set_armrate(struct clk *clk, unsigned long rate)
961 {
962 return -EINVAL;
963 }
964
965 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
966 {
967 return -EINVAL;
968 }
969
970 static int da850_round_armrate(struct clk *clk, unsigned long rate)
971 {
972 return clk->rate;
973 }
974 #endif
975
976 static struct davinci_soc_info davinci_soc_info_da850 = {
977 .io_desc = da850_io_desc,
978 .io_desc_num = ARRAY_SIZE(da850_io_desc),
979 .ids = da850_ids,
980 .ids_num = ARRAY_SIZE(da850_ids),
981 .cpu_clks = da850_clks,
982 .psc_bases = da850_psc_bases,
983 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
984 .pinmux_pins = da850_pins,
985 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
986 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
987 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
988 .intc_irq_prios = da850_default_priorities,
989 .intc_irq_num = DA850_N_CP_INTC_IRQ,
990 .timer_info = &da850_timer_info,
991 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
992 .gpio_num = 144,
993 .gpio_irq = IRQ_DA8XX_GPIO0,
994 .serial_dev = &da8xx_serial_device,
995 .emac_pdata = &da8xx_emac_pdata,
996 };
997
998 void __init da850_init(void)
999 {
1000 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1001 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1002 return;
1003
1004 davinci_soc_info_da850.jtag_id_base =
1005 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
1006 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1007
1008 davinci_common_init(&davinci_soc_info_da850);
1009
1010 /*
1011 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1012 * This helps keeping the peripherals on this domain insulated
1013 * from CPU frequency changes caused by DVFS. The firmware sets
1014 * both PLL0 and PLL1 to the same frequency so, there should not
1015 * be any noticible change even in non-DVFS use cases.
1016 */
1017 da850_set_async3_src(1);
1018 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree