2 * driver/dma/coh901318.c
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/slab.h> /* kmalloc() */
15 #include <linux/dmaengine.h>
16 #include <linux/platform_device.h>
17 #include <linux/device.h>
18 #include <linux/irqreturn.h>
19 #include <linux/interrupt.h>
21 #include <linux/uaccess.h>
22 #include <linux/debugfs.h>
23 #include <mach/coh901318.h>
25 #include "coh901318_lli.h"
27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
30 #define COH_DBG(x) ({ if (1) x; 0; })
32 #define COH_DBG(x) ({ if (0) x; 0; })
35 struct coh901318_desc
{
36 struct dma_async_tx_descriptor desc
;
37 struct list_head node
;
38 struct scatterlist
*sg
;
40 struct coh901318_lli
*lli
;
41 enum dma_data_direction dir
;
45 struct coh901318_base
{
47 void __iomem
*virtbase
;
48 struct coh901318_pool pool
;
50 struct dma_device dma_slave
;
51 struct dma_device dma_memcpy
;
52 struct coh901318_chan
*chans
;
53 struct coh901318_platform
*platform
;
56 struct coh901318_chan
{
63 struct work_struct free_work
;
66 struct tasklet_struct tasklet
;
68 struct list_head active
;
69 struct list_head queue
;
70 struct list_head free
;
72 unsigned long nbr_active_done
;
78 struct coh901318_base
*base
;
81 static void coh901318_list_print(struct coh901318_chan
*cohc
,
82 struct coh901318_lli
*lli
)
84 struct coh901318_lli
*l
= lli
;
88 dev_vdbg(COHC_2_DEV(cohc
), "i %d, lli %p, ctrl 0x%x, src 0x%x"
89 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
90 i
, l
, l
->control
, l
->src_addr
, l
->dst_addr
,
91 l
->link_addr
, l
->virt_link_addr
);
93 l
= l
->virt_link_addr
;
97 #ifdef CONFIG_DEBUG_FS
99 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
101 static struct coh901318_base
*debugfs_dma_base
;
102 static struct dentry
*dma_dentry
;
104 static int coh901318_debugfs_open(struct inode
*inode
, struct file
*file
)
107 file
->private_data
= inode
->i_private
;
111 static int coh901318_debugfs_read(struct file
*file
, char __user
*buf
,
112 size_t count
, loff_t
*f_pos
)
114 u64 started_channels
= debugfs_dma_base
->pm
.started_channels
;
115 int pool_count
= debugfs_dma_base
->pool
.debugfs_pool_counter
;
122 dev_buf
= kmalloc(4*1024, GFP_KERNEL
);
127 tmp
+= sprintf(tmp
, "DMA -- enabled dma channels\n");
129 for (i
= 0; i
< debugfs_dma_base
->platform
->max_channels
; i
++)
130 if (started_channels
& (1 << i
))
131 tmp
+= sprintf(tmp
, "channel %d\n", i
);
133 tmp
+= sprintf(tmp
, "Pool alloc nbr %d\n", pool_count
);
134 dev_size
= tmp
- dev_buf
;
136 /* No more to read if offset != 0 */
137 if (*f_pos
> dev_size
)
140 if (count
> dev_size
- *f_pos
)
141 count
= dev_size
- *f_pos
;
143 if (copy_to_user(buf
, dev_buf
+ *f_pos
, count
))
156 static const struct file_operations coh901318_debugfs_status_operations
= {
157 .owner
= THIS_MODULE
,
158 .open
= coh901318_debugfs_open
,
159 .read
= coh901318_debugfs_read
,
160 .llseek
= default_llseek
,
164 static int __init
init_coh901318_debugfs(void)
167 dma_dentry
= debugfs_create_dir("dma", NULL
);
169 (void) debugfs_create_file("status",
172 &coh901318_debugfs_status_operations
);
176 static void __exit
exit_coh901318_debugfs(void)
178 debugfs_remove_recursive(dma_dentry
);
181 module_init(init_coh901318_debugfs
);
182 module_exit(exit_coh901318_debugfs
);
185 #define COH901318_DEBUGFS_ASSIGN(x, y)
187 #endif /* CONFIG_DEBUG_FS */
189 static inline struct coh901318_chan
*to_coh901318_chan(struct dma_chan
*chan
)
191 return container_of(chan
, struct coh901318_chan
, chan
);
194 static inline dma_addr_t
195 cohc_dev_addr(struct coh901318_chan
*cohc
)
197 /* Runtime supplied address will take precedence */
198 if (cohc
->runtime_addr
)
199 return cohc
->runtime_addr
;
200 return cohc
->base
->platform
->chan_conf
[cohc
->id
].dev_addr
;
203 static inline const struct coh901318_params
*
204 cohc_chan_param(struct coh901318_chan
*cohc
)
206 return &cohc
->base
->platform
->chan_conf
[cohc
->id
].param
;
209 static inline const struct coh_dma_channel
*
210 cohc_chan_conf(struct coh901318_chan
*cohc
)
212 return &cohc
->base
->platform
->chan_conf
[cohc
->id
];
215 static void enable_powersave(struct coh901318_chan
*cohc
)
218 struct powersave
*pm
= &cohc
->base
->pm
;
220 spin_lock_irqsave(&pm
->lock
, flags
);
222 pm
->started_channels
&= ~(1ULL << cohc
->id
);
224 if (!pm
->started_channels
) {
225 /* DMA no longer intends to access memory */
226 cohc
->base
->platform
->access_memory_state(cohc
->base
->dev
,
230 spin_unlock_irqrestore(&pm
->lock
, flags
);
232 static void disable_powersave(struct coh901318_chan
*cohc
)
235 struct powersave
*pm
= &cohc
->base
->pm
;
237 spin_lock_irqsave(&pm
->lock
, flags
);
239 if (!pm
->started_channels
) {
240 /* DMA intends to access memory */
241 cohc
->base
->platform
->access_memory_state(cohc
->base
->dev
,
245 pm
->started_channels
|= (1ULL << cohc
->id
);
247 spin_unlock_irqrestore(&pm
->lock
, flags
);
250 static inline int coh901318_set_ctrl(struct coh901318_chan
*cohc
, u32 control
)
252 int channel
= cohc
->id
;
253 void __iomem
*virtbase
= cohc
->base
->virtbase
;
256 virtbase
+ COH901318_CX_CTRL
+
257 COH901318_CX_CTRL_SPACING
* channel
);
261 static inline int coh901318_set_conf(struct coh901318_chan
*cohc
, u32 conf
)
263 int channel
= cohc
->id
;
264 void __iomem
*virtbase
= cohc
->base
->virtbase
;
267 virtbase
+ COH901318_CX_CFG
+
268 COH901318_CX_CFG_SPACING
*channel
);
273 static int coh901318_start(struct coh901318_chan
*cohc
)
276 int channel
= cohc
->id
;
277 void __iomem
*virtbase
= cohc
->base
->virtbase
;
279 disable_powersave(cohc
);
281 val
= readl(virtbase
+ COH901318_CX_CFG
+
282 COH901318_CX_CFG_SPACING
* channel
);
285 val
|= COH901318_CX_CFG_CH_ENABLE
;
286 writel(val
, virtbase
+ COH901318_CX_CFG
+
287 COH901318_CX_CFG_SPACING
* channel
);
292 static int coh901318_prep_linked_list(struct coh901318_chan
*cohc
,
293 struct coh901318_lli
*lli
)
295 int channel
= cohc
->id
;
296 void __iomem
*virtbase
= cohc
->base
->virtbase
;
298 BUG_ON(readl(virtbase
+ COH901318_CX_STAT
+
299 COH901318_CX_STAT_SPACING
*channel
) &
300 COH901318_CX_STAT_ACTIVE
);
302 writel(lli
->src_addr
,
303 virtbase
+ COH901318_CX_SRC_ADDR
+
304 COH901318_CX_SRC_ADDR_SPACING
* channel
);
306 writel(lli
->dst_addr
, virtbase
+
307 COH901318_CX_DST_ADDR
+
308 COH901318_CX_DST_ADDR_SPACING
* channel
);
310 writel(lli
->link_addr
, virtbase
+ COH901318_CX_LNK_ADDR
+
311 COH901318_CX_LNK_ADDR_SPACING
* channel
);
313 writel(lli
->control
, virtbase
+ COH901318_CX_CTRL
+
314 COH901318_CX_CTRL_SPACING
* channel
);
319 coh901318_assign_cookie(struct coh901318_chan
*cohc
,
320 struct coh901318_desc
*cohd
)
322 dma_cookie_t cookie
= cohc
->chan
.cookie
;
327 cohc
->chan
.cookie
= cookie
;
328 cohd
->desc
.cookie
= cookie
;
333 static struct coh901318_desc
*
334 coh901318_desc_get(struct coh901318_chan
*cohc
)
336 struct coh901318_desc
*desc
;
338 if (list_empty(&cohc
->free
)) {
339 /* alloc new desc because we're out of used ones
340 * TODO: alloc a pile of descs instead of just one,
341 * avoid many small allocations.
343 desc
= kzalloc(sizeof(struct coh901318_desc
), GFP_NOWAIT
);
346 INIT_LIST_HEAD(&desc
->node
);
347 dma_async_tx_descriptor_init(&desc
->desc
, &cohc
->chan
);
349 /* Reuse an old desc. */
350 desc
= list_first_entry(&cohc
->free
,
351 struct coh901318_desc
,
353 list_del(&desc
->node
);
354 /* Initialize it a bit so it's not insane */
357 desc
->desc
.callback
= NULL
;
358 desc
->desc
.callback_param
= NULL
;
366 coh901318_desc_free(struct coh901318_chan
*cohc
, struct coh901318_desc
*cohd
)
368 list_add_tail(&cohd
->node
, &cohc
->free
);
371 /* call with irq lock held */
373 coh901318_desc_submit(struct coh901318_chan
*cohc
, struct coh901318_desc
*desc
)
375 list_add_tail(&desc
->node
, &cohc
->active
);
378 static struct coh901318_desc
*
379 coh901318_first_active_get(struct coh901318_chan
*cohc
)
381 struct coh901318_desc
*d
;
383 if (list_empty(&cohc
->active
))
386 d
= list_first_entry(&cohc
->active
,
387 struct coh901318_desc
,
393 coh901318_desc_remove(struct coh901318_desc
*cohd
)
395 list_del(&cohd
->node
);
399 coh901318_desc_queue(struct coh901318_chan
*cohc
, struct coh901318_desc
*desc
)
401 list_add_tail(&desc
->node
, &cohc
->queue
);
404 static struct coh901318_desc
*
405 coh901318_first_queued(struct coh901318_chan
*cohc
)
407 struct coh901318_desc
*d
;
409 if (list_empty(&cohc
->queue
))
412 d
= list_first_entry(&cohc
->queue
,
413 struct coh901318_desc
,
418 static inline u32
coh901318_get_bytes_in_lli(struct coh901318_lli
*in_lli
)
420 struct coh901318_lli
*lli
= in_lli
;
424 bytes
+= lli
->control
& COH901318_CX_CTRL_TC_VALUE_MASK
;
425 lli
= lli
->virt_link_addr
;
431 * Get the number of bytes left to transfer on this channel,
432 * it is unwise to call this before stopping the channel for
433 * absolute measures, but for a rough guess you can still call
436 static u32
coh901318_get_bytes_left(struct dma_chan
*chan
)
438 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
439 struct coh901318_desc
*cohd
;
440 struct list_head
*pos
;
445 spin_lock_irqsave(&cohc
->lock
, flags
);
448 * If there are many queued jobs, we iterate and add the
449 * size of them all. We take a special look on the first
450 * job though, since it is probably active.
452 list_for_each(pos
, &cohc
->active
) {
454 * The first job in the list will be working on the
455 * hardware. The job can be stopped but still active,
456 * so that the transfer counter is somewhere inside
459 cohd
= list_entry(pos
, struct coh901318_desc
, node
);
462 struct coh901318_lli
*lli
;
465 /* Read current transfer count value */
466 left
= readl(cohc
->base
->virtbase
+
468 COH901318_CX_CTRL_SPACING
* cohc
->id
) &
469 COH901318_CX_CTRL_TC_VALUE_MASK
;
471 /* See if the transfer is linked... */
472 ladd
= readl(cohc
->base
->virtbase
+
473 COH901318_CX_LNK_ADDR
+
474 COH901318_CX_LNK_ADDR_SPACING
*
476 ~COH901318_CX_LNK_LINK_IMMEDIATE
;
477 /* Single transaction */
482 * Linked transaction, follow the lli, find the
483 * currently processing lli, and proceed to the next
486 while (lli
&& lli
->link_addr
!= ladd
)
487 lli
= lli
->virt_link_addr
;
490 lli
= lli
->virt_link_addr
;
493 * Follow remaining lli links around to count the total
494 * number of bytes left
496 left
+= coh901318_get_bytes_in_lli(lli
);
498 left
+= coh901318_get_bytes_in_lli(cohd
->lli
);
503 /* Also count bytes in the queued jobs */
504 list_for_each(pos
, &cohc
->queue
) {
505 cohd
= list_entry(pos
, struct coh901318_desc
, node
);
506 left
+= coh901318_get_bytes_in_lli(cohd
->lli
);
509 spin_unlock_irqrestore(&cohc
->lock
, flags
);
515 * Pauses a transfer without losing data. Enables power save.
516 * Use this function in conjunction with coh901318_resume.
518 static void coh901318_pause(struct dma_chan
*chan
)
522 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
523 int channel
= cohc
->id
;
524 void __iomem
*virtbase
= cohc
->base
->virtbase
;
526 spin_lock_irqsave(&cohc
->lock
, flags
);
528 /* Disable channel in HW */
529 val
= readl(virtbase
+ COH901318_CX_CFG
+
530 COH901318_CX_CFG_SPACING
* channel
);
532 /* Stopping infinite transfer */
533 if ((val
& COH901318_CX_CTRL_TC_ENABLE
) == 0 &&
534 (val
& COH901318_CX_CFG_CH_ENABLE
))
538 val
&= ~COH901318_CX_CFG_CH_ENABLE
;
539 /* Enable twice, HW bug work around */
540 writel(val
, virtbase
+ COH901318_CX_CFG
+
541 COH901318_CX_CFG_SPACING
* channel
);
542 writel(val
, virtbase
+ COH901318_CX_CFG
+
543 COH901318_CX_CFG_SPACING
* channel
);
545 /* Spin-wait for it to actually go inactive */
546 while (readl(virtbase
+ COH901318_CX_STAT
+COH901318_CX_STAT_SPACING
*
547 channel
) & COH901318_CX_STAT_ACTIVE
)
550 /* Check if we stopped an active job */
551 if ((readl(virtbase
+ COH901318_CX_CTRL
+COH901318_CX_CTRL_SPACING
*
552 channel
) & COH901318_CX_CTRL_TC_VALUE_MASK
) > 0)
555 enable_powersave(cohc
);
557 spin_unlock_irqrestore(&cohc
->lock
, flags
);
560 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
561 Power save is handled.
563 static void coh901318_resume(struct dma_chan
*chan
)
567 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
568 int channel
= cohc
->id
;
570 spin_lock_irqsave(&cohc
->lock
, flags
);
572 disable_powersave(cohc
);
575 /* Enable channel in HW */
576 val
= readl(cohc
->base
->virtbase
+ COH901318_CX_CFG
+
577 COH901318_CX_CFG_SPACING
* channel
);
579 val
|= COH901318_CX_CFG_CH_ENABLE
;
581 writel(val
, cohc
->base
->virtbase
+ COH901318_CX_CFG
+
582 COH901318_CX_CFG_SPACING
*channel
);
587 spin_unlock_irqrestore(&cohc
->lock
, flags
);
590 bool coh901318_filter_id(struct dma_chan
*chan
, void *chan_id
)
592 unsigned int ch_nr
= (unsigned int) chan_id
;
594 if (ch_nr
== to_coh901318_chan(chan
)->id
)
599 EXPORT_SYMBOL(coh901318_filter_id
);
602 * DMA channel allocation
604 static int coh901318_config(struct coh901318_chan
*cohc
,
605 struct coh901318_params
*param
)
608 const struct coh901318_params
*p
;
609 int channel
= cohc
->id
;
610 void __iomem
*virtbase
= cohc
->base
->virtbase
;
612 spin_lock_irqsave(&cohc
->lock
, flags
);
617 p
= &cohc
->base
->platform
->chan_conf
[channel
].param
;
619 /* Clear any pending BE or TC interrupt */
621 writel(1 << channel
, virtbase
+ COH901318_BE_INT_CLEAR1
);
622 writel(1 << channel
, virtbase
+ COH901318_TC_INT_CLEAR1
);
624 writel(1 << (channel
- 32), virtbase
+
625 COH901318_BE_INT_CLEAR2
);
626 writel(1 << (channel
- 32), virtbase
+
627 COH901318_TC_INT_CLEAR2
);
630 coh901318_set_conf(cohc
, p
->config
);
631 coh901318_set_ctrl(cohc
, p
->ctrl_lli_last
);
633 spin_unlock_irqrestore(&cohc
->lock
, flags
);
638 /* must lock when calling this function
639 * start queued jobs, if any
640 * TODO: start all queued jobs in one go
642 * Returns descriptor if queued job is started otherwise NULL.
643 * If the queue is empty NULL is returned.
645 static struct coh901318_desc
*coh901318_queue_start(struct coh901318_chan
*cohc
)
647 struct coh901318_desc
*cohd
;
650 * start queued jobs, if any
651 * TODO: transmit all queued jobs in one go
653 cohd
= coh901318_first_queued(cohc
);
656 /* Remove from queue */
657 coh901318_desc_remove(cohd
);
658 /* initiate DMA job */
661 coh901318_desc_submit(cohc
, cohd
);
663 coh901318_prep_linked_list(cohc
, cohd
->lli
);
665 /* start dma job on this channel */
666 coh901318_start(cohc
);
674 * This tasklet is called from the interrupt handler to
675 * handle each descriptor (DMA job) that is sent to a channel.
677 static void dma_tasklet(unsigned long data
)
679 struct coh901318_chan
*cohc
= (struct coh901318_chan
*) data
;
680 struct coh901318_desc
*cohd_fin
;
682 dma_async_tx_callback callback
;
683 void *callback_param
;
685 dev_vdbg(COHC_2_DEV(cohc
), "[%s] chan_id %d"
686 " nbr_active_done %ld\n", __func__
,
687 cohc
->id
, cohc
->nbr_active_done
);
689 spin_lock_irqsave(&cohc
->lock
, flags
);
691 /* get first active descriptor entry from list */
692 cohd_fin
= coh901318_first_active_get(cohc
);
694 if (cohd_fin
== NULL
)
697 /* locate callback to client */
698 callback
= cohd_fin
->desc
.callback
;
699 callback_param
= cohd_fin
->desc
.callback_param
;
701 /* sign this job as completed on the channel */
702 cohc
->completed
= cohd_fin
->desc
.cookie
;
704 /* release the lli allocation and remove the descriptor */
705 coh901318_lli_free(&cohc
->base
->pool
, &cohd_fin
->lli
);
707 /* return desc to free-list */
708 coh901318_desc_remove(cohd_fin
);
709 coh901318_desc_free(cohc
, cohd_fin
);
711 spin_unlock_irqrestore(&cohc
->lock
, flags
);
713 /* Call the callback when we're done */
715 callback(callback_param
);
717 spin_lock_irqsave(&cohc
->lock
, flags
);
720 * If another interrupt fired while the tasklet was scheduling,
721 * we don't get called twice, so we have this number of active
722 * counter that keep track of the number of IRQs expected to
723 * be handled for this channel. If there happen to be more than
724 * one IRQ to be ack:ed, we simply schedule this tasklet again.
726 cohc
->nbr_active_done
--;
727 if (cohc
->nbr_active_done
) {
728 dev_dbg(COHC_2_DEV(cohc
), "scheduling tasklet again, new IRQs "
729 "came in while we were scheduling this tasklet\n");
730 if (cohc_chan_conf(cohc
)->priority_high
)
731 tasklet_hi_schedule(&cohc
->tasklet
);
733 tasklet_schedule(&cohc
->tasklet
);
736 spin_unlock_irqrestore(&cohc
->lock
, flags
);
741 spin_unlock_irqrestore(&cohc
->lock
, flags
);
742 dev_err(COHC_2_DEV(cohc
), "[%s] No active dma desc\n", __func__
);
746 /* called from interrupt context */
747 static void dma_tc_handle(struct coh901318_chan
*cohc
)
750 * If the channel is not allocated, then we shouldn't have
751 * any TC interrupts on it.
753 if (!cohc
->allocated
) {
754 dev_err(COHC_2_DEV(cohc
), "spurious interrupt from "
755 "unallocated channel\n");
759 spin_lock(&cohc
->lock
);
762 * When we reach this point, at least one queue item
763 * should have been moved over from cohc->queue to
764 * cohc->active and run to completion, that is why we're
765 * getting a terminal count interrupt is it not?
766 * If you get this BUG() the most probable cause is that
767 * the individual nodes in the lli chain have IRQ enabled,
768 * so check your platform config for lli chain ctrl.
770 BUG_ON(list_empty(&cohc
->active
));
772 cohc
->nbr_active_done
++;
775 * This attempt to take a job from cohc->queue, put it
776 * into cohc->active and start it.
778 if (coh901318_queue_start(cohc
) == NULL
)
781 spin_unlock(&cohc
->lock
);
784 * This tasklet will remove items from cohc->active
785 * and thus terminates them.
787 if (cohc_chan_conf(cohc
)->priority_high
)
788 tasklet_hi_schedule(&cohc
->tasklet
);
790 tasklet_schedule(&cohc
->tasklet
);
794 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
800 struct coh901318_base
*base
= dev_id
;
801 struct coh901318_chan
*cohc
;
802 void __iomem
*virtbase
= base
->virtbase
;
804 status1
= readl(virtbase
+ COH901318_INT_STATUS1
);
805 status2
= readl(virtbase
+ COH901318_INT_STATUS2
);
807 if (unlikely(status1
== 0 && status2
== 0)) {
808 dev_warn(base
->dev
, "spurious DMA IRQ from no channel!\n");
812 /* TODO: consider handle IRQ in tasklet here to
813 * minimize interrupt latency */
815 /* Check the first 32 DMA channels for IRQ */
817 /* Find first bit set, return as a number. */
818 i
= ffs(status1
) - 1;
821 cohc
= &base
->chans
[ch
];
822 spin_lock(&cohc
->lock
);
824 /* Mask off this bit */
825 status1
&= ~(1 << i
);
826 /* Check the individual channel bits */
827 if (test_bit(i
, virtbase
+ COH901318_BE_INT_STATUS1
)) {
828 dev_crit(COHC_2_DEV(cohc
),
829 "DMA bus error on channel %d!\n", ch
);
831 /* Clear BE interrupt */
832 __set_bit(i
, virtbase
+ COH901318_BE_INT_CLEAR1
);
834 /* Caused by TC, really? */
835 if (unlikely(!test_bit(i
, virtbase
+
836 COH901318_TC_INT_STATUS1
))) {
837 dev_warn(COHC_2_DEV(cohc
),
838 "ignoring interrupt not caused by terminal count on channel %d\n", ch
);
839 /* Clear TC interrupt */
841 __set_bit(i
, virtbase
+ COH901318_TC_INT_CLEAR1
);
843 /* Enable powersave if transfer has finished */
844 if (!(readl(virtbase
+ COH901318_CX_STAT
+
845 COH901318_CX_STAT_SPACING
*ch
) &
846 COH901318_CX_STAT_ENABLED
)) {
847 enable_powersave(cohc
);
850 /* Must clear TC interrupt before calling
852 * in case tc_handle initiate a new dma job
854 __set_bit(i
, virtbase
+ COH901318_TC_INT_CLEAR1
);
859 spin_unlock(&cohc
->lock
);
862 /* Check the remaining 32 DMA channels for IRQ */
864 /* Find first bit set, return as a number. */
865 i
= ffs(status2
) - 1;
867 cohc
= &base
->chans
[ch
];
868 spin_lock(&cohc
->lock
);
870 /* Mask off this bit */
871 status2
&= ~(1 << i
);
872 /* Check the individual channel bits */
873 if (test_bit(i
, virtbase
+ COH901318_BE_INT_STATUS2
)) {
874 dev_crit(COHC_2_DEV(cohc
),
875 "DMA bus error on channel %d!\n", ch
);
876 /* Clear BE interrupt */
878 __set_bit(i
, virtbase
+ COH901318_BE_INT_CLEAR2
);
880 /* Caused by TC, really? */
881 if (unlikely(!test_bit(i
, virtbase
+
882 COH901318_TC_INT_STATUS2
))) {
883 dev_warn(COHC_2_DEV(cohc
),
884 "ignoring interrupt not caused by terminal count on channel %d\n", ch
);
885 /* Clear TC interrupt */
886 __set_bit(i
, virtbase
+ COH901318_TC_INT_CLEAR2
);
889 /* Enable powersave if transfer has finished */
890 if (!(readl(virtbase
+ COH901318_CX_STAT
+
891 COH901318_CX_STAT_SPACING
*ch
) &
892 COH901318_CX_STAT_ENABLED
)) {
893 enable_powersave(cohc
);
895 /* Must clear TC interrupt before calling
897 * in case tc_handle initiate a new dma job
899 __set_bit(i
, virtbase
+ COH901318_TC_INT_CLEAR2
);
904 spin_unlock(&cohc
->lock
);
910 static int coh901318_alloc_chan_resources(struct dma_chan
*chan
)
912 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
915 dev_vdbg(COHC_2_DEV(cohc
), "[%s] DMA channel %d\n",
918 if (chan
->client_count
> 1)
921 spin_lock_irqsave(&cohc
->lock
, flags
);
923 coh901318_config(cohc
, NULL
);
926 cohc
->completed
= chan
->cookie
= 1;
928 spin_unlock_irqrestore(&cohc
->lock
, flags
);
934 coh901318_free_chan_resources(struct dma_chan
*chan
)
936 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
937 int channel
= cohc
->id
;
940 spin_lock_irqsave(&cohc
->lock
, flags
);
943 writel(0x00000000U
, cohc
->base
->virtbase
+ COH901318_CX_CFG
+
944 COH901318_CX_CFG_SPACING
*channel
);
945 writel(0x00000000U
, cohc
->base
->virtbase
+ COH901318_CX_CTRL
+
946 COH901318_CX_CTRL_SPACING
*channel
);
950 spin_unlock_irqrestore(&cohc
->lock
, flags
);
952 chan
->device
->device_control(chan
, DMA_TERMINATE_ALL
, 0);
957 coh901318_tx_submit(struct dma_async_tx_descriptor
*tx
)
959 struct coh901318_desc
*cohd
= container_of(tx
, struct coh901318_desc
,
961 struct coh901318_chan
*cohc
= to_coh901318_chan(tx
->chan
);
964 spin_lock_irqsave(&cohc
->lock
, flags
);
966 tx
->cookie
= coh901318_assign_cookie(cohc
, cohd
);
968 coh901318_desc_queue(cohc
, cohd
);
970 spin_unlock_irqrestore(&cohc
->lock
, flags
);
975 static struct dma_async_tx_descriptor
*
976 coh901318_prep_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
977 size_t size
, unsigned long flags
)
979 struct coh901318_lli
*lli
;
980 struct coh901318_desc
*cohd
;
982 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
984 u32 ctrl_last
= cohc_chan_param(cohc
)->ctrl_lli_last
;
987 spin_lock_irqsave(&cohc
->lock
, flg
);
989 dev_vdbg(COHC_2_DEV(cohc
),
990 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
991 __func__
, cohc
->id
, src
, dest
, size
);
993 if (flags
& DMA_PREP_INTERRUPT
)
994 /* Trigger interrupt after last lli */
995 ctrl_last
|= COH901318_CX_CTRL_TC_IRQ_ENABLE
;
997 lli_len
= size
>> MAX_DMA_PACKET_SIZE_SHIFT
;
998 if ((lli_len
<< MAX_DMA_PACKET_SIZE_SHIFT
) < size
)
1001 lli
= coh901318_lli_alloc(&cohc
->base
->pool
, lli_len
);
1006 ret
= coh901318_lli_fill_memcpy(
1007 &cohc
->base
->pool
, lli
, src
, size
, dest
,
1008 cohc_chan_param(cohc
)->ctrl_lli_chained
,
1013 COH_DBG(coh901318_list_print(cohc
, lli
));
1015 /* Pick a descriptor to handle this transfer */
1016 cohd
= coh901318_desc_get(cohc
);
1018 cohd
->flags
= flags
;
1019 cohd
->desc
.tx_submit
= coh901318_tx_submit
;
1021 spin_unlock_irqrestore(&cohc
->lock
, flg
);
1025 spin_unlock_irqrestore(&cohc
->lock
, flg
);
1029 static struct dma_async_tx_descriptor
*
1030 coh901318_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
1031 unsigned int sg_len
, enum dma_data_direction direction
,
1032 unsigned long flags
)
1034 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
1035 struct coh901318_lli
*lli
;
1036 struct coh901318_desc
*cohd
;
1037 const struct coh901318_params
*params
;
1038 struct scatterlist
*sg
;
1042 u32 ctrl_chained
= cohc_chan_param(cohc
)->ctrl_lli_chained
;
1043 u32 ctrl
= cohc_chan_param(cohc
)->ctrl_lli
;
1044 u32 ctrl_last
= cohc_chan_param(cohc
)->ctrl_lli_last
;
1051 if (sgl
->length
== 0)
1054 spin_lock_irqsave(&cohc
->lock
, flg
);
1056 dev_vdbg(COHC_2_DEV(cohc
), "[%s] sg_len %d dir %d\n",
1057 __func__
, sg_len
, direction
);
1059 if (flags
& DMA_PREP_INTERRUPT
)
1060 /* Trigger interrupt after last lli */
1061 ctrl_last
|= COH901318_CX_CTRL_TC_IRQ_ENABLE
;
1063 params
= cohc_chan_param(cohc
);
1064 config
= params
->config
;
1066 * Add runtime-specific control on top, make
1067 * sure the bits you set per peripheral channel are
1068 * cleared in the default config from the platform.
1070 ctrl_chained
|= cohc
->runtime_ctrl
;
1071 ctrl_last
|= cohc
->runtime_ctrl
;
1072 ctrl
|= cohc
->runtime_ctrl
;
1074 if (direction
== DMA_TO_DEVICE
) {
1075 u32 tx_flags
= COH901318_CX_CTRL_PRDD_SOURCE
|
1076 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE
;
1078 config
|= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY
;
1079 ctrl_chained
|= tx_flags
;
1080 ctrl_last
|= tx_flags
;
1082 } else if (direction
== DMA_FROM_DEVICE
) {
1083 u32 rx_flags
= COH901318_CX_CTRL_PRDD_DEST
|
1084 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE
;
1086 config
|= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY
;
1087 ctrl_chained
|= rx_flags
;
1088 ctrl_last
|= rx_flags
;
1093 coh901318_set_conf(cohc
, config
);
1095 /* The dma only supports transmitting packages up to
1096 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1097 * dma elemts required to send the entire sg list
1099 for_each_sg(sgl
, sg
, sg_len
, i
) {
1100 unsigned int factor
;
1101 size
= sg_dma_len(sg
);
1103 if (size
<= MAX_DMA_PACKET_SIZE
) {
1108 factor
= size
>> MAX_DMA_PACKET_SIZE_SHIFT
;
1109 if ((factor
<< MAX_DMA_PACKET_SIZE_SHIFT
) < size
)
1115 pr_debug("Allocate %d lli:s for this transfer\n", len
);
1116 lli
= coh901318_lli_alloc(&cohc
->base
->pool
, len
);
1121 /* initiate allocated lli list */
1122 ret
= coh901318_lli_fill_sg(&cohc
->base
->pool
, lli
, sgl
, sg_len
,
1123 cohc_dev_addr(cohc
),
1127 direction
, COH901318_CX_CTRL_TC_IRQ_ENABLE
);
1132 * Set the default ctrl for the channel to the one from the lli,
1133 * things may have changed due to odd buffer alignment etc.
1135 coh901318_set_ctrl(cohc
, lli
->control
);
1137 COH_DBG(coh901318_list_print(cohc
, lli
));
1139 /* Pick a descriptor to handle this transfer */
1140 cohd
= coh901318_desc_get(cohc
);
1141 cohd
->dir
= direction
;
1142 cohd
->flags
= flags
;
1143 cohd
->desc
.tx_submit
= coh901318_tx_submit
;
1146 spin_unlock_irqrestore(&cohc
->lock
, flg
);
1152 spin_unlock_irqrestore(&cohc
->lock
, flg
);
1157 static enum dma_status
1158 coh901318_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
1159 struct dma_tx_state
*txstate
)
1161 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
1162 dma_cookie_t last_used
;
1163 dma_cookie_t last_complete
;
1166 last_complete
= cohc
->completed
;
1167 last_used
= chan
->cookie
;
1169 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
1171 dma_set_tx_state(txstate
, last_complete
, last_used
,
1172 coh901318_get_bytes_left(chan
));
1173 if (ret
== DMA_IN_PROGRESS
&& cohc
->stopped
)
1180 coh901318_issue_pending(struct dma_chan
*chan
)
1182 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
1183 unsigned long flags
;
1185 spin_lock_irqsave(&cohc
->lock
, flags
);
1188 * Busy means that pending jobs are already being processed,
1189 * and then there is no point in starting the queue: the
1190 * terminal count interrupt on the channel will take the next
1191 * job on the queue and execute it anyway.
1194 coh901318_queue_start(cohc
);
1196 spin_unlock_irqrestore(&cohc
->lock
, flags
);
1200 * Here we wrap in the runtime dma control interface
1202 struct burst_table
{
1209 static const struct burst_table burst_sizes
[] = {
1214 .reg
= COH901318_CX_CTRL_BURST_COUNT_64_BYTES
,
1220 .reg
= COH901318_CX_CTRL_BURST_COUNT_48_BYTES
,
1226 .reg
= COH901318_CX_CTRL_BURST_COUNT_32_BYTES
,
1232 .reg
= COH901318_CX_CTRL_BURST_COUNT_16_BYTES
,
1238 .reg
= COH901318_CX_CTRL_BURST_COUNT_8_BYTES
,
1244 .reg
= COH901318_CX_CTRL_BURST_COUNT_4_BYTES
,
1250 .reg
= COH901318_CX_CTRL_BURST_COUNT_2_BYTES
,
1256 .reg
= COH901318_CX_CTRL_BURST_COUNT_1_BYTE
,
1260 static void coh901318_dma_set_runtimeconfig(struct dma_chan
*chan
,
1261 struct dma_slave_config
*config
)
1263 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
1265 enum dma_slave_buswidth addr_width
;
1267 u32 runtime_ctrl
= 0;
1270 /* We only support mem to per or per to mem transfers */
1271 if (config
->direction
== DMA_FROM_DEVICE
) {
1272 addr
= config
->src_addr
;
1273 addr_width
= config
->src_addr_width
;
1274 maxburst
= config
->src_maxburst
;
1275 } else if (config
->direction
== DMA_TO_DEVICE
) {
1276 addr
= config
->dst_addr
;
1277 addr_width
= config
->dst_addr_width
;
1278 maxburst
= config
->dst_maxburst
;
1280 dev_err(COHC_2_DEV(cohc
), "illegal channel mode\n");
1284 dev_dbg(COHC_2_DEV(cohc
), "configure channel for %d byte transfers\n",
1286 switch (addr_width
) {
1287 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1289 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS
|
1290 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS
;
1292 while (i
< ARRAY_SIZE(burst_sizes
)) {
1293 if (burst_sizes
[i
].burst_8bit
<= maxburst
)
1299 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1301 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS
|
1302 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS
;
1304 while (i
< ARRAY_SIZE(burst_sizes
)) {
1305 if (burst_sizes
[i
].burst_16bit
<= maxburst
)
1311 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1312 /* Direction doesn't matter here, it's 32/32 bits */
1314 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS
|
1315 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS
;
1317 while (i
< ARRAY_SIZE(burst_sizes
)) {
1318 if (burst_sizes
[i
].burst_32bit
<= maxburst
)
1325 dev_err(COHC_2_DEV(cohc
),
1326 "bad runtimeconfig: alien address width\n");
1330 runtime_ctrl
|= burst_sizes
[i
].reg
;
1331 dev_dbg(COHC_2_DEV(cohc
),
1332 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1333 burst_sizes
[i
].burst_8bit
, addr_width
, maxburst
);
1335 cohc
->runtime_addr
= addr
;
1336 cohc
->runtime_ctrl
= runtime_ctrl
;
1340 coh901318_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1343 unsigned long flags
;
1344 struct coh901318_chan
*cohc
= to_coh901318_chan(chan
);
1345 struct coh901318_desc
*cohd
;
1346 void __iomem
*virtbase
= cohc
->base
->virtbase
;
1348 if (cmd
== DMA_SLAVE_CONFIG
) {
1349 struct dma_slave_config
*config
=
1350 (struct dma_slave_config
*) arg
;
1352 coh901318_dma_set_runtimeconfig(chan
, config
);
1356 if (cmd
== DMA_PAUSE
) {
1357 coh901318_pause(chan
);
1361 if (cmd
== DMA_RESUME
) {
1362 coh901318_resume(chan
);
1366 if (cmd
!= DMA_TERMINATE_ALL
)
1369 /* The remainder of this function terminates the transfer */
1370 coh901318_pause(chan
);
1371 spin_lock_irqsave(&cohc
->lock
, flags
);
1373 /* Clear any pending BE or TC interrupt */
1374 if (cohc
->id
< 32) {
1375 writel(1 << cohc
->id
, virtbase
+ COH901318_BE_INT_CLEAR1
);
1376 writel(1 << cohc
->id
, virtbase
+ COH901318_TC_INT_CLEAR1
);
1378 writel(1 << (cohc
->id
- 32), virtbase
+
1379 COH901318_BE_INT_CLEAR2
);
1380 writel(1 << (cohc
->id
- 32), virtbase
+
1381 COH901318_TC_INT_CLEAR2
);
1384 enable_powersave(cohc
);
1386 while ((cohd
= coh901318_first_active_get(cohc
))) {
1387 /* release the lli allocation*/
1388 coh901318_lli_free(&cohc
->base
->pool
, &cohd
->lli
);
1390 /* return desc to free-list */
1391 coh901318_desc_remove(cohd
);
1392 coh901318_desc_free(cohc
, cohd
);
1395 while ((cohd
= coh901318_first_queued(cohc
))) {
1396 /* release the lli allocation*/
1397 coh901318_lli_free(&cohc
->base
->pool
, &cohd
->lli
);
1399 /* return desc to free-list */
1400 coh901318_desc_remove(cohd
);
1401 coh901318_desc_free(cohc
, cohd
);
1405 cohc
->nbr_active_done
= 0;
1408 spin_unlock_irqrestore(&cohc
->lock
, flags
);
1413 void coh901318_base_init(struct dma_device
*dma
, const int *pick_chans
,
1414 struct coh901318_base
*base
)
1418 struct coh901318_chan
*cohc
;
1420 INIT_LIST_HEAD(&dma
->channels
);
1422 for (chans_i
= 0; pick_chans
[chans_i
] != -1; chans_i
+= 2) {
1423 for (i
= pick_chans
[chans_i
]; i
<= pick_chans
[chans_i
+1]; i
++) {
1424 cohc
= &base
->chans
[i
];
1427 cohc
->chan
.device
= dma
;
1430 /* TODO: do we really need this lock if only one
1431 * client is connected to each channel?
1434 spin_lock_init(&cohc
->lock
);
1436 cohc
->nbr_active_done
= 0;
1438 INIT_LIST_HEAD(&cohc
->free
);
1439 INIT_LIST_HEAD(&cohc
->active
);
1440 INIT_LIST_HEAD(&cohc
->queue
);
1442 tasklet_init(&cohc
->tasklet
, dma_tasklet
,
1443 (unsigned long) cohc
);
1445 list_add_tail(&cohc
->chan
.device_node
,
1451 static int __init
coh901318_probe(struct platform_device
*pdev
)
1454 struct coh901318_platform
*pdata
;
1455 struct coh901318_base
*base
;
1457 struct resource
*io
;
1459 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1461 goto err_get_resource
;
1463 /* Map DMA controller registers to virtual memory */
1464 if (request_mem_region(io
->start
,
1466 pdev
->dev
.driver
->name
) == NULL
) {
1468 goto err_request_mem
;
1471 pdata
= pdev
->dev
.platform_data
;
1473 goto err_no_platformdata
;
1475 base
= kmalloc(ALIGN(sizeof(struct coh901318_base
), 4) +
1476 pdata
->max_channels
*
1477 sizeof(struct coh901318_chan
),
1480 goto err_alloc_coh_dma_channels
;
1482 base
->chans
= ((void *)base
) + ALIGN(sizeof(struct coh901318_base
), 4);
1484 base
->virtbase
= ioremap(io
->start
, resource_size(io
));
1485 if (!base
->virtbase
) {
1487 goto err_no_ioremap
;
1490 base
->dev
= &pdev
->dev
;
1491 base
->platform
= pdata
;
1492 spin_lock_init(&base
->pm
.lock
);
1493 base
->pm
.started_channels
= 0;
1495 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base
, base
);
1497 platform_set_drvdata(pdev
, base
);
1499 irq
= platform_get_irq(pdev
, 0);
1503 err
= request_irq(irq
, dma_irq_handler
, IRQF_DISABLED
,
1506 dev_crit(&pdev
->dev
,
1507 "Cannot allocate IRQ for DMA controller!\n");
1508 goto err_request_irq
;
1511 err
= coh901318_pool_create(&base
->pool
, &pdev
->dev
,
1512 sizeof(struct coh901318_lli
),
1515 goto err_pool_create
;
1517 /* init channels for device transfers */
1518 coh901318_base_init(&base
->dma_slave
, base
->platform
->chans_slave
,
1521 dma_cap_zero(base
->dma_slave
.cap_mask
);
1522 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
1524 base
->dma_slave
.device_alloc_chan_resources
= coh901318_alloc_chan_resources
;
1525 base
->dma_slave
.device_free_chan_resources
= coh901318_free_chan_resources
;
1526 base
->dma_slave
.device_prep_slave_sg
= coh901318_prep_slave_sg
;
1527 base
->dma_slave
.device_tx_status
= coh901318_tx_status
;
1528 base
->dma_slave
.device_issue_pending
= coh901318_issue_pending
;
1529 base
->dma_slave
.device_control
= coh901318_control
;
1530 base
->dma_slave
.dev
= &pdev
->dev
;
1532 err
= dma_async_device_register(&base
->dma_slave
);
1535 goto err_register_slave
;
1537 /* init channels for memcpy */
1538 coh901318_base_init(&base
->dma_memcpy
, base
->platform
->chans_memcpy
,
1541 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
1542 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
1544 base
->dma_memcpy
.device_alloc_chan_resources
= coh901318_alloc_chan_resources
;
1545 base
->dma_memcpy
.device_free_chan_resources
= coh901318_free_chan_resources
;
1546 base
->dma_memcpy
.device_prep_dma_memcpy
= coh901318_prep_memcpy
;
1547 base
->dma_memcpy
.device_tx_status
= coh901318_tx_status
;
1548 base
->dma_memcpy
.device_issue_pending
= coh901318_issue_pending
;
1549 base
->dma_memcpy
.device_control
= coh901318_control
;
1550 base
->dma_memcpy
.dev
= &pdev
->dev
;
1552 * This controller can only access address at even 32bit boundaries,
1555 base
->dma_memcpy
.copy_align
= 2;
1556 err
= dma_async_device_register(&base
->dma_memcpy
);
1559 goto err_register_memcpy
;
1561 dev_info(&pdev
->dev
, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1562 (u32
) base
->virtbase
);
1566 err_register_memcpy
:
1567 dma_async_device_unregister(&base
->dma_slave
);
1569 coh901318_pool_destroy(&base
->pool
);
1571 free_irq(platform_get_irq(pdev
, 0), base
);
1574 iounmap(base
->virtbase
);
1577 err_alloc_coh_dma_channels
:
1578 err_no_platformdata
:
1579 release_mem_region(pdev
->resource
->start
,
1580 resource_size(pdev
->resource
));
1586 static int __exit
coh901318_remove(struct platform_device
*pdev
)
1588 struct coh901318_base
*base
= platform_get_drvdata(pdev
);
1590 dma_async_device_unregister(&base
->dma_memcpy
);
1591 dma_async_device_unregister(&base
->dma_slave
);
1592 coh901318_pool_destroy(&base
->pool
);
1593 free_irq(platform_get_irq(pdev
, 0), base
);
1594 iounmap(base
->virtbase
);
1596 release_mem_region(pdev
->resource
->start
,
1597 resource_size(pdev
->resource
));
1602 static struct platform_driver coh901318_driver
= {
1603 .remove
= __exit_p(coh901318_remove
),
1605 .name
= "coh901318",
1609 int __init
coh901318_init(void)
1611 return platform_driver_probe(&coh901318_driver
, coh901318_probe
);
1613 arch_initcall(coh901318_init
);
1615 void __exit
coh901318_exit(void)
1617 platform_driver_unregister(&coh901318_driver
);
1619 module_exit(coh901318_exit
);
1621 MODULE_LICENSE("GPL");
1622 MODULE_AUTHOR("Per Friden");