2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/sysdev.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
29 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
35 #include <asm/pmac_feature.h>
49 /* Default addresses */
50 static volatile struct pmac_irq_hw __iomem
*pmac_irq_hw
[4];
52 #define GC_LEVEL_MASK 0x3ff00000
53 #define OHARE_LEVEL_MASK 0x1ff00000
54 #define HEATHROW_LEVEL_MASK 0x1ff00000
57 static int max_real_irqs
;
58 static u32 level_mask
[4];
60 static DEFINE_SPINLOCK(pmac_pic_lock
);
62 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
63 static unsigned long ppc_lost_interrupts
[NR_MASK_WORDS
];
64 static unsigned long ppc_cached_irq_mask
[NR_MASK_WORDS
];
65 static int pmac_irq_cascade
= -1;
66 static struct irq_host
*pmac_pic_host
;
68 static void __pmac_retrigger(unsigned int irq_nr
)
70 if (irq_nr
>= max_real_irqs
&& pmac_irq_cascade
> 0) {
71 __set_bit(irq_nr
, ppc_lost_interrupts
);
72 irq_nr
= pmac_irq_cascade
;
75 if (!__test_and_set_bit(irq_nr
, ppc_lost_interrupts
)) {
76 atomic_inc(&ppc_n_lost_interrupts
);
81 static void pmac_mask_and_ack_irq(unsigned int virq
)
83 unsigned int src
= irq_map
[virq
].hwirq
;
84 unsigned long bit
= 1UL << (src
& 0x1f);
88 spin_lock_irqsave(&pmac_pic_lock
, flags
);
89 __clear_bit(src
, ppc_cached_irq_mask
);
90 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
91 atomic_dec(&ppc_n_lost_interrupts
);
92 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
93 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
95 /* make sure ack gets to controller before we enable
98 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
99 != (ppc_cached_irq_mask
[i
] & bit
));
100 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
103 static void pmac_ack_irq(unsigned int virq
)
105 unsigned int src
= irq_map
[virq
].hwirq
;
106 unsigned long bit
= 1UL << (src
& 0x1f);
110 spin_lock_irqsave(&pmac_pic_lock
, flags
);
111 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
112 atomic_dec(&ppc_n_lost_interrupts
);
113 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
114 (void)in_le32(&pmac_irq_hw
[i
]->ack
);
115 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
118 static void __pmac_set_irq_mask(unsigned int irq_nr
, int nokicklost
)
120 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
123 if ((unsigned)irq_nr
>= max_irqs
)
126 /* enable unmasked interrupts */
127 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
130 /* make sure mask gets to controller before we
133 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
134 != (ppc_cached_irq_mask
[i
] & bit
));
137 * Unfortunately, setting the bit in the enable register
138 * when the device interrupt is already on *doesn't* set
139 * the bit in the flag register or request another interrupt.
141 if (bit
& ppc_cached_irq_mask
[i
] & in_le32(&pmac_irq_hw
[i
]->level
))
142 __pmac_retrigger(irq_nr
);
145 /* When an irq gets requested for the first client, if it's an
146 * edge interrupt, we clear any previous one on the controller
148 static unsigned int pmac_startup_irq(unsigned int virq
)
151 unsigned int src
= irq_map
[virq
].hwirq
;
152 unsigned long bit
= 1UL << (src
& 0x1f);
155 spin_lock_irqsave(&pmac_pic_lock
, flags
);
156 if ((irq_desc
[virq
].status
& IRQ_LEVEL
) == 0)
157 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
158 __set_bit(src
, ppc_cached_irq_mask
);
159 __pmac_set_irq_mask(src
, 0);
160 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
165 static void pmac_mask_irq(unsigned int virq
)
168 unsigned int src
= irq_map
[virq
].hwirq
;
170 spin_lock_irqsave(&pmac_pic_lock
, flags
);
171 __clear_bit(src
, ppc_cached_irq_mask
);
172 __pmac_set_irq_mask(src
, 1);
173 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
176 static void pmac_unmask_irq(unsigned int virq
)
179 unsigned int src
= irq_map
[virq
].hwirq
;
181 spin_lock_irqsave(&pmac_pic_lock
, flags
);
182 __set_bit(src
, ppc_cached_irq_mask
);
183 __pmac_set_irq_mask(src
, 0);
184 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
187 static int pmac_retrigger(unsigned int virq
)
191 spin_lock_irqsave(&pmac_pic_lock
, flags
);
192 __pmac_retrigger(irq_map
[virq
].hwirq
);
193 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
197 static struct irq_chip pmac_pic
= {
198 .typename
= " PMAC-PIC ",
199 .startup
= pmac_startup_irq
,
200 .mask
= pmac_mask_irq
,
202 .mask_ack
= pmac_mask_and_ack_irq
,
203 .unmask
= pmac_unmask_irq
,
204 .retrigger
= pmac_retrigger
,
207 static irqreturn_t
gatwick_action(int cpl
, void *dev_id
)
213 spin_lock_irqsave(&pmac_pic_lock
, flags
);
214 for (irq
= max_irqs
; (irq
-= 32) >= max_real_irqs
; ) {
216 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
217 /* We must read level interrupts from the level register */
218 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
219 bits
&= ppc_cached_irq_mask
[i
];
222 irq
+= __ilog2(bits
);
223 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
225 spin_lock_irqsave(&pmac_pic_lock
, flags
);
228 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
232 static unsigned int pmac_pic_get_irq(void)
235 unsigned long bits
= 0;
239 void psurge_smp_message_recv(void);
241 /* IPI's are a hack on the powersurge -- Cort */
242 if ( smp_processor_id() != 0 ) {
243 psurge_smp_message_recv();
244 return NO_IRQ_IGNORE
; /* ignore, already handled */
246 #endif /* CONFIG_SMP */
247 spin_lock_irqsave(&pmac_pic_lock
, flags
);
248 for (irq
= max_real_irqs
; (irq
-= 32) >= 0; ) {
250 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
251 /* We must read level interrupts from the level register */
252 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
253 bits
&= ppc_cached_irq_mask
[i
];
256 irq
+= __ilog2(bits
);
259 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
260 if (unlikely(irq
< 0))
262 return irq_linear_revmap(pmac_pic_host
, irq
);
266 static struct irqaction xmon_action
= {
269 .mask
= CPU_MASK_NONE
,
274 static struct irqaction gatwick_cascade_action
= {
275 .handler
= gatwick_action
,
276 .flags
= IRQF_DISABLED
,
277 .mask
= CPU_MASK_NONE
,
281 static int pmac_pic_host_match(struct irq_host
*h
, struct device_node
*node
)
283 /* We match all, we don't always have a node anyway */
287 static int pmac_pic_host_map(struct irq_host
*h
, unsigned int virq
,
290 struct irq_desc
*desc
= get_irq_desc(virq
);
296 /* Mark level interrupts, set delayed disable for edge ones and set
299 level
= !!(level_mask
[hw
>> 5] & (1UL << (hw
& 0x1f)));
301 desc
->status
|= IRQ_LEVEL
;
302 set_irq_chip_and_handler(virq
, &pmac_pic
, level
?
303 handle_level_irq
: handle_edge_irq
);
307 static int pmac_pic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
308 u32
*intspec
, unsigned int intsize
,
309 irq_hw_number_t
*out_hwirq
,
310 unsigned int *out_flags
)
313 *out_flags
= IRQ_TYPE_NONE
;
314 *out_hwirq
= *intspec
;
318 static struct irq_host_ops pmac_pic_host_ops
= {
319 .match
= pmac_pic_host_match
,
320 .map
= pmac_pic_host_map
,
321 .xlate
= pmac_pic_host_xlate
,
324 static void __init
pmac_pic_probe_oldstyle(void)
327 struct device_node
*master
= NULL
;
328 struct device_node
*slave
= NULL
;
332 /* Set our get_irq function */
333 ppc_md
.get_irq
= pmac_pic_get_irq
;
336 * Find the interrupt controller type & node
339 if ((master
= of_find_node_by_name(NULL
, "gc")) != NULL
) {
340 max_irqs
= max_real_irqs
= 32;
341 level_mask
[0] = GC_LEVEL_MASK
;
342 } else if ((master
= of_find_node_by_name(NULL
, "ohare")) != NULL
) {
343 max_irqs
= max_real_irqs
= 32;
344 level_mask
[0] = OHARE_LEVEL_MASK
;
346 /* We might have a second cascaded ohare */
347 slave
= of_find_node_by_name(NULL
, "pci106b,7");
350 level_mask
[1] = OHARE_LEVEL_MASK
;
352 } else if ((master
= of_find_node_by_name(NULL
, "mac-io")) != NULL
) {
353 max_irqs
= max_real_irqs
= 64;
354 level_mask
[0] = HEATHROW_LEVEL_MASK
;
357 /* We might have a second cascaded heathrow */
358 slave
= of_find_node_by_name(master
, "mac-io");
360 /* Check ordering of master & slave */
361 if (of_device_is_compatible(master
, "gatwick")) {
362 struct device_node
*tmp
;
363 BUG_ON(slave
== NULL
);
369 /* We found a slave */
372 level_mask
[2] = HEATHROW_LEVEL_MASK
;
376 BUG_ON(master
== NULL
);
379 * Allocate an irq host
381 pmac_pic_host
= irq_alloc_host(master
, IRQ_HOST_MAP_LINEAR
, max_irqs
,
384 BUG_ON(pmac_pic_host
== NULL
);
385 irq_set_default_host(pmac_pic_host
);
387 /* Get addresses of first controller if we have a node for it */
388 BUG_ON(of_address_to_resource(master
, 0, &r
));
390 /* Map interrupts of primary controller */
391 addr
= (u8 __iomem
*) ioremap(r
.start
, 0x40);
393 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
395 if (max_real_irqs
> 32)
396 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
400 printk(KERN_INFO
"irq: Found primary Apple PIC %s for %d irqs\n",
401 master
->full_name
, max_real_irqs
);
403 /* Map interrupts of cascaded controller */
404 if (slave
&& !of_address_to_resource(slave
, 0, &r
)) {
405 addr
= (u8 __iomem
*)ioremap(r
.start
, 0x40);
406 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
410 (volatile struct pmac_irq_hw __iomem
*)
412 pmac_irq_cascade
= irq_of_parse_and_map(slave
, 0);
414 printk(KERN_INFO
"irq: Found slave Apple PIC %s for %d irqs"
415 " cascade: %d\n", slave
->full_name
,
416 max_irqs
- max_real_irqs
, pmac_irq_cascade
);
420 /* Disable all interrupts in all controllers */
421 for (i
= 0; i
* 32 < max_irqs
; ++i
)
422 out_le32(&pmac_irq_hw
[i
]->enable
, 0);
424 /* Hookup cascade irq */
425 if (slave
&& pmac_irq_cascade
!= NO_IRQ
)
426 setup_irq(pmac_irq_cascade
, &gatwick_cascade_action
);
428 printk(KERN_INFO
"irq: System has %d possible interrupts\n", max_irqs
);
430 setup_irq(irq_create_mapping(NULL
, 20), &xmon_action
);
433 #endif /* CONFIG_PPC32 */
435 static void pmac_u3_cascade(unsigned int irq
, struct irq_desc
*desc
)
437 struct mpic
*mpic
= desc
->handler_data
;
439 unsigned int cascade_irq
= mpic_get_one_irq(mpic
);
440 if (cascade_irq
!= NO_IRQ
)
441 generic_handle_irq(cascade_irq
);
442 desc
->chip
->eoi(irq
);
445 static void __init
pmac_pic_setup_mpic_nmi(struct mpic
*mpic
)
447 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
448 struct device_node
* pswitch
;
451 pswitch
= of_find_node_by_name(NULL
, "programmer-switch");
453 nmi_irq
= irq_of_parse_and_map(pswitch
, 0);
454 if (nmi_irq
!= NO_IRQ
) {
455 mpic_irq_set_priority(nmi_irq
, 9);
456 setup_irq(nmi_irq
, &xmon_action
);
458 of_node_put(pswitch
);
460 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
463 static struct mpic
* __init
pmac_setup_one_mpic(struct device_node
*np
,
466 const char *name
= master
? " MPIC 1 " : " MPIC 2 ";
469 unsigned int flags
= master
? MPIC_PRIMARY
: 0;
472 rc
= of_address_to_resource(np
, 0, &r
);
476 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, np
, 0, 0);
478 flags
|= MPIC_WANTS_RESET
;
479 if (of_get_property(np
, "big-endian", NULL
))
480 flags
|= MPIC_BIG_ENDIAN
;
482 /* Primary Big Endian means HT interrupts. This is quite dodgy
483 * but works until I find a better way
485 if (master
&& (flags
& MPIC_BIG_ENDIAN
))
486 flags
|= MPIC_U3_HT_IRQS
;
488 mpic
= mpic_alloc(np
, r
.start
, flags
, 0, 0, name
);
497 static int __init
pmac_pic_probe_mpic(void)
499 struct mpic
*mpic1
, *mpic2
;
500 struct device_node
*np
, *master
= NULL
, *slave
= NULL
;
501 unsigned int cascade
;
503 /* We can have up to 2 MPICs cascaded */
504 for (np
= NULL
; (np
= of_find_node_by_type(np
, "open-pic"))
506 if (master
== NULL
&&
507 of_get_property(np
, "interrupts", NULL
) == NULL
)
508 master
= of_node_get(np
);
509 else if (slave
== NULL
)
510 slave
= of_node_get(np
);
515 /* Check for bogus setups */
516 if (master
== NULL
&& slave
!= NULL
) {
521 /* Not found, default to good old pmac pic */
525 /* Set master handler */
526 ppc_md
.get_irq
= mpic_get_irq
;
529 mpic1
= pmac_setup_one_mpic(master
, 1);
530 BUG_ON(mpic1
== NULL
);
532 /* Install NMI if any */
533 pmac_pic_setup_mpic_nmi(mpic1
);
537 /* No slave, let's go out */
541 /* Get/Map slave interrupt */
542 cascade
= irq_of_parse_and_map(slave
, 0);
543 if (cascade
== NO_IRQ
) {
544 printk(KERN_ERR
"Failed to map cascade IRQ\n");
548 mpic2
= pmac_setup_one_mpic(slave
, 0);
550 printk(KERN_ERR
"Failed to setup slave MPIC\n");
554 set_irq_data(cascade
, mpic2
);
555 set_irq_chained_handler(cascade
, pmac_u3_cascade
);
562 void __init
pmac_pic_init(void)
564 unsigned int flags
= 0;
566 /* We configure the OF parsing based on our oldworld vs. newworld
567 * platform type and wether we were booted by BootX.
571 flags
|= OF_IMAP_OLDWORLD_MAC
;
572 if (of_get_property(of_chosen
, "linux,bootx", NULL
) != NULL
)
573 flags
|= OF_IMAP_NO_PHANDLE
;
574 #endif /* CONFIG_PPC_32 */
576 of_irq_map_init(flags
);
578 /* We first try to detect Apple's new Core99 chipset, since mac-io
579 * is quite different on those machines and contains an IBM MPIC2.
581 if (pmac_pic_probe_mpic() == 0)
585 pmac_pic_probe_oldstyle();
589 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
591 * These procedures are used in implementing sleep on the powerbooks.
592 * sleep_save_intrs() saves the states of all interrupt enables
593 * and disables all interrupts except for the nominated one.
594 * sleep_restore_intrs() restores the states of all interrupt enables.
596 unsigned long sleep_save_mask
[2];
598 /* This used to be passed by the PMU driver but that link got
599 * broken with the new driver model. We use this tweak for now...
600 * We really want to do things differently though...
602 static int pmacpic_find_viaint(void)
606 #ifdef CONFIG_ADB_PMU
607 struct device_node
*np
;
609 if (pmu_get_model() != PMU_OHARE_BASED
)
611 np
= of_find_node_by_name(NULL
, "via-pmu");
614 viaint
= irq_of_parse_and_map(np
, 0);;
617 #endif /* CONFIG_ADB_PMU */
621 static int pmacpic_suspend(struct sys_device
*sysdev
, pm_message_t state
)
623 int viaint
= pmacpic_find_viaint();
625 sleep_save_mask
[0] = ppc_cached_irq_mask
[0];
626 sleep_save_mask
[1] = ppc_cached_irq_mask
[1];
627 ppc_cached_irq_mask
[0] = 0;
628 ppc_cached_irq_mask
[1] = 0;
630 set_bit(viaint
, ppc_cached_irq_mask
);
631 out_le32(&pmac_irq_hw
[0]->enable
, ppc_cached_irq_mask
[0]);
632 if (max_real_irqs
> 32)
633 out_le32(&pmac_irq_hw
[1]->enable
, ppc_cached_irq_mask
[1]);
634 (void)in_le32(&pmac_irq_hw
[0]->event
);
635 /* make sure mask gets to controller before we return to caller */
637 (void)in_le32(&pmac_irq_hw
[0]->enable
);
642 static int pmacpic_resume(struct sys_device
*sysdev
)
646 out_le32(&pmac_irq_hw
[0]->enable
, 0);
647 if (max_real_irqs
> 32)
648 out_le32(&pmac_irq_hw
[1]->enable
, 0);
650 for (i
= 0; i
< max_real_irqs
; ++i
)
651 if (test_bit(i
, sleep_save_mask
))
657 #endif /* CONFIG_PM && CONFIG_PPC32 */
659 static struct sysdev_class pmacpic_sysclass
= {
663 static struct sys_device device_pmacpic
= {
665 .cls
= &pmacpic_sysclass
,
668 static struct sysdev_driver driver_pmacpic
= {
669 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
670 .suspend
= &pmacpic_suspend
,
671 .resume
= &pmacpic_resume
,
672 #endif /* CONFIG_PM && CONFIG_PPC32 */
675 static int __init
init_pmacpic_sysfs(void)
681 printk(KERN_DEBUG
"Registering pmac pic with sysfs...\n");
682 sysdev_class_register(&pmacpic_sysclass
);
683 sysdev_register(&device_pmacpic
);
684 sysdev_driver_register(&pmacpic_sysclass
, &driver_pmacpic
);
687 machine_subsys_initcall(powermac
, init_pmacpic_sysfs
);