include/asm-v850/me2.h

   1 /*
   2  * include/asm-v850/me2.h -- V850E/ME2 cpu chip
   3  *
   4  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
   5  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General
   8  * Public License.  See the file COPYING in the main directory of this
   9  * archive for more details.
  10  *
  11  * Written by Miles Bader <miles@gnu.org>
  12  */
  13
  14 #ifndef __V850_ME2_H__
  15 #define __V850_ME2_H__
  16
  17 #include <asm/v850e.h>
  18 #include <asm/v850e_cache.h>
  19
  20
  21 #define CPU_MODEL       "v850e/me2"
  22 #define CPU_MODEL_LONG  "NEC V850E/ME2"
  23
  24
  25 /* Hardware-specific interrupt numbers (in the kernel IRQ namespace).  */
  26 #define IRQ_INTP(n)       (n) /* Pnnn (pin) interrupts */
  27 #define IRQ_INTP_NUM      31
  28 #define IRQ_INTCMD(n)     (0x31 + (n)) /* interval timer interrupts 0-3 */
  29 #define IRQ_INTCMD_NUM    4
  30 #define IRQ_INTDMA(n)     (0x41 + (n)) /* DMA interrupts 0-3 */
  31 #define IRQ_INTDMA_NUM    4
  32 #define IRQ_INTUBTIRE(n)  (0x49 + (n)*5)/* UARTB 0-1 reception error */
  33 #define IRQ_INTUBTIRE_NUM 2
  34 #define IRQ_INTUBTIR(n)   (0x4a + (n)*5) /* UARTB 0-1 reception complete */
  35 #define IRQ_INTUBTIR_NUM  2
  36 #define IRQ_INTUBTIT(n)   (0x4b + (n)*5) /* UARTB 0-1 transmission complete */
  37 #define IRQ_INTUBTIT_NUM  2
  38 #define IRQ_INTUBTIF(n)   (0x4c + (n)*5) /* UARTB 0-1 FIFO trans. complete */
  39 #define IRQ_INTUBTIF_NUM  2
  40 #define IRQ_INTUBTITO(n)  (0x4d + (n)*5) /* UARTB 0-1 reception timeout */
  41 #define IRQ_INTUBTITO_NUM 2
  42
  43 /* For <asm/irq.h> */
  44 #define NUM_CPU_IRQS            0x59 /* V850E/ME2 */
  45
  46
  47 /* For <asm/entry.h> */
  48 /* We use on-chip RAM, for a few miscellaneous variables that must be
  49    accessible using a load instruction relative to R0.  */
  50 #define R0_RAM_ADDR                     0xFFFFB000 /* V850E/ME2 */
  51
  52
  53 /* V850E/ME2 UARTB details.*/
  54 #define V850E_UART_NUM_CHANNELS         2
  55 #define V850E_UARTB_BASE_FREQ           (CPU_CLOCK_FREQ / 4)
  56
  57 /* This is a function that gets called before configuring the UART.  */
  58 #define V850E_UART_PRE_CONFIGURE        me2_uart_pre_configure
  59 #ifndef __ASSEMBLY__
  60 extern void me2_uart_pre_configure (unsigned chan,
  61                                     unsigned cflags, unsigned baud);
  62 #endif /* __ASSEMBLY__ */
  63
  64
  65 /* V850E/ME2 timer C details.  */
  66 #define V850E_TIMER_C_BASE_ADDR         0xFFFFF600
  67
  68
  69 /* V850E/ME2 timer D details.  */
  70 #define V850E_TIMER_D_BASE_ADDR         0xFFFFF540
  71 #define V850E_TIMER_D_TMD_BASE_ADDR     (V850E_TIMER_D_BASE_ADDR + 0x0)
  72 #define V850E_TIMER_D_CMD_BASE_ADDR     (V850E_TIMER_D_BASE_ADDR + 0x2)
  73 #define V850E_TIMER_D_TMCD_BASE_ADDR    (V850E_TIMER_D_BASE_ADDR + 0x4)
  74
  75 #define V850E_TIMER_D_BASE_FREQ         (CPU_CLOCK_FREQ / 2)
  76
  77
  78 /* Select iRAM mode.  */
  79 #define ME2_IRAMM_ADDR                  0xFFFFF80A
  80 #define ME2_IRAMM                       (*(volatile u8*)ME2_IRAMM_ADDR)
  81
  82
  83 /* Interrupt edge-detection configuration.  INTF(n) and INTR(n) are only
  84    valid for n == 1, 2, or 5.  */
  85 #define ME2_INTF_ADDR(n)                (0xFFFFFC00 + (n) * 0x2)
  86 #define ME2_INTF(n)                     (*(volatile u8*)ME2_INTF_ADDR(n))
  87 #define ME2_INTR_ADDR(n)                (0xFFFFFC20 + (n) * 0x2)
  88 #define ME2_INTR(n)                     (*(volatile u8*)ME2_INTR_ADDR(n))
  89 #define ME2_INTFAL_ADDR                 0xFFFFFC10
  90 #define ME2_INTFAL                      (*(volatile u8*)ME2_INTFAL_ADDR)
  91 #define ME2_INTRAL_ADDR                 0xFFFFFC30
  92 #define ME2_INTRAL                      (*(volatile u8*)ME2_INTRAL_ADDR)
  93 #define ME2_INTFDH_ADDR                 0xFFFFFC16
  94 #define ME2_INTFDH                      (*(volatile u16*)ME2_INTFDH_ADDR)
  95 #define ME2_INTRDH_ADDR                 0xFFFFFC36
  96 #define ME2_INTRDH                      (*(volatile u16*)ME2_INTRDH_ADDR)
  97 #define ME2_SESC_ADDR(n)                (0xFFFFF609 + (n) * 0x10)
  98 #define ME2_SESC(n)                     (*(volatile u8*)ME2_SESC_ADDR(n))
  99 #define ME2_SESA10_ADDR                 0xFFFFF5AD
 100 #define ME2_SESA10                      (*(volatile u8*)ME2_SESA10_ADDR)
 101 #define ME2_SESA11_ADDR                 0xFFFFF5DD
 102 #define ME2_SESA11                      (*(volatile u8*)ME2_SESA11_ADDR)
 103
 104
 105 /* Port 1 */
 106 /* Direct I/O.  Bits 0-3 are pins P10-P13.  */
 107 #define ME2_PORT1_IO_ADDR               0xFFFFF402
 108 #define ME2_PORT1_IO                    (*(volatile u8 *)ME2_PORT1_IO_ADDR)
 109 /* Port mode (for direct I/O, 0 = output, 1 = input).  */
 110 #define ME2_PORT1_PM_ADDR               0xFFFFF422
 111 #define ME2_PORT1_PM                    (*(volatile u8 *)ME2_PORT1_PM_ADDR)
 112 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode).  */
 113 #define ME2_PORT1_PMC_ADDR              0xFFFFF442
 114 #define ME2_PORT1_PMC                   (*(volatile u8 *)ME2_PORT1_PMC_ADDR)
 115 /* Port function control (for serial interfaces, 0 = CSI30, 1 = UARTB0 ).  */
 116 #define ME2_PORT1_PFC_ADDR              0xFFFFF462
 117 #define ME2_PORT1_PFC                   (*(volatile u8 *)ME2_PORT1_PFC_ADDR)
 118
 119 /* Port 2 */
 120 /* Direct I/O.  Bits 0-3 are pins P20-P25.  */
 121 #define ME2_PORT2_IO_ADDR               0xFFFFF404
 122 #define ME2_PORT2_IO                    (*(volatile u8 *)ME2_PORT2_IO_ADDR)
 123 /* Port mode (for direct I/O, 0 = output, 1 = input).  */
 124 #define ME2_PORT2_PM_ADDR               0xFFFFF424
 125 #define ME2_PORT2_PM                    (*(volatile u8 *)ME2_PORT2_PM_ADDR)
 126 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode).  */
 127 #define ME2_PORT2_PMC_ADDR              0xFFFFF444
 128 #define ME2_PORT2_PMC                   (*(volatile u8 *)ME2_PORT2_PMC_ADDR)
 129 /* Port function control (for serial interfaces, 0 = INTP2x, 1 = UARTB1 ).  */
 130 #define ME2_PORT2_PFC_ADDR              0xFFFFF464
 131 #define ME2_PORT2_PFC                   (*(volatile u8 *)ME2_PORT2_PFC_ADDR)
 132
 133 /* Port 5 */
 134 /* Direct I/O.  Bits 0-5 are pins P50-P55.  */
 135 #define ME2_PORT5_IO_ADDR               0xFFFFF40A
 136 #define ME2_PORT5_IO                    (*(volatile u8 *)ME2_PORT5_IO_ADDR)
 137 /* Port mode (for direct I/O, 0 = output, 1 = input).  */
 138 #define ME2_PORT5_PM_ADDR               0xFFFFF42A
 139 #define ME2_PORT5_PM                    (*(volatile u8 *)ME2_PORT5_PM_ADDR)
 140 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode).  */
 141 #define ME2_PORT5_PMC_ADDR              0xFFFFF44A
 142 #define ME2_PORT5_PMC                   (*(volatile u8 *)ME2_PORT5_PMC_ADDR)
 143 /* Port function control ().  */
 144 #define ME2_PORT5_PFC_ADDR              0xFFFFF46A
 145 #define ME2_PORT5_PFC                   (*(volatile u8 *)ME2_PORT5_PFC_ADDR)
 146
 147 /* Port 6 */
 148 /* Direct I/O.  Bits 5-7 are pins P65-P67.  */
 149 #define ME2_PORT6_IO_ADDR               0xFFFFF40C
 150 #define ME2_PORT6_IO                    (*(volatile u8 *)ME2_PORT6_IO_ADDR)
 151 /* Port mode (for direct I/O, 0 = output, 1 = input).  */
 152 #define ME2_PORT6_PM_ADDR               0xFFFFF42C
 153 #define ME2_PORT6_PM                    (*(volatile u8 *)ME2_PORT6_PM_ADDR)
 154 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode).  */
 155 #define ME2_PORT6_PMC_ADDR              0xFFFFF44C
 156 #define ME2_PORT6_PMC                   (*(volatile u8 *)ME2_PORT6_PMC_ADDR)
 157 /* Port function control ().  */
 158 #define ME2_PORT6_PFC_ADDR              0xFFFFF46C
 159 #define ME2_PORT6_PFC                   (*(volatile u8 *)ME2_PORT6_PFC_ADDR)
 160
 161 /* Port 7 */
 162 /* Direct I/O.  Bits 2-7 are pins P72-P77.  */
 163 #define ME2_PORT7_IO_ADDR               0xFFFFF40E
 164 #define ME2_PORT7_IO                    (*(volatile u8 *)ME2_PORT7_IO_ADDR)
 165 /* Port mode (for direct I/O, 0 = output, 1 = input).  */
 166 #define ME2_PORT7_PM_ADDR               0xFFFFF42E
 167 #define ME2_PORT7_PM                    (*(volatile u8 *)ME2_PORT7_PM_ADDR)
 168 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode).  */
 169 #define ME2_PORT7_PMC_ADDR              0xFFFFF44E
 170 #define ME2_PORT7_PMC                   (*(volatile u8 *)ME2_PORT7_PMC_ADDR)
 171 /* Port function control ().  */
 172 #define ME2_PORT7_PFC_ADDR              0xFFFFF46E
 173 #define ME2_PORT7_PFC                   (*(volatile u8 *)ME2_PORT7_PFC_ADDR)
 174
 175
 176 #ifndef __ASSEMBLY__
 177 /* Initialize V850E/ME2 chip interrupts.  */
 178 extern void me2_init_irqs (void);
 179 #endif /* !__ASSEMBLY__ */
 180
 181
 182 #endif /* __V850_ME2_H__ */