2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
80 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
82 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
84 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
85 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
86 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* 5424 Condor (PCI-E)*/
99 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
102 static struct ath5k_srev_name srev_names
[] = {
103 { "5210", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5210
},
104 { "5311", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311
},
105 { "5311A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311A
},
106 { "5311B", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311B
},
107 { "5211", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5211
},
108 { "5212", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5212
},
109 { "5213", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213
},
110 { "5213A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213A
},
111 { "2413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2413
},
112 { "2414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2414
},
113 { "2424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2424
},
114 { "5424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5424
},
115 { "5413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5413
},
116 { "5414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5414
},
117 { "5416", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5416
},
118 { "5418", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5418
},
119 { "2425", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2425
},
120 { "xxxxx", AR5K_VERSION_VER
, AR5K_SREV_UNKNOWN
},
121 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
122 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
123 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
124 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
125 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
126 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
127 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
128 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC0
},
129 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC1
},
130 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC2
},
131 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
132 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
136 * Prototypes - PCI stack related functions
138 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
139 const struct pci_device_id
*id
);
140 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
142 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
144 static int ath5k_pci_resume(struct pci_dev
*pdev
);
146 #define ath5k_pci_suspend NULL
147 #define ath5k_pci_resume NULL
148 #endif /* CONFIG_PM */
150 static struct pci_driver ath5k_pci_driver
= {
152 .id_table
= ath5k_pci_id_table
,
153 .probe
= ath5k_pci_probe
,
154 .remove
= __devexit_p(ath5k_pci_remove
),
155 .suspend
= ath5k_pci_suspend
,
156 .resume
= ath5k_pci_resume
,
162 * Prototypes - MAC 802.11 stack related functions
164 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
165 static int ath5k_reset(struct ieee80211_hw
*hw
);
166 static int ath5k_start(struct ieee80211_hw
*hw
);
167 static void ath5k_stop(struct ieee80211_hw
*hw
);
168 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
169 struct ieee80211_if_init_conf
*conf
);
170 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
171 struct ieee80211_if_init_conf
*conf
);
172 static int ath5k_config(struct ieee80211_hw
*hw
,
173 struct ieee80211_conf
*conf
);
174 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
175 struct ieee80211_vif
*vif
,
176 struct ieee80211_if_conf
*conf
);
177 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
178 unsigned int changed_flags
,
179 unsigned int *new_flags
,
180 int mc_count
, struct dev_mc_list
*mclist
);
181 static int ath5k_set_key(struct ieee80211_hw
*hw
,
182 enum set_key_cmd cmd
,
183 const u8
*local_addr
, const u8
*addr
,
184 struct ieee80211_key_conf
*key
);
185 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
186 struct ieee80211_low_level_stats
*stats
);
187 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
188 struct ieee80211_tx_queue_stats
*stats
);
189 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
190 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
191 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
192 struct sk_buff
*skb
);
194 static struct ieee80211_ops ath5k_hw_ops
= {
196 .start
= ath5k_start
,
198 .add_interface
= ath5k_add_interface
,
199 .remove_interface
= ath5k_remove_interface
,
200 .config
= ath5k_config
,
201 .config_interface
= ath5k_config_interface
,
202 .configure_filter
= ath5k_configure_filter
,
203 .set_key
= ath5k_set_key
,
204 .get_stats
= ath5k_get_stats
,
206 .get_tx_stats
= ath5k_get_tx_stats
,
207 .get_tsf
= ath5k_get_tsf
,
208 .reset_tsf
= ath5k_reset_tsf
,
212 * Prototypes - Internal functions
215 static int ath5k_attach(struct pci_dev
*pdev
,
216 struct ieee80211_hw
*hw
);
217 static void ath5k_detach(struct pci_dev
*pdev
,
218 struct ieee80211_hw
*hw
);
219 /* Channel/mode setup */
220 static inline short ath5k_ieee2mhz(short chan
);
221 static unsigned int ath5k_copy_rates(struct ieee80211_rate
*rates
,
222 const struct ath5k_rate_table
*rt
,
224 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
225 struct ieee80211_channel
*channels
,
228 static int ath5k_getchannels(struct ieee80211_hw
*hw
);
229 static int ath5k_chan_set(struct ath5k_softc
*sc
,
230 struct ieee80211_channel
*chan
);
231 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
233 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
234 static void ath5k_set_total_hw_rates(struct ath5k_softc
*sc
);
236 /* Descriptor setup */
237 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
238 struct pci_dev
*pdev
);
239 static void ath5k_desc_free(struct ath5k_softc
*sc
,
240 struct pci_dev
*pdev
);
242 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
243 struct ath5k_buf
*bf
);
244 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
245 struct ath5k_buf
*bf
);
246 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
247 struct ath5k_buf
*bf
)
252 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
254 dev_kfree_skb_any(bf
->skb
);
259 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
260 int qtype
, int subtype
);
261 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
262 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
263 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
264 struct ath5k_txq
*txq
);
265 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
266 static void ath5k_txq_release(struct ath5k_softc
*sc
);
268 static int ath5k_rx_start(struct ath5k_softc
*sc
);
269 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
270 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
271 struct ath5k_desc
*ds
,
273 struct ath5k_rx_status
*rs
);
274 static void ath5k_tasklet_rx(unsigned long data
);
276 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
277 struct ath5k_txq
*txq
);
278 static void ath5k_tasklet_tx(unsigned long data
);
279 /* Beacon handling */
280 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
281 struct ath5k_buf
*bf
);
282 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
283 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
284 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
286 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
288 u64 tsf
= ath5k_hw_get_tsf64(ah
);
290 if ((tsf
& 0x7fff) < rstamp
)
293 return (tsf
& ~0x7fff) | rstamp
;
296 /* Interrupt handling */
297 static int ath5k_init(struct ath5k_softc
*sc
);
298 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
299 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
300 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
301 static void ath5k_tasklet_reset(unsigned long data
);
303 static void ath5k_calibrate(unsigned long data
);
305 static int ath5k_init_leds(struct ath5k_softc
*sc
);
306 static void ath5k_led_enable(struct ath5k_softc
*sc
);
307 static void ath5k_led_off(struct ath5k_softc
*sc
);
308 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
311 * Module init/exit functions
320 ret
= pci_register_driver(&ath5k_pci_driver
);
322 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
332 pci_unregister_driver(&ath5k_pci_driver
);
334 ath5k_debug_finish();
337 module_init(init_ath5k_pci
);
338 module_exit(exit_ath5k_pci
);
341 /********************\
342 * PCI Initialization *
343 \********************/
346 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
348 const char *name
= "xxxxx";
351 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
352 if (srev_names
[i
].sr_type
!= type
)
354 if ((val
& 0xff) < srev_names
[i
+ 1].sr_val
) {
355 name
= srev_names
[i
].sr_name
;
364 ath5k_pci_probe(struct pci_dev
*pdev
,
365 const struct pci_device_id
*id
)
368 struct ath5k_softc
*sc
;
369 struct ieee80211_hw
*hw
;
373 ret
= pci_enable_device(pdev
);
375 dev_err(&pdev
->dev
, "can't enable device\n");
379 /* XXX 32-bit addressing only */
380 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
382 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
387 * Cache line size is used to size and align various
388 * structures used to communicate with the hardware.
390 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
393 * Linux 2.4.18 (at least) writes the cache line size
394 * register as a 16-bit wide register which is wrong.
395 * We must have this setup properly for rx buffer
396 * DMA to work so force a reasonable value here if it
399 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
400 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
403 * The default setting of latency timer yields poor results,
404 * set it to the value used by other systems. It may be worth
405 * tweaking this setting more.
407 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
409 /* Enable bus mastering */
410 pci_set_master(pdev
);
413 * Disable the RETRY_TIMEOUT register (0x41) to keep
414 * PCI Tx retries from interfering with C3 CPU state.
416 pci_write_config_byte(pdev
, 0x41, 0);
418 ret
= pci_request_region(pdev
, 0, "ath5k");
420 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
424 mem
= pci_iomap(pdev
, 0, 0);
426 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
432 * Allocate hw (mac80211 main struct)
433 * and hw->priv (driver private data)
435 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
437 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
442 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
444 /* Initialize driver private data */
445 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
446 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
447 IEEE80211_HW_SIGNAL_DBM
|
448 IEEE80211_HW_NOISE_DBM
;
449 hw
->extra_tx_headroom
= 2;
450 hw
->channel_change_time
= 5000;
455 ath5k_debug_init_device(sc
);
458 * Mark the device as detached to avoid processing
459 * interrupts until setup is complete.
461 __set_bit(ATH_STAT_INVALID
, sc
->status
);
463 sc
->iobase
= mem
; /* So we can unmap it on detach */
464 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
465 sc
->opmode
= IEEE80211_IF_TYPE_STA
;
466 mutex_init(&sc
->lock
);
467 spin_lock_init(&sc
->rxbuflock
);
468 spin_lock_init(&sc
->txbuflock
);
469 spin_lock_init(&sc
->block
);
471 /* Set private data */
472 pci_set_drvdata(pdev
, hw
);
474 /* Setup interrupt handler */
475 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
477 ATH5K_ERR(sc
, "request_irq failed\n");
481 /* Initialize device */
482 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
483 if (IS_ERR(sc
->ah
)) {
484 ret
= PTR_ERR(sc
->ah
);
488 /* Finish private driver data initialization */
489 ret
= ath5k_attach(pdev
, hw
);
493 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
494 ath5k_chip_name(AR5K_VERSION_VER
,sc
->ah
->ah_mac_srev
),
496 sc
->ah
->ah_phy_revision
);
498 if (!sc
->ah
->ah_single_chip
) {
499 /* Single chip radio (!RF5111) */
500 if (sc
->ah
->ah_radio_5ghz_revision
&&
501 !sc
->ah
->ah_radio_2ghz_revision
) {
502 /* No 5GHz support -> report 2GHz radio */
503 if (!test_bit(AR5K_MODE_11A
,
504 sc
->ah
->ah_capabilities
.cap_mode
)) {
505 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
506 ath5k_chip_name(AR5K_VERSION_RAD
,
507 sc
->ah
->ah_radio_5ghz_revision
),
508 sc
->ah
->ah_radio_5ghz_revision
);
509 /* No 2GHz support (5110 and some
510 * 5Ghz only cards) -> report 5Ghz radio */
511 } else if (!test_bit(AR5K_MODE_11B
,
512 sc
->ah
->ah_capabilities
.cap_mode
)) {
513 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
514 ath5k_chip_name(AR5K_VERSION_RAD
,
515 sc
->ah
->ah_radio_5ghz_revision
),
516 sc
->ah
->ah_radio_5ghz_revision
);
517 /* Multiband radio */
519 ATH5K_INFO(sc
, "RF%s multiband radio found"
521 ath5k_chip_name(AR5K_VERSION_RAD
,
522 sc
->ah
->ah_radio_5ghz_revision
),
523 sc
->ah
->ah_radio_5ghz_revision
);
526 /* Multi chip radio (RF5111 - RF2111) ->
527 * report both 2GHz/5GHz radios */
528 else if (sc
->ah
->ah_radio_5ghz_revision
&&
529 sc
->ah
->ah_radio_2ghz_revision
){
530 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
531 ath5k_chip_name(AR5K_VERSION_RAD
,
532 sc
->ah
->ah_radio_5ghz_revision
),
533 sc
->ah
->ah_radio_5ghz_revision
);
534 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
535 ath5k_chip_name(AR5K_VERSION_RAD
,
536 sc
->ah
->ah_radio_2ghz_revision
),
537 sc
->ah
->ah_radio_2ghz_revision
);
542 /* ready to process interrupts */
543 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
547 ath5k_hw_detach(sc
->ah
);
549 free_irq(pdev
->irq
, sc
);
551 ieee80211_free_hw(hw
);
553 pci_iounmap(pdev
, mem
);
555 pci_release_region(pdev
, 0);
557 pci_disable_device(pdev
);
562 static void __devexit
563 ath5k_pci_remove(struct pci_dev
*pdev
)
565 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
566 struct ath5k_softc
*sc
= hw
->priv
;
568 ath5k_debug_finish_device(sc
);
569 ath5k_detach(pdev
, hw
);
570 ath5k_hw_detach(sc
->ah
);
571 free_irq(pdev
->irq
, sc
);
572 pci_iounmap(pdev
, sc
->iobase
);
573 pci_release_region(pdev
, 0);
574 pci_disable_device(pdev
);
575 ieee80211_free_hw(hw
);
580 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
582 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
583 struct ath5k_softc
*sc
= hw
->priv
;
589 free_irq(pdev
->irq
, sc
);
590 pci_save_state(pdev
);
591 pci_disable_device(pdev
);
592 pci_set_power_state(pdev
, PCI_D3hot
);
598 ath5k_pci_resume(struct pci_dev
*pdev
)
600 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
601 struct ath5k_softc
*sc
= hw
->priv
;
602 struct ath5k_hw
*ah
= sc
->ah
;
605 pci_restore_state(pdev
);
607 err
= pci_enable_device(pdev
);
612 * Suspend/Resume resets the PCI configuration space, so we have to
613 * re-disable the RETRY_TIMEOUT register (0x41) to keep
614 * PCI Tx retries from interfering with C3 CPU state
616 pci_write_config_byte(pdev
, 0x41, 0);
618 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
620 ATH5K_ERR(sc
, "request_irq failed\n");
624 err
= ath5k_init(sc
);
627 ath5k_led_enable(sc
);
630 * Reset the key cache since some parts do not
631 * reset the contents on initial power up or resume.
633 * FIXME: This may need to be revisited when mac80211 becomes
634 * aware of suspend/resume.
636 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
637 ath5k_hw_reset_key(ah
, i
);
641 free_irq(pdev
->irq
, sc
);
643 pci_disable_device(pdev
);
646 #endif /* CONFIG_PM */
650 /***********************\
651 * Driver Initialization *
652 \***********************/
655 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
657 struct ath5k_softc
*sc
= hw
->priv
;
658 struct ath5k_hw
*ah
= sc
->ah
;
663 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
666 * Check if the MAC has multi-rate retry support.
667 * We do this by trying to setup a fake extended
668 * descriptor. MAC's that don't have support will
669 * return false w/o doing anything. MAC's that do
670 * support it will return true w/o doing anything.
672 ret
= ah
->ah_setup_xtx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
676 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
679 * Reset the key cache since some parts do not
680 * reset the contents on initial power up.
682 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
683 ath5k_hw_reset_key(ah
, i
);
686 * Collect the channel list. The 802.11 layer
687 * is resposible for filtering this list based
688 * on settings like the phy mode and regulatory
689 * domain restrictions.
691 ret
= ath5k_getchannels(hw
);
693 ATH5K_ERR(sc
, "can't get channels\n");
697 /* Set *_rates so we can map hw rate index */
698 ath5k_set_total_hw_rates(sc
);
700 /* NB: setup here so ath5k_rate_update is happy */
701 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
702 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
704 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
707 * Allocate tx+rx descriptors and populate the lists.
709 ret
= ath5k_desc_alloc(sc
, pdev
);
711 ATH5K_ERR(sc
, "can't allocate descriptors\n");
716 * Allocate hardware transmit queues: one queue for
717 * beacon frames and one data queue for each QoS
718 * priority. Note that hw functions handle reseting
719 * these queues at the needed time.
721 ret
= ath5k_beaconq_setup(ah
);
723 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
728 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
729 if (IS_ERR(sc
->txq
)) {
730 ATH5K_ERR(sc
, "can't setup xmit queue\n");
731 ret
= PTR_ERR(sc
->txq
);
735 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
736 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
737 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
738 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
740 ath5k_hw_get_lladdr(ah
, mac
);
741 SET_IEEE80211_PERM_ADDR(hw
, mac
);
742 /* All MAC address bits matter for ACKs */
743 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
744 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
746 ret
= ieee80211_register_hw(hw
);
748 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
756 ath5k_txq_release(sc
);
758 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
760 ath5k_desc_free(sc
, pdev
);
766 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
768 struct ath5k_softc
*sc
= hw
->priv
;
771 * NB: the order of these is important:
772 * o call the 802.11 layer before detaching ath5k_hw to
773 * insure callbacks into the driver to delete global
774 * key cache entries can be handled
775 * o reclaim the tx queue data structures after calling
776 * the 802.11 layer as we'll get called back to reclaim
777 * node state and potentially want to use them
778 * o to cleanup the tx queues the hal is called, so detach
780 * XXX: ??? detach ath5k_hw ???
781 * Other than that, it's straightforward...
783 ieee80211_unregister_hw(hw
);
784 ath5k_desc_free(sc
, pdev
);
785 ath5k_txq_release(sc
);
786 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
787 ath5k_unregister_leds(sc
);
790 * NB: can't reclaim these until after ieee80211_ifdetach
791 * returns because we'll get called back to reclaim node
792 * state and potentially want to use them.
799 /********************\
800 * Channel/mode setup *
801 \********************/
804 * Convert IEEE channel number to MHz frequency.
807 ath5k_ieee2mhz(short chan
)
809 if (chan
<= 14 || chan
>= 27)
810 return ieee80211chan2mhz(chan
);
812 return 2212 + chan
* 20;
816 ath5k_copy_rates(struct ieee80211_rate
*rates
,
817 const struct ath5k_rate_table
*rt
,
820 unsigned int i
, count
;
825 for (i
= 0, count
= 0; i
< rt
->rate_count
&& max
> 0; i
++) {
826 rates
[count
].bitrate
= rt
->rates
[i
].rate_kbps
/ 100;
827 rates
[count
].hw_value
= rt
->rates
[i
].rate_code
;
828 rates
[count
].flags
= rt
->rates
[i
].modulation
;
837 ath5k_copy_channels(struct ath5k_hw
*ah
,
838 struct ieee80211_channel
*channels
,
842 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
844 if (!test_bit(mode
, ah
->ah_modes
))
849 case AR5K_MODE_11A_TURBO
:
850 /* 1..220, but 2GHz frequencies are filtered by check_channel */
852 chfreq
= CHANNEL_5GHZ
;
856 case AR5K_MODE_11G_TURBO
:
858 chfreq
= CHANNEL_2GHZ
;
861 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
865 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
867 freq
= ath5k_ieee2mhz(ch
);
869 /* Check if channel is supported by the chipset */
870 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
873 /* Write channel info and increment counter */
874 channels
[count
].center_freq
= freq
;
875 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
876 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
880 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
882 case AR5K_MODE_11A_TURBO
:
883 case AR5K_MODE_11G_TURBO
:
884 channels
[count
].hw_value
= chfreq
|
885 CHANNEL_OFDM
| CHANNEL_TURBO
;
888 channels
[count
].hw_value
= CHANNEL_B
;
899 ath5k_getchannels(struct ieee80211_hw
*hw
)
901 struct ath5k_softc
*sc
= hw
->priv
;
902 struct ath5k_hw
*ah
= sc
->ah
;
903 struct ieee80211_supported_band
*sbands
= sc
->sbands
;
904 const struct ath5k_rate_table
*hw_rates
;
905 unsigned int max_r
, max_c
, count_r
, count_c
;
906 int mode2g
= AR5K_MODE_11G
;
908 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
910 max_r
= ARRAY_SIZE(sc
->rates
);
911 max_c
= ARRAY_SIZE(sc
->channels
);
912 count_r
= count_c
= 0;
915 if (!test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
916 mode2g
= AR5K_MODE_11B
;
917 if (!test_bit(AR5K_MODE_11B
,
918 sc
->ah
->ah_capabilities
.cap_mode
))
923 struct ieee80211_supported_band
*sband
=
924 &sbands
[IEEE80211_BAND_2GHZ
];
926 sband
->bitrates
= sc
->rates
;
927 sband
->channels
= sc
->channels
;
929 sband
->band
= IEEE80211_BAND_2GHZ
;
930 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
933 hw_rates
= ath5k_hw_get_rate_table(ah
, mode2g
);
934 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
937 count_c
= sband
->n_channels
;
938 count_r
= sband
->n_bitrates
;
940 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
949 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
950 struct ieee80211_supported_band
*sband
=
951 &sbands
[IEEE80211_BAND_5GHZ
];
953 sband
->bitrates
= &sc
->rates
[count_r
];
954 sband
->channels
= &sc
->channels
[count_c
];
956 sband
->band
= IEEE80211_BAND_5GHZ
;
957 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
958 AR5K_MODE_11A
, max_c
);
960 hw_rates
= ath5k_hw_get_rate_table(ah
, AR5K_MODE_11A
);
961 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
964 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
967 ath5k_debug_dump_bands(sc
);
973 * Set/change channels. If the channel is really being changed,
974 * it's done by reseting the chip. To accomplish this we must
975 * first cleanup any pending DMA, then restart stuff after a la
979 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
981 struct ath5k_hw
*ah
= sc
->ah
;
984 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
985 sc
->curchan
->center_freq
, chan
->center_freq
);
987 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
988 chan
->hw_value
!= sc
->curchan
->hw_value
) {
991 sc
->curband
= &sc
->sbands
[chan
->band
];
994 * To switch channels clear any pending DMA operations;
995 * wait long enough for the RX fifo to drain, reset the
996 * hardware at the new frequency, and then re-enable
997 * the relevant bits of the h/w.
999 ath5k_hw_set_intr(ah
, 0); /* disable interrupts */
1000 ath5k_txq_cleanup(sc
); /* clear pending tx frames */
1001 ath5k_rx_stop(sc
); /* turn off frame recv */
1002 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
1004 ATH5K_ERR(sc
, "%s: unable to reset channel "
1005 "(%u Mhz)\n", __func__
, chan
->center_freq
);
1009 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
1012 * Re-enable rx framework.
1014 ret
= ath5k_rx_start(sc
);
1016 ATH5K_ERR(sc
, "%s: unable to restart recv logic\n",
1022 * Change channels and update the h/w rate map
1023 * if we're switching; e.g. 11a to 11b/g.
1027 /* ath5k_chan_change(sc, chan); */
1029 ath5k_beacon_config(sc
);
1031 * Re-enable interrupts.
1033 ath5k_hw_set_intr(ah
, sc
->imask
);
1040 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1044 if (mode
== AR5K_MODE_11A
) {
1045 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1047 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1052 ath5k_mode_setup(struct ath5k_softc
*sc
)
1054 struct ath5k_hw
*ah
= sc
->ah
;
1057 /* configure rx filter */
1058 rfilt
= sc
->filter_flags
;
1059 ath5k_hw_set_rx_filter(ah
, rfilt
);
1061 if (ath5k_hw_hasbssidmask(ah
))
1062 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1064 /* configure operational mode */
1065 ath5k_hw_set_opmode(ah
);
1067 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1068 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1072 * Match the hw provided rate index (through descriptors)
1073 * to an index for sc->curband->bitrates, so it can be used
1076 * This one is a little bit tricky but i think i'm right
1079 * We have 4 rate tables in the following order:
1083 * 802.11g (12 rates)
1084 * that make the hw rate table.
1086 * Lets take a 5211 for example that supports a and b modes only.
1087 * First comes the 802.11a table and then 802.11b (total 12 rates).
1088 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1089 * if it returns 2 it points to the second 802.11a rate etc.
1091 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1092 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1093 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1096 ath5k_set_total_hw_rates(struct ath5k_softc
*sc
) {
1098 struct ath5k_hw
*ah
= sc
->ah
;
1100 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
1103 if (test_bit(AR5K_MODE_11B
, ah
->ah_modes
))
1106 if (test_bit(AR5K_MODE_11G
, ah
->ah_modes
))
1109 /* XXX: Need to see what what happens when
1110 xr disable bits in eeprom are set */
1111 if (ah
->ah_version
>= AR5K_AR5212
)
1117 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
) {
1121 if(sc
->curband
->band
== IEEE80211_BAND_2GHZ
) {
1122 /* We setup a g ratetable for both b/g modes */
1124 hw_rix
- sc
->b_rates
- sc
->a_rates
- sc
->xr_rates
;
1126 mac80211_rix
= hw_rix
- sc
->xr_rates
;
1129 /* Something went wrong, fallback to basic rate for this band */
1130 if ((mac80211_rix
>= sc
->curband
->n_bitrates
) ||
1131 (mac80211_rix
<= 0 ))
1134 return mac80211_rix
;
1145 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1147 struct ath5k_hw
*ah
= sc
->ah
;
1148 struct sk_buff
*skb
= bf
->skb
;
1149 struct ath5k_desc
*ds
;
1151 if (likely(skb
== NULL
)) {
1155 * Allocate buffer with headroom_needed space for the
1156 * fake physical layer header at the start.
1158 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1159 if (unlikely(skb
== NULL
)) {
1160 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1161 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1165 * Cache-line-align. This is important (for the
1166 * 5210 at least) as not doing so causes bogus data
1169 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1171 skb_reserve(skb
, sc
->cachelsz
- off
);
1174 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1175 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1176 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
))) {
1177 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1185 * Setup descriptors. For receive we always terminate
1186 * the descriptor list with a self-linked entry so we'll
1187 * not get overrun under high load (as can happen with a
1188 * 5212 when ANI processing enables PHY error frames).
1190 * To insure the last descriptor is self-linked we create
1191 * each descriptor as self-linked and add it to the end. As
1192 * each additional descriptor is added the previous self-linked
1193 * entry is ``fixed'' naturally. This should be safe even
1194 * if DMA is happening. When processing RX interrupts we
1195 * never remove/process the last, self-linked, entry on the
1196 * descriptor list. This insures the hardware always has
1197 * someplace to write a new frame.
1200 ds
->ds_link
= bf
->daddr
; /* link to self */
1201 ds
->ds_data
= bf
->skbaddr
;
1202 ath5k_hw_setup_rx_desc(ah
, ds
,
1203 skb_tailroom(skb
), /* buffer size */
1206 if (sc
->rxlink
!= NULL
)
1207 *sc
->rxlink
= bf
->daddr
;
1208 sc
->rxlink
= &ds
->ds_link
;
1213 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1215 struct ath5k_hw
*ah
= sc
->ah
;
1216 struct ath5k_txq
*txq
= sc
->txq
;
1217 struct ath5k_desc
*ds
= bf
->desc
;
1218 struct sk_buff
*skb
= bf
->skb
;
1219 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1220 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1223 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1225 /* XXX endianness */
1226 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1229 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1230 flags
|= AR5K_TXDESC_NOACK
;
1234 if (info
->control
.hw_key
) {
1235 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1236 pktlen
+= info
->control
.icv_len
;
1238 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1239 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1240 (sc
->power_level
* 2),
1241 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1242 info
->control
.retry_limit
, keyidx
, 0, flags
, 0, 0);
1247 ds
->ds_data
= bf
->skbaddr
;
1249 spin_lock_bh(&txq
->lock
);
1250 list_add_tail(&bf
->list
, &txq
->q
);
1251 sc
->tx_stats
[txq
->qnum
].len
++;
1252 if (txq
->link
== NULL
) /* is this first packet? */
1253 ath5k_hw_put_tx_buf(ah
, txq
->qnum
, bf
->daddr
);
1254 else /* no, so only link it */
1255 *txq
->link
= bf
->daddr
;
1257 txq
->link
= &ds
->ds_link
;
1258 ath5k_hw_tx_start(ah
, txq
->qnum
);
1260 spin_unlock_bh(&txq
->lock
);
1264 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1268 /*******************\
1269 * Descriptors setup *
1270 \*******************/
1273 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1275 struct ath5k_desc
*ds
;
1276 struct ath5k_buf
*bf
;
1281 /* allocate descriptors */
1282 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1283 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1284 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1285 if (sc
->desc
== NULL
) {
1286 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1291 da
= sc
->desc_daddr
;
1292 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1293 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1295 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1296 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1298 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1304 INIT_LIST_HEAD(&sc
->rxbuf
);
1305 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1308 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1311 INIT_LIST_HEAD(&sc
->txbuf
);
1312 sc
->txbuf_len
= ATH_TXBUF
;
1313 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1314 da
+= sizeof(*ds
)) {
1317 list_add_tail(&bf
->list
, &sc
->txbuf
);
1327 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1334 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1336 struct ath5k_buf
*bf
;
1338 ath5k_txbuf_free(sc
, sc
->bbuf
);
1339 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1340 ath5k_txbuf_free(sc
, bf
);
1341 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1342 ath5k_txbuf_free(sc
, bf
);
1344 /* Free memory associated with all descriptors */
1345 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1359 static struct ath5k_txq
*
1360 ath5k_txq_setup(struct ath5k_softc
*sc
,
1361 int qtype
, int subtype
)
1363 struct ath5k_hw
*ah
= sc
->ah
;
1364 struct ath5k_txq
*txq
;
1365 struct ath5k_txq_info qi
= {
1366 .tqi_subtype
= subtype
,
1367 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1368 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1369 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1374 * Enable interrupts only for EOL and DESC conditions.
1375 * We mark tx descriptors to receive a DESC interrupt
1376 * when a tx queue gets deep; otherwise waiting for the
1377 * EOL to reap descriptors. Note that this is done to
1378 * reduce interrupt load and this only defers reaping
1379 * descriptors, never transmitting frames. Aside from
1380 * reducing interrupts this also permits more concurrency.
1381 * The only potential downside is if the tx queue backs
1382 * up in which case the top half of the kernel may backup
1383 * due to a lack of tx descriptors.
1385 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1386 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1387 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1390 * NB: don't print a message, this happens
1391 * normally on parts with too few tx queues
1393 return ERR_PTR(qnum
);
1395 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1396 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1397 qnum
, ARRAY_SIZE(sc
->txqs
));
1398 ath5k_hw_release_tx_queue(ah
, qnum
);
1399 return ERR_PTR(-EINVAL
);
1401 txq
= &sc
->txqs
[qnum
];
1405 INIT_LIST_HEAD(&txq
->q
);
1406 spin_lock_init(&txq
->lock
);
1409 return &sc
->txqs
[qnum
];
1413 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1415 struct ath5k_txq_info qi
= {
1416 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1417 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1418 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1419 /* NB: for dynamic turbo, don't enable any other interrupts */
1420 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1423 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1427 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1429 struct ath5k_hw
*ah
= sc
->ah
;
1430 struct ath5k_txq_info qi
;
1433 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1436 if (sc
->opmode
== IEEE80211_IF_TYPE_AP
) {
1438 * Always burst out beacon and CAB traffic
1439 * (aifs = cwmin = cwmax = 0)
1444 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
1446 * Adhoc mode; backoff between 0 and (2 * cw_min).
1450 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1453 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1454 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1455 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1457 ret
= ath5k_hw_setup_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1459 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1460 "hardware queue!\n", __func__
);
1464 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1468 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1470 struct ath5k_buf
*bf
, *bf0
;
1473 * NB: this assumes output has been stopped and
1474 * we do not need to block ath5k_tx_tasklet
1476 spin_lock_bh(&txq
->lock
);
1477 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1478 ath5k_debug_printtxbuf(sc
, bf
);
1480 ath5k_txbuf_free(sc
, bf
);
1482 spin_lock_bh(&sc
->txbuflock
);
1483 sc
->tx_stats
[txq
->qnum
].len
--;
1484 list_move_tail(&bf
->list
, &sc
->txbuf
);
1486 spin_unlock_bh(&sc
->txbuflock
);
1489 spin_unlock_bh(&txq
->lock
);
1493 * Drain the transmit queues and reclaim resources.
1496 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1498 struct ath5k_hw
*ah
= sc
->ah
;
1501 /* XXX return value */
1502 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1503 /* don't touch the hardware if marked invalid */
1504 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1505 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1506 ath5k_hw_get_tx_buf(ah
, sc
->bhalq
));
1507 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1508 if (sc
->txqs
[i
].setup
) {
1509 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1510 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1513 ath5k_hw_get_tx_buf(ah
,
1518 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1520 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1521 if (sc
->txqs
[i
].setup
)
1522 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1526 ath5k_txq_release(struct ath5k_softc
*sc
)
1528 struct ath5k_txq
*txq
= sc
->txqs
;
1531 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1533 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1546 * Enable the receive h/w following a reset.
1549 ath5k_rx_start(struct ath5k_softc
*sc
)
1551 struct ath5k_hw
*ah
= sc
->ah
;
1552 struct ath5k_buf
*bf
;
1555 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1557 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1558 sc
->cachelsz
, sc
->rxbufsize
);
1562 spin_lock_bh(&sc
->rxbuflock
);
1563 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1564 ret
= ath5k_rxbuf_setup(sc
, bf
);
1566 spin_unlock_bh(&sc
->rxbuflock
);
1570 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1571 spin_unlock_bh(&sc
->rxbuflock
);
1573 ath5k_hw_put_rx_buf(ah
, bf
->daddr
);
1574 ath5k_hw_start_rx(ah
); /* enable recv descriptors */
1575 ath5k_mode_setup(sc
); /* set filters, etc. */
1576 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1584 * Disable the receive h/w in preparation for a reset.
1587 ath5k_rx_stop(struct ath5k_softc
*sc
)
1589 struct ath5k_hw
*ah
= sc
->ah
;
1591 ath5k_hw_stop_pcu_recv(ah
); /* disable PCU */
1592 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1593 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1595 ath5k_debug_printrxbuffs(sc
, ah
);
1597 sc
->rxlink
= NULL
; /* just in case */
1601 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1602 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1604 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1605 unsigned int keyix
, hlen
= ieee80211_get_hdrlen_from_skb(skb
);
1607 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1608 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1609 return RX_FLAG_DECRYPTED
;
1611 /* Apparently when a default key is used to decrypt the packet
1612 the hw does not set the index used to decrypt. In such cases
1613 get the index from the packet. */
1614 if (ieee80211_has_protected(hdr
->frame_control
) &&
1615 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1616 skb
->len
>= hlen
+ 4) {
1617 keyix
= skb
->data
[hlen
+ 3] >> 6;
1619 if (test_bit(keyix
, sc
->keymap
))
1620 return RX_FLAG_DECRYPTED
;
1628 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1629 struct ieee80211_rx_status
*rxs
)
1633 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1635 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1636 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1637 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1639 * Received an IBSS beacon with the same BSSID. Hardware *must*
1640 * have updated the local TSF. We have to work around various
1641 * hardware bugs, though...
1643 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1644 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1645 hw_tu
= TSF_TO_TU(tsf
);
1647 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1648 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1649 (unsigned long long)bc_tstamp
,
1650 (unsigned long long)rxs
->mactime
,
1651 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1652 (unsigned long long)tsf
);
1655 * Sometimes the HW will give us a wrong tstamp in the rx
1656 * status, causing the timestamp extension to go wrong.
1657 * (This seems to happen especially with beacon frames bigger
1658 * than 78 byte (incl. FCS))
1659 * But we know that the receive timestamp must be later than the
1660 * timestamp of the beacon since HW must have synced to that.
1662 * NOTE: here we assume mactime to be after the frame was
1663 * received, not like mac80211 which defines it at the start.
1665 if (bc_tstamp
> rxs
->mactime
) {
1666 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1667 "fixing mactime from %llx to %llx\n",
1668 (unsigned long long)rxs
->mactime
,
1669 (unsigned long long)tsf
);
1674 * Local TSF might have moved higher than our beacon timers,
1675 * in that case we have to update them to continue sending
1676 * beacons. This also takes care of synchronizing beacon sending
1677 * times with other stations.
1679 if (hw_tu
>= sc
->nexttbtt
)
1680 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1686 ath5k_tasklet_rx(unsigned long data
)
1688 struct ieee80211_rx_status rxs
= {};
1689 struct ath5k_rx_status rs
= {};
1690 struct sk_buff
*skb
;
1691 struct ath5k_softc
*sc
= (void *)data
;
1692 struct ath5k_buf
*bf
, *bf_last
;
1693 struct ath5k_desc
*ds
;
1698 spin_lock(&sc
->rxbuflock
);
1699 if (list_empty(&sc
->rxbuf
)) {
1700 ATH5K_WARN(sc
, "empty rx buf pool\n");
1703 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1707 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1708 BUG_ON(bf
->skb
== NULL
);
1713 * last buffer must not be freed to ensure proper hardware
1714 * function. When the hardware finishes also a packet next to
1715 * it, we are sure, it doesn't use it anymore and we can go on.
1720 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1721 struct ath5k_buf
, list
);
1722 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1727 /* skip the overwritten one (even status is martian) */
1731 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1732 if (unlikely(ret
== -EINPROGRESS
))
1734 else if (unlikely(ret
)) {
1735 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1736 spin_unlock(&sc
->rxbuflock
);
1740 if (unlikely(rs
.rs_more
)) {
1741 ATH5K_WARN(sc
, "unsupported jumbo\n");
1745 if (unlikely(rs
.rs_status
)) {
1746 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1748 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1750 * Decrypt error. If the error occurred
1751 * because there was no hardware key, then
1752 * let the frame through so the upper layers
1753 * can process it. This is necessary for 5210
1754 * parts which have no way to setup a ``clear''
1757 * XXX do key cache faulting
1759 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1760 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1763 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1764 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1768 /* let crypto-error packets fall through in MNTR */
1770 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1771 sc
->opmode
!= IEEE80211_IF_TYPE_MNTR
)
1775 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1776 PCI_DMA_FROMDEVICE
);
1779 skb_put(skb
, rs
.rs_datalen
);
1782 * the hardware adds a padding to 4 byte boundaries between
1783 * the header and the payload data if the header length is
1784 * not multiples of 4 - remove it
1786 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1789 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1794 * always extend the mac timestamp, since this information is
1795 * also needed for proper IBSS merging.
1797 * XXX: it might be too late to do it here, since rs_tstamp is
1798 * 15bit only. that means TSF extension has to be done within
1799 * 32768usec (about 32ms). it might be necessary to move this to
1800 * the interrupt handler, like it is done in madwifi.
1802 * Unfortunately we don't know when the hardware takes the rx
1803 * timestamp (beginning of phy frame, data frame, end of rx?).
1804 * The only thing we know is that it is hardware specific...
1805 * On AR5213 it seems the rx timestamp is at the end of the
1806 * frame, but i'm not sure.
1808 * NOTE: mac80211 defines mactime at the beginning of the first
1809 * data symbol. Since we don't have any time references it's
1810 * impossible to comply to that. This affects IBSS merge only
1811 * right now, so it's not too bad...
1813 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1814 rxs
.flag
|= RX_FLAG_TSFT
;
1816 rxs
.freq
= sc
->curchan
->center_freq
;
1817 rxs
.band
= sc
->curband
->band
;
1819 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1820 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1821 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1823 rxs
.antenna
= rs
.rs_antenna
;
1824 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1825 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1827 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1829 /* check beacons in IBSS mode */
1830 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
1831 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1833 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1835 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1836 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1838 spin_unlock(&sc
->rxbuflock
);
1849 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1851 struct ath5k_tx_status ts
= {};
1852 struct ath5k_buf
*bf
, *bf0
;
1853 struct ath5k_desc
*ds
;
1854 struct sk_buff
*skb
;
1855 struct ieee80211_tx_info
*info
;
1858 spin_lock(&txq
->lock
);
1859 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1862 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1863 if (unlikely(ret
== -EINPROGRESS
))
1865 else if (unlikely(ret
)) {
1866 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1872 info
= IEEE80211_SKB_CB(skb
);
1875 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1878 info
->status
.retry_count
= ts
.ts_shortretry
+ ts
.ts_longretry
/ 6;
1879 if (unlikely(ts
.ts_status
)) {
1880 sc
->ll_stats
.dot11ACKFailureCount
++;
1881 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1882 info
->status
.excessive_retries
= 1;
1883 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1884 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1886 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1887 info
->status
.ack_signal
= ts
.ts_rssi
;
1890 ieee80211_tx_status(sc
->hw
, skb
);
1891 sc
->tx_stats
[txq
->qnum
].count
++;
1893 spin_lock(&sc
->txbuflock
);
1894 sc
->tx_stats
[txq
->qnum
].len
--;
1895 list_move_tail(&bf
->list
, &sc
->txbuf
);
1897 spin_unlock(&sc
->txbuflock
);
1899 if (likely(list_empty(&txq
->q
)))
1901 spin_unlock(&txq
->lock
);
1902 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1903 ieee80211_wake_queues(sc
->hw
);
1907 ath5k_tasklet_tx(unsigned long data
)
1909 struct ath5k_softc
*sc
= (void *)data
;
1911 ath5k_tx_processq(sc
, sc
->txq
);
1920 * Setup the beacon frame for transmit.
1923 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1925 struct sk_buff
*skb
= bf
->skb
;
1926 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1927 struct ath5k_hw
*ah
= sc
->ah
;
1928 struct ath5k_desc
*ds
;
1929 int ret
, antenna
= 0;
1932 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1934 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1935 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1936 (unsigned long long)bf
->skbaddr
);
1937 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1938 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1944 flags
= AR5K_TXDESC_NOACK
;
1945 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
&& ath5k_hw_hasveol(ah
)) {
1946 ds
->ds_link
= bf
->daddr
; /* self-linked */
1947 flags
|= AR5K_TXDESC_VEOL
;
1949 * Let hardware handle antenna switching if txantenna is not set
1954 * Switch antenna every 4 beacons if txantenna is not set
1955 * XXX assumes two antennas
1958 antenna
= sc
->bsent
& 4 ? 2 : 1;
1961 ds
->ds_data
= bf
->skbaddr
;
1962 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1963 ieee80211_get_hdrlen_from_skb(skb
),
1964 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1965 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1966 1, AR5K_TXKEYIX_INVALID
,
1967 antenna
, flags
, 0, 0);
1973 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1978 * Transmit a beacon frame at SWBA. Dynamic updates to the
1979 * frame contents are done as needed and the slot time is
1980 * also adjusted based on current state.
1982 * this is usually called from interrupt context (ath5k_intr())
1983 * but also from ath5k_beacon_config() in IBSS mode which in turn
1984 * can be called from a tasklet and user context
1987 ath5k_beacon_send(struct ath5k_softc
*sc
)
1989 struct ath5k_buf
*bf
= sc
->bbuf
;
1990 struct ath5k_hw
*ah
= sc
->ah
;
1992 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1994 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== IEEE80211_IF_TYPE_STA
||
1995 sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)) {
1996 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2000 * Check if the previous beacon has gone out. If
2001 * not don't don't try to post another, skip this
2002 * period and wait for the next. Missed beacons
2003 * indicate a problem and should not occur. If we
2004 * miss too many consecutive beacons reset the device.
2006 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2008 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2009 "missed %u consecutive beacons\n", sc
->bmisscount
);
2010 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
2011 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2012 "stuck beacon time (%u missed)\n",
2014 tasklet_schedule(&sc
->restq
);
2018 if (unlikely(sc
->bmisscount
!= 0)) {
2019 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2020 "resume beacon xmit after %u misses\n",
2026 * Stop any current dma and put the new frame on the queue.
2027 * This should never fail since we check above that no frames
2028 * are still pending on the queue.
2030 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2031 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2032 /* NB: hw still stops DMA, so proceed */
2035 ath5k_hw_put_tx_buf(ah
, sc
->bhalq
, bf
->daddr
);
2036 ath5k_hw_tx_start(ah
, sc
->bhalq
);
2037 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2038 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2045 * ath5k_beacon_update_timers - update beacon timers
2047 * @sc: struct ath5k_softc pointer we are operating on
2048 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2049 * beacon timer update based on the current HW TSF.
2051 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2052 * of a received beacon or the current local hardware TSF and write it to the
2053 * beacon timer registers.
2055 * This is called in a variety of situations, e.g. when a beacon is received,
2056 * when a TSF update has been detected, but also when an new IBSS is created or
2057 * when we otherwise know we have to update the timers, but we keep it in this
2058 * function to have it all together in one place.
2061 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2063 struct ath5k_hw
*ah
= sc
->ah
;
2064 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2067 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2068 if (WARN_ON(!intval
))
2071 /* beacon TSF converted to TU */
2072 bc_tu
= TSF_TO_TU(bc_tsf
);
2074 /* current TSF converted to TU */
2075 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2076 hw_tu
= TSF_TO_TU(hw_tsf
);
2079 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2082 * no beacons received, called internally.
2083 * just need to refresh timers based on HW TSF.
2085 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2086 } else if (bc_tsf
== 0) {
2088 * no beacon received, probably called by ath5k_reset_tsf().
2089 * reset TSF to start with 0.
2092 intval
|= AR5K_BEACON_RESET_TSF
;
2093 } else if (bc_tsf
> hw_tsf
) {
2095 * beacon received, SW merge happend but HW TSF not yet updated.
2096 * not possible to reconfigure timers yet, but next time we
2097 * receive a beacon with the same BSSID, the hardware will
2098 * automatically update the TSF and then we need to reconfigure
2101 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2102 "need to wait for HW TSF sync\n");
2106 * most important case for beacon synchronization between STA.
2108 * beacon received and HW TSF has been already updated by HW.
2109 * update next TBTT based on the TSF of the beacon, but make
2110 * sure it is ahead of our local TSF timer.
2112 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2116 sc
->nexttbtt
= nexttbtt
;
2118 intval
|= AR5K_BEACON_ENA
;
2119 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2122 * debugging output last in order to preserve the time critical aspect
2126 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2127 "reconfigured timers based on HW TSF\n");
2128 else if (bc_tsf
== 0)
2129 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2130 "reset HW TSF and timers\n");
2132 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2133 "updated timers based on beacon TSF\n");
2135 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2136 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2137 (unsigned long long) bc_tsf
,
2138 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2139 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2140 intval
& AR5K_BEACON_PERIOD
,
2141 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2142 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2147 * ath5k_beacon_config - Configure the beacon queues and interrupts
2149 * @sc: struct ath5k_softc pointer we are operating on
2151 * When operating in station mode we want to receive a BMISS interrupt when we
2152 * stop seeing beacons from the AP we've associated with so we can look for
2153 * another AP to associate with.
2155 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2156 * interrupts to detect TSF updates only.
2158 * AP mode is missing.
2161 ath5k_beacon_config(struct ath5k_softc
*sc
)
2163 struct ath5k_hw
*ah
= sc
->ah
;
2165 ath5k_hw_set_intr(ah
, 0);
2167 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2169 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
) {
2170 sc
->imask
|= AR5K_INT_BMISS
;
2171 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2173 * In IBSS mode we use a self-linked tx descriptor and let the
2174 * hardware send the beacons automatically. We have to load it
2176 * We use the SWBA interrupt only to keep track of the beacon
2177 * timers in order to detect automatic TSF updates.
2179 ath5k_beaconq_config(sc
);
2181 sc
->imask
|= AR5K_INT_SWBA
;
2183 if (ath5k_hw_hasveol(ah
)) {
2184 spin_lock(&sc
->block
);
2185 ath5k_beacon_send(sc
);
2186 spin_unlock(&sc
->block
);
2191 ath5k_hw_set_intr(ah
, sc
->imask
);
2195 /********************\
2196 * Interrupt handling *
2197 \********************/
2200 ath5k_init(struct ath5k_softc
*sc
)
2204 mutex_lock(&sc
->lock
);
2206 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2209 * Stop anything previously setup. This is safe
2210 * no matter this is the first time through or not.
2212 ath5k_stop_locked(sc
);
2215 * The basic interface to setting the hardware in a good
2216 * state is ``reset''. On return the hardware is known to
2217 * be powered up and with interrupts disabled. This must
2218 * be followed by initialization of the appropriate bits
2219 * and then setup of the interrupt mask.
2221 sc
->curchan
= sc
->hw
->conf
.channel
;
2222 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2223 ret
= ath5k_hw_reset(sc
->ah
, sc
->opmode
, sc
->curchan
, false);
2225 ATH5K_ERR(sc
, "unable to reset hardware: %d\n", ret
);
2229 * This is needed only to setup initial state
2230 * but it's best done after a reset.
2232 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2235 * Setup the hardware after reset: the key cache
2236 * is filled as needed and the receive engine is
2237 * set going. Frame transmit is handled entirely
2238 * in the frame output path; there's nothing to do
2239 * here except setup the interrupt mask.
2241 ret
= ath5k_rx_start(sc
);
2246 * Enable interrupts.
2248 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2249 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2252 ath5k_hw_set_intr(sc
->ah
, sc
->imask
);
2253 /* Set ack to be sent at low bit-rates */
2254 ath5k_hw_set_ack_bitrate_high(sc
->ah
, false);
2256 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2257 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2262 mutex_unlock(&sc
->lock
);
2267 ath5k_stop_locked(struct ath5k_softc
*sc
)
2269 struct ath5k_hw
*ah
= sc
->ah
;
2271 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2272 test_bit(ATH_STAT_INVALID
, sc
->status
));
2275 * Shutdown the hardware and driver:
2276 * stop output from above
2277 * disable interrupts
2279 * turn off the radio
2280 * clear transmit machinery
2281 * clear receive machinery
2282 * drain and release tx queues
2283 * reclaim beacon resources
2284 * power down hardware
2286 * Note that some of this work is not possible if the
2287 * hardware is gone (invalid).
2289 ieee80211_stop_queues(sc
->hw
);
2291 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2293 ath5k_hw_set_intr(ah
, 0);
2294 synchronize_irq(sc
->pdev
->irq
);
2296 ath5k_txq_cleanup(sc
);
2297 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2299 ath5k_hw_phy_disable(ah
);
2307 * Stop the device, grabbing the top-level lock to protect
2308 * against concurrent entry through ath5k_init (which can happen
2309 * if another thread does a system call and the thread doing the
2310 * stop is preempted).
2313 ath5k_stop_hw(struct ath5k_softc
*sc
)
2317 mutex_lock(&sc
->lock
);
2318 ret
= ath5k_stop_locked(sc
);
2319 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2321 * Set the chip in full sleep mode. Note that we are
2322 * careful to do this only when bringing the interface
2323 * completely to a stop. When the chip is in this state
2324 * it must be carefully woken up or references to
2325 * registers in the PCI clock domain may freeze the bus
2326 * (and system). This varies by chip and is mostly an
2327 * issue with newer parts that go to sleep more quickly.
2329 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2332 * don't put newer MAC revisions > 7.8 to sleep because
2333 * of the above mentioned problems
2335 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2336 "not putting device to sleep\n");
2338 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2339 "putting device to full sleep\n");
2340 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2343 ath5k_txbuf_free(sc
, sc
->bbuf
);
2345 mutex_unlock(&sc
->lock
);
2347 del_timer_sync(&sc
->calib_tim
);
2348 tasklet_kill(&sc
->rxtq
);
2349 tasklet_kill(&sc
->txtq
);
2350 tasklet_kill(&sc
->restq
);
2356 ath5k_intr(int irq
, void *dev_id
)
2358 struct ath5k_softc
*sc
= dev_id
;
2359 struct ath5k_hw
*ah
= sc
->ah
;
2360 enum ath5k_int status
;
2361 unsigned int counter
= 1000;
2363 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2364 !ath5k_hw_is_intr_pending(ah
)))
2369 * Figure out the reason(s) for the interrupt. Note
2370 * that get_isr returns a pseudo-ISR that may include
2371 * bits we haven't explicitly enabled so we mask the
2372 * value to insure we only process bits we requested.
2374 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2375 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2377 status
&= sc
->imask
; /* discard unasked for bits */
2378 if (unlikely(status
& AR5K_INT_FATAL
)) {
2380 * Fatal errors are unrecoverable.
2381 * Typically these are caused by DMA errors.
2383 tasklet_schedule(&sc
->restq
);
2384 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2385 tasklet_schedule(&sc
->restq
);
2387 if (status
& AR5K_INT_SWBA
) {
2389 * Software beacon alert--time to send a beacon.
2390 * Handle beacon transmission directly; deferring
2391 * this is too slow to meet timing constraints
2394 * In IBSS mode we use this interrupt just to
2395 * keep track of the next TBTT (target beacon
2396 * transmission time) in order to detect wether
2397 * automatic TSF updates happened.
2399 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2400 /* XXX: only if VEOL suppported */
2401 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2402 sc
->nexttbtt
+= sc
->bintval
;
2403 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2404 "SWBA nexttbtt: %x hw_tu: %x "
2408 (unsigned long long) tsf
);
2410 spin_lock(&sc
->block
);
2411 ath5k_beacon_send(sc
);
2412 spin_unlock(&sc
->block
);
2415 if (status
& AR5K_INT_RXEOL
) {
2417 * NB: the hardware should re-read the link when
2418 * RXE bit is written, but it doesn't work at
2419 * least on older hardware revs.
2423 if (status
& AR5K_INT_TXURN
) {
2424 /* bump tx trigger level */
2425 ath5k_hw_update_tx_triglevel(ah
, true);
2427 if (status
& AR5K_INT_RX
)
2428 tasklet_schedule(&sc
->rxtq
);
2429 if (status
& AR5K_INT_TX
)
2430 tasklet_schedule(&sc
->txtq
);
2431 if (status
& AR5K_INT_BMISS
) {
2433 if (status
& AR5K_INT_MIB
) {
2435 * These stats are also used for ANI i think
2436 * so how about updating them more often ?
2438 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2441 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2443 if (unlikely(!counter
))
2444 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2450 ath5k_tasklet_reset(unsigned long data
)
2452 struct ath5k_softc
*sc
= (void *)data
;
2454 ath5k_reset(sc
->hw
);
2458 * Periodically recalibrate the PHY to account
2459 * for temperature/environment changes.
2462 ath5k_calibrate(unsigned long data
)
2464 struct ath5k_softc
*sc
= (void *)data
;
2465 struct ath5k_hw
*ah
= sc
->ah
;
2467 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2468 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2469 sc
->curchan
->hw_value
);
2471 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2473 * Rfgain is out of bounds, reset the chip
2474 * to load new gain values.
2476 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2477 ath5k_reset(sc
->hw
);
2479 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2480 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2481 ieee80211_frequency_to_channel(
2482 sc
->curchan
->center_freq
));
2484 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2485 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2495 ath5k_led_enable(struct ath5k_softc
*sc
)
2497 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2498 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2504 ath5k_led_on(struct ath5k_softc
*sc
)
2506 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2508 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2512 ath5k_led_off(struct ath5k_softc
*sc
)
2514 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2516 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2520 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2521 enum led_brightness brightness
)
2523 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2526 if (brightness
== LED_OFF
)
2527 ath5k_led_off(led
->sc
);
2529 ath5k_led_on(led
->sc
);
2533 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2534 const char *name
, char *trigger
)
2539 strncpy(led
->name
, name
, sizeof(led
->name
));
2540 led
->led_dev
.name
= led
->name
;
2541 led
->led_dev
.default_trigger
= trigger
;
2542 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2544 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2547 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2554 ath5k_unregister_led(struct ath5k_led
*led
)
2558 led_classdev_unregister(&led
->led_dev
);
2559 ath5k_led_off(led
->sc
);
2564 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2566 ath5k_unregister_led(&sc
->rx_led
);
2567 ath5k_unregister_led(&sc
->tx_led
);
2572 ath5k_init_leds(struct ath5k_softc
*sc
)
2575 struct ieee80211_hw
*hw
= sc
->hw
;
2576 struct pci_dev
*pdev
= sc
->pdev
;
2577 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2580 * Auto-enable soft led processing for IBM cards and for
2581 * 5211 minipci cards.
2583 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2584 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2585 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2587 sc
->led_on
= 0; /* active low */
2589 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2590 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2591 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2593 sc
->led_on
= 1; /* active high */
2595 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2598 ath5k_led_enable(sc
);
2600 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2601 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2602 ieee80211_get_rx_led_name(hw
));
2606 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2607 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2608 ieee80211_get_tx_led_name(hw
));
2614 /********************\
2615 * Mac80211 functions *
2616 \********************/
2619 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2621 struct ath5k_softc
*sc
= hw
->priv
;
2622 struct ath5k_buf
*bf
;
2623 unsigned long flags
;
2627 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2629 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2630 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2633 * the hardware expects the header padded to 4 byte boundaries
2634 * if this is not the case we add the padding after the header
2636 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2639 if (skb_headroom(skb
) < pad
) {
2640 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2641 " headroom to pad %d\n", hdrlen
, pad
);
2645 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2648 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2649 if (list_empty(&sc
->txbuf
)) {
2650 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2651 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2652 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2655 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2656 list_del(&bf
->list
);
2658 if (list_empty(&sc
->txbuf
))
2659 ieee80211_stop_queues(hw
);
2660 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2664 if (ath5k_txbuf_setup(sc
, bf
)) {
2666 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2667 list_add_tail(&bf
->list
, &sc
->txbuf
);
2669 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2670 dev_kfree_skb_any(skb
);
2678 ath5k_reset(struct ieee80211_hw
*hw
)
2680 struct ath5k_softc
*sc
= hw
->priv
;
2681 struct ath5k_hw
*ah
= sc
->ah
;
2684 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2686 ath5k_hw_set_intr(ah
, 0);
2687 ath5k_txq_cleanup(sc
);
2690 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2691 if (unlikely(ret
)) {
2692 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2695 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2697 ret
= ath5k_rx_start(sc
);
2698 if (unlikely(ret
)) {
2699 ATH5K_ERR(sc
, "can't start recv logic\n");
2703 * We may be doing a reset in response to an ioctl
2704 * that changes the channel so update any state that
2705 * might change as a result.
2709 /* ath5k_chan_change(sc, c); */
2710 ath5k_beacon_config(sc
);
2711 /* intrs are started by ath5k_beacon_config */
2713 ieee80211_wake_queues(hw
);
2720 static int ath5k_start(struct ieee80211_hw
*hw
)
2722 return ath5k_init(hw
->priv
);
2725 static void ath5k_stop(struct ieee80211_hw
*hw
)
2727 ath5k_stop_hw(hw
->priv
);
2730 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2731 struct ieee80211_if_init_conf
*conf
)
2733 struct ath5k_softc
*sc
= hw
->priv
;
2736 mutex_lock(&sc
->lock
);
2742 sc
->vif
= conf
->vif
;
2744 switch (conf
->type
) {
2745 case IEEE80211_IF_TYPE_STA
:
2746 case IEEE80211_IF_TYPE_IBSS
:
2747 case IEEE80211_IF_TYPE_MNTR
:
2748 sc
->opmode
= conf
->type
;
2755 /* Set to a reasonable value. Note that this will
2756 * be set to mac80211's value at ath5k_config(). */
2761 mutex_unlock(&sc
->lock
);
2766 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2767 struct ieee80211_if_init_conf
*conf
)
2769 struct ath5k_softc
*sc
= hw
->priv
;
2771 mutex_lock(&sc
->lock
);
2772 if (sc
->vif
!= conf
->vif
)
2777 mutex_unlock(&sc
->lock
);
2781 * TODO: Phy disable/diversity etc
2784 ath5k_config(struct ieee80211_hw
*hw
,
2785 struct ieee80211_conf
*conf
)
2787 struct ath5k_softc
*sc
= hw
->priv
;
2789 sc
->bintval
= conf
->beacon_int
;
2790 sc
->power_level
= conf
->power_level
;
2792 return ath5k_chan_set(sc
, conf
->channel
);
2796 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2797 struct ieee80211_if_conf
*conf
)
2799 struct ath5k_softc
*sc
= hw
->priv
;
2800 struct ath5k_hw
*ah
= sc
->ah
;
2803 mutex_lock(&sc
->lock
);
2804 if (sc
->vif
!= vif
) {
2809 /* Cache for later use during resets */
2810 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2811 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2812 * a clean way of letting us retrieve this yet. */
2813 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2817 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2818 vif
->type
== IEEE80211_IF_TYPE_IBSS
) {
2819 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2824 /* call old handler for now */
2825 ath5k_beacon_update(hw
, beacon
);
2828 mutex_unlock(&sc
->lock
);
2830 return ath5k_reset(hw
);
2832 mutex_unlock(&sc
->lock
);
2836 #define SUPPORTED_FIF_FLAGS \
2837 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2838 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2839 FIF_BCN_PRBRESP_PROMISC
2841 * o always accept unicast, broadcast, and multicast traffic
2842 * o multicast traffic for all BSSIDs will be enabled if mac80211
2844 * o maintain current state of phy ofdm or phy cck error reception.
2845 * If the hardware detects any of these type of errors then
2846 * ath5k_hw_get_rx_filter() will pass to us the respective
2847 * hardware filters to be able to receive these type of frames.
2848 * o probe request frames are accepted only when operating in
2849 * hostap, adhoc, or monitor modes
2850 * o enable promiscuous mode according to the interface state
2852 * - when operating in adhoc mode so the 802.11 layer creates
2853 * node table entries for peers,
2854 * - when operating in station mode for collecting rssi data when
2855 * the station is otherwise quiet, or
2858 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2859 unsigned int changed_flags
,
2860 unsigned int *new_flags
,
2861 int mc_count
, struct dev_mc_list
*mclist
)
2863 struct ath5k_softc
*sc
= hw
->priv
;
2864 struct ath5k_hw
*ah
= sc
->ah
;
2865 u32 mfilt
[2], val
, rfilt
;
2872 /* Only deal with supported flags */
2873 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2874 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2876 /* If HW detects any phy or radar errors, leave those filters on.
2877 * Also, always enable Unicast, Broadcasts and Multicast
2878 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2879 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2880 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2881 AR5K_RX_FILTER_MCAST
);
2883 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2884 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2885 rfilt
|= AR5K_RX_FILTER_PROM
;
2886 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2889 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2892 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2893 if (*new_flags
& FIF_ALLMULTI
) {
2897 for (i
= 0; i
< mc_count
; i
++) {
2900 /* calculate XOR of eight 6-bit values */
2901 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2902 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2903 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2904 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2906 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2907 /* XXX: we might be able to just do this instead,
2908 * but not sure, needs testing, if we do use this we'd
2909 * neet to inform below to not reset the mcast */
2910 /* ath5k_hw_set_mcast_filterindex(ah,
2911 * mclist->dmi_addr[5]); */
2912 mclist
= mclist
->next
;
2916 /* This is the best we can do */
2917 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2918 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2920 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2921 * and probes for any BSSID, this needs testing */
2922 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2923 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2925 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2926 * set we should only pass on control frames for this
2927 * station. This needs testing. I believe right now this
2928 * enables *all* control frames, which is OK.. but
2929 * but we should see if we can improve on granularity */
2930 if (*new_flags
& FIF_CONTROL
)
2931 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2933 /* Additional settings per mode -- this is per ath5k */
2935 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2937 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2938 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2939 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2940 if (sc
->opmode
!= IEEE80211_IF_TYPE_STA
)
2941 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2942 if (sc
->opmode
!= IEEE80211_IF_TYPE_AP
&&
2943 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2944 rfilt
|= AR5K_RX_FILTER_PROM
;
2945 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2946 sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2947 rfilt
|= AR5K_RX_FILTER_BEACON
;
2951 ath5k_hw_set_rx_filter(ah
,rfilt
);
2953 /* Set multicast bits */
2954 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2955 /* Set the cached hw filter flags, this will alter actually
2957 sc
->filter_flags
= rfilt
;
2961 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2962 const u8
*local_addr
, const u8
*addr
,
2963 struct ieee80211_key_conf
*key
)
2965 struct ath5k_softc
*sc
= hw
->priv
;
2970 /* XXX: fix hardware encryption, its not working. For now
2971 * allow software encryption */
2981 mutex_lock(&sc
->lock
);
2985 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2987 ATH5K_ERR(sc
, "can't set the key\n");
2990 __set_bit(key
->keyidx
, sc
->keymap
);
2991 key
->hw_key_idx
= key
->keyidx
;
2994 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2995 __clear_bit(key
->keyidx
, sc
->keymap
);
3004 mutex_unlock(&sc
->lock
);
3009 ath5k_get_stats(struct ieee80211_hw
*hw
,
3010 struct ieee80211_low_level_stats
*stats
)
3012 struct ath5k_softc
*sc
= hw
->priv
;
3013 struct ath5k_hw
*ah
= sc
->ah
;
3016 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3018 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3024 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3025 struct ieee80211_tx_queue_stats
*stats
)
3027 struct ath5k_softc
*sc
= hw
->priv
;
3029 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3035 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3037 struct ath5k_softc
*sc
= hw
->priv
;
3039 return ath5k_hw_get_tsf64(sc
->ah
);
3043 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3045 struct ath5k_softc
*sc
= hw
->priv
;
3048 * in IBSS mode we need to update the beacon timers too.
3049 * this will also reset the TSF if we call it with 0
3051 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
3052 ath5k_beacon_update_timers(sc
, 0);
3054 ath5k_hw_reset_tsf(sc
->ah
);
3058 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3060 struct ath5k_softc
*sc
= hw
->priv
;
3061 unsigned long flags
;
3064 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3066 if (sc
->opmode
!= IEEE80211_IF_TYPE_IBSS
) {
3071 spin_lock_irqsave(&sc
->block
, flags
);
3072 ath5k_txbuf_free(sc
, sc
->bbuf
);
3073 sc
->bbuf
->skb
= skb
;
3074 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3076 sc
->bbuf
->skb
= NULL
;
3077 spin_unlock_irqrestore(&sc
->block
, flags
);
3079 ath5k_beacon_config(sc
);