2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
36 void __iomem
*mapbase
;
38 unsigned long width
; /* 16 or 32 bit version of hardware block */
39 unsigned long overflow_bit
;
40 unsigned long clear_bits
;
41 struct irqaction irqaction
;
42 struct platform_device
*pdev
;
45 unsigned long match_value
;
46 unsigned long next_match_value
;
47 unsigned long max_match_value
;
50 struct clock_event_device ced
;
51 struct clocksource cs
;
52 unsigned long total_cycles
;
55 static DEFINE_SPINLOCK(sh_cmt_lock
);
57 #define CMSTR -1 /* shared register */
58 #define CMCSR 0 /* channel register */
59 #define CMCNT 1 /* channel register */
60 #define CMCOR 2 /* channel register */
62 static inline unsigned long sh_cmt_read(struct sh_cmt_priv
*p
, int reg_nr
)
64 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
65 void __iomem
*base
= p
->mapbase
;
68 if (reg_nr
== CMSTR
) {
70 base
-= cfg
->channel_offset
;
78 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
))
79 return ioread32(base
+ offs
);
82 return ioread16(base
+ offs
);
85 static inline void sh_cmt_write(struct sh_cmt_priv
*p
, int reg_nr
,
88 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
89 void __iomem
*base
= p
->mapbase
;
92 if (reg_nr
== CMSTR
) {
94 base
-= cfg
->channel_offset
;
102 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
)) {
103 iowrite32(value
, base
+ offs
);
108 iowrite16(value
, base
+ offs
);
111 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv
*p
,
114 unsigned long v1
, v2
, v3
;
117 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
119 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
122 v1
= sh_cmt_read(p
, CMCNT
);
123 v2
= sh_cmt_read(p
, CMCNT
);
124 v3
= sh_cmt_read(p
, CMCNT
);
125 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
126 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
127 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
134 static void sh_cmt_start_stop_ch(struct sh_cmt_priv
*p
, int start
)
136 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
137 unsigned long flags
, value
;
139 /* start stop register shared by multiple timer channels */
140 spin_lock_irqsave(&sh_cmt_lock
, flags
);
141 value
= sh_cmt_read(p
, CMSTR
);
144 value
|= 1 << cfg
->timer_bit
;
146 value
&= ~(1 << cfg
->timer_bit
);
148 sh_cmt_write(p
, CMSTR
, value
);
149 spin_unlock_irqrestore(&sh_cmt_lock
, flags
);
152 static int sh_cmt_enable(struct sh_cmt_priv
*p
, unsigned long *rate
)
156 /* wake up device and enable clock */
157 pm_runtime_get_sync(&p
->pdev
->dev
);
158 ret
= clk_enable(p
->clk
);
160 dev_err(&p
->pdev
->dev
, "cannot enable clock\n");
161 pm_runtime_put_sync(&p
->pdev
->dev
);
165 /* make sure channel is disabled */
166 sh_cmt_start_stop_ch(p
, 0);
168 /* configure channel, periodic mode and maximum timeout */
169 if (p
->width
== 16) {
170 *rate
= clk_get_rate(p
->clk
) / 512;
171 sh_cmt_write(p
, CMCSR
, 0x43);
173 *rate
= clk_get_rate(p
->clk
) / 8;
174 sh_cmt_write(p
, CMCSR
, 0x01a4);
177 sh_cmt_write(p
, CMCOR
, 0xffffffff);
178 sh_cmt_write(p
, CMCNT
, 0);
181 sh_cmt_start_stop_ch(p
, 1);
185 static void sh_cmt_disable(struct sh_cmt_priv
*p
)
187 /* disable channel */
188 sh_cmt_start_stop_ch(p
, 0);
190 /* disable interrupts in CMT block */
191 sh_cmt_write(p
, CMCSR
, 0);
193 /* stop clock and mark device as idle */
195 pm_runtime_put_sync(&p
->pdev
->dev
);
199 #define FLAG_CLOCKEVENT (1 << 0)
200 #define FLAG_CLOCKSOURCE (1 << 1)
201 #define FLAG_REPROGRAM (1 << 2)
202 #define FLAG_SKIPEVENT (1 << 3)
203 #define FLAG_IRQCONTEXT (1 << 4)
205 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv
*p
,
208 unsigned long new_match
;
209 unsigned long value
= p
->next_match_value
;
210 unsigned long delay
= 0;
211 unsigned long now
= 0;
214 now
= sh_cmt_get_counter(p
, &has_wrapped
);
215 p
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
218 /* we're competing with the interrupt handler.
219 * -> let the interrupt handler reprogram the timer.
220 * -> interrupt number two handles the event.
222 p
->flags
|= FLAG_SKIPEVENT
;
230 /* reprogram the timer hardware,
231 * but don't save the new match value yet.
233 new_match
= now
+ value
+ delay
;
234 if (new_match
> p
->max_match_value
)
235 new_match
= p
->max_match_value
;
237 sh_cmt_write(p
, CMCOR
, new_match
);
239 now
= sh_cmt_get_counter(p
, &has_wrapped
);
240 if (has_wrapped
&& (new_match
> p
->match_value
)) {
241 /* we are changing to a greater match value,
242 * so this wrap must be caused by the counter
243 * matching the old value.
244 * -> first interrupt reprograms the timer.
245 * -> interrupt number two handles the event.
247 p
->flags
|= FLAG_SKIPEVENT
;
252 /* we are changing to a smaller match value,
253 * so the wrap must be caused by the counter
254 * matching the new value.
255 * -> save programmed match value.
256 * -> let isr handle the event.
258 p
->match_value
= new_match
;
262 /* be safe: verify hardware settings */
263 if (now
< new_match
) {
264 /* timer value is below match value, all good.
265 * this makes sure we won't miss any match events.
266 * -> save programmed match value.
267 * -> let isr handle the event.
269 p
->match_value
= new_match
;
273 /* the counter has reached a value greater
274 * than our new match value. and since the
275 * has_wrapped flag isn't set we must have
276 * programmed a too close event.
277 * -> increase delay and retry.
285 dev_warn(&p
->pdev
->dev
, "too long delay\n");
290 static void __sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
292 if (delta
> p
->max_match_value
)
293 dev_warn(&p
->pdev
->dev
, "delta out of range\n");
295 p
->next_match_value
= delta
;
296 sh_cmt_clock_event_program_verify(p
, 0);
299 static void sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
303 spin_lock_irqsave(&p
->lock
, flags
);
304 __sh_cmt_set_next(p
, delta
);
305 spin_unlock_irqrestore(&p
->lock
, flags
);
308 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
310 struct sh_cmt_priv
*p
= dev_id
;
313 sh_cmt_write(p
, CMCSR
, sh_cmt_read(p
, CMCSR
) & p
->clear_bits
);
315 /* update clock source counter to begin with if enabled
316 * the wrap flag should be cleared by the timer specific
317 * isr before we end up here.
319 if (p
->flags
& FLAG_CLOCKSOURCE
)
320 p
->total_cycles
+= p
->match_value
+ 1;
322 if (!(p
->flags
& FLAG_REPROGRAM
))
323 p
->next_match_value
= p
->max_match_value
;
325 p
->flags
|= FLAG_IRQCONTEXT
;
327 if (p
->flags
& FLAG_CLOCKEVENT
) {
328 if (!(p
->flags
& FLAG_SKIPEVENT
)) {
329 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
) {
330 p
->next_match_value
= p
->max_match_value
;
331 p
->flags
|= FLAG_REPROGRAM
;
334 p
->ced
.event_handler(&p
->ced
);
338 p
->flags
&= ~FLAG_SKIPEVENT
;
340 if (p
->flags
& FLAG_REPROGRAM
) {
341 p
->flags
&= ~FLAG_REPROGRAM
;
342 sh_cmt_clock_event_program_verify(p
, 1);
344 if (p
->flags
& FLAG_CLOCKEVENT
)
345 if ((p
->ced
.mode
== CLOCK_EVT_MODE_SHUTDOWN
)
346 || (p
->match_value
== p
->next_match_value
))
347 p
->flags
&= ~FLAG_REPROGRAM
;
350 p
->flags
&= ~FLAG_IRQCONTEXT
;
355 static int sh_cmt_start(struct sh_cmt_priv
*p
, unsigned long flag
)
360 spin_lock_irqsave(&p
->lock
, flags
);
362 if (!(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
363 ret
= sh_cmt_enable(p
, &p
->rate
);
369 /* setup timeout if no clockevent */
370 if ((flag
== FLAG_CLOCKSOURCE
) && (!(p
->flags
& FLAG_CLOCKEVENT
)))
371 __sh_cmt_set_next(p
, p
->max_match_value
);
373 spin_unlock_irqrestore(&p
->lock
, flags
);
378 static void sh_cmt_stop(struct sh_cmt_priv
*p
, unsigned long flag
)
383 spin_lock_irqsave(&p
->lock
, flags
);
385 f
= p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
388 if (f
&& !(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
391 /* adjust the timeout to maximum if only clocksource left */
392 if ((flag
== FLAG_CLOCKEVENT
) && (p
->flags
& FLAG_CLOCKSOURCE
))
393 __sh_cmt_set_next(p
, p
->max_match_value
);
395 spin_unlock_irqrestore(&p
->lock
, flags
);
398 static struct sh_cmt_priv
*cs_to_sh_cmt(struct clocksource
*cs
)
400 return container_of(cs
, struct sh_cmt_priv
, cs
);
403 static cycle_t
sh_cmt_clocksource_read(struct clocksource
*cs
)
405 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
406 unsigned long flags
, raw
;
410 spin_lock_irqsave(&p
->lock
, flags
);
411 value
= p
->total_cycles
;
412 raw
= sh_cmt_get_counter(p
, &has_wrapped
);
414 if (unlikely(has_wrapped
))
415 raw
+= p
->match_value
+ 1;
416 spin_unlock_irqrestore(&p
->lock
, flags
);
421 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
424 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
428 ret
= sh_cmt_start(p
, FLAG_CLOCKSOURCE
);
430 __clocksource_updatefreq_hz(cs
, p
->rate
);
434 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
436 sh_cmt_stop(cs_to_sh_cmt(cs
), FLAG_CLOCKSOURCE
);
439 static void sh_cmt_clocksource_resume(struct clocksource
*cs
)
441 sh_cmt_start(cs_to_sh_cmt(cs
), FLAG_CLOCKSOURCE
);
444 static int sh_cmt_register_clocksource(struct sh_cmt_priv
*p
,
445 char *name
, unsigned long rating
)
447 struct clocksource
*cs
= &p
->cs
;
451 cs
->read
= sh_cmt_clocksource_read
;
452 cs
->enable
= sh_cmt_clocksource_enable
;
453 cs
->disable
= sh_cmt_clocksource_disable
;
454 cs
->suspend
= sh_cmt_clocksource_disable
;
455 cs
->resume
= sh_cmt_clocksource_resume
;
456 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
457 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
459 dev_info(&p
->pdev
->dev
, "used as clock source\n");
461 /* Register with dummy 1 Hz value, gets updated in ->enable() */
462 clocksource_register_hz(cs
, 1);
466 static struct sh_cmt_priv
*ced_to_sh_cmt(struct clock_event_device
*ced
)
468 return container_of(ced
, struct sh_cmt_priv
, ced
);
471 static void sh_cmt_clock_event_start(struct sh_cmt_priv
*p
, int periodic
)
473 struct clock_event_device
*ced
= &p
->ced
;
475 sh_cmt_start(p
, FLAG_CLOCKEVENT
);
477 /* TODO: calculate good shift from rate and counter bit width */
480 ced
->mult
= div_sc(p
->rate
, NSEC_PER_SEC
, ced
->shift
);
481 ced
->max_delta_ns
= clockevent_delta2ns(p
->max_match_value
, ced
);
482 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
485 sh_cmt_set_next(p
, ((p
->rate
+ HZ
/2) / HZ
) - 1);
487 sh_cmt_set_next(p
, p
->max_match_value
);
490 static void sh_cmt_clock_event_mode(enum clock_event_mode mode
,
491 struct clock_event_device
*ced
)
493 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
495 /* deal with old setting first */
497 case CLOCK_EVT_MODE_PERIODIC
:
498 case CLOCK_EVT_MODE_ONESHOT
:
499 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
506 case CLOCK_EVT_MODE_PERIODIC
:
507 dev_info(&p
->pdev
->dev
, "used for periodic clock events\n");
508 sh_cmt_clock_event_start(p
, 1);
510 case CLOCK_EVT_MODE_ONESHOT
:
511 dev_info(&p
->pdev
->dev
, "used for oneshot clock events\n");
512 sh_cmt_clock_event_start(p
, 0);
514 case CLOCK_EVT_MODE_SHUTDOWN
:
515 case CLOCK_EVT_MODE_UNUSED
:
516 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
523 static int sh_cmt_clock_event_next(unsigned long delta
,
524 struct clock_event_device
*ced
)
526 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
528 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
529 if (likely(p
->flags
& FLAG_IRQCONTEXT
))
530 p
->next_match_value
= delta
- 1;
532 sh_cmt_set_next(p
, delta
- 1);
537 static void sh_cmt_register_clockevent(struct sh_cmt_priv
*p
,
538 char *name
, unsigned long rating
)
540 struct clock_event_device
*ced
= &p
->ced
;
542 memset(ced
, 0, sizeof(*ced
));
545 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
546 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
547 ced
->rating
= rating
;
548 ced
->cpumask
= cpumask_of(0);
549 ced
->set_next_event
= sh_cmt_clock_event_next
;
550 ced
->set_mode
= sh_cmt_clock_event_mode
;
552 dev_info(&p
->pdev
->dev
, "used for clock events\n");
553 clockevents_register_device(ced
);
556 static int sh_cmt_register(struct sh_cmt_priv
*p
, char *name
,
557 unsigned long clockevent_rating
,
558 unsigned long clocksource_rating
)
560 if (p
->width
== (sizeof(p
->max_match_value
) * 8))
561 p
->max_match_value
= ~0;
563 p
->max_match_value
= (1 << p
->width
) - 1;
565 p
->match_value
= p
->max_match_value
;
566 spin_lock_init(&p
->lock
);
568 if (clockevent_rating
)
569 sh_cmt_register_clockevent(p
, name
, clockevent_rating
);
571 if (clocksource_rating
)
572 sh_cmt_register_clocksource(p
, name
, clocksource_rating
);
577 static int sh_cmt_setup(struct sh_cmt_priv
*p
, struct platform_device
*pdev
)
579 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
580 struct resource
*res
;
584 memset(p
, 0, sizeof(*p
));
588 dev_err(&p
->pdev
->dev
, "missing platform data\n");
592 platform_set_drvdata(pdev
, p
);
594 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
596 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
600 irq
= platform_get_irq(p
->pdev
, 0);
602 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
606 /* map memory, let mapbase point to our channel */
607 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
608 if (p
->mapbase
== NULL
) {
609 dev_err(&p
->pdev
->dev
, "failed to remap I/O memory\n");
613 /* request irq using setup_irq() (too early for request_irq()) */
614 p
->irqaction
.name
= dev_name(&p
->pdev
->dev
);
615 p
->irqaction
.handler
= sh_cmt_interrupt
;
616 p
->irqaction
.dev_id
= p
;
617 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| \
618 IRQF_IRQPOLL
| IRQF_NOBALANCING
;
620 /* get hold of clock */
621 p
->clk
= clk_get(&p
->pdev
->dev
, "cmt_fck");
622 if (IS_ERR(p
->clk
)) {
623 dev_err(&p
->pdev
->dev
, "cannot get clock\n");
624 ret
= PTR_ERR(p
->clk
);
628 if (resource_size(res
) == 6) {
630 p
->overflow_bit
= 0x80;
631 p
->clear_bits
= ~0x80;
634 p
->overflow_bit
= 0x8000;
635 p
->clear_bits
= ~0xc000;
638 ret
= sh_cmt_register(p
, (char *)dev_name(&p
->pdev
->dev
),
639 cfg
->clockevent_rating
,
640 cfg
->clocksource_rating
);
642 dev_err(&p
->pdev
->dev
, "registration failed\n");
646 ret
= setup_irq(irq
, &p
->irqaction
);
648 dev_err(&p
->pdev
->dev
, "failed to request irq %d\n", irq
);
660 static int __devinit
sh_cmt_probe(struct platform_device
*pdev
)
662 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
666 dev_info(&pdev
->dev
, "kept as earlytimer\n");
667 pm_runtime_enable(&pdev
->dev
);
671 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
673 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
677 ret
= sh_cmt_setup(p
, pdev
);
680 platform_set_drvdata(pdev
, NULL
);
683 if (!is_early_platform_device(pdev
))
684 pm_runtime_enable(&pdev
->dev
);
688 static int __devexit
sh_cmt_remove(struct platform_device
*pdev
)
690 return -EBUSY
; /* cannot unregister clockevent and clocksource */
693 static struct platform_driver sh_cmt_device_driver
= {
694 .probe
= sh_cmt_probe
,
695 .remove
= __devexit_p(sh_cmt_remove
),
701 static int __init
sh_cmt_init(void)
703 return platform_driver_register(&sh_cmt_device_driver
);
706 static void __exit
sh_cmt_exit(void)
708 platform_driver_unregister(&sh_cmt_device_driver
);
711 early_platform_init("earlytimer", &sh_cmt_device_driver
);
712 module_init(sh_cmt_init
);
713 module_exit(sh_cmt_exit
);
715 MODULE_AUTHOR("Magnus Damm");
716 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
717 MODULE_LICENSE("GPL v2");