include/asm-arm/tlbflush.h

   1 /*
   2  *  linux/include/asm-arm/tlbflush.h
   3  *
   4  *  Copyright (C) 1999-2003 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_TLBFLUSH_H
  11 #define _ASMARM_TLBFLUSH_H
  12
  13 #include <linux/config.h>
  14
  15 #ifndef CONFIG_MMU
  16
  17 #define tlb_flush(tlb)  ((void) tlb)
  18
  19 #else /* CONFIG_MMU */
  20
  21 #include <asm/glue.h>
  22
  23 #define TLB_V3_PAGE     (1 << 0)
  24 #define TLB_V4_U_PAGE   (1 << 1)
  25 #define TLB_V4_D_PAGE   (1 << 2)
  26 #define TLB_V4_I_PAGE   (1 << 3)
  27 #define TLB_V6_U_PAGE   (1 << 4)
  28 #define TLB_V6_D_PAGE   (1 << 5)
  29 #define TLB_V6_I_PAGE   (1 << 6)
  30
  31 #define TLB_V3_FULL     (1 << 8)
  32 #define TLB_V4_U_FULL   (1 << 9)
  33 #define TLB_V4_D_FULL   (1 << 10)
  34 #define TLB_V4_I_FULL   (1 << 11)
  35 #define TLB_V6_U_FULL   (1 << 12)
  36 #define TLB_V6_D_FULL   (1 << 13)
  37 #define TLB_V6_I_FULL   (1 << 14)
  38
  39 #define TLB_V6_U_ASID   (1 << 16)
  40 #define TLB_V6_D_ASID   (1 << 17)
  41 #define TLB_V6_I_ASID   (1 << 18)
  42
  43 #define TLB_DCLEAN      (1 << 30)
  44 #define TLB_WB          (1 << 31)
  45
  46 /*
  47  *      MMU TLB Model
  48  *      =============
  49  *
  50  *      We have the following to choose from:
  51  *        v3    - ARMv3
  52  *        v4    - ARMv4 without write buffer
  53  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  54  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  55  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  56  */
  57 #undef _TLB
  58 #undef MULTI_TLB
  59
  60 #define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
  61
  62 #ifdef CONFIG_CPU_TLB_V3
  63 # define v3_possible_flags      v3_tlb_flags
  64 # define v3_always_flags        v3_tlb_flags
  65 # ifdef _TLB
  66 #  define MULTI_TLB 1
  67 # else
  68 #  define _TLB v3
  69 # endif
  70 #else
  71 # define v3_possible_flags      0
  72 # define v3_always_flags        (-1UL)
  73 #endif
  74
  75 #define v4_tlb_flags    (TLB_V4_U_FULL | TLB_V4_U_PAGE)
  76
  77 #ifdef CONFIG_CPU_TLB_V4WT
  78 # define v4_possible_flags      v4_tlb_flags
  79 # define v4_always_flags        v4_tlb_flags
  80 # ifdef _TLB
  81 #  define MULTI_TLB 1
  82 # else
  83 #  define _TLB v4
  84 # endif
  85 #else
  86 # define v4_possible_flags      0
  87 # define v4_always_flags        (-1UL)
  88 #endif
  89
  90 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
  91                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
  92                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
  93
  94 #ifdef CONFIG_CPU_TLB_V4WBI
  95 # define v4wbi_possible_flags   v4wbi_tlb_flags
  96 # define v4wbi_always_flags     v4wbi_tlb_flags
  97 # ifdef _TLB
  98 #  define MULTI_TLB 1
  99 # else
 100 #  define _TLB v4wbi
 101 # endif
 102 #else
 103 # define v4wbi_possible_flags   0
 104 # define v4wbi_always_flags     (-1UL)
 105 #endif
 106
 107 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
 108                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
 109                          TLB_V4_D_PAGE)
 110
 111 #ifdef CONFIG_CPU_TLB_V4WB
 112 # define v4wb_possible_flags    v4wb_tlb_flags
 113 # define v4wb_always_flags      v4wb_tlb_flags
 114 # ifdef _TLB
 115 #  define MULTI_TLB 1
 116 # else
 117 #  define _TLB v4wb
 118 # endif
 119 #else
 120 # define v4wb_possible_flags    0
 121 # define v4wb_always_flags      (-1UL)
 122 #endif
 123
 124 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
 125                          TLB_V6_I_FULL | TLB_V6_D_FULL | \
 126                          TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
 127                          TLB_V6_I_ASID | TLB_V6_D_ASID)
 128
 129 #ifdef CONFIG_CPU_TLB_V6
 130 # define v6wbi_possible_flags   v6wbi_tlb_flags
 131 # define v6wbi_always_flags     v6wbi_tlb_flags
 132 # ifdef _TLB
 133 #  define MULTI_TLB 1
 134 # else
 135 #  define _TLB v6wbi
 136 # endif
 137 #else
 138 # define v6wbi_possible_flags   0
 139 # define v6wbi_always_flags     (-1UL)
 140 #endif
 141
 142 #ifndef _TLB
 143 #error Unknown TLB model
 144 #endif
 145
 146 #ifndef __ASSEMBLY__
 147
 148 struct cpu_tlb_fns {
 149         void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
 150         void (*flush_kern_range)(unsigned long, unsigned long);
 151         unsigned long tlb_flags;
 152 };
 153
 154 /*
 155  * Select the calling method
 156  */
 157 #ifdef MULTI_TLB
 158
 159 #define __cpu_flush_user_tlb_range      cpu_tlb.flush_user_range
 160 #define __cpu_flush_kern_tlb_range      cpu_tlb.flush_kern_range
 161
 162 #else
 163
 164 #define __cpu_flush_user_tlb_range      __glue(_TLB,_flush_user_tlb_range)
 165 #define __cpu_flush_kern_tlb_range      __glue(_TLB,_flush_kern_tlb_range)
 166
 167 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
 168 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
 169
 170 #endif
 171
 172 extern struct cpu_tlb_fns cpu_tlb;
 173
 174 #define __cpu_tlb_flags                 cpu_tlb.tlb_flags
 175
 176 /*
 177  *      TLB Management
 178  *      ==============
 179  *
 180  *      The arch/arm/mm/tlb-*.S files implement these methods.
 181  *
 182  *      The TLB specific code is expected to perform whatever tests it
 183  *      needs to determine if it should invalidate the TLB for each
 184  *      call.  Start addresses are inclusive and end addresses are
 185  *      exclusive; it is safe to round these addresses down.
 186  *
 187  *      flush_tlb_all()
 188  *
 189  *              Invalidate the entire TLB.
 190  *
 191  *      flush_tlb_mm(mm)
 192  *
 193  *              Invalidate all TLB entries in a particular address
 194  *              space.
 195  *              - mm    - mm_struct describing address space
 196  *
 197  *      flush_tlb_range(mm,start,end)
 198  *
 199  *              Invalidate a range of TLB entries in the specified
 200  *              address space.
 201  *              - mm    - mm_struct describing address space
 202  *              - start - start address (may not be aligned)
 203  *              - end   - end address (exclusive, may not be aligned)
 204  *
 205  *      flush_tlb_page(vaddr,vma)
 206  *
 207  *              Invalidate the specified page in the specified address range.
 208  *              - vaddr - virtual address (may not be aligned)
 209  *              - vma   - vma_struct describing address range
 210  *
 211  *      flush_kern_tlb_page(kaddr)
 212  *
 213  *              Invalidate the TLB entry for the specified page.  The address
 214  *              will be in the kernels virtual memory space.  Current uses
 215  *              only require the D-TLB to be invalidated.
 216  *              - kaddr - Kernel virtual memory address
 217  */
 218
 219 /*
 220  * We optimise the code below by:
 221  *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 222  *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 223  *  - if we're going to need __cpu_tlb_flags, access it once and only once
 224  *
 225  * This allows us to build optimal assembly for the single-CPU type case,
 226  * and as close to optimal given the compiler constrants for multi-CPU
 227  * case.  We could do better for the multi-CPU case if the compiler
 228  * implemented the "%?" method, but this has been discontinued due to too
 229  * many people getting it wrong.
 230  */
 231 #define possible_tlb_flags      (v3_possible_flags | \
 232                                  v4_possible_flags | \
 233                                  v4wbi_possible_flags | \
 234                                  v4wb_possible_flags | \
 235                                  v6wbi_possible_flags)
 236
 237 #define always_tlb_flags        (v3_always_flags & \
 238                                  v4_always_flags & \
 239                                  v4wbi_always_flags & \
 240                                  v4wb_always_flags & \
 241                                  v6wbi_always_flags)
 242
 243 #define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
 244
 245 static inline void local_flush_tlb_all(void)
 246 {
 247         const int zero = 0;
 248         const unsigned int __tlb_flag = __cpu_tlb_flags;
 249
 250         if (tlb_flag(TLB_WB))
 251                 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 252
 253         if (tlb_flag(TLB_V3_FULL))
 254                 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
 255         if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
 256                 asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
 257         if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
 258                 asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
 259         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
 260                 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 261 }
 262
 263 static inline void local_flush_tlb_mm(struct mm_struct *mm)
 264 {
 265         const int zero = 0;
 266         const int asid = ASID(mm);
 267         const unsigned int __tlb_flag = __cpu_tlb_flags;
 268
 269         if (tlb_flag(TLB_WB))
 270                 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 271
 272         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
 273                 if (tlb_flag(TLB_V3_FULL))
 274                         asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
 275                 if (tlb_flag(TLB_V4_U_FULL))
 276                         asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
 277                 if (tlb_flag(TLB_V4_D_FULL))
 278                         asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
 279                 if (tlb_flag(TLB_V4_I_FULL))
 280                         asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 281         }
 282
 283         if (tlb_flag(TLB_V6_U_ASID))
 284                 asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
 285         if (tlb_flag(TLB_V6_D_ASID))
 286                 asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
 287         if (tlb_flag(TLB_V6_I_ASID))
 288                 asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
 289 }
 290
 291 static inline void
 292 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 293 {
 294         const int zero = 0;
 295         const unsigned int __tlb_flag = __cpu_tlb_flags;
 296
 297         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
 298
 299         if (tlb_flag(TLB_WB))
 300                 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 301
 302         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 303                 if (tlb_flag(TLB_V3_PAGE))
 304                         asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
 305                 if (tlb_flag(TLB_V4_U_PAGE))
 306                         asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
 307                 if (tlb_flag(TLB_V4_D_PAGE))
 308                         asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
 309                 if (tlb_flag(TLB_V4_I_PAGE))
 310                         asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
 311                 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 312                         asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 313         }
 314
 315         if (tlb_flag(TLB_V6_U_PAGE))
 316                 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
 317         if (tlb_flag(TLB_V6_D_PAGE))
 318                 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
 319         if (tlb_flag(TLB_V6_I_PAGE))
 320                 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
 321 }
 322
 323 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 324 {
 325         const int zero = 0;
 326         const unsigned int __tlb_flag = __cpu_tlb_flags;
 327
 328         kaddr &= PAGE_MASK;
 329
 330         if (tlb_flag(TLB_WB))
 331                 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 332
 333         if (tlb_flag(TLB_V3_PAGE))
 334                 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
 335         if (tlb_flag(TLB_V4_U_PAGE))
 336                 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
 337         if (tlb_flag(TLB_V4_D_PAGE))
 338                 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
 339         if (tlb_flag(TLB_V4_I_PAGE))
 340                 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
 341         if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 342                 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 343
 344         if (tlb_flag(TLB_V6_U_PAGE))
 345                 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
 346         if (tlb_flag(TLB_V6_D_PAGE))
 347                 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
 348         if (tlb_flag(TLB_V6_I_PAGE))
 349                 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
 350
 351         /* The ARM ARM states that the completion of a TLB maintenance
 352          * operation is only guaranteed by a DSB instruction
 353          */
 354         if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
 355                 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 356 }
 357
 358 /*
 359  *      flush_pmd_entry
 360  *
 361  *      Flush a PMD entry (word aligned, or double-word aligned) to
 362  *      RAM if the TLB for the CPU we are running on requires this.
 363  *      This is typically used when we are creating PMD entries.
 364  *
 365  *      clean_pmd_entry
 366  *
 367  *      Clean (but don't drain the write buffer) if the CPU requires
 368  *      these operations.  This is typically used when we are removing
 369  *      PMD entries.
 370  */
 371 static inline void flush_pmd_entry(pmd_t *pmd)
 372 {
 373         const unsigned int zero = 0;
 374         const unsigned int __tlb_flag = __cpu_tlb_flags;
 375
 376         if (tlb_flag(TLB_DCLEAN))
 377                 asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
 378                         : : "r" (pmd));
 379         if (tlb_flag(TLB_WB))
 380                 asm("mcr%?      p15, 0, %0, c7, c10, 4  @ flush_pmd"
 381                         : : "r" (zero));
 382 }
 383
 384 static inline void clean_pmd_entry(pmd_t *pmd)
 385 {
 386         const unsigned int __tlb_flag = __cpu_tlb_flags;
 387
 388         if (tlb_flag(TLB_DCLEAN))
 389                 asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
 390                         : : "r" (pmd));
 391 }
 392
 393 #undef tlb_flag
 394 #undef always_tlb_flags
 395 #undef possible_tlb_flags
 396
 397 /*
 398  * Convert calls to our calling convention.
 399  */
 400 #define local_flush_tlb_range(vma,start,end)    __cpu_flush_user_tlb_range(start,end,vma)
 401 #define local_flush_tlb_kernel_range(s,e)       __cpu_flush_kern_tlb_range(s,e)
 402
 403 #ifndef CONFIG_SMP
 404 #define flush_tlb_all           local_flush_tlb_all
 405 #define flush_tlb_mm            local_flush_tlb_mm
 406 #define flush_tlb_page          local_flush_tlb_page
 407 #define flush_tlb_kernel_page   local_flush_tlb_kernel_page
 408 #define flush_tlb_range         local_flush_tlb_range
 409 #define flush_tlb_kernel_range  local_flush_tlb_kernel_range
 410 #else
 411 extern void flush_tlb_all(void);
 412 extern void flush_tlb_mm(struct mm_struct *mm);
 413 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
 414 extern void flush_tlb_kernel_page(unsigned long kaddr);
 415 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 416 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 417 #endif
 418
 419 /*
 420  * if PG_dcache_dirty is set for the page, we need to ensure that any
 421  * cache entries for the kernels virtual memory range are written
 422  * back to the page.
 423  */
 424 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
 425
 426 /*
 427  * ARM processors do not cache TLB tables in RAM.
 428  */
 429 #define flush_tlb_pgtables(mm,start,end)        do { } while (0)
 430
 431 #endif
 432
 433 #endif /* CONFIG_MMU */
 434
 435 #endif