arch/mips/kernel/mips-mt.c

   1 /*
   2  * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
   3  * Copyright (C) 2005 Mips Technologies, Inc
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/sched.h>
   8 #include <linux/cpumask.h>
   9 #include <linux/interrupt.h>
  10
  11 #include <asm/cpu.h>
  12 #include <asm/processor.h>
  13 #include <asm/atomic.h>
  14 #include <asm/system.h>
  15 #include <asm/hardirq.h>
  16 #include <asm/mmu_context.h>
  17 #include <asm/smp.h>
  18 #include <asm/mipsmtregs.h>
  19 #include <asm/r4kcache.h>
  20 #include <asm/cacheflush.h>
  21
  22 /*
  23  * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
  24  */
  25
  26 cpumask_t mt_fpu_cpumask;
  27
  28 #ifdef CONFIG_MIPS_MT_FPAFF
  29
  30 #include <linux/cpu.h>
  31 #include <linux/delay.h>
  32 #include <asm/uaccess.h>
  33
  34 unsigned long mt_fpemul_threshold = 0;
  35
  36 /*
  37  * Replacement functions for the sys_sched_setaffinity() and
  38  * sys_sched_getaffinity() system calls, so that we can integrate
  39  * FPU affinity with the user's requested processor affinity.
  40  * This code is 98% identical with the sys_sched_setaffinity()
  41  * and sys_sched_getaffinity() system calls, and should be
  42  * updated when kernel/sched.c changes.
  43  */
  44
  45 /*
  46  * find_process_by_pid - find a process with a matching PID value.
  47  * used in sys_sched_set/getaffinity() in kernel/sched.c, so
  48  * cloned here.
  49  */
  50 static inline struct task_struct *find_process_by_pid(pid_t pid)
  51 {
  52         return pid ? find_task_by_pid(pid) : current;
  53 }
  54
  55
  56 /*
  57  * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
  58  */
  59 asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
  60                                       unsigned long __user *user_mask_ptr)
  61 {
  62         cpumask_t new_mask;
  63         cpumask_t effective_mask;
  64         int retval;
  65         struct task_struct *p;
  66
  67         if (len < sizeof(new_mask))
  68                 return -EINVAL;
  69
  70         if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
  71                 return -EFAULT;
  72
  73         lock_cpu_hotplug();
  74         read_lock(&tasklist_lock);
  75
  76         p = find_process_by_pid(pid);
  77         if (!p) {
  78                 read_unlock(&tasklist_lock);
  79                 unlock_cpu_hotplug();
  80                 return -ESRCH;
  81         }
  82
  83         /*
  84          * It is not safe to call set_cpus_allowed with the
  85          * tasklist_lock held.  We will bump the task_struct's
  86          * usage count and drop tasklist_lock before invoking
  87          * set_cpus_allowed.
  88          */
  89         get_task_struct(p);
  90
  91         retval = -EPERM;
  92         if ((current->euid != p->euid) && (current->euid != p->uid) &&
  93                         !capable(CAP_SYS_NICE)) {
  94                 read_unlock(&tasklist_lock);
  95                 goto out_unlock;
  96         }
  97
  98         /* Record new user-specified CPU set for future reference */
  99         p->thread.user_cpus_allowed = new_mask;
 100
 101         /* Unlock the task list */
 102         read_unlock(&tasklist_lock);
 103
 104         /* Compute new global allowed CPU set if necessary */
 105         if( (p->thread.mflags & MF_FPUBOUND)
 106         && cpus_intersects(new_mask, mt_fpu_cpumask)) {
 107                 cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
 108                 retval = set_cpus_allowed(p, effective_mask);
 109         } else {
 110                 p->thread.mflags &= ~MF_FPUBOUND;
 111                 retval = set_cpus_allowed(p, new_mask);
 112         }
 113
 114
 115 out_unlock:
 116         put_task_struct(p);
 117         unlock_cpu_hotplug();
 118         return retval;
 119 }
 120
 121 /*
 122  * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
 123  */
 124 asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
 125                                       unsigned long __user *user_mask_ptr)
 126 {
 127         unsigned int real_len;
 128         cpumask_t mask;
 129         int retval;
 130         struct task_struct *p;
 131
 132         real_len = sizeof(mask);
 133         if (len < real_len)
 134                 return -EINVAL;
 135
 136         lock_cpu_hotplug();
 137         read_lock(&tasklist_lock);
 138
 139         retval = -ESRCH;
 140         p = find_process_by_pid(pid);
 141         if (!p)
 142                 goto out_unlock;
 143
 144         retval = 0;
 145
 146         cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
 147
 148 out_unlock:
 149         read_unlock(&tasklist_lock);
 150         unlock_cpu_hotplug();
 151         if (retval)
 152                 return retval;
 153         if (copy_to_user(user_mask_ptr, &mask, real_len))
 154                 return -EFAULT;
 155         return real_len;
 156 }
 157
 158 #endif /* CONFIG_MIPS_MT_FPAFF */
 159
 160 /*
 161  * Dump new MIPS MT state for the core. Does not leave TCs halted.
 162  * Takes an argument which taken to be a pre-call MVPControl value.
 163  */
 164
 165 void mips_mt_regdump(unsigned long mvpctl)
 166 {
 167         unsigned long flags;
 168         unsigned long vpflags;
 169         unsigned long mvpconf0;
 170         int nvpe;
 171         int ntc;
 172         int i;
 173         int tc;
 174         unsigned long haltval;
 175         unsigned long tcstatval;
 176 #ifdef CONFIG_MIPS_MT_SMTC
 177         void smtc_soft_dump(void);
 178 #endif /* CONFIG_MIPT_MT_SMTC */
 179
 180         local_irq_save(flags);
 181         vpflags = dvpe();
 182         printk("=== MIPS MT State Dump ===\n");
 183         printk("-- Global State --\n");
 184         printk("   MVPControl Passed: %08lx\n", mvpctl);
 185         printk("   MVPControl Read: %08lx\n", vpflags);
 186         printk("   MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
 187         nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
 188         ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
 189         printk("-- per-VPE State --\n");
 190         for(i = 0; i < nvpe; i++) {
 191             for(tc = 0; tc < ntc; tc++) {
 192                         settc(tc);
 193                 if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
 194                     printk("  VPE %d\n", i);
 195                     printk("   VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
 196                     printk("   VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
 197                     printk("   VPE%d.Status : %08lx\n",
 198                                 i, read_vpe_c0_status());
 199                     printk("   VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc());
 200                     printk("   VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause());
 201                     printk("   VPE%d.Config7 : %08lx\n",
 202                                 i, read_vpe_c0_config7());
 203                     break; /* Next VPE */
 204                 }
 205             }
 206         }
 207         printk("-- per-TC State --\n");
 208         for(tc = 0; tc < ntc; tc++) {
 209                 settc(tc);
 210                 if(read_tc_c0_tcbind() == read_c0_tcbind()) {
 211                         /* Are we dumping ourself?  */
 212                         haltval = 0; /* Then we're not halted, and mustn't be */
 213                         tcstatval = flags; /* And pre-dump TCStatus is flags */
 214                         printk("  TC %d (current TC with VPE EPC above)\n", tc);
 215                 } else {
 216                         haltval = read_tc_c0_tchalt();
 217                         write_tc_c0_tchalt(1);
 218                         tcstatval = read_tc_c0_tcstatus();
 219                         printk("  TC %d\n", tc);
 220                 }
 221                 printk("   TCStatus : %08lx\n", tcstatval);
 222                 printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
 223                 printk("   TCRestart : %08lx\n", read_tc_c0_tcrestart());
 224                 printk("   TCHalt : %08lx\n", haltval);
 225                 printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
 226                 if (!haltval)
 227                         write_tc_c0_tchalt(0);
 228         }
 229 #ifdef CONFIG_MIPS_MT_SMTC
 230         smtc_soft_dump();
 231 #endif /* CONFIG_MIPT_MT_SMTC */
 232         printk("===========================\n");
 233         evpe(vpflags);
 234         local_irq_restore(flags);
 235 }
 236
 237 static int mt_opt_norps = 0;
 238 static int mt_opt_rpsctl = -1;
 239 static int mt_opt_nblsu = -1;
 240 static int mt_opt_forceconfig7 = 0;
 241 static int mt_opt_config7 = -1;
 242
 243 static int __init rps_disable(char *s)
 244 {
 245         mt_opt_norps = 1;
 246         return 1;
 247 }
 248 __setup("norps", rps_disable);
 249
 250 static int __init rpsctl_set(char *str)
 251 {
 252         get_option(&str, &mt_opt_rpsctl);
 253         return 1;
 254 }
 255 __setup("rpsctl=", rpsctl_set);
 256
 257 static int __init nblsu_set(char *str)
 258 {
 259         get_option(&str, &mt_opt_nblsu);
 260         return 1;
 261 }
 262 __setup("nblsu=", nblsu_set);
 263
 264 static int __init config7_set(char *str)
 265 {
 266         get_option(&str, &mt_opt_config7);
 267         mt_opt_forceconfig7 = 1;
 268         return 1;
 269 }
 270 __setup("config7=", config7_set);
 271
 272 /* Experimental cache flush control parameters that should go away some day */
 273 int mt_protiflush = 0;
 274 int mt_protdflush = 0;
 275 int mt_n_iflushes = 1;
 276 int mt_n_dflushes = 1;
 277
 278 static int __init set_protiflush(char *s)
 279 {
 280         mt_protiflush = 1;
 281         return 1;
 282 }
 283 __setup("protiflush", set_protiflush);
 284
 285 static int __init set_protdflush(char *s)
 286 {
 287         mt_protdflush = 1;
 288         return 1;
 289 }
 290 __setup("protdflush", set_protdflush);
 291
 292 static int __init niflush(char *s)
 293 {
 294         get_option(&s, &mt_n_iflushes);
 295         return 1;
 296 }
 297 __setup("niflush=", niflush);
 298
 299 static int __init ndflush(char *s)
 300 {
 301         get_option(&s, &mt_n_dflushes);
 302         return 1;
 303 }
 304 __setup("ndflush=", ndflush);
 305 #ifdef CONFIG_MIPS_MT_FPAFF
 306 static int fpaff_threshold = -1;
 307
 308 static int __init fpaff_thresh(char *str)
 309 {
 310         get_option(&str, &fpaff_threshold);
 311         return 1;
 312 }
 313
 314 __setup("fpaff=", fpaff_thresh);
 315 #endif /* CONFIG_MIPS_MT_FPAFF */
 316
 317 static unsigned int itc_base = 0;
 318
 319 static int __init set_itc_base(char *str)
 320 {
 321         get_option(&str, &itc_base);
 322         return 1;
 323 }
 324
 325 __setup("itcbase=", set_itc_base);
 326
 327 void mips_mt_set_cpuoptions(void)
 328 {
 329         unsigned int oconfig7 = read_c0_config7();
 330         unsigned int nconfig7 = oconfig7;
 331
 332         if (mt_opt_norps) {
 333                 printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
 334         }
 335         if (mt_opt_rpsctl >= 0) {
 336                 printk("34K return prediction stack override set to %d.\n",
 337                         mt_opt_rpsctl);
 338                 if (mt_opt_rpsctl)
 339                         nconfig7 |= (1 << 2);
 340                 else
 341                         nconfig7 &= ~(1 << 2);
 342         }
 343         if (mt_opt_nblsu >= 0) {
 344                 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
 345                 if (mt_opt_nblsu)
 346                         nconfig7 |= (1 << 5);
 347                 else
 348                         nconfig7 &= ~(1 << 5);
 349         }
 350         if (mt_opt_forceconfig7) {
 351                 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
 352                 nconfig7 = mt_opt_config7;
 353         }
 354         if (oconfig7 != nconfig7) {
 355                 __asm__ __volatile("sync");
 356                 write_c0_config7(nconfig7);
 357                 ehb ();
 358                 printk("Config7: 0x%08x\n", read_c0_config7());
 359         }
 360
 361         /* Report Cache management debug options */
 362         if (mt_protiflush)
 363                 printk("I-cache flushes single-threaded\n");
 364         if (mt_protdflush)
 365                 printk("D-cache flushes single-threaded\n");
 366         if (mt_n_iflushes != 1)
 367                 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
 368         if (mt_n_dflushes != 1)
 369                 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
 370
 371 #ifdef CONFIG_MIPS_MT_FPAFF
 372         /* FPU Use Factor empirically derived from experiments on 34K */
 373 #define FPUSEFACTOR 333
 374
 375         if (fpaff_threshold >= 0) {
 376                 mt_fpemul_threshold = fpaff_threshold;
 377         } else {
 378                 mt_fpemul_threshold =
 379                         (FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
 380         }
 381         printk("FPU Affinity set after %ld emulations\n",
 382                         mt_fpemul_threshold);
 383 #endif /* CONFIG_MIPS_MT_FPAFF */
 384
 385         if (itc_base != 0) {
 386                 /*
 387                  * Configure ITC mapping.  This code is very
 388                  * specific to the 34K core family, which uses
 389                  * a special mode bit ("ITC") in the ErrCtl
 390                  * register to enable access to ITC control
 391                  * registers via cache "tag" operations.
 392                  */
 393                 unsigned long ectlval;
 394                 unsigned long itcblkgrn;
 395
 396                 /* ErrCtl register is known as "ecc" to Linux */
 397                 ectlval = read_c0_ecc();
 398                 write_c0_ecc(ectlval | (0x1 << 26));
 399                 ehb();
 400 #define INDEX_0 (0x80000000)
 401 #define INDEX_8 (0x80000008)
 402                 /* Read "cache tag" for Dcache pseudo-index 8 */
 403                 cache_op(Index_Load_Tag_D, INDEX_8);
 404                 ehb();
 405                 itcblkgrn = read_c0_dtaglo();
 406                 itcblkgrn &= 0xfffe0000;
 407                 /* Set for 128 byte pitch of ITC cells */
 408                 itcblkgrn |= 0x00000c00;
 409                 /* Stage in Tag register */
 410                 write_c0_dtaglo(itcblkgrn);
 411                 ehb();
 412                 /* Write out to ITU with CACHE op */
 413                 cache_op(Index_Store_Tag_D, INDEX_8);
 414                 /* Now set base address, and turn ITC on with 0x1 bit */
 415                 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
 416                 ehb();
 417                 /* Write out to ITU with CACHE op */
 418                 cache_op(Index_Store_Tag_D, INDEX_0);
 419                 write_c0_ecc(ectlval);
 420                 ehb();
 421                 printk("Mapped %ld ITC cells starting at 0x%08x\n",
 422                         ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
 423         }
 424 }
 425
 426 /*
 427  * Function to protect cache flushes from concurrent execution
 428  * depends on MP software model chosen.
 429  */
 430
 431 void mt_cflush_lockdown(void)
 432 {
 433 #ifdef CONFIG_MIPS_MT_SMTC
 434         void smtc_cflush_lockdown(void);
 435
 436         smtc_cflush_lockdown();
 437 #endif /* CONFIG_MIPS_MT_SMTC */
 438         /* FILL IN VSMP and AP/SP VERSIONS HERE */
 439 }
 440
 441 void mt_cflush_release(void)
 442 {
 443 #ifdef CONFIG_MIPS_MT_SMTC
 444         void smtc_cflush_release(void);
 445
 446         smtc_cflush_release();
 447 #endif /* CONFIG_MIPS_MT_SMTC */
 448         /* FILL IN VSMP and AP/SP VERSIONS HERE */
 449 }