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crypto: omap-aes - unnecessary code removed
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / crypto / omap-aes.c
blob0b21dcef028929a61691971402c1d854946dfeb5
1 /*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 */
14
15 #define pr_fmt(fmt) "%s: " fmt, __func__
16
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/io.h>
27 #include <linux/crypto.h>
28 #include <linux/interrupt.h>
29 #include <crypto/scatterwalk.h>
30 #include <crypto/aes.h>
31
32 #include <plat/cpu.h>
33 #include <plat/dma.h>
34
35 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
36 number. For example 7:0 */
37 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
38 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
39
40 #define AES_REG_KEY(x) (0x1C - ((x ^ 0x01) * 0x04))
41 #define AES_REG_IV(x) (0x20 + ((x) * 0x04))
42
43 #define AES_REG_CTRL 0x30
44 #define AES_REG_CTRL_CTR_WIDTH (1 << 7)
45 #define AES_REG_CTRL_CTR (1 << 6)
46 #define AES_REG_CTRL_CBC (1 << 5)
47 #define AES_REG_CTRL_KEY_SIZE (3 << 3)
48 #define AES_REG_CTRL_DIRECTION (1 << 2)
49 #define AES_REG_CTRL_INPUT_READY (1 << 1)
50 #define AES_REG_CTRL_OUTPUT_READY (1 << 0)
51
52 #define AES_REG_DATA 0x34
53 #define AES_REG_DATA_N(x) (0x34 + ((x) * 0x04))
54
55 #define AES_REG_REV 0x44
56 #define AES_REG_REV_MAJOR 0xF0
57 #define AES_REG_REV_MINOR 0x0F
58
59 #define AES_REG_MASK 0x48
60 #define AES_REG_MASK_SIDLE (1 << 6)
61 #define AES_REG_MASK_START (1 << 5)
62 #define AES_REG_MASK_DMA_OUT_EN (1 << 3)
63 #define AES_REG_MASK_DMA_IN_EN (1 << 2)
64 #define AES_REG_MASK_SOFTRESET (1 << 1)
65 #define AES_REG_AUTOIDLE (1 << 0)
66
67 #define AES_REG_SYSSTATUS 0x4C
68 #define AES_REG_SYSSTATUS_RESETDONE (1 << 0)
69
70 #define DEFAULT_TIMEOUT (5*HZ)
71
72 #define FLAGS_MODE_MASK 0x000f
73 #define FLAGS_ENCRYPT BIT(0)
74 #define FLAGS_CBC BIT(1)
75 #define FLAGS_GIV BIT(2)
76
77 #define FLAGS_INIT BIT(4)
78 #define FLAGS_FAST BIT(5)
79 #define FLAGS_BUSY BIT(6)
80
81 struct omap_aes_ctx {
82 struct omap_aes_dev *dd;
83
84 int keylen;
85 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
86 unsigned long flags;
87 };
88
89 struct omap_aes_reqctx {
90 unsigned long mode;
91 };
92
93 #define OMAP_AES_QUEUE_LENGTH 1
94 #define OMAP_AES_CACHE_SIZE 0
95
96 struct omap_aes_dev {
97 struct list_head list;
98 unsigned long phys_base;
99 void __iomem *io_base;
100 struct clk *iclk;
101 struct omap_aes_ctx *ctx;
102 struct device *dev;
103 unsigned long flags;
104 int err;
105
106 spinlock_t lock;
107 struct crypto_queue queue;
108
109 struct tasklet_struct done_task;
110 struct tasklet_struct queue_task;
111
112 struct ablkcipher_request *req;
113 size_t total;
114 struct scatterlist *in_sg;
115 size_t in_offset;
116 struct scatterlist *out_sg;
117 size_t out_offset;
118
119 size_t buflen;
120 void *buf_in;
121 size_t dma_size;
122 int dma_in;
123 int dma_lch_in;
124 dma_addr_t dma_addr_in;
125 void *buf_out;
126 int dma_out;
127 int dma_lch_out;
128 dma_addr_t dma_addr_out;
129 };
130
131 /* keep registered devices data here */
132 static LIST_HEAD(dev_list);
133 static DEFINE_SPINLOCK(list_lock);
134
135 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
136 {
137 return __raw_readl(dd->io_base + offset);
138 }
139
140 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
141 u32 value)
142 {
143 __raw_writel(value, dd->io_base + offset);
144 }
145
146 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
147 u32 value, u32 mask)
148 {
149 u32 val;
150
151 val = omap_aes_read(dd, offset);
152 val &= ~mask;
153 val |= value;
154 omap_aes_write(dd, offset, val);
155 }
156
157 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
158 u32 *value, int count)
159 {
160 for (; count--; value++, offset += 4)
161 omap_aes_write(dd, offset, *value);
162 }
163
164 static int omap_aes_wait(struct omap_aes_dev *dd, u32 offset, u32 bit)
165 {
166 unsigned long timeout = jiffies + DEFAULT_TIMEOUT;
167
168 while (!(omap_aes_read(dd, offset) & bit)) {
169 if (time_is_before_jiffies(timeout)) {
170 dev_err(dd->dev, "omap-aes timeout\n");
171 return -ETIMEDOUT;
172 }
173 }
174 return 0;
175 }
176
177 static int omap_aes_hw_init(struct omap_aes_dev *dd)
178 {
179 clk_enable(dd->iclk);
180
181 if (!(dd->flags & FLAGS_INIT)) {
182 /* is it necessary to reset before every operation? */
183 omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_SOFTRESET,
184 AES_REG_MASK_SOFTRESET);
185 /*
186 * prevent OCP bus error (SRESP) in case an access to the module
187 * is performed while the module is coming out of soft reset
188 */
189 __asm__ __volatile__("nop");
190 __asm__ __volatile__("nop");
191
192 if (omap_aes_wait(dd, AES_REG_SYSSTATUS,
193 AES_REG_SYSSTATUS_RESETDONE)) {
194 clk_disable(dd->iclk);
195 return -ETIMEDOUT;
196 }
197 dd->flags |= FLAGS_INIT;
198 dd->err = 0;
199 }
200
201 return 0;
202 }
203
204 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
205 {
206 unsigned int key32;
207 int i, err;
208 u32 val, mask;
209
210 err = omap_aes_hw_init(dd);
211 if (err)
212 return err;
213
214 val = 0;
215 if (dd->dma_lch_out >= 0)
216 val |= AES_REG_MASK_DMA_OUT_EN;
217 if (dd->dma_lch_in >= 0)
218 val |= AES_REG_MASK_DMA_IN_EN;
219
220 mask = AES_REG_MASK_DMA_IN_EN | AES_REG_MASK_DMA_OUT_EN;
221
222 omap_aes_write_mask(dd, AES_REG_MASK, val, mask);
223
224 key32 = dd->ctx->keylen / sizeof(u32);
225
226 /* it seems a key should always be set even if it has not changed */
227 for (i = 0; i < key32; i++) {
228 omap_aes_write(dd, AES_REG_KEY(i),
229 __le32_to_cpu(dd->ctx->key[i]));
230 }
231
232 if ((dd->flags & FLAGS_CBC) && dd->req->info)
233 omap_aes_write_n(dd, AES_REG_IV(0), dd->req->info, 4);
234
235 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
236 if (dd->flags & FLAGS_CBC)
237 val |= AES_REG_CTRL_CBC;
238 if (dd->flags & FLAGS_ENCRYPT)
239 val |= AES_REG_CTRL_DIRECTION;
240
241 mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
242 AES_REG_CTRL_KEY_SIZE;
243
244 omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
245
246 /* start DMA or disable idle mode */
247 omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
248 AES_REG_MASK_START);
249
250 return 0;
251 }
252
253 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
254 {
255 struct omap_aes_dev *dd = NULL, *tmp;
256
257 spin_lock_bh(&list_lock);
258 if (!ctx->dd) {
259 list_for_each_entry(tmp, &dev_list, list) {
260 /* FIXME: take fist available aes core */
261 dd = tmp;
262 break;
263 }
264 ctx->dd = dd;
265 } else {
266 /* already found before */
267 dd = ctx->dd;
268 }
269 spin_unlock_bh(&list_lock);
270
271 return dd;
272 }
273
274 static void omap_aes_dma_callback(int lch, u16 ch_status, void *data)
275 {
276 struct omap_aes_dev *dd = data;
277
278 if (ch_status != OMAP_DMA_BLOCK_IRQ) {
279 pr_err("omap-aes DMA error status: 0x%hx\n", ch_status);
280 dd->err = -EIO;
281 dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
282 } else if (lch == dd->dma_lch_in) {
283 return;
284 }
285
286 /* dma_lch_out - completed */
287 tasklet_schedule(&dd->done_task);
288 }
289
290 static int omap_aes_dma_init(struct omap_aes_dev *dd)
291 {
292 int err = -ENOMEM;
293
294 dd->dma_lch_out = -1;
295 dd->dma_lch_in = -1;
296
297 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
298 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
299 dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE;
300 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
301
302 if (!dd->buf_in || !dd->buf_out) {
303 dev_err(dd->dev, "unable to alloc pages.\n");
304 goto err_alloc;
305 }
306
307 /* MAP here */
308 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen,
309 DMA_TO_DEVICE);
310 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
311 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
312 err = -EINVAL;
313 goto err_map_in;
314 }
315
316 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen,
317 DMA_FROM_DEVICE);
318 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
319 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
320 err = -EINVAL;
321 goto err_map_out;
322 }
323
324 err = omap_request_dma(dd->dma_in, "omap-aes-rx",
325 omap_aes_dma_callback, dd, &dd->dma_lch_in);
326 if (err) {
327 dev_err(dd->dev, "Unable to request DMA channel\n");
328 goto err_dma_in;
329 }
330 err = omap_request_dma(dd->dma_out, "omap-aes-tx",
331 omap_aes_dma_callback, dd, &dd->dma_lch_out);
332 if (err) {
333 dev_err(dd->dev, "Unable to request DMA channel\n");
334 goto err_dma_out;
335 }
336
337 return 0;
338
339 err_dma_out:
340 omap_free_dma(dd->dma_lch_in);
341 err_dma_in:
342 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
343 DMA_FROM_DEVICE);
344 err_map_out:
345 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
346 err_map_in:
347 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
348 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
349 err_alloc:
350 if (err)
351 pr_err("error: %d\n", err);
352 return err;
353 }
354
355 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
356 {
357 omap_free_dma(dd->dma_lch_out);
358 omap_free_dma(dd->dma_lch_in);
359 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
360 DMA_FROM_DEVICE);
361 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
362 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
363 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
364 }
365
366 static void sg_copy_buf(void *buf, struct scatterlist *sg,
367 unsigned int start, unsigned int nbytes, int out)
368 {
369 struct scatter_walk walk;
370
371 if (!nbytes)
372 return;
373
374 scatterwalk_start(&walk, sg);
375 scatterwalk_advance(&walk, start);
376 scatterwalk_copychunks(buf, &walk, nbytes, out);
377 scatterwalk_done(&walk, out, 0);
378 }
379
380 static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
381 size_t buflen, size_t total, int out)
382 {
383 unsigned int count, off = 0;
384
385 while (buflen && total) {
386 count = min((*sg)->length - *offset, total);
387 count = min(count, buflen);
388
389 if (!count)
390 return off;
391
392 /*
393 * buflen and total are AES_BLOCK_SIZE size aligned,
394 * so count should be also aligned
395 */
396
397 sg_copy_buf(buf + off, *sg, *offset, count, out);
398
399 off += count;
400 buflen -= count;
401 *offset += count;
402 total -= count;
403
404 if (*offset == (*sg)->length) {
405 *sg = sg_next(*sg);
406 if (*sg)
407 *offset = 0;
408 else
409 total = 0;
410 }
411 }
412
413 return off;
414 }
415
416 static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
417 dma_addr_t dma_addr_out, int length)
418 {
419 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
420 struct omap_aes_dev *dd = ctx->dd;
421 int len32;
422 int err;
423
424 pr_debug("len: %d\n", length);
425
426 dd->dma_size = length;
427
428 if (!(dd->flags & FLAGS_FAST))
429 dma_sync_single_for_device(dd->dev, dma_addr_in, length,
430 DMA_TO_DEVICE);
431
432 len32 = DIV_ROUND_UP(length, sizeof(u32));
433
434 /* IN */
435 omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
436 dd->phys_base + AES_REG_DATA, 0, 4);
437
438 omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
439 omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
440
441 omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32,
442 len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in,
443 OMAP_DMA_DST_SYNC);
444
445 omap_set_dma_src_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_POST_INC,
446 dma_addr_in, 0, 0);
447
448 /* OUT */
449 omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
450 dd->phys_base + AES_REG_DATA, 0, 4);
451
452 omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
453 omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
454
455 omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32,
456 len32, 1, OMAP_DMA_SYNC_PACKET,
457 dd->dma_out, OMAP_DMA_SRC_SYNC);
458
459 omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
460 dma_addr_out, 0, 0);
461
462 err = omap_aes_write_ctrl(dd);
463 if (err)
464 return err;
465
466 omap_start_dma(dd->dma_lch_in);
467 omap_start_dma(dd->dma_lch_out);
468
469 return 0;
470 }
471
472 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
473 {
474 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
475 crypto_ablkcipher_reqtfm(dd->req));
476 int err, fast = 0, in, out;
477 size_t count;
478 dma_addr_t addr_in, addr_out;
479
480 pr_debug("total: %d\n", dd->total);
481
482 if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
483 /* check for alignment */
484 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
485 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
486
487 fast = in && out;
488 }
489
490 if (fast) {
491 count = min(dd->total, sg_dma_len(dd->in_sg));
492 count = min(count, sg_dma_len(dd->out_sg));
493
494 if (count != dd->total) {
495 pr_err("request length != buffer length\n");
496 return -EINVAL;
497 }
498
499 pr_debug("fast\n");
500
501 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
502 if (!err) {
503 dev_err(dd->dev, "dma_map_sg() error\n");
504 return -EINVAL;
505 }
506
507 err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
508 if (!err) {
509 dev_err(dd->dev, "dma_map_sg() error\n");
510 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
511 return -EINVAL;
512 }
513
514 addr_in = sg_dma_address(dd->in_sg);
515 addr_out = sg_dma_address(dd->out_sg);
516
517 dd->flags |= FLAGS_FAST;
518
519 } else {
520 /* use cache buffers */
521 count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
522 dd->buflen, dd->total, 0);
523
524 addr_in = dd->dma_addr_in;
525 addr_out = dd->dma_addr_out;
526
527 dd->flags &= ~FLAGS_FAST;
528
529 }
530
531 dd->total -= count;
532
533 err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count);
534 if (err) {
535 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
536 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
537 }
538
539 return err;
540 }
541
542 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
543 {
544 struct ablkcipher_request *req = dd->req;
545
546 pr_debug("err: %d\n", err);
547
548 dd->flags &= ~FLAGS_BUSY;
549
550 req->base.complete(&req->base, err);
551 }
552
553 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
554 {
555 int err = 0;
556 size_t count;
557
558 pr_debug("total: %d\n", dd->total);
559
560 omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START);
561
562 omap_stop_dma(dd->dma_lch_in);
563 omap_stop_dma(dd->dma_lch_out);
564
565 clk_disable(dd->iclk);
566
567 if (dd->flags & FLAGS_FAST) {
568 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
569 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
570 } else {
571 dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
572 dd->dma_size, DMA_FROM_DEVICE);
573
574 /* copy data */
575 count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out,
576 dd->buflen, dd->dma_size, 1);
577 if (count != dd->dma_size) {
578 err = -EINVAL;
579 pr_err("not all data converted: %u\n", count);
580 }
581 }
582
583 return err;
584 }
585
586 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
587 struct ablkcipher_request *req)
588 {
589 struct crypto_async_request *async_req, *backlog;
590 struct omap_aes_ctx *ctx;
591 struct omap_aes_reqctx *rctx;
592 unsigned long flags;
593 int err, ret = 0;
594
595 spin_lock_irqsave(&dd->lock, flags);
596 if (req)
597 ret = ablkcipher_enqueue_request(&dd->queue, req);
598 if (dd->flags & FLAGS_BUSY) {
599 spin_unlock_irqrestore(&dd->lock, flags);
600 return ret;
601 }
602 backlog = crypto_get_backlog(&dd->queue);
603 async_req = crypto_dequeue_request(&dd->queue);
604 if (async_req)
605 dd->flags |= FLAGS_BUSY;
606 spin_unlock_irqrestore(&dd->lock, flags);
607
608 if (!async_req)
609 return ret;
610
611 if (backlog)
612 backlog->complete(backlog, -EINPROGRESS);
613
614 req = ablkcipher_request_cast(async_req);
615
616 /* assign new request to device */
617 dd->req = req;
618 dd->total = req->nbytes;
619 dd->in_offset = 0;
620 dd->in_sg = req->src;
621 dd->out_offset = 0;
622 dd->out_sg = req->dst;
623
624 rctx = ablkcipher_request_ctx(req);
625 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
626 rctx->mode &= FLAGS_MODE_MASK;
627 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
628
629 dd->ctx = ctx;
630 ctx->dd = dd;
631
632 err = omap_aes_crypt_dma_start(dd);
633 if (err) {
634 /* aes_task will not finish it, so do it here */
635 omap_aes_finish_req(dd, err);
636 tasklet_schedule(&dd->queue_task);
637 }
638
639 return ret; /* return ret, which is enqueue return value */
640 }
641
642 static void omap_aes_done_task(unsigned long data)
643 {
644 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
645 int err;
646
647 pr_debug("enter\n");
648
649 err = omap_aes_crypt_dma_stop(dd);
650
651 err = dd->err ? : err;
652
653 if (dd->total && !err) {
654 err = omap_aes_crypt_dma_start(dd);
655 if (!err)
656 return; /* DMA started. Not fininishing. */
657 }
658
659 omap_aes_finish_req(dd, err);
660 omap_aes_handle_queue(dd, NULL);
661
662 pr_debug("exit\n");
663 }
664
665 static void omap_aes_queue_task(unsigned long data)
666 {
667 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
668
669 omap_aes_handle_queue(dd, NULL);
670 }
671
672 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
673 {
674 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
675 crypto_ablkcipher_reqtfm(req));
676 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
677 struct omap_aes_dev *dd;
678
679 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
680 !!(mode & FLAGS_ENCRYPT),
681 !!(mode & FLAGS_CBC));
682
683 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
684 pr_err("request size is not exact amount of AES blocks\n");
685 return -EINVAL;
686 }
687
688 dd = omap_aes_find_dev(ctx);
689 if (!dd)
690 return -ENODEV;
691
692 rctx->mode = mode;
693
694 return omap_aes_handle_queue(dd, req);
695 }
696
697 /* ********************** ALG API ************************************ */
698
699 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
700 unsigned int keylen)
701 {
702 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
703
704 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
705 keylen != AES_KEYSIZE_256)
706 return -EINVAL;
707
708 pr_debug("enter, keylen: %d\n", keylen);
709
710 memcpy(ctx->key, key, keylen);
711 ctx->keylen = keylen;
712
713 return 0;
714 }
715
716 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
717 {
718 return omap_aes_crypt(req, FLAGS_ENCRYPT);
719 }
720
721 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
722 {
723 return omap_aes_crypt(req, 0);
724 }
725
726 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
727 {
728 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
729 }
730
731 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
732 {
733 return omap_aes_crypt(req, FLAGS_CBC);
734 }
735
736 static int omap_aes_cra_init(struct crypto_tfm *tfm)
737 {
738 pr_debug("enter\n");
739
740 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
741
742 return 0;
743 }
744
745 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
746 {
747 pr_debug("enter\n");
748 }
749
750 /* ********************** ALGS ************************************ */
751
752 static struct crypto_alg algs[] = {
753 {
754 .cra_name = "ecb(aes)",
755 .cra_driver_name = "ecb-aes-omap",
756 .cra_priority = 100,
757 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
758 .cra_blocksize = AES_BLOCK_SIZE,
759 .cra_ctxsize = sizeof(struct omap_aes_ctx),
760 .cra_alignmask = 0,
761 .cra_type = &crypto_ablkcipher_type,
762 .cra_module = THIS_MODULE,
763 .cra_init = omap_aes_cra_init,
764 .cra_exit = omap_aes_cra_exit,
765 .cra_u.ablkcipher = {
766 .min_keysize = AES_MIN_KEY_SIZE,
767 .max_keysize = AES_MAX_KEY_SIZE,
768 .setkey = omap_aes_setkey,
769 .encrypt = omap_aes_ecb_encrypt,
770 .decrypt = omap_aes_ecb_decrypt,
771 }
772 },
773 {
774 .cra_name = "cbc(aes)",
775 .cra_driver_name = "cbc-aes-omap",
776 .cra_priority = 100,
777 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
778 .cra_blocksize = AES_BLOCK_SIZE,
779 .cra_ctxsize = sizeof(struct omap_aes_ctx),
780 .cra_alignmask = 0,
781 .cra_type = &crypto_ablkcipher_type,
782 .cra_module = THIS_MODULE,
783 .cra_init = omap_aes_cra_init,
784 .cra_exit = omap_aes_cra_exit,
785 .cra_u.ablkcipher = {
786 .min_keysize = AES_MIN_KEY_SIZE,
787 .max_keysize = AES_MAX_KEY_SIZE,
788 .ivsize = AES_BLOCK_SIZE,
789 .setkey = omap_aes_setkey,
790 .encrypt = omap_aes_cbc_encrypt,
791 .decrypt = omap_aes_cbc_decrypt,
792 }
793 }
794 };
795
796 static int omap_aes_probe(struct platform_device *pdev)
797 {
798 struct device *dev = &pdev->dev;
799 struct omap_aes_dev *dd;
800 struct resource *res;
801 int err = -ENOMEM, i, j;
802 u32 reg;
803
804 dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
805 if (dd == NULL) {
806 dev_err(dev, "unable to alloc data struct.\n");
807 goto err_data;
808 }
809 dd->dev = dev;
810 platform_set_drvdata(pdev, dd);
811
812 spin_lock_init(&dd->lock);
813 crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
814
815 /* Get the base address */
816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817 if (!res) {
818 dev_err(dev, "invalid resource type\n");
819 err = -ENODEV;
820 goto err_res;
821 }
822 dd->phys_base = res->start;
823
824 /* Get the DMA */
825 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
826 if (!res)
827 dev_info(dev, "no DMA info\n");
828 else
829 dd->dma_out = res->start;
830
831 /* Get the DMA */
832 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
833 if (!res)
834 dev_info(dev, "no DMA info\n");
835 else
836 dd->dma_in = res->start;
837
838 /* Initializing the clock */
839 dd->iclk = clk_get(dev, "ick");
840 if (!dd->iclk) {
841 dev_err(dev, "clock intialization failed.\n");
842 err = -ENODEV;
843 goto err_res;
844 }
845
846 dd->io_base = ioremap(dd->phys_base, SZ_4K);
847 if (!dd->io_base) {
848 dev_err(dev, "can't ioremap\n");
849 err = -ENOMEM;
850 goto err_io;
851 }
852
853 clk_enable(dd->iclk);
854 reg = omap_aes_read(dd, AES_REG_REV);
855 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
856 (reg & AES_REG_REV_MAJOR) >> 4, reg & AES_REG_REV_MINOR);
857 clk_disable(dd->iclk);
858
859 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
860 tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
861
862 err = omap_aes_dma_init(dd);
863 if (err)
864 goto err_dma;
865
866 INIT_LIST_HEAD(&dd->list);
867 spin_lock(&list_lock);
868 list_add_tail(&dd->list, &dev_list);
869 spin_unlock(&list_lock);
870
871 for (i = 0; i < ARRAY_SIZE(algs); i++) {
872 pr_debug("i: %d\n", i);
873 INIT_LIST_HEAD(&algs[i].cra_list);
874 err = crypto_register_alg(&algs[i]);
875 if (err)
876 goto err_algs;
877 }
878
879 pr_info("probe() done\n");
880
881 return 0;
882 err_algs:
883 for (j = 0; j < i; j++)
884 crypto_unregister_alg(&algs[j]);
885 omap_aes_dma_cleanup(dd);
886 err_dma:
887 tasklet_kill(&dd->done_task);
888 tasklet_kill(&dd->queue_task);
889 iounmap(dd->io_base);
890 err_io:
891 clk_put(dd->iclk);
892 err_res:
893 kfree(dd);
894 dd = NULL;
895 err_data:
896 dev_err(dev, "initialization failed.\n");
897 return err;
898 }
899
900 static int omap_aes_remove(struct platform_device *pdev)
901 {
902 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
903 int i;
904
905 if (!dd)
906 return -ENODEV;
907
908 spin_lock(&list_lock);
909 list_del(&dd->list);
910 spin_unlock(&list_lock);
911
912 for (i = 0; i < ARRAY_SIZE(algs); i++)
913 crypto_unregister_alg(&algs[i]);
914
915 tasklet_kill(&dd->done_task);
916 tasklet_kill(&dd->queue_task);
917 omap_aes_dma_cleanup(dd);
918 iounmap(dd->io_base);
919 clk_put(dd->iclk);
920 kfree(dd);
921 dd = NULL;
922
923 return 0;
924 }
925
926 static struct platform_driver omap_aes_driver = {
927 .probe = omap_aes_probe,
928 .remove = omap_aes_remove,
929 .driver = {
930 .name = "omap-aes",
931 .owner = THIS_MODULE,
932 },
933 };
934
935 static int __init omap_aes_mod_init(void)
936 {
937 pr_info("loading %s driver\n", "omap-aes");
938
939 if (!cpu_class_is_omap2() || omap_type() != OMAP2_DEVICE_TYPE_SEC) {
940 pr_err("Unsupported cpu\n");
941 return -ENODEV;
942 }
943
944 return platform_driver_register(&omap_aes_driver);
945 }
946
947 static void __exit omap_aes_mod_exit(void)
948 {
949 platform_driver_unregister(&omap_aes_driver);
950 }
951
952 module_init(omap_aes_mod_init);
953 module_exit(omap_aes_mod_exit);
954
955 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
956 MODULE_LICENSE("GPL v2");
957 MODULE_AUTHOR("Dmitry Kasatkin");
958
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree