include/asm-x86_64/ipi.h

   1 #ifndef __ASM_IPI_H
   2 #define __ASM_IPI_H
   3
   4 /*
   5  * Copyright 2004 James Cleverdon, IBM.
   6  * Subject to the GNU Public License, v.2
   7  *
   8  * Generic APIC InterProcessor Interrupt code.
   9  *
  10  * Moved to include file by James Cleverdon from
  11  * arch/x86-64/kernel/smp.c
  12  *
  13  * Copyrights from kernel/smp.c:
  14  *
  15  * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  16  * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
  17  * (c) 2002,2003 Andi Kleen, SuSE Labs.
  18  * Subject to the GNU Public License, v.2
  19  */
  20
  21 #include <asm/fixmap.h>
  22 #include <asm/hw_irq.h>
  23 #include <asm/apicdef.h>
  24 #include <asm/genapic.h>
  25
  26 /*
  27  * the following functions deal with sending IPIs between CPUs.
  28  *
  29  * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
  30  */
  31
  32 static inline unsigned int __prepare_ICR (unsigned int shortcut, int vector, unsigned int dest)
  33 {
  34         unsigned int icr = shortcut | dest;
  35
  36         switch (vector) {
  37         default:
  38                 icr |= APIC_DM_FIXED | vector;
  39                 break;
  40         case NMI_VECTOR:
  41                 /*
  42                  * Setup KDB IPI to be delivered as an NMI
  43                  */
  44         case KDB_VECTOR:
  45                 icr |= APIC_DM_NMI;
  46                 break;
  47         }
  48         return icr;
  49 }
  50
  51 static inline int __prepare_ICR2 (unsigned int mask)
  52 {
  53         return SET_APIC_DEST_FIELD(mask);
  54 }
  55
  56 static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest)
  57 {
  58         /*
  59          * Subtle. In the case of the 'never do double writes' workaround
  60          * we have to lock out interrupts to be safe.  As we don't care
  61          * of the value read we use an atomic rmw access to avoid costly
  62          * cli/sti.  Otherwise we use an even cheaper single atomic write
  63          * to the APIC.
  64          */
  65         unsigned int cfg;
  66
  67         /*
  68          * Wait for idle.
  69          */
  70         apic_wait_icr_idle();
  71
  72         /*
  73          * No need to touch the target chip field
  74          */
  75         cfg = __prepare_ICR(shortcut, vector, dest);
  76
  77         /*
  78          * Send the IPI. The write to APIC_ICR fires this off.
  79          */
  80         apic_write(APIC_ICR, cfg);
  81 }
  82
  83
  84 static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
  85 {
  86         unsigned long cfg, flags;
  87         unsigned long query_cpu;
  88
  89         /*
  90          * Hack. The clustered APIC addressing mode doesn't allow us to send
  91          * to an arbitrary mask, so I do a unicast to each CPU instead.
  92          * - mbligh
  93          */
  94         local_irq_save(flags);
  95
  96         for_each_cpu_mask(query_cpu, mask) {
  97                 /*
  98                  * Wait for idle.
  99                  */
 100                 apic_wait_icr_idle();
 101
 102                 /*
 103                  * prepare target chip field
 104                  */
 105                 cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
 106                 apic_write(APIC_ICR2, cfg);
 107
 108                 /*
 109                  * program the ICR
 110                  */
 111                 cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
 112
 113                 /*
 114                  * Send the IPI. The write to APIC_ICR fires this off.
 115                  */
 116                 apic_write(APIC_ICR, cfg);
 117         }
 118         local_irq_restore(flags);
 119 }
 120
 121 #endif /* __ASM_IPI_H */