2 * Copyright 2007 David Gibson, IBM Corporation.
4 * Based on earlier code:
5 * Matt Porter <mporter@kernel.crashing.org>
6 * Copyright 2002-2005 MontaVista Software Inc.
8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 * Copyright (c) 2003, 2004 Zultys Technologies
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
24 /* Read the 4xx SDRAM controller to get size of system memory. */
25 void ibm4xx_sdram_fixup_memsize(void)
28 unsigned long memsize
, bank_config
;
31 for (i
= 0; i
< ARRAY_SIZE(sdram_bxcr
); i
++) {
32 bank_config
= SDRAM0_READ(sdram_bxcr
[i
]);
33 if (bank_config
& SDRAM_CONFIG_BANK_ENABLE
)
34 memsize
+= SDRAM_CONFIG_BANK_SIZE(bank_config
);
37 dt_fixup_memory(0, memsize
);
40 /* Read the 440SPe MQ controller to get size of system memory. */
41 #define DCRN_MQ0_B0BAS 0x40
42 #define DCRN_MQ0_B1BAS 0x41
43 #define DCRN_MQ0_B2BAS 0x42
44 #define DCRN_MQ0_B3BAS 0x43
46 static u64
ibm440spe_decode_bas(u32 bas
)
48 u64 base
= ((u64
)(bas
& 0xFFE00000u
)) << 2;
50 /* open coded because I'm paranoid about invalid values */
51 switch ((bas
>> 4) & 0xFFF) {
55 return base
+ 0x000800000ull
;
57 return base
+ 0x001000000ull
;
59 return base
+ 0x002000000ull
;
61 return base
+ 0x004000000ull
;
63 return base
+ 0x008000000ull
;
65 return base
+ 0x010000000ull
;
67 return base
+ 0x020000000ull
;
69 return base
+ 0x040000000ull
;
71 return base
+ 0x080000000ull
;
73 return base
+ 0x100000000ull
;
75 printf("Memory BAS value 0x%08x unsupported !\n", bas
);
79 void ibm440spe_fixup_memsize(void)
81 u64 banktop
, memsize
= 0;
83 /* Ultimately, we should directly construct the memory node
84 * so we are able to handle holes in the memory address space
86 banktop
= ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS
));
87 if (banktop
> memsize
)
89 banktop
= ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS
));
90 if (banktop
> memsize
)
92 banktop
= ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS
));
93 if (banktop
> memsize
)
95 banktop
= ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS
));
96 if (banktop
> memsize
)
99 dt_fixup_memory(0, memsize
);
103 /* 4xx DDR1/2 Denali memory controller support */
113 #define DDR_START 0x1
114 #define DDR_START_SHIFT 0
115 #define DDR_MAX_CS_REG 0x3
116 #define DDR_MAX_CS_REG_SHIFT 24
117 #define DDR_MAX_COL_REG 0xf
118 #define DDR_MAX_COL_REG_SHIFT 16
119 #define DDR_MAX_ROW_REG 0xf
120 #define DDR_MAX_ROW_REG_SHIFT 8
122 #define DDR_DDR2_MODE 0x1
123 #define DDR_DDR2_MODE_SHIFT 0
125 #define DDR_CS_MAP 0x3
126 #define DDR_CS_MAP_SHIFT 8
128 #define DDR_REDUC 0x1
129 #define DDR_REDUC_SHIFT 16
132 #define DDR_APIN_SHIFT 24
134 #define DDR_COL_SZ 0x7
135 #define DDR_COL_SZ_SHIFT 8
136 #define DDR_BANK8 0x1
137 #define DDR_BANK8_SHIFT 0
139 #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
141 void ibm4xx_denali_fixup_memsize(void)
143 u32 val
, max_cs
, max_col
, max_row
;
144 u32 cs
, col
, row
, bank
, dpath
;
145 unsigned long memsize
;
147 val
= SDRAM0_READ(DDR0_02
);
148 if (!DDR_GET_VAL(val
, DDR_START
, DDR_START_SHIFT
))
149 fatal("DDR controller is not initialized\n");
151 /* get maximum cs col and row values */
152 max_cs
= DDR_GET_VAL(val
, DDR_MAX_CS_REG
, DDR_MAX_CS_REG_SHIFT
);
153 max_col
= DDR_GET_VAL(val
, DDR_MAX_COL_REG
, DDR_MAX_COL_REG_SHIFT
);
154 max_row
= DDR_GET_VAL(val
, DDR_MAX_ROW_REG
, DDR_MAX_ROW_REG_SHIFT
);
157 val
= SDRAM0_READ(DDR0_10
);
159 val
= DDR_GET_VAL(val
, DDR_CS_MAP
, DDR_CS_MAP_SHIFT
);
168 fatal("No memory installed\n");
170 fatal("DDR wrong CS configuration\n");
172 /* get data path bytes */
173 val
= SDRAM0_READ(DDR0_14
);
175 if (DDR_GET_VAL(val
, DDR_REDUC
, DDR_REDUC_SHIFT
))
176 dpath
= 8; /* 64 bits */
178 dpath
= 4; /* 32 bits */
180 /* get address pins (rows) */
181 val
= SDRAM0_READ(DDR0_42
);
183 row
= DDR_GET_VAL(val
, DDR_APIN
, DDR_APIN_SHIFT
);
185 fatal("DDR wrong APIN configuration\n");
188 /* get collomn size and banks */
189 val
= SDRAM0_READ(DDR0_43
);
191 col
= DDR_GET_VAL(val
, DDR_COL_SZ
, DDR_COL_SZ_SHIFT
);
193 fatal("DDR wrong COL configuration\n");
196 if (DDR_GET_VAL(val
, DDR_BANK8
, DDR_BANK8_SHIFT
))
197 bank
= 8; /* 8 banks */
199 bank
= 4; /* 4 banks */
201 memsize
= cs
* (1 << (col
+row
)) * bank
* dpath
;
202 dt_fixup_memory(0, memsize
);
205 #define SPRN_DBCR0_40X 0x3F2
206 #define SPRN_DBCR0_44X 0x134
207 #define DBCR0_RST_SYSTEM 0x30000000
209 void ibm44x_dbcr_reset(void)
217 : "=&r"(tmp
) : "i"(SPRN_DBCR0_44X
), "i"(DBCR0_RST_SYSTEM
)
222 void ibm40x_dbcr_reset(void)
230 : "=&r"(tmp
) : "i"(SPRN_DBCR0_40X
), "i"(DBCR0_RST_SYSTEM
)
234 #define EMAC_RESET 0x20000000
235 void ibm4xx_quiesce_eth(u32
*emac0
, u32
*emac1
)
237 /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
245 mtdcr(DCRN_MAL0_CFG
, MAL_RESET
);
246 while (mfdcr(DCRN_MAL0_CFG
) & MAL_RESET
)
247 ; /* loop until reset takes effect */
250 /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
251 * banks into the OPB address space */
252 void ibm4xx_fixup_ebc_ranges(const char *ebc
)
256 u32 ranges
[EBC_NUM_BANKS
*4];
260 for (i
= 0; i
< EBC_NUM_BANKS
; i
++) {
261 mtdcr(DCRN_EBC0_CFGADDR
, EBC_BXCR(i
));
262 bxcr
= mfdcr(DCRN_EBC0_CFGDATA
);
264 if ((bxcr
& EBC_BXCR_BU
) != EBC_BXCR_BU_OFF
) {
267 *p
++ = bxcr
& EBC_BXCR_BAS
;
268 *p
++ = EBC_BXCR_BANK_SIZE(bxcr
);
272 devp
= finddevice(ebc
);
274 fatal("Couldn't locate EBC node %s\n\r", ebc
);
276 setprop(devp
, "ranges", ranges
, (p
- ranges
) * sizeof(u32
));
279 /* Calculate 440GP clocks */
280 void ibm440gp_fixup_clocks(unsigned int sys_clk
, unsigned int ser_clk
)
282 u32 sys0
= mfdcr(DCRN_CPC0_SYS0
);
283 u32 cr0
= mfdcr(DCRN_CPC0_CR0
);
284 u32 cpu
, plb
, opb
, ebc
, tb
, uart0
, uart1
, m
;
285 u32 opdv
= CPC0_SYS0_OPDV(sys0
);
286 u32 epdv
= CPC0_SYS0_EPDV(sys0
);
288 if (sys0
& CPC0_SYS0_BYPASS
) {
289 /* Bypass system PLL */
292 if (sys0
& CPC0_SYS0_EXTSL
)
294 m
= CPC0_SYS0_FWDVB(sys0
) * opdv
* epdv
;
297 m
= CPC0_SYS0_FBDV(sys0
) * CPC0_SYS0_FWDVA(sys0
);
298 cpu
= sys_clk
* m
/ CPC0_SYS0_FWDVA(sys0
);
299 plb
= sys_clk
* m
/ CPC0_SYS0_FWDVB(sys0
);
305 /* FIXME: Check if this is for all 440GP, or just Ebony */
306 if ((mfpvr() & 0xf0000fff) == 0x40000440)
307 /* Rev. B 440GP, use external system clock */
310 /* Rev. C 440GP, errata force us to use internal clock */
313 if (cr0
& CPC0_CR0_U0EC
)
314 /* External UART clock */
317 /* Internal UART clock */
318 uart0
= plb
/ CPC0_CR0_UDIV(cr0
);
320 if (cr0
& CPC0_CR0_U1EC
)
321 /* External UART clock */
324 /* Internal UART clock */
325 uart1
= plb
/ CPC0_CR0_UDIV(cr0
);
327 printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
328 (sys_clk
+ 500000) / 1000000, sys_clk
);
330 dt_fixup_cpu_clocks(cpu
, tb
, 0);
332 dt_fixup_clock("/plb", plb
);
333 dt_fixup_clock("/plb/opb", opb
);
334 dt_fixup_clock("/plb/opb/ebc", ebc
);
335 dt_fixup_clock("/plb/opb/serial@40000200", uart0
);
336 dt_fixup_clock("/plb/opb/serial@40000300", uart1
);
339 #define SPRN_CCR1 0x378
341 static inline u32
__fix_zero(u32 v
, u32 def
)
346 static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk
,
347 unsigned int tmr_clk
,
348 int per_clk_from_opb
)
351 u32 pllc
= CPR0_READ(DCRN_CPR0_PLLC
);
352 u32 plld
= CPR0_READ(DCRN_CPR0_PLLD
);
355 u32 fbdv
= __fix_zero((plld
>> 24) & 0x1f, 32);
356 u32 fwdva
= __fix_zero((plld
>> 16) & 0xf, 16);
357 u32 fwdvb
= __fix_zero((plld
>> 8) & 7, 8);
358 u32 lfbdv
= __fix_zero(plld
& 0x3f, 64);
359 u32 pradv0
= __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD
) >> 24) & 7, 8);
360 u32 prbdv0
= __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD
) >> 24) & 7, 8);
361 u32 opbdv0
= __fix_zero((CPR0_READ(DCRN_CPR0_OPBD
) >> 24) & 3, 4);
362 u32 perdv0
= __fix_zero((CPR0_READ(DCRN_CPR0_PERD
) >> 24) & 3, 4);
364 /* Input clocks for primary dividers */
367 /* Resulting clocks */
368 u32 cpu
, plb
, opb
, ebc
, vco
;
371 u32 ccr1
, tb
= tmr_clk
;
373 if (pllc
& 0x40000000) {
377 switch ((pllc
>> 24) & 7) {
380 m
= ((pllc
& 0x20000000) ? fwdvb
: fwdva
) * lfbdv
;
388 m
= fwdvb
* prbdv0
* opbdv0
* perdv0
;
391 printf("WARNING ! Invalid PLL feedback source !\n");
400 /* Bypass system PLL */
402 clk_a
= clk_b
= sys_clk
;
405 cpu
= clk_a
/ pradv0
;
406 plb
= clk_b
/ prbdv0
;
408 ebc
= (per_clk_from_opb
? opb
: plb
) / perdv0
;
410 /* Figure out timebase. Either CPU or default TmrClk */
411 ccr1
= mfspr(SPRN_CCR1
);
413 /* If passed a 0 tmr_clk, force CPU clock */
416 mtspr(SPRN_CCR1
, ccr1
);
418 if ((ccr1
& 0x0080) == 0)
421 dt_fixup_cpu_clocks(cpu
, tb
, 0);
422 dt_fixup_clock("/plb", plb
);
423 dt_fixup_clock("/plb/opb", opb
);
424 dt_fixup_clock("/plb/opb/ebc", ebc
);
429 static void eplike_fixup_uart_clk(int index
, const char *path
,
430 unsigned int ser_clk
,
431 unsigned int plb_clk
)
438 sdr
= SDR0_READ(DCRN_SDR0_UART0
);
441 sdr
= SDR0_READ(DCRN_SDR0_UART1
);
444 sdr
= SDR0_READ(DCRN_SDR0_UART2
);
447 sdr
= SDR0_READ(DCRN_SDR0_UART3
);
453 if (sdr
& 0x00800000u
)
456 clock
= plb_clk
/ __fix_zero(sdr
& 0xff, 256);
458 dt_fixup_clock(path
, clock
);
461 void ibm440ep_fixup_clocks(unsigned int sys_clk
,
462 unsigned int ser_clk
,
463 unsigned int tmr_clk
)
465 unsigned int plb_clk
= __ibm440eplike_fixup_clocks(sys_clk
, tmr_clk
, 0);
467 /* serial clocks beed fixup based on int/ext */
468 eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk
, plb_clk
);
469 eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk
, plb_clk
);
470 eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk
, plb_clk
);
471 eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk
, plb_clk
);
474 void ibm440gx_fixup_clocks(unsigned int sys_clk
,
475 unsigned int ser_clk
,
476 unsigned int tmr_clk
)
478 unsigned int plb_clk
= __ibm440eplike_fixup_clocks(sys_clk
, tmr_clk
, 1);
480 /* serial clocks beed fixup based on int/ext */
481 eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk
, plb_clk
);
482 eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk
, plb_clk
);
485 void ibm440spe_fixup_clocks(unsigned int sys_clk
,
486 unsigned int ser_clk
,
487 unsigned int tmr_clk
)
489 unsigned int plb_clk
= __ibm440eplike_fixup_clocks(sys_clk
, tmr_clk
, 1);
491 /* serial clocks beed fixup based on int/ext */
492 eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk
, plb_clk
);
493 eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk
, plb_clk
);
494 eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk
, plb_clk
);
497 void ibm405gp_fixup_clocks(unsigned int sys_clk
, unsigned int ser_clk
)
499 u32 pllmr
= mfdcr(DCRN_CPC0_PLLMR
);
500 u32 cpc0_cr0
= mfdcr(DCRN_405_CPC0_CR0
);
501 u32 cpc0_cr1
= mfdcr(DCRN_405_CPC0_CR1
);
502 u32 cpu
, plb
, opb
, ebc
, tb
, uart0
, uart1
, m
;
503 u32 fwdv
, fbdv
, cbdv
, opdv
, epdv
, udiv
;
505 fwdv
= (8 - ((pllmr
& 0xe0000000) >> 29));
506 fbdv
= (pllmr
& 0x1e000000) >> 25;
507 cbdv
= ((pllmr
& 0x00060000) >> 17) + 1;
508 opdv
= ((pllmr
& 0x00018000) >> 15) + 1;
509 epdv
= ((pllmr
& 0x00001800) >> 13) + 2;
510 udiv
= ((cpc0_cr0
& 0x3e) >> 1) + 1;
512 m
= fwdv
* fbdv
* cbdv
;
514 cpu
= sys_clk
* m
/ fwdv
;
520 /* uart0 uses the external clock */
526 /* uart1 uses the external clock */
531 /* setup the timebase clock to tick at the cpu frequency */
532 cpc0_cr1
= cpc0_cr1
& ~0x00800000;
533 mtdcr(DCRN_405_CPC0_CR1
, cpc0_cr1
);
536 dt_fixup_cpu_clocks(cpu
, tb
, 0);
537 dt_fixup_clock("/plb", plb
);
538 dt_fixup_clock("/plb/opb", opb
);
539 dt_fixup_clock("/plb/ebc", ebc
);
540 dt_fixup_clock("/plb/opb/serial@ef600300", uart0
);
541 dt_fixup_clock("/plb/opb/serial@ef600400", uart1
);