arch/arm/mach-at91rm9200/gpio.c

   1 /*
   2  * linux/arch/arm/mach-at91rm9200/gpio.c
   3  *
   4  * Copyright (C) 2005 HP Labs
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/errno.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/module.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/hardware.h>
  22 #include <asm/arch/at91_pio.h>
  23 #include <asm/arch/at91_pmc.h>
  24 #include <asm/arch/gpio.h>
  25
  26 #include "generic.h"
  27
  28
  29 static struct at91_gpio_bank *gpio;
  30 static int gpio_banks;
  31
  32
  33 static inline void __iomem *pin_to_controller(unsigned pin)
  34 {
  35         void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
  36
  37         pin -= PIN_BASE;
  38         pin /= 32;
  39         if (likely(pin < gpio_banks))
  40                 return sys_base + gpio[pin].offset;
  41
  42         return NULL;
  43 }
  44
  45 static inline unsigned pin_to_mask(unsigned pin)
  46 {
  47         pin -= PIN_BASE;
  48         return 1 << (pin % 32);
  49 }
  50
  51
  52 /*--------------------------------------------------------------------------*/
  53
  54 /* Not all hardware capabilities are exposed through these calls; they
  55  * only encapsulate the most common features and modes.  (So if you
  56  * want to change signals in groups, do it directly.)
  57  *
  58  * Bootloaders will usually handle some of the pin multiplexing setup.
  59  * The intent is certainly that by the time Linux is fully booted, all
  60  * pins should have been fully initialized.  These setup calls should
  61  * only be used by board setup routines, or possibly in driver probe().
  62  *
  63  * For bootloaders doing all that setup, these calls could be inlined
  64  * as NOPs so Linux won't duplicate any setup code
  65  */
  66
  67
  68 /*
  69  * mux the pin to the "A" internal peripheral role.
  70  */
  71 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
  72 {
  73         void __iomem    *pio = pin_to_controller(pin);
  74         unsigned        mask = pin_to_mask(pin);
  75
  76         if (!pio)
  77                 return -EINVAL;
  78
  79         __raw_writel(mask, pio + PIO_IDR);
  80         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
  81         __raw_writel(mask, pio + PIO_ASR);
  82         __raw_writel(mask, pio + PIO_PDR);
  83         return 0;
  84 }
  85 EXPORT_SYMBOL(at91_set_A_periph);
  86
  87
  88 /*
  89  * mux the pin to the "B" internal peripheral role.
  90  */
  91 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
  92 {
  93         void __iomem    *pio = pin_to_controller(pin);
  94         unsigned        mask = pin_to_mask(pin);
  95
  96         if (!pio)
  97                 return -EINVAL;
  98
  99         __raw_writel(mask, pio + PIO_IDR);
 100         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 101         __raw_writel(mask, pio + PIO_BSR);
 102         __raw_writel(mask, pio + PIO_PDR);
 103         return 0;
 104 }
 105 EXPORT_SYMBOL(at91_set_B_periph);
 106
 107
 108 /*
 109  * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 110  * configure it for an input.
 111  */
 112 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 113 {
 114         void __iomem    *pio = pin_to_controller(pin);
 115         unsigned        mask = pin_to_mask(pin);
 116
 117         if (!pio)
 118                 return -EINVAL;
 119
 120         __raw_writel(mask, pio + PIO_IDR);
 121         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 122         __raw_writel(mask, pio + PIO_ODR);
 123         __raw_writel(mask, pio + PIO_PER);
 124         return 0;
 125 }
 126 EXPORT_SYMBOL(at91_set_gpio_input);
 127
 128
 129 /*
 130  * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 131  * and configure it for an output.
 132  */
 133 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 134 {
 135         void __iomem    *pio = pin_to_controller(pin);
 136         unsigned        mask = pin_to_mask(pin);
 137
 138         if (!pio)
 139                 return -EINVAL;
 140
 141         __raw_writel(mask, pio + PIO_IDR);
 142         __raw_writel(mask, pio + PIO_PUDR);
 143         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 144         __raw_writel(mask, pio + PIO_OER);
 145         __raw_writel(mask, pio + PIO_PER);
 146         return 0;
 147 }
 148 EXPORT_SYMBOL(at91_set_gpio_output);
 149
 150
 151 /*
 152  * enable/disable the glitch filter; mostly used with IRQ handling.
 153  */
 154 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 155 {
 156         void __iomem    *pio = pin_to_controller(pin);
 157         unsigned        mask = pin_to_mask(pin);
 158
 159         if (!pio)
 160                 return -EINVAL;
 161         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 162         return 0;
 163 }
 164 EXPORT_SYMBOL(at91_set_deglitch);
 165
 166 /*
 167  * enable/disable the multi-driver; This is only valid for output and
 168  * allows the output pin to run as an open collector output.
 169  */
 170 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 171 {
 172         void __iomem    *pio = pin_to_controller(pin);
 173         unsigned        mask = pin_to_mask(pin);
 174
 175         if (!pio)
 176                 return -EINVAL;
 177
 178         __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
 179         return 0;
 180 }
 181 EXPORT_SYMBOL(at91_set_multi_drive);
 182
 183 /*--------------------------------------------------------------------------*/
 184
 185 /*
 186  * assuming the pin is muxed as a gpio output, set its value.
 187  */
 188 int at91_set_gpio_value(unsigned pin, int value)
 189 {
 190         void __iomem    *pio = pin_to_controller(pin);
 191         unsigned        mask = pin_to_mask(pin);
 192
 193         if (!pio)
 194                 return -EINVAL;
 195         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 196         return 0;
 197 }
 198 EXPORT_SYMBOL(at91_set_gpio_value);
 199
 200
 201 /*
 202  * read the pin's value (works even if it's not muxed as a gpio).
 203  */
 204 int at91_get_gpio_value(unsigned pin)
 205 {
 206         void __iomem    *pio = pin_to_controller(pin);
 207         unsigned        mask = pin_to_mask(pin);
 208         u32             pdsr;
 209
 210         if (!pio)
 211                 return -EINVAL;
 212         pdsr = __raw_readl(pio + PIO_PDSR);
 213         return (pdsr & mask) != 0;
 214 }
 215 EXPORT_SYMBOL(at91_get_gpio_value);
 216
 217 /*--------------------------------------------------------------------------*/
 218
 219 #ifdef CONFIG_PM
 220
 221 static u32 wakeups[MAX_GPIO_BANKS];
 222 static u32 backups[MAX_GPIO_BANKS];
 223
 224 static int gpio_irq_set_wake(unsigned pin, unsigned state)
 225 {
 226         unsigned        mask = pin_to_mask(pin);
 227
 228         pin -= PIN_BASE;
 229         pin /= 32;
 230
 231         if (unlikely(pin >= MAX_GPIO_BANKS))
 232                 return -EINVAL;
 233
 234         if (state)
 235                 wakeups[pin] |= mask;
 236         else
 237                 wakeups[pin] &= ~mask;
 238
 239         return 0;
 240 }
 241
 242 void at91_gpio_suspend(void)
 243 {
 244         int i;
 245
 246         for (i = 0; i < gpio_banks; i++) {
 247                 u32 pio = gpio[i].offset;
 248
 249                 /*
 250                  * Note: drivers should have disabled GPIO interrupts that
 251                  * aren't supposed to be wakeup sources.
 252                  * But that is not much good on ARM.....  disable_irq() does
 253                  * not update the hardware immediately, so the hardware mask
 254                  * (IMR) has the wrong value (not current, too much is
 255                  * permitted).
 256                  *
 257                  * Our workaround is to disable all non-wakeup IRQs ...
 258                  * which is exactly what correct drivers asked for in the
 259                  * first place!
 260                  */
 261                 backups[i] = at91_sys_read(pio + PIO_IMR);
 262                 at91_sys_write(pio + PIO_IDR, backups[i]);
 263                 at91_sys_write(pio + PIO_IER, wakeups[i]);
 264
 265                 if (!wakeups[i]) {
 266                         disable_irq_wake(gpio[i].id);
 267                         at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
 268                 } else {
 269                         enable_irq_wake(gpio[i].id);
 270 #ifdef CONFIG_PM_DEBUG
 271                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
 272 #endif
 273                 }
 274         }
 275 }
 276
 277 void at91_gpio_resume(void)
 278 {
 279         int i;
 280
 281         for (i = 0; i < gpio_banks; i++) {
 282                 u32 pio = gpio[i].offset;
 283
 284                 at91_sys_write(pio + PIO_IDR, wakeups[i]);
 285                 at91_sys_write(pio + PIO_IER, backups[i]);
 286                 at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
 287         }
 288 }
 289
 290 #else
 291 #define gpio_irq_set_wake       NULL
 292 #endif
 293
 294
 295 /* Several AIC controller irqs are dispatched through this GPIO handler.
 296  * To use any AT91_PIN_* as an externally triggered IRQ, first call
 297  * at91_set_gpio_input() then maybe enable its glitch filter.
 298  * Then just request_irq() with the pin ID; it works like any ARM IRQ
 299  * handler, though it always triggers on rising and falling edges.
 300  *
 301  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 302  * configuring them with at91_set_a_periph() or at91_set_b_periph().
 303  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 304  */
 305
 306 static void gpio_irq_mask(unsigned pin)
 307 {
 308         void __iomem    *pio = pin_to_controller(pin);
 309         unsigned        mask = pin_to_mask(pin);
 310
 311         if (pio)
 312                 __raw_writel(mask, pio + PIO_IDR);
 313 }
 314
 315 static void gpio_irq_unmask(unsigned pin)
 316 {
 317         void __iomem    *pio = pin_to_controller(pin);
 318         unsigned        mask = pin_to_mask(pin);
 319
 320         if (pio)
 321                 __raw_writel(mask, pio + PIO_IER);
 322 }
 323
 324 static int gpio_irq_type(unsigned pin, unsigned type)
 325 {
 326         return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
 327 }
 328
 329 static struct irq_chip gpio_irqchip = {
 330         .name           = "GPIO",
 331         .mask           = gpio_irq_mask,
 332         .unmask         = gpio_irq_unmask,
 333         .set_type       = gpio_irq_type,
 334         .set_wake       = gpio_irq_set_wake,
 335 };
 336
 337 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 338 {
 339         unsigned        pin;
 340         struct irq_desc *gpio;
 341         void __iomem    *pio;
 342         u32             isr;
 343
 344         pio = get_irq_chip_data(irq);
 345
 346         /* temporarily mask (level sensitive) parent IRQ */
 347         desc->chip->ack(irq);
 348         for (;;) {
 349                 /* reading ISR acks the pending (edge triggered) GPIO interrupt */
 350                 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
 351                 if (!isr)
 352                         break;
 353
 354                 pin = (unsigned) get_irq_data(irq);
 355                 gpio = &irq_desc[pin];
 356
 357                 while (isr) {
 358                         if (isr & 1) {
 359                                 if (unlikely(gpio->depth)) {
 360                                         /*
 361                                          * The core ARM interrupt handler lazily disables IRQs so
 362                                          * another IRQ must be generated before it actually gets
 363                                          * here to be disabled on the GPIO controller.
 364                                          */
 365                                         gpio_irq_mask(pin);
 366                                 }
 367                                 else
 368                                         desc_handle_irq(pin, gpio);
 369                         }
 370                         pin++;
 371                         gpio++;
 372                         isr >>= 1;
 373                 }
 374         }
 375         desc->chip->unmask(irq);
 376         /* now it may re-trigger */
 377 }
 378
 379 /*--------------------------------------------------------------------------*/
 380
 381 /*
 382  * Called from the processor-specific init to enable GPIO interrupt support.
 383  */
 384 void __init at91_gpio_irq_setup(void)
 385 {
 386         unsigned        pioc, pin;
 387
 388         for (pioc = 0, pin = PIN_BASE;
 389                         pioc < gpio_banks;
 390                         pioc++) {
 391                 void __iomem    *controller;
 392                 unsigned        id = gpio[pioc].id;
 393                 unsigned        i;
 394
 395                 clk_enable(gpio[pioc].clock);   /* enable PIO controller's clock */
 396
 397                 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
 398                 __raw_writel(~0, controller + PIO_IDR);
 399
 400                 set_irq_data(id, (void *) pin);
 401                 set_irq_chip_data(id, controller);
 402
 403                 for (i = 0; i < 32; i++, pin++) {
 404                         /*
 405                          * Can use the "simple" and not "edge" handler since it's
 406                          * shorter, and the AIC handles interupts sanely.
 407                          */
 408                         set_irq_chip(pin, &gpio_irqchip);
 409                         set_irq_handler(pin, handle_simple_irq);
 410                         set_irq_flags(pin, IRQF_VALID);
 411                 }
 412
 413                 set_irq_chained_handler(id, gpio_irq_handler);
 414         }
 415         pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
 416 }
 417
 418 /*
 419  * Called from the processor-specific init to enable GPIO pin support.
 420  */
 421 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 422 {
 423         BUG_ON(nr_banks > MAX_GPIO_BANKS);
 424
 425         gpio = data;
 426         gpio_banks = nr_banks;
 427 }