5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime"
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary, or theoretically 64K
208 for the MSM machine class.
210 config ARM_PATCH_PHYS_VIRT_16BIT
212 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
214 This option extends the physical to virtual translation patching
215 to allow physical memory down to a theoretical minimum of 64K
218 source "init/Kconfig"
220 source "kernel/Kconfig.freezer"
225 bool "MMU-based Paged Memory Management Support"
228 Select if you want MMU-based virtualised addressing space
229 support by paged memory management. If unsure, say 'Y'.
232 # The "ARM system type" choice list is ordered alphabetically by option
233 # text. Please add new entries in the option alphabetic order.
236 prompt "ARM system type"
237 default ARCH_VERSATILE
239 config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
242 select ARCH_HAS_CPUFREQ
244 select HAVE_MACH_CLKDEV
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
250 Support for ARM's Integrator platform.
253 bool "ARM Ltd. RealView family"
256 select HAVE_MACH_CLKDEV
258 select GENERIC_CLOCKEVENTS
259 select ARCH_WANT_OPTIONAL_GPIOLIB
260 select PLAT_VERSATILE
261 select PLAT_VERSATILE_CLCD
262 select ARM_TIMER_SP804
263 select GPIO_PL061 if GPIOLIB
265 This enables support for ARM Ltd RealView boards.
267 config ARCH_VERSATILE
268 bool "ARM Ltd. Versatile family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select PLAT_VERSATILE_FPGA_IRQ
279 select ARM_TIMER_SP804
281 This enables support for ARM Ltd Versatile board.
284 bool "ARM Ltd. Versatile Express family"
285 select ARCH_WANT_OPTIONAL_GPIOLIB
287 select ARM_TIMER_SP804
289 select HAVE_MACH_CLKDEV
290 select GENERIC_CLOCKEVENTS
292 select HAVE_PATA_PLATFORM
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
297 This enables support for the ARM Ltd Versatile Express boards.
301 select ARCH_REQUIRE_GPIOLIB
304 select ARM_PATCH_PHYS_VIRT if MMU
306 This enables support for systems based on the Atmel AT91RM9200,
307 AT91SAM9 and AT91CAP9 processors.
310 bool "Broadcom BCMRING"
314 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select ARCH_WANT_OPTIONAL_GPIOLIB
319 Support for Broadcom's BCMRing platform.
322 bool "Cirrus Logic CLPS711x/EP721x-based"
324 select ARCH_USES_GETTIMEOFFSET
326 Support for Cirrus Logic 711x/721x based boards.
329 bool "Cavium Networks CNS3XXX family"
331 select GENERIC_CLOCKEVENTS
333 select MIGHT_HAVE_PCI
334 select PCI_DOMAINS if PCI
336 Support for Cavium Networks CNS3XXX platform.
339 bool "Cortina Systems Gemini"
341 select ARCH_REQUIRE_GPIOLIB
342 select ARCH_USES_GETTIMEOFFSET
344 Support for the Cortina Systems Gemini family SoCs
347 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
351 select GENERIC_CLOCKEVENTS
353 select GENERIC_IRQ_CHIP
357 Support for CSR SiRFSoC ARM Cortex A9 Platform
364 select ARCH_USES_GETTIMEOFFSET
366 This is an evaluation board for the StrongARM processor available
367 from Digital. It has limited hardware on-board, including an
368 Ethernet interface, two PCMCIA sockets, two serial ports and a
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_HAS_HOLES_MEMORYMODEL
379 select ARCH_USES_GETTIMEOFFSET
381 This enables support for the Cirrus EP93xx series of CPUs.
383 config ARCH_FOOTBRIDGE
387 select GENERIC_CLOCKEVENTS
389 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
393 bool "Freescale MXC/iMX-based"
394 select GENERIC_CLOCKEVENTS
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_IRQ_CHIP
399 select HAVE_SCHED_CLOCK
401 Support for Freescale MXC/iMX-based family of processors
404 bool "Freescale MXS-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
410 Support for Freescale MXS-based family of processors
413 bool "Hilscher NetX based"
417 select GENERIC_CLOCKEVENTS
419 This enables support for systems based on the Hilscher NetX Soc
422 bool "Hynix HMS720x-based"
425 select ARCH_USES_GETTIMEOFFSET
427 This enables support for systems based on the Hynix HMS720x
435 select ARCH_SUPPORTS_MSI
438 Support for Intel's IOP13XX (XScale) family of processors.
446 select ARCH_REQUIRE_GPIOLIB
448 Support for Intel's 80219 and IOP32X (XScale) family of
457 select ARCH_REQUIRE_GPIOLIB
459 Support for Intel's IOP33X (XScale) family of processors.
466 select ARCH_USES_GETTIMEOFFSET
468 Support for Intel's IXP23xx (XScale) family of processors.
471 bool "IXP2400/2800-based"
475 select ARCH_USES_GETTIMEOFFSET
477 Support for Intel's IXP2400/2800 (XScale) family of processors.
485 select GENERIC_CLOCKEVENTS
486 select HAVE_SCHED_CLOCK
487 select MIGHT_HAVE_PCI
488 select DMABOUNCE if PCI
490 Support for Intel's IXP4XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Dove SoC 88AP510
503 bool "Marvell Kirkwood"
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
510 Support for the following Marvell Kirkwood series SoCs:
511 88F6180, 88F6192 and 88F6281.
517 select ARCH_REQUIRE_GPIOLIB
520 select USB_ARCH_HAS_OHCI
523 select GENERIC_CLOCKEVENTS
525 Support for the NXP LPC32XX family of processors
528 bool "Marvell MV78xx0"
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell MV78xx0 series SoCs:
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select HAVE_SCHED_CLOCK
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
567 select ARCH_REQUIRE_GPIOLIB
568 select ARCH_USES_GETTIMEOFFSET
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 bool "Nuvoton NUC93X CPU"
594 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
595 low-power and high performance MPEG-4/JPEG multimedia controller chip.
602 select GENERIC_CLOCKEVENTS
605 select HAVE_SCHED_CLOCK
606 select ARCH_HAS_CPUFREQ
608 This enables support for NVIDIA Tegra based systems (Tegra APX,
609 Tegra 6xx and Tegra 2 series).
612 bool "Philips Nexperia PNX4008 Mobile"
615 select ARCH_USES_GETTIMEOFFSET
617 This enables support for Philips PNX4008 mobile platform.
620 bool "PXA2xx/PXA3xx-based"
623 select ARCH_HAS_CPUFREQ
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
633 select MULTI_IRQ_HANDLER
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
640 select GENERIC_CLOCKEVENTS
641 select ARCH_REQUIRE_GPIOLIB
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
651 bool "Renesas SH-Mobile / R-Mobile"
654 select HAVE_MACH_CLKDEV
655 select GENERIC_CLOCKEVENTS
658 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
668 select ARCH_MAY_HAVE_PC_FDC
669 select HAVE_PATA_PLATFORM
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
675 On the Acorn Risc-PC, Linux can support the internal IDE disk and
676 CD-ROM interface, serial and parallel port, and the floppy drive.
683 select ARCH_SPARSEMEM_ENABLE
685 select ARCH_HAS_CPUFREQ
687 select GENERIC_CLOCKEVENTS
689 select HAVE_SCHED_CLOCK
691 select ARCH_REQUIRE_GPIOLIB
693 Support for StrongARM 11x0 based boards.
696 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
698 select ARCH_HAS_CPUFREQ
701 select ARCH_USES_GETTIMEOFFSET
702 select HAVE_S3C2410_I2C if I2C
704 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
705 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
706 the Samsung SMDK2410 development board (and derivatives).
708 Note, the S3C2416 and the S3C2450 are so close that they even share
709 the same SoC ID code. This means that there is no separate machine
710 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
713 bool "Samsung S3C64XX"
721 select ARCH_USES_GETTIMEOFFSET
722 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
724 select SAMSUNG_CLKSRC
725 select SAMSUNG_IRQ_VIC_TIMER
726 select SAMSUNG_IRQ_UART
727 select S3C_GPIO_TRACK
729 select USB_ARCH_HAS_OHCI
730 select SAMSUNG_GPIOLIB_4BIT
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 Samsung S3C64XX series based systems
737 bool "Samsung S5P6440 S5P6450"
743 select HAVE_S3C2410_WATCHDOG if WATCHDOG
744 select GENERIC_CLOCKEVENTS
745 select HAVE_SCHED_CLOCK
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C_RTC if RTC_CLASS
749 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
753 bool "Samsung S5PC100"
758 select ARM_L1_CACHE_SHIFT_6
759 select ARCH_USES_GETTIMEOFFSET
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C_RTC if RTC_CLASS
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 Samsung S5PC100 series based systems
767 bool "Samsung S5PV210/S5PC110"
769 select ARCH_SPARSEMEM_ENABLE
770 select ARCH_HAS_HOLES_MEMORYMODEL
775 select ARM_L1_CACHE_SHIFT_6
776 select ARCH_HAS_CPUFREQ
777 select GENERIC_CLOCKEVENTS
778 select HAVE_SCHED_CLOCK
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C_RTC if RTC_CLASS
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 Samsung S5PV210/S5PC110 series based systems
786 bool "Samsung EXYNOS4"
788 select ARCH_SPARSEMEM_ENABLE
789 select ARCH_HAS_HOLES_MEMORYMODEL
793 select ARCH_HAS_CPUFREQ
794 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C_RTC if RTC_CLASS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 Samsung EXYNOS4 series based systems
808 select ARCH_USES_GETTIMEOFFSET
810 Support for the StrongARM based Digital DNARD machine, also known
811 as "Shark" (<http://www.shark-linux.de/shark.html>).
814 bool "Telechips TCC ARM926-based systems"
819 select GENERIC_CLOCKEVENTS
821 Support for Telechips TCC ARM926-based systems.
824 bool "ST-Ericsson U300 Series"
828 select HAVE_SCHED_CLOCK
832 select GENERIC_CLOCKEVENTS
834 select HAVE_MACH_CLKDEV
837 Support for ST-Ericsson U300 series mobile platforms.
840 bool "ST-Ericsson U8500 Series"
843 select GENERIC_CLOCKEVENTS
845 select ARCH_REQUIRE_GPIOLIB
846 select ARCH_HAS_CPUFREQ
848 Support for ST-Ericsson's Ux500 architecture
851 bool "STMicroelectronics Nomadik"
856 select GENERIC_CLOCKEVENTS
857 select ARCH_REQUIRE_GPIOLIB
859 Support for the Nomadik platform by ST-Ericsson
863 select GENERIC_CLOCKEVENTS
864 select ARCH_REQUIRE_GPIOLIB
868 select GENERIC_ALLOCATOR
869 select GENERIC_IRQ_CHIP
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 Support for TI's DaVinci platform.
877 select ARCH_REQUIRE_GPIOLIB
878 select ARCH_HAS_CPUFREQ
880 select GENERIC_CLOCKEVENTS
881 select HAVE_SCHED_CLOCK
882 select ARCH_HAS_HOLES_MEMORYMODEL
884 Support for TI's OMAP platform (OMAP1/2/3/4).
889 select ARCH_REQUIRE_GPIOLIB
892 select GENERIC_CLOCKEVENTS
895 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
898 bool "VIA/WonderMedia 85xx"
901 select ARCH_HAS_CPUFREQ
902 select GENERIC_CLOCKEVENTS
903 select ARCH_REQUIRE_GPIOLIB
906 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
909 bool "Xilinx Zynq ARM Cortex A9 Platform"
912 select GENERIC_CLOCKEVENTS
919 Support for Xilinx Zynq ARM Cortex A9 Platform
923 # This is sorted alphabetically by mach-* pathname. However, plat-*
924 # Kconfigs may be included either alphabetically (according to the
925 # plat- suffix) or along side the corresponding mach-* source.
927 source "arch/arm/mach-at91/Kconfig"
929 source "arch/arm/mach-bcmring/Kconfig"
931 source "arch/arm/mach-clps711x/Kconfig"
933 source "arch/arm/mach-cns3xxx/Kconfig"
935 source "arch/arm/mach-davinci/Kconfig"
937 source "arch/arm/mach-dove/Kconfig"
939 source "arch/arm/mach-ep93xx/Kconfig"
941 source "arch/arm/mach-footbridge/Kconfig"
943 source "arch/arm/mach-gemini/Kconfig"
945 source "arch/arm/mach-h720x/Kconfig"
947 source "arch/arm/mach-integrator/Kconfig"
949 source "arch/arm/mach-iop32x/Kconfig"
951 source "arch/arm/mach-iop33x/Kconfig"
953 source "arch/arm/mach-iop13xx/Kconfig"
955 source "arch/arm/mach-ixp4xx/Kconfig"
957 source "arch/arm/mach-ixp2000/Kconfig"
959 source "arch/arm/mach-ixp23xx/Kconfig"
961 source "arch/arm/mach-kirkwood/Kconfig"
963 source "arch/arm/mach-ks8695/Kconfig"
965 source "arch/arm/mach-lpc32xx/Kconfig"
967 source "arch/arm/mach-msm/Kconfig"
969 source "arch/arm/mach-mv78xx0/Kconfig"
971 source "arch/arm/plat-mxc/Kconfig"
973 source "arch/arm/mach-mxs/Kconfig"
975 source "arch/arm/mach-netx/Kconfig"
977 source "arch/arm/mach-nomadik/Kconfig"
978 source "arch/arm/plat-nomadik/Kconfig"
980 source "arch/arm/mach-nuc93x/Kconfig"
982 source "arch/arm/plat-omap/Kconfig"
984 source "arch/arm/mach-omap1/Kconfig"
986 source "arch/arm/mach-omap2/Kconfig"
988 source "arch/arm/mach-orion5x/Kconfig"
990 source "arch/arm/mach-pxa/Kconfig"
991 source "arch/arm/plat-pxa/Kconfig"
993 source "arch/arm/mach-mmp/Kconfig"
995 source "arch/arm/mach-realview/Kconfig"
997 source "arch/arm/mach-sa1100/Kconfig"
999 source "arch/arm/plat-samsung/Kconfig"
1000 source "arch/arm/plat-s3c24xx/Kconfig"
1001 source "arch/arm/plat-s5p/Kconfig"
1003 source "arch/arm/plat-spear/Kconfig"
1005 source "arch/arm/plat-tcc/Kconfig"
1008 source "arch/arm/mach-s3c2410/Kconfig"
1009 source "arch/arm/mach-s3c2412/Kconfig"
1010 source "arch/arm/mach-s3c2416/Kconfig"
1011 source "arch/arm/mach-s3c2440/Kconfig"
1012 source "arch/arm/mach-s3c2443/Kconfig"
1016 source "arch/arm/mach-s3c64xx/Kconfig"
1019 source "arch/arm/mach-s5p64x0/Kconfig"
1021 source "arch/arm/mach-s5pc100/Kconfig"
1023 source "arch/arm/mach-s5pv210/Kconfig"
1025 source "arch/arm/mach-exynos4/Kconfig"
1027 source "arch/arm/mach-shmobile/Kconfig"
1029 source "arch/arm/mach-tegra/Kconfig"
1031 source "arch/arm/mach-u300/Kconfig"
1033 source "arch/arm/mach-ux500/Kconfig"
1035 source "arch/arm/mach-versatile/Kconfig"
1037 source "arch/arm/mach-vexpress/Kconfig"
1038 source "arch/arm/plat-versatile/Kconfig"
1040 source "arch/arm/mach-vt8500/Kconfig"
1042 source "arch/arm/mach-w90x900/Kconfig"
1044 # Definitions to make life easier
1050 select GENERIC_CLOCKEVENTS
1051 select HAVE_SCHED_CLOCK
1056 select GENERIC_IRQ_CHIP
1057 select HAVE_SCHED_CLOCK
1062 config PLAT_VERSATILE
1065 config ARM_TIMER_SP804
1069 source arch/arm/mm/Kconfig
1072 bool "Enable iWMMXt support"
1073 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1074 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1076 Enable support for iWMMXt context switching at run time if
1077 running on a CPU that supports it.
1079 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1082 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1086 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1087 (!ARCH_OMAP3 || OMAP3_EMU)
1091 config MULTI_IRQ_HANDLER
1094 Allow each machine to specify it's own IRQ handler at run time.
1097 source "arch/arm/Kconfig-nommu"
1100 config ARM_ERRATA_411920
1101 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1102 depends on CPU_V6 || CPU_V6K
1104 Invalidation of the Instruction Cache operation can
1105 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1106 It does not affect the MPCore. This option enables the ARM Ltd.
1107 recommended workaround.
1109 config ARM_ERRATA_430973
1110 bool "ARM errata: Stale prediction on replaced interworking branch"
1113 This option enables the workaround for the 430973 Cortex-A8
1114 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1115 interworking branch is replaced with another code sequence at the
1116 same virtual address, whether due to self-modifying code or virtual
1117 to physical address re-mapping, Cortex-A8 does not recover from the
1118 stale interworking branch prediction. This results in Cortex-A8
1119 executing the new code sequence in the incorrect ARM or Thumb state.
1120 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1121 and also flushes the branch target cache at every context switch.
1122 Note that setting specific bits in the ACTLR register may not be
1123 available in non-secure mode.
1125 config ARM_ERRATA_458693
1126 bool "ARM errata: Processor deadlock when a false hazard is created"
1129 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1130 erratum. For very specific sequences of memory operations, it is
1131 possible for a hazard condition intended for a cache line to instead
1132 be incorrectly associated with a different cache line. This false
1133 hazard might then cause a processor deadlock. The workaround enables
1134 the L1 caching of the NEON accesses and disables the PLD instruction
1135 in the ACTLR register. Note that setting specific bits in the ACTLR
1136 register may not be available in non-secure mode.
1138 config ARM_ERRATA_460075
1139 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1142 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1143 erratum. Any asynchronous access to the L2 cache may encounter a
1144 situation in which recent store transactions to the L2 cache are lost
1145 and overwritten with stale memory contents from external memory. The
1146 workaround disables the write-allocate mode for the L2 cache via the
1147 ACTLR register. Note that setting specific bits in the ACTLR register
1148 may not be available in non-secure mode.
1150 config ARM_ERRATA_742230
1151 bool "ARM errata: DMB operation may be faulty"
1152 depends on CPU_V7 && SMP
1154 This option enables the workaround for the 742230 Cortex-A9
1155 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1156 between two write operations may not ensure the correct visibility
1157 ordering of the two writes. This workaround sets a specific bit in
1158 the diagnostic register of the Cortex-A9 which causes the DMB
1159 instruction to behave as a DSB, ensuring the correct behaviour of
1162 config ARM_ERRATA_742231
1163 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1164 depends on CPU_V7 && SMP
1166 This option enables the workaround for the 742231 Cortex-A9
1167 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1168 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1169 accessing some data located in the same cache line, may get corrupted
1170 data due to bad handling of the address hazard when the line gets
1171 replaced from one of the CPUs at the same time as another CPU is
1172 accessing it. This workaround sets specific bits in the diagnostic
1173 register of the Cortex-A9 which reduces the linefill issuing
1174 capabilities of the processor.
1176 config PL310_ERRATA_588369
1177 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1178 depends on CACHE_L2X0
1180 The PL310 L2 cache controller implements three types of Clean &
1181 Invalidate maintenance operations: by Physical Address
1182 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1183 They are architecturally defined to behave as the execution of a
1184 clean operation followed immediately by an invalidate operation,
1185 both performing to the same memory location. This functionality
1186 is not correctly implemented in PL310 as clean lines are not
1187 invalidated as a result of these operations.
1189 config ARM_ERRATA_720789
1190 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1191 depends on CPU_V7 && SMP
1193 This option enables the workaround for the 720789 Cortex-A9 (prior to
1194 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1195 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1196 As a consequence of this erratum, some TLB entries which should be
1197 invalidated are not, resulting in an incoherency in the system page
1198 tables. The workaround changes the TLB flushing routines to invalidate
1199 entries regardless of the ASID.
1201 config PL310_ERRATA_727915
1202 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1203 depends on CACHE_L2X0
1205 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1206 operation (offset 0x7FC). This operation runs in background so that
1207 PL310 can handle normal accesses while it is in progress. Under very
1208 rare circumstances, due to this erratum, write data can be lost when
1209 PL310 treats a cacheable write transaction during a Clean &
1210 Invalidate by Way operation.
1212 config ARM_ERRATA_743622
1213 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1216 This option enables the workaround for the 743622 Cortex-A9
1217 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1218 optimisation in the Cortex-A9 Store Buffer may lead to data
1219 corruption. This workaround sets a specific bit in the diagnostic
1220 register of the Cortex-A9 which disables the Store Buffer
1221 optimisation, preventing the defect from occurring. This has no
1222 visible impact on the overall performance or power consumption of the
1225 config ARM_ERRATA_751472
1226 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 751472 Cortex-A9 (prior
1230 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1231 completion of a following broadcasted operation if the second
1232 operation is received by a CPU before the ICIALLUIS has completed,
1233 potentially leading to corrupted entries in the cache or TLB.
1235 config ARM_ERRATA_753970
1236 bool "ARM errata: cache sync operation may be faulty"
1237 depends on CACHE_PL310
1239 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1241 Under some condition the effect of cache sync operation on
1242 the store buffer still remains when the operation completes.
1243 This means that the store buffer is always asked to drain and
1244 this prevents it from merging any further writes. The workaround
1245 is to replace the normal offset of cache sync operation (0x730)
1246 by another offset targeting an unmapped PL310 register 0x740.
1247 This has the same effect as the cache sync operation: store buffer
1248 drain and waiting for all buffers empty.
1250 config ARM_ERRATA_754322
1251 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1254 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1255 r3p*) erratum. A speculative memory access may cause a page table walk
1256 which starts prior to an ASID switch but completes afterwards. This
1257 can populate the micro-TLB with a stale entry which may be hit with
1258 the new ASID. This workaround places two dsb instructions in the mm
1259 switching code so that no page table walks can cross the ASID switch.
1261 config ARM_ERRATA_754327
1262 bool "ARM errata: no automatic Store Buffer drain"
1263 depends on CPU_V7 && SMP
1265 This option enables the workaround for the 754327 Cortex-A9 (prior to
1266 r2p0) erratum. The Store Buffer does not have any automatic draining
1267 mechanism and therefore a livelock may occur if an external agent
1268 continuously polls a memory location waiting to observe an update.
1269 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1270 written polling loops from denying visibility of updates to memory.
1272 config ARM_ERRATA_364296
1273 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1274 depends on CPU_V6 && !SMP
1276 This options enables the workaround for the 364296 ARM1136
1277 r0p2 erratum (possible cache data corruption with
1278 hit-under-miss enabled). It sets the undocumented bit 31 in
1279 the auxiliary control register and the FI bit in the control
1280 register, thus disabling hit-under-miss without putting the
1281 processor into full low interrupt latency mode. ARM11MPCore
1284 config ARM_ERRATA_764369
1285 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1286 depends on CPU_V7 && SMP
1288 This option enables the workaround for erratum 764369
1289 affecting Cortex-A9 MPCore with two or more processors (all
1290 current revisions). Under certain timing circumstances, a data
1291 cache line maintenance operation by MVA targeting an Inner
1292 Shareable memory region may fail to proceed up to either the
1293 Point of Coherency or to the Point of Unification of the
1294 system. This workaround adds a DSB instruction before the
1295 relevant cache maintenance functions and sets a specific bit
1296 in the diagnostic control register of the SCU.
1300 source "arch/arm/common/Kconfig"
1310 Find out whether you have ISA slots on your motherboard. ISA is the
1311 name of a bus system, i.e. the way the CPU talks to the other stuff
1312 inside your box. Other bus systems are PCI, EISA, MicroChannel
1313 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1314 newer boards don't support it. If you have ISA, say Y, otherwise N.
1316 # Select ISA DMA controller support
1321 # Select ISA DMA interface
1326 bool "PCI support" if MIGHT_HAVE_PCI
1328 Find out whether you have a PCI motherboard. PCI is the name of a
1329 bus system, i.e. the way the CPU talks to the other stuff inside
1330 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1331 VESA. If you have PCI, say Y, otherwise N.
1337 config PCI_NANOENGINE
1338 bool "BSE nanoEngine PCI support"
1339 depends on SA1100_NANOENGINE
1341 Enable PCI on the BSE nanoEngine board.
1346 # Select the host bridge type
1347 config PCI_HOST_VIA82C505
1349 depends on PCI && ARCH_SHARK
1352 config PCI_HOST_ITE8152
1354 depends on PCI && MACH_ARMCORE
1358 source "drivers/pci/Kconfig"
1360 source "drivers/pcmcia/Kconfig"
1364 menu "Kernel Features"
1366 source "kernel/time/Kconfig"
1369 bool "Symmetric Multi-Processing"
1370 depends on CPU_V6K || CPU_V7
1371 depends on GENERIC_CLOCKEVENTS
1372 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1373 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1374 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1375 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1376 select USE_GENERIC_SMP_HELPERS
1377 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1379 This enables support for systems with more than one CPU. If you have
1380 a system with only one CPU, like most personal computers, say N. If
1381 you have a system with more than one CPU, say Y.
1383 If you say N here, the kernel will run on single and multiprocessor
1384 machines, but will use only one CPU of a multiprocessor machine. If
1385 you say Y here, the kernel will run on many, but not all, single
1386 processor machines. On a single processor machine, the kernel will
1387 run faster if you say N here.
1389 See also <file:Documentation/i386/IO-APIC.txt>,
1390 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1391 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1393 If you don't know what to do here, say N.
1396 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1397 depends on EXPERIMENTAL
1398 depends on SMP && !XIP_KERNEL
1401 SMP kernels contain instructions which fail on non-SMP processors.
1402 Enabling this option allows the kernel to modify itself to make
1403 these instructions safe. Disabling it allows about 1K of space
1406 If you don't know what to do here, say Y.
1411 This option enables support for the ARM system coherency unit
1418 This options enables support for the ARM timer and watchdog unit
1421 prompt "Memory split"
1424 Select the desired split between kernel and user memory.
1426 If you are not absolutely sure what you are doing, leave this
1430 bool "3G/1G user/kernel split"
1432 bool "2G/2G user/kernel split"
1434 bool "1G/3G user/kernel split"
1439 default 0x40000000 if VMSPLIT_1G
1440 default 0x80000000 if VMSPLIT_2G
1444 int "Maximum number of CPUs (2-32)"
1450 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1451 depends on SMP && HOTPLUG && EXPERIMENTAL
1453 Say Y here to experiment with turning CPUs off and on. CPUs
1454 can be controlled through /sys/devices/system/cpu.
1457 bool "Use local timer interrupts"
1460 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1462 Enable support for local timers on SMP platforms, rather then the
1463 legacy IPI broadcast method. Local timers allows the system
1464 accounting to be spread across the timer interval, preventing a
1465 "thundering herd" at every timer tick.
1467 source kernel/Kconfig.preempt
1471 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1472 ARCH_S5PV210 || ARCH_EXYNOS4
1473 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1474 default AT91_TIMER_HZ if ARCH_AT91
1475 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1478 config THUMB2_KERNEL
1479 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1480 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1482 select ARM_ASM_UNIFIED
1484 By enabling this option, the kernel will be compiled in
1485 Thumb-2 mode. A compiler/assembler that understand the unified
1486 ARM-Thumb syntax is needed.
1490 config THUMB2_AVOID_R_ARM_THM_JUMP11
1491 bool "Work around buggy Thumb-2 short branch relocations in gas"
1492 depends on THUMB2_KERNEL && MODULES
1495 Various binutils versions can resolve Thumb-2 branches to
1496 locally-defined, preemptible global symbols as short-range "b.n"
1497 branch instructions.
1499 This is a problem, because there's no guarantee the final
1500 destination of the symbol, or any candidate locations for a
1501 trampoline, are within range of the branch. For this reason, the
1502 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1503 relocation in modules at all, and it makes little sense to add
1506 The symptom is that the kernel fails with an "unsupported
1507 relocation" error when loading some modules.
1509 Until fixed tools are available, passing
1510 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1511 code which hits this problem, at the cost of a bit of extra runtime
1512 stack usage in some cases.
1514 The problem is described in more detail at:
1515 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1517 Only Thumb-2 kernels are affected.
1519 Unless you are sure your tools don't have this problem, say Y.
1521 config ARM_ASM_UNIFIED
1525 bool "Use the ARM EABI to compile the kernel"
1527 This option allows for the kernel to be compiled using the latest
1528 ARM ABI (aka EABI). This is only useful if you are using a user
1529 space environment that is also compiled with EABI.
1531 Since there are major incompatibilities between the legacy ABI and
1532 EABI, especially with regard to structure member alignment, this
1533 option also changes the kernel syscall calling convention to
1534 disambiguate both ABIs and allow for backward compatibility support
1535 (selected with CONFIG_OABI_COMPAT).
1537 To use this you need GCC version 4.0.0 or later.
1540 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1541 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1544 This option preserves the old syscall interface along with the
1545 new (ARM EABI) one. It also provides a compatibility layer to
1546 intercept syscalls that have structure arguments which layout
1547 in memory differs between the legacy ABI and the new ARM EABI
1548 (only for non "thumb" binaries). This option adds a tiny
1549 overhead to all syscalls and produces a slightly larger kernel.
1550 If you know you'll be using only pure EABI user space then you
1551 can say N here. If this option is not selected and you attempt
1552 to execute a legacy ABI binary then the result will be
1553 UNPREDICTABLE (in fact it can be predicted that it won't work
1554 at all). If in doubt say Y.
1556 config ARCH_HAS_HOLES_MEMORYMODEL
1559 config ARCH_SPARSEMEM_ENABLE
1562 config ARCH_SPARSEMEM_DEFAULT
1563 def_bool ARCH_SPARSEMEM_ENABLE
1565 config ARCH_SELECT_MEMORY_MODEL
1566 def_bool ARCH_SPARSEMEM_ENABLE
1568 config HAVE_ARCH_PFN_VALID
1569 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1572 bool "High Memory Support"
1575 The address space of ARM processors is only 4 Gigabytes large
1576 and it has to accommodate user address space, kernel address
1577 space as well as some memory mapped IO. That means that, if you
1578 have a large amount of physical memory and/or IO, not all of the
1579 memory can be "permanently mapped" by the kernel. The physical
1580 memory that is not permanently mapped is called "high memory".
1582 Depending on the selected kernel/user memory split, minimum
1583 vmalloc space and actual amount of RAM, you may not need this
1584 option which should result in a slightly faster kernel.
1589 bool "Allocate 2nd-level pagetables from highmem"
1592 config HW_PERF_EVENTS
1593 bool "Enable hardware performance counter support for perf events"
1594 depends on PERF_EVENTS && CPU_HAS_PMU
1597 Enable hardware performance counter support for perf events. If
1598 disabled, perf events will use software events only.
1602 config FORCE_MAX_ZONEORDER
1603 int "Maximum zone order" if ARCH_SHMOBILE
1604 range 11 64 if ARCH_SHMOBILE
1605 default "9" if SA1111
1608 The kernel memory allocator divides physically contiguous memory
1609 blocks into "zones", where each zone is a power of two number of
1610 pages. This option selects the largest power of two that the kernel
1611 keeps in the memory allocator. If you need to allocate very large
1612 blocks of physically contiguous memory, then you may need to
1613 increase this value.
1615 This config option is actually maximum order plus one. For example,
1616 a value of 11 means that the largest free memory block is 2^10 pages.
1619 bool "Timer and CPU usage LEDs"
1620 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1621 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1622 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1623 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1624 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1625 ARCH_AT91 || ARCH_DAVINCI || \
1626 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1628 If you say Y here, the LEDs on your machine will be used
1629 to provide useful information about your current system status.
1631 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1632 be able to select which LEDs are active using the options below. If
1633 you are compiling a kernel for the EBSA-110 or the LART however, the
1634 red LED will simply flash regularly to indicate that the system is
1635 still functional. It is safe to say Y here if you have a CATS
1636 system, but the driver will do nothing.
1639 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1640 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1641 || MACH_OMAP_PERSEUS2
1643 depends on !GENERIC_CLOCKEVENTS
1644 default y if ARCH_EBSA110
1646 If you say Y here, one of the system LEDs (the green one on the
1647 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1648 will flash regularly to indicate that the system is still
1649 operational. This is mainly useful to kernel hackers who are
1650 debugging unstable kernels.
1652 The LART uses the same LED for both Timer LED and CPU usage LED
1653 functions. You may choose to use both, but the Timer LED function
1654 will overrule the CPU usage LED.
1657 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1659 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1660 || MACH_OMAP_PERSEUS2
1663 If you say Y here, the red LED will be used to give a good real
1664 time indication of CPU usage, by lighting whenever the idle task
1665 is not currently executing.
1667 The LART uses the same LED for both Timer LED and CPU usage LED
1668 functions. You may choose to use both, but the Timer LED function
1669 will overrule the CPU usage LED.
1671 config ALIGNMENT_TRAP
1673 depends on CPU_CP15_MMU
1674 default y if !ARCH_EBSA110
1675 select HAVE_PROC_CPU if PROC_FS
1677 ARM processors cannot fetch/store information which is not
1678 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1679 address divisible by 4. On 32-bit ARM processors, these non-aligned
1680 fetch/store instructions will be emulated in software if you say
1681 here, which has a severe performance impact. This is necessary for
1682 correct operation of some network protocols. With an IP-only
1683 configuration it is safe to say N, otherwise say Y.
1685 config UACCESS_WITH_MEMCPY
1686 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1687 depends on MMU && EXPERIMENTAL
1688 default y if CPU_FEROCEON
1690 Implement faster copy_to_user and clear_user methods for CPU
1691 cores where a 8-word STM instruction give significantly higher
1692 memory write throughput than a sequence of individual 32bit stores.
1694 A possible side effect is a slight increase in scheduling latency
1695 between threads sharing the same address space if they invoke
1696 such copy operations with large buffers.
1698 However, if the CPU data cache is using a write-allocate mode,
1699 this option is unlikely to provide any performance gain.
1703 prompt "Enable seccomp to safely compute untrusted bytecode"
1705 This kernel feature is useful for number crunching applications
1706 that may need to compute untrusted bytecode during their
1707 execution. By using pipes or other transports made available to
1708 the process as file descriptors supporting the read/write
1709 syscalls, it's possible to isolate those applications in
1710 their own address space using seccomp. Once seccomp is
1711 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1712 and the task is only allowed to execute a few safe syscalls
1713 defined by each seccomp mode.
1715 config CC_STACKPROTECTOR
1716 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1717 depends on EXPERIMENTAL
1719 This option turns on the -fstack-protector GCC feature. This
1720 feature puts, at the beginning of functions, a canary value on
1721 the stack just before the return address, and validates
1722 the value just before actually returning. Stack based buffer
1723 overflows (that need to overwrite this return address) now also
1724 overwrite the canary, which gets detected and the attack is then
1725 neutralized via a kernel panic.
1726 This feature requires gcc version 4.2 or above.
1728 config DEPRECATED_PARAM_STRUCT
1729 bool "Provide old way to pass kernel parameters"
1731 This was deprecated in 2001 and announced to live on for 5 years.
1732 Some old boot loaders still use this way.
1739 bool "Flattened Device Tree support"
1741 select OF_EARLY_FLATTREE
1744 Include support for flattened device tree machine descriptions.
1746 # Compressed boot loader in ROM. Yes, we really want to ask about
1747 # TEXT and BSS so we preserve their values in the config files.
1748 config ZBOOT_ROM_TEXT
1749 hex "Compressed ROM boot loader base address"
1752 The physical address at which the ROM-able zImage is to be
1753 placed in the target. Platforms which normally make use of
1754 ROM-able zImage formats normally set this to a suitable
1755 value in their defconfig file.
1757 If ZBOOT_ROM is not enabled, this has no effect.
1759 config ZBOOT_ROM_BSS
1760 hex "Compressed ROM boot loader BSS address"
1763 The base address of an area of read/write memory in the target
1764 for the ROM-able zImage which must be available while the
1765 decompressor is running. It must be large enough to hold the
1766 entire decompressed kernel plus an additional 128 KiB.
1767 Platforms which normally make use of ROM-able zImage formats
1768 normally set this to a suitable value in their defconfig file.
1770 If ZBOOT_ROM is not enabled, this has no effect.
1773 bool "Compressed boot loader in ROM/flash"
1774 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1776 Say Y here if you intend to execute your compressed kernel image
1777 (zImage) directly from ROM or flash. If unsure, say N.
1780 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1781 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1782 default ZBOOT_ROM_NONE
1784 Include experimental SD/MMC loading code in the ROM-able zImage.
1785 With this enabled it is possible to write the the ROM-able zImage
1786 kernel image to an MMC or SD card and boot the kernel straight
1787 from the reset vector. At reset the processor Mask ROM will load
1788 the first part of the the ROM-able zImage which in turn loads the
1789 rest the kernel image to RAM.
1791 config ZBOOT_ROM_NONE
1792 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1794 Do not load image from SD or MMC
1796 config ZBOOT_ROM_MMCIF
1797 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1799 Load image from MMCIF hardware block.
1801 config ZBOOT_ROM_SH_MOBILE_SDHI
1802 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1804 Load image from SDHI hardware block
1809 string "Default kernel command string"
1812 On some architectures (EBSA110 and CATS), there is currently no way
1813 for the boot loader to pass arguments to the kernel. For these
1814 architectures, you should supply some command-line options at build
1815 time by entering them here. As a minimum, you should specify the
1816 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1819 prompt "Kernel command line type" if CMDLINE != ""
1820 default CMDLINE_FROM_BOOTLOADER
1822 config CMDLINE_FROM_BOOTLOADER
1823 bool "Use bootloader kernel arguments if available"
1825 Uses the command-line options passed by the boot loader. If
1826 the boot loader doesn't provide any, the default kernel command
1827 string provided in CMDLINE will be used.
1829 config CMDLINE_EXTEND
1830 bool "Extend bootloader kernel arguments"
1832 The command-line arguments provided by the boot loader will be
1833 appended to the default kernel command string.
1835 config CMDLINE_FORCE
1836 bool "Always use the default kernel command string"
1838 Always use the default kernel command string, even if the boot
1839 loader passes other arguments to the kernel.
1840 This is useful if you cannot or don't want to change the
1841 command-line options your boot loader passes to the kernel.
1845 bool "Kernel Execute-In-Place from ROM"
1846 depends on !ZBOOT_ROM
1848 Execute-In-Place allows the kernel to run from non-volatile storage
1849 directly addressable by the CPU, such as NOR flash. This saves RAM
1850 space since the text section of the kernel is not loaded from flash
1851 to RAM. Read-write sections, such as the data section and stack,
1852 are still copied to RAM. The XIP kernel is not compressed since
1853 it has to run directly from flash, so it will take more space to
1854 store it. The flash address used to link the kernel object files,
1855 and for storing it, is configuration dependent. Therefore, if you
1856 say Y here, you must know the proper physical address where to
1857 store the kernel image depending on your own flash memory usage.
1859 Also note that the make target becomes "make xipImage" rather than
1860 "make zImage" or "make Image". The final kernel binary to put in
1861 ROM memory will be arch/arm/boot/xipImage.
1865 config XIP_PHYS_ADDR
1866 hex "XIP Kernel Physical Location"
1867 depends on XIP_KERNEL
1868 default "0x00080000"
1870 This is the physical address in your flash memory the kernel will
1871 be linked for and stored to. This address is dependent on your
1875 bool "Kexec system call (EXPERIMENTAL)"
1876 depends on EXPERIMENTAL
1878 kexec is a system call that implements the ability to shutdown your
1879 current kernel, and to start another kernel. It is like a reboot
1880 but it is independent of the system firmware. And like a reboot
1881 you can start any kernel with it, not just Linux.
1883 It is an ongoing process to be certain the hardware in a machine
1884 is properly shutdown, so do not be surprised if this code does not
1885 initially work for you. It may help to enable device hotplugging
1889 bool "Export atags in procfs"
1893 Should the atags used to boot the kernel be exported in an "atags"
1894 file in procfs. Useful with kexec.
1897 bool "Build kdump crash kernel (EXPERIMENTAL)"
1898 depends on EXPERIMENTAL
1900 Generate crash dump after being started by kexec. This should
1901 be normally only set in special crash dump kernels which are
1902 loaded in the main kernel with kexec-tools into a specially
1903 reserved region and then later executed after a crash by
1904 kdump/kexec. The crash dump kernel must be compiled to a
1905 memory address not used by the main kernel
1907 For more details see Documentation/kdump/kdump.txt
1909 config AUTO_ZRELADDR
1910 bool "Auto calculation of the decompressed kernel image address"
1911 depends on !ZBOOT_ROM && !ARCH_U300
1913 ZRELADDR is the physical address where the decompressed kernel
1914 image will be placed. If AUTO_ZRELADDR is selected, the address
1915 will be determined at run-time by masking the current IP with
1916 0xf8000000. This assumes the zImage being placed in the first 128MB
1917 from start of memory.
1921 menu "CPU Power Management"
1925 source "drivers/cpufreq/Kconfig"
1928 tristate "CPUfreq driver for i.MX CPUs"
1929 depends on ARCH_MXC && CPU_FREQ
1931 This enables the CPUfreq driver for i.MX CPUs.
1933 config CPU_FREQ_SA1100
1936 config CPU_FREQ_SA1110
1939 config CPU_FREQ_INTEGRATOR
1940 tristate "CPUfreq driver for ARM Integrator CPUs"
1941 depends on ARCH_INTEGRATOR && CPU_FREQ
1944 This enables the CPUfreq driver for ARM Integrator CPUs.
1946 For details, take a look at <file:Documentation/cpu-freq>.
1952 depends on CPU_FREQ && ARCH_PXA && PXA25x
1954 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1959 Internal configuration node for common cpufreq on Samsung SoC
1961 config CPU_FREQ_S3C24XX
1962 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1963 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1966 This enables the CPUfreq driver for the Samsung S3C24XX family
1969 For details, take a look at <file:Documentation/cpu-freq>.
1973 config CPU_FREQ_S3C24XX_PLL
1974 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1975 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1977 Compile in support for changing the PLL frequency from the
1978 S3C24XX series CPUfreq driver. The PLL takes time to settle
1979 after a frequency change, so by default it is not enabled.
1981 This also means that the PLL tables for the selected CPU(s) will
1982 be built which may increase the size of the kernel image.
1984 config CPU_FREQ_S3C24XX_DEBUG
1985 bool "Debug CPUfreq Samsung driver core"
1986 depends on CPU_FREQ_S3C24XX
1988 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1990 config CPU_FREQ_S3C24XX_IODEBUG
1991 bool "Debug CPUfreq Samsung driver IO timing"
1992 depends on CPU_FREQ_S3C24XX
1994 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1996 config CPU_FREQ_S3C24XX_DEBUGFS
1997 bool "Export debugfs for CPUFreq"
1998 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2000 Export status information via debugfs.
2004 source "drivers/cpuidle/Kconfig"
2008 menu "Floating point emulation"
2010 comment "At least one emulation must be selected"
2013 bool "NWFPE math emulation"
2014 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2016 Say Y to include the NWFPE floating point emulator in the kernel.
2017 This is necessary to run most binaries. Linux does not currently
2018 support floating point hardware so you need to say Y here even if
2019 your machine has an FPA or floating point co-processor podule.
2021 You may say N here if you are going to load the Acorn FPEmulator
2022 early in the bootup.
2025 bool "Support extended precision"
2026 depends on FPE_NWFPE
2028 Say Y to include 80-bit support in the kernel floating-point
2029 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2030 Note that gcc does not generate 80-bit operations by default,
2031 so in most cases this option only enlarges the size of the
2032 floating point emulator without any good reason.
2034 You almost surely want to say N here.
2037 bool "FastFPE math emulation (EXPERIMENTAL)"
2038 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2040 Say Y here to include the FAST floating point emulator in the kernel.
2041 This is an experimental much faster emulator which now also has full
2042 precision for the mantissa. It does not support any exceptions.
2043 It is very simple, and approximately 3-6 times faster than NWFPE.
2045 It should be sufficient for most programs. It may be not suitable
2046 for scientific calculations, but you have to check this for yourself.
2047 If you do not feel you need a faster FP emulation you should better
2051 bool "VFP-format floating point maths"
2052 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2054 Say Y to include VFP support code in the kernel. This is needed
2055 if your hardware includes a VFP unit.
2057 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2058 release notes and additional status information.
2060 Say N if your target does not have VFP hardware.
2068 bool "Advanced SIMD (NEON) Extension support"
2069 depends on VFPv3 && CPU_V7
2071 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2076 menu "Userspace binary formats"
2078 source "fs/Kconfig.binfmt"
2081 tristate "RISC OS personality"
2084 Say Y here to include the kernel code necessary if you want to run
2085 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2086 experimental; if this sounds frightening, say N and sleep in peace.
2087 You can also say M here to compile this support as a module (which
2088 will be called arthur).
2092 menu "Power management options"
2094 source "kernel/power/Kconfig"
2096 config ARCH_SUSPEND_POSSIBLE
2097 depends on !ARCH_S5PC100
2098 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2099 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2104 source "net/Kconfig"
2106 source "drivers/Kconfig"
2110 source "arch/arm/Kconfig.debug"
2112 source "security/Kconfig"
2114 source "crypto/Kconfig"
2116 source "lib/Kconfig"