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ixgbe: Cleanup FCOE and VLAN handling in xmit_frame_ring
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
blob44ded0c092da982939193d4e654b78ba5a19ef1f
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 4
60 #define BUILD 8
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
99 board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
101 board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
103 board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
105 board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
111 board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
113 board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
115 board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
117 board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
119 board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
121 board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
123 board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
125 board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
127 board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
129 board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
131 board_82599 },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
133 board_82599 },
134
135 /* required last entry */
136 {0, }
137 };
138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
139
140 #ifdef CONFIG_IXGBE_DCA
141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
142 void *p);
143 static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
145 .next = NULL,
146 .priority = 0
147 };
148 #endif
149
150 #ifdef CONFIG_PCI_IOV
151 static unsigned int max_vfs;
152 module_param(max_vfs, uint, 0);
153 MODULE_PARM_DESC(max_vfs,
154 "Maximum number of virtual functions to allocate per physical function");
155 #endif /* CONFIG_PCI_IOV */
156
157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
161
162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
163
164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
165 {
166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 gcr;
168 u32 gpie;
169 u32 vmdctl;
170
171 #ifdef CONFIG_PCI_IOV
172 /* disable iov and allow time for transactions to clear */
173 pci_disable_sriov(adapter->pdev);
174 #endif
175
176 /* turn off device IOV mode */
177 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
178 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
179 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
180 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
183
184 /* set default pool back to 0 */
185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
187 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
188 IXGBE_WRITE_FLUSH(hw);
189
190 /* take a breather then clean up driver data */
191 msleep(100);
192
193 kfree(adapter->vfinfo);
194 adapter->vfinfo = NULL;
195
196 adapter->num_vfs = 0;
197 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
198 }
199
200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
201 {
202 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
203 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
204 schedule_work(&adapter->service_task);
205 }
206
207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
208 {
209 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
210
211 /* flush memory to make sure state is correct before next watchog */
212 smp_mb__before_clear_bit();
213 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
214 }
215
216 struct ixgbe_reg_info {
217 u32 ofs;
218 char *name;
219 };
220
221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
222
223 /* General Registers */
224 {IXGBE_CTRL, "CTRL"},
225 {IXGBE_STATUS, "STATUS"},
226 {IXGBE_CTRL_EXT, "CTRL_EXT"},
227
228 /* Interrupt Registers */
229 {IXGBE_EICR, "EICR"},
230
231 /* RX Registers */
232 {IXGBE_SRRCTL(0), "SRRCTL"},
233 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
234 {IXGBE_RDLEN(0), "RDLEN"},
235 {IXGBE_RDH(0), "RDH"},
236 {IXGBE_RDT(0), "RDT"},
237 {IXGBE_RXDCTL(0), "RXDCTL"},
238 {IXGBE_RDBAL(0), "RDBAL"},
239 {IXGBE_RDBAH(0), "RDBAH"},
240
241 /* TX Registers */
242 {IXGBE_TDBAL(0), "TDBAL"},
243 {IXGBE_TDBAH(0), "TDBAH"},
244 {IXGBE_TDLEN(0), "TDLEN"},
245 {IXGBE_TDH(0), "TDH"},
246 {IXGBE_TDT(0), "TDT"},
247 {IXGBE_TXDCTL(0), "TXDCTL"},
248
249 /* List Terminator */
250 {}
251 };
252
253
254 /*
255 * ixgbe_regdump - register printout routine
256 */
257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
258 {
259 int i = 0, j = 0;
260 char rname[16];
261 u32 regs[64];
262
263 switch (reginfo->ofs) {
264 case IXGBE_SRRCTL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
267 break;
268 case IXGBE_DCA_RXCTRL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
271 break;
272 case IXGBE_RDLEN(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
275 break;
276 case IXGBE_RDH(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
279 break;
280 case IXGBE_RDT(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
283 break;
284 case IXGBE_RXDCTL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
287 break;
288 case IXGBE_RDBAL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
291 break;
292 case IXGBE_RDBAH(0):
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
295 break;
296 case IXGBE_TDBAL(0):
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
299 break;
300 case IXGBE_TDBAH(0):
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
303 break;
304 case IXGBE_TDLEN(0):
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
307 break;
308 case IXGBE_TDH(0):
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
311 break;
312 case IXGBE_TDT(0):
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
315 break;
316 case IXGBE_TXDCTL(0):
317 for (i = 0; i < 64; i++)
318 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
319 break;
320 default:
321 pr_info("%-15s %08x\n", reginfo->name,
322 IXGBE_READ_REG(hw, reginfo->ofs));
323 return;
324 }
325
326 for (i = 0; i < 8; i++) {
327 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
328 pr_err("%-15s", rname);
329 for (j = 0; j < 8; j++)
330 pr_cont(" %08x", regs[i*8+j]);
331 pr_cont("\n");
332 }
333
334 }
335
336 /*
337 * ixgbe_dump - Print registers, tx-rings and rx-rings
338 */
339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
340 {
341 struct net_device *netdev = adapter->netdev;
342 struct ixgbe_hw *hw = &adapter->hw;
343 struct ixgbe_reg_info *reginfo;
344 int n = 0;
345 struct ixgbe_ring *tx_ring;
346 struct ixgbe_tx_buffer *tx_buffer_info;
347 union ixgbe_adv_tx_desc *tx_desc;
348 struct my_u0 { u64 a; u64 b; } *u0;
349 struct ixgbe_ring *rx_ring;
350 union ixgbe_adv_rx_desc *rx_desc;
351 struct ixgbe_rx_buffer *rx_buffer_info;
352 u32 staterr;
353 int i = 0;
354
355 if (!netif_msg_hw(adapter))
356 return;
357
358 /* Print netdevice Info */
359 if (netdev) {
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
361 pr_info("Device Name state "
362 "trans_start last_rx\n");
363 pr_info("%-15s %016lX %016lX %016lX\n",
364 netdev->name,
365 netdev->state,
366 netdev->trans_start,
367 netdev->last_rx);
368 }
369
370 /* Print Registers */
371 dev_info(&adapter->pdev->dev, "Register Dump\n");
372 pr_info(" Register Name Value\n");
373 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
374 reginfo->name; reginfo++) {
375 ixgbe_regdump(hw, reginfo);
376 }
377
378 /* Print TX Ring Summary */
379 if (!netdev || !netif_running(netdev))
380 goto exit;
381
382 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
383 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer_info =
387 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
388 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
389 n, tx_ring->next_to_use, tx_ring->next_to_clean,
390 (u64)tx_buffer_info->dma,
391 tx_buffer_info->length,
392 tx_buffer_info->next_to_watch,
393 (u64)tx_buffer_info->time_stamp);
394 }
395
396 /* Print TX Rings */
397 if (!netif_msg_tx_done(adapter))
398 goto rx_ring_summary;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
401
402 /* Transmit Descriptor Formats
403 *
404 * Advanced Transmit Descriptor
405 * +--------------------------------------------------------------+
406 * 0 | Buffer Address [63:0] |
407 * +--------------------------------------------------------------+
408 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
409 * +--------------------------------------------------------------+
410 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 */
412
413 for (n = 0; n < adapter->num_tx_queues; n++) {
414 tx_ring = adapter->tx_ring[n];
415 pr_info("------------------------------------\n");
416 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
417 pr_info("------------------------------------\n");
418 pr_info("T [desc] [address 63:0 ] "
419 "[PlPOIdStDDt Ln] [bi->dma ] "
420 "leng ntw timestamp bi->skb\n");
421
422 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
423 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
425 u0 = (struct my_u0 *)tx_desc;
426 pr_info("T [0x%03X] %016llX %016llX %016llX"
427 " %04X %p %016llX %p", i,
428 le64_to_cpu(u0->a),
429 le64_to_cpu(u0->b),
430 (u64)tx_buffer_info->dma,
431 tx_buffer_info->length,
432 tx_buffer_info->next_to_watch,
433 (u64)tx_buffer_info->time_stamp,
434 tx_buffer_info->skb);
435 if (i == tx_ring->next_to_use &&
436 i == tx_ring->next_to_clean)
437 pr_cont(" NTC/U\n");
438 else if (i == tx_ring->next_to_use)
439 pr_cont(" NTU\n");
440 else if (i == tx_ring->next_to_clean)
441 pr_cont(" NTC\n");
442 else
443 pr_cont("\n");
444
445 if (netif_msg_pktdata(adapter) &&
446 tx_buffer_info->dma != 0)
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16, 1,
449 phys_to_virt(tx_buffer_info->dma),
450 tx_buffer_info->length, true);
451 }
452 }
453
454 /* Print RX Rings Summary */
455 rx_ring_summary:
456 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
457 pr_info("Queue [NTU] [NTC]\n");
458 for (n = 0; n < adapter->num_rx_queues; n++) {
459 rx_ring = adapter->rx_ring[n];
460 pr_info("%5d %5X %5X\n",
461 n, rx_ring->next_to_use, rx_ring->next_to_clean);
462 }
463
464 /* Print RX Rings */
465 if (!netif_msg_rx_status(adapter))
466 goto exit;
467
468 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
469
470 /* Advanced Receive Descriptor (Read) Format
471 * 63 1 0
472 * +-----------------------------------------------------+
473 * 0 | Packet Buffer Address [63:1] |A0/NSE|
474 * +----------------------------------------------+------+
475 * 8 | Header Buffer Address [63:1] | DD |
476 * +-----------------------------------------------------+
477 *
478 *
479 * Advanced Receive Descriptor (Write-Back) Format
480 *
481 * 63 48 47 32 31 30 21 20 16 15 4 3 0
482 * +------------------------------------------------------+
483 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
484 * | Checksum Ident | | | | Type | Type |
485 * +------------------------------------------------------+
486 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
487 * +------------------------------------------------------+
488 * 63 48 47 32 31 20 19 0
489 */
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] "
496 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
497 "<-- Adv Rx Read format\n");
498 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
499 "[vl er S cks ln] ---------------- [bi->skb] "
500 "<-- Adv Rx Write-Back format\n");
501
502 for (i = 0; i < rx_ring->count; i++) {
503 rx_buffer_info = &rx_ring->rx_buffer_info[i];
504 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
507 if (staterr & IXGBE_RXD_STAT_DD) {
508 /* Descriptor Done */
509 pr_info("RWB[0x%03X] %016llX "
510 "%016llX ---------------- %p", i,
511 le64_to_cpu(u0->a),
512 le64_to_cpu(u0->b),
513 rx_buffer_info->skb);
514 } else {
515 pr_info("R [0x%03X] %016llX "
516 "%016llX %016llX %p", i,
517 le64_to_cpu(u0->a),
518 le64_to_cpu(u0->b),
519 (u64)rx_buffer_info->dma,
520 rx_buffer_info->skb);
521
522 if (netif_msg_pktdata(adapter)) {
523 print_hex_dump(KERN_INFO, "",
524 DUMP_PREFIX_ADDRESS, 16, 1,
525 phys_to_virt(rx_buffer_info->dma),
526 rx_ring->rx_buf_len, true);
527
528 if (rx_ring->rx_buf_len
529 < IXGBE_RXBUFFER_2048)
530 print_hex_dump(KERN_INFO, "",
531 DUMP_PREFIX_ADDRESS, 16, 1,
532 phys_to_virt(
533 rx_buffer_info->page_dma +
534 rx_buffer_info->page_offset
535 ),
536 PAGE_SIZE/2, true);
537 }
538 }
539
540 if (i == rx_ring->next_to_use)
541 pr_cont(" NTU\n");
542 else if (i == rx_ring->next_to_clean)
543 pr_cont(" NTC\n");
544 else
545 pr_cont("\n");
546
547 }
548 }
549
550 exit:
551 return;
552 }
553
554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555 {
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
562 }
563
564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565 {
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
572 }
573
574 /*
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
583 u8 queue, u8 msix_vector)
584 {
585 u32 ivar, index;
586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
599 case ixgbe_mac_X540:
600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
622 }
623
624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
625 u64 qmask)
626 {
627 u32 mask;
628
629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
633 break;
634 case ixgbe_mac_82599EB:
635 case ixgbe_mac_X540:
636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
640 break;
641 default:
642 break;
643 }
644 }
645
646 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
648 {
649 if (tx_buffer->dma) {
650 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
651 dma_unmap_page(ring->dev,
652 tx_buffer->dma,
653 tx_buffer->length,
654 DMA_TO_DEVICE);
655 else
656 dma_unmap_single(ring->dev,
657 tx_buffer->dma,
658 tx_buffer->length,
659 DMA_TO_DEVICE);
660 }
661 tx_buffer->dma = 0;
662 }
663
664 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
665 struct ixgbe_tx_buffer *tx_buffer_info)
666 {
667 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
668 if (tx_buffer_info->skb)
669 dev_kfree_skb_any(tx_buffer_info->skb);
670 tx_buffer_info->skb = NULL;
671 /* tx_buffer_info must be completely set up in the transmit path */
672 }
673
674 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
675 {
676 struct ixgbe_hw *hw = &adapter->hw;
677 struct ixgbe_hw_stats *hwstats = &adapter->stats;
678 u32 data = 0;
679 u32 xoff[8] = {0};
680 int i;
681
682 if ((hw->fc.current_mode == ixgbe_fc_full) ||
683 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
684 switch (hw->mac.type) {
685 case ixgbe_mac_82598EB:
686 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
687 break;
688 default:
689 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
690 }
691 hwstats->lxoffrxc += data;
692
693 /* refill credits (no tx hang) if we received xoff */
694 if (!data)
695 return;
696
697 for (i = 0; i < adapter->num_tx_queues; i++)
698 clear_bit(__IXGBE_HANG_CHECK_ARMED,
699 &adapter->tx_ring[i]->state);
700 return;
701 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
702 return;
703
704 /* update stats for each tc, only valid with PFC enabled */
705 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
706 switch (hw->mac.type) {
707 case ixgbe_mac_82598EB:
708 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
709 break;
710 default:
711 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
712 }
713 hwstats->pxoffrxc[i] += xoff[i];
714 }
715
716 /* disarm tx queues that have received xoff frames */
717 for (i = 0; i < adapter->num_tx_queues; i++) {
718 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
719 u8 tc = tx_ring->dcb_tc;
720
721 if (xoff[tc])
722 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
723 }
724 }
725
726 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
727 {
728 return ring->tx_stats.completed;
729 }
730
731 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
732 {
733 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
734 struct ixgbe_hw *hw = &adapter->hw;
735
736 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
737 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
738
739 if (head != tail)
740 return (head < tail) ?
741 tail - head : (tail + ring->count - head);
742
743 return 0;
744 }
745
746 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
747 {
748 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
749 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
750 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
751 bool ret = false;
752
753 clear_check_for_tx_hang(tx_ring);
754
755 /*
756 * Check for a hung queue, but be thorough. This verifies
757 * that a transmit has been completed since the previous
758 * check AND there is at least one packet pending. The
759 * ARMED bit is set to indicate a potential hang. The
760 * bit is cleared if a pause frame is received to remove
761 * false hang detection due to PFC or 802.3x frames. By
762 * requiring this to fail twice we avoid races with
763 * pfc clearing the ARMED bit and conditions where we
764 * run the check_tx_hang logic with a transmit completion
765 * pending but without time to complete it yet.
766 */
767 if ((tx_done_old == tx_done) && tx_pending) {
768 /* make sure it is true for two checks in a row */
769 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
770 &tx_ring->state);
771 } else {
772 /* update completed stats and continue */
773 tx_ring->tx_stats.tx_done_old = tx_done;
774 /* reset the countdown */
775 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
776 }
777
778 return ret;
779 }
780
781 /**
782 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
783 * @adapter: driver private struct
784 **/
785 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
786 {
787
788 /* Do the reset outside of interrupt context */
789 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
790 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
791 ixgbe_service_event_schedule(adapter);
792 }
793 }
794
795 /**
796 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
797 * @q_vector: structure containing interrupt and ring information
798 * @tx_ring: tx ring to clean
799 **/
800 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
801 struct ixgbe_ring *tx_ring)
802 {
803 struct ixgbe_adapter *adapter = q_vector->adapter;
804 struct ixgbe_tx_buffer *tx_buffer;
805 union ixgbe_adv_tx_desc *tx_desc;
806 unsigned int total_bytes = 0, total_packets = 0;
807 u16 i = tx_ring->next_to_clean;
808 u16 count;
809
810 tx_buffer = &tx_ring->tx_buffer_info[i];
811 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
812
813 for (count = 0; count < q_vector->tx.work_limit; count++) {
814 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
815
816 /* if next_to_watch is not set then there is no work pending */
817 if (!eop_desc)
818 break;
819
820 /* if DD is not set pending work has not been completed */
821 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
822 break;
823
824 /* count the packet as being completed */
825 tx_ring->tx_stats.completed++;
826
827 /* clear next_to_watch to prevent false hangs */
828 tx_buffer->next_to_watch = NULL;
829
830 /* prevent any other reads prior to eop_desc being verified */
831 rmb();
832
833 do {
834 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
835 tx_desc->wb.status = 0;
836 if (likely(tx_desc == eop_desc)) {
837 eop_desc = NULL;
838 dev_kfree_skb_any(tx_buffer->skb);
839 tx_buffer->skb = NULL;
840
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843 }
844
845 tx_buffer++;
846 tx_desc++;
847 i++;
848 if (unlikely(i == tx_ring->count)) {
849 i = 0;
850
851 tx_buffer = tx_ring->tx_buffer_info;
852 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
853 }
854
855 } while (eop_desc);
856 }
857
858 tx_ring->next_to_clean = i;
859 u64_stats_update_begin(&tx_ring->syncp);
860 tx_ring->stats.bytes += total_bytes;
861 tx_ring->stats.packets += total_packets;
862 u64_stats_update_end(&tx_ring->syncp);
863 q_vector->tx.total_bytes += total_bytes;
864 q_vector->tx.total_packets += total_packets;
865
866 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
867 /* schedule immediate reset if we believe we hung */
868 struct ixgbe_hw *hw = &adapter->hw;
869 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
870 e_err(drv, "Detected Tx Unit Hang\n"
871 " Tx Queue <%d>\n"
872 " TDH, TDT <%x>, <%x>\n"
873 " next_to_use <%x>\n"
874 " next_to_clean <%x>\n"
875 "tx_buffer_info[next_to_clean]\n"
876 " time_stamp <%lx>\n"
877 " jiffies <%lx>\n",
878 tx_ring->queue_index,
879 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
880 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
881 tx_ring->next_to_use, i,
882 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
883
884 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
885
886 e_info(probe,
887 "tx hang %d detected on queue %d, resetting adapter\n",
888 adapter->tx_timeout_count + 1, tx_ring->queue_index);
889
890 /* schedule immediate reset if we believe we hung */
891 ixgbe_tx_timeout_reset(adapter);
892
893 /* the adapter is about to reset, no point in enabling stuff */
894 return true;
895 }
896
897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
898 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
899 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
900 /* Make sure that anybody stopping the queue after this
901 * sees the new next_to_clean.
902 */
903 smp_mb();
904 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
905 !test_bit(__IXGBE_DOWN, &adapter->state)) {
906 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
907 ++tx_ring->tx_stats.restart_queue;
908 }
909 }
910
911 return count < q_vector->tx.work_limit;
912 }
913
914 #ifdef CONFIG_IXGBE_DCA
915 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
916 struct ixgbe_ring *rx_ring,
917 int cpu)
918 {
919 struct ixgbe_hw *hw = &adapter->hw;
920 u32 rxctrl;
921 u8 reg_idx = rx_ring->reg_idx;
922
923 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
924 switch (hw->mac.type) {
925 case ixgbe_mac_82598EB:
926 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
927 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
928 break;
929 case ixgbe_mac_82599EB:
930 case ixgbe_mac_X540:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
932 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
933 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
934 break;
935 default:
936 break;
937 }
938 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
939 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
940 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
941 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
942 }
943
944 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *tx_ring,
946 int cpu)
947 {
948 struct ixgbe_hw *hw = &adapter->hw;
949 u32 txctrl;
950 u8 reg_idx = tx_ring->reg_idx;
951
952 switch (hw->mac.type) {
953 case ixgbe_mac_82598EB:
954 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
955 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
956 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
957 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
958 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
959 break;
960 case ixgbe_mac_82599EB:
961 case ixgbe_mac_X540:
962 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
963 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
964 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
965 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
966 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
967 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
968 break;
969 default:
970 break;
971 }
972 }
973
974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975 {
976 struct ixgbe_adapter *adapter = q_vector->adapter;
977 int cpu = get_cpu();
978 long r_idx;
979 int i;
980
981 if (q_vector->cpu == cpu)
982 goto out_no_update;
983
984 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
985 for (i = 0; i < q_vector->tx.count; i++) {
986 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
987 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
988 r_idx + 1);
989 }
990
991 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
992 for (i = 0; i < q_vector->rx.count; i++) {
993 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
994 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
995 r_idx + 1);
996 }
997
998 q_vector->cpu = cpu;
999 out_no_update:
1000 put_cpu();
1001 }
1002
1003 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1004 {
1005 int num_q_vectors;
1006 int i;
1007
1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return;
1010
1011 /* always use CB2 mode, difference is masked in the CB driver */
1012 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1013
1014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1015 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1016 else
1017 num_q_vectors = 1;
1018
1019 for (i = 0; i < num_q_vectors; i++) {
1020 adapter->q_vector[i]->cpu = -1;
1021 ixgbe_update_dca(adapter->q_vector[i]);
1022 }
1023 }
1024
1025 static int __ixgbe_notify_dca(struct device *dev, void *data)
1026 {
1027 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1028 unsigned long event = *(unsigned long *)data;
1029
1030 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1031 return 0;
1032
1033 switch (event) {
1034 case DCA_PROVIDER_ADD:
1035 /* if we're already enabled, don't do it again */
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1037 break;
1038 if (dca_add_requester(dev) == 0) {
1039 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1040 ixgbe_setup_dca(adapter);
1041 break;
1042 }
1043 /* Fall Through since DCA is disabled. */
1044 case DCA_PROVIDER_REMOVE:
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1046 dca_remove_requester(dev);
1047 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1048 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1049 }
1050 break;
1051 }
1052
1053 return 0;
1054 }
1055 #endif /* CONFIG_IXGBE_DCA */
1056
1057 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1058 struct sk_buff *skb)
1059 {
1060 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1061 }
1062
1063 /**
1064 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1065 * @adapter: address of board private structure
1066 * @rx_desc: advanced rx descriptor
1067 *
1068 * Returns : true if it is FCoE pkt
1069 */
1070 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1071 union ixgbe_adv_rx_desc *rx_desc)
1072 {
1073 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1074
1075 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1076 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1077 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1078 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1079 }
1080
1081 /**
1082 * ixgbe_receive_skb - Send a completed packet up the stack
1083 * @adapter: board private structure
1084 * @skb: packet to send up
1085 * @status: hardware indication of status of receive
1086 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1087 * @rx_desc: rx descriptor
1088 **/
1089 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1090 struct sk_buff *skb, u8 status,
1091 struct ixgbe_ring *ring,
1092 union ixgbe_adv_rx_desc *rx_desc)
1093 {
1094 struct ixgbe_adapter *adapter = q_vector->adapter;
1095 struct napi_struct *napi = &q_vector->napi;
1096 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1097 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1098
1099 if (is_vlan && (tag & VLAN_VID_MASK))
1100 __vlan_hwaccel_put_tag(skb, tag);
1101
1102 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1103 napi_gro_receive(napi, skb);
1104 else
1105 netif_rx(skb);
1106 }
1107
1108 /**
1109 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1110 * @adapter: address of board private structure
1111 * @status_err: hardware indication of status of receive
1112 * @skb: skb currently being received and modified
1113 * @status_err: status error value of last descriptor in packet
1114 **/
1115 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1116 union ixgbe_adv_rx_desc *rx_desc,
1117 struct sk_buff *skb,
1118 u32 status_err)
1119 {
1120 skb->ip_summed = CHECKSUM_NONE;
1121
1122 /* Rx csum disabled */
1123 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1124 return;
1125
1126 /* if IP and error */
1127 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1128 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1129 adapter->hw_csum_rx_error++;
1130 return;
1131 }
1132
1133 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1134 return;
1135
1136 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1137 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1138
1139 /*
1140 * 82599 errata, UDP frames with a 0 checksum can be marked as
1141 * checksum errors.
1142 */
1143 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1144 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1145 return;
1146
1147 adapter->hw_csum_rx_error++;
1148 return;
1149 }
1150
1151 /* It must be a TCP or UDP packet with a valid checksum */
1152 skb->ip_summed = CHECKSUM_UNNECESSARY;
1153 }
1154
1155 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1156 {
1157 /*
1158 * Force memory writes to complete before letting h/w
1159 * know there are new descriptors to fetch. (Only
1160 * applicable for weak-ordered memory model archs,
1161 * such as IA-64).
1162 */
1163 wmb();
1164 writel(val, rx_ring->tail);
1165 }
1166
1167 /**
1168 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1169 * @rx_ring: ring to place buffers on
1170 * @cleaned_count: number of buffers to replace
1171 **/
1172 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1173 {
1174 union ixgbe_adv_rx_desc *rx_desc;
1175 struct ixgbe_rx_buffer *bi;
1176 struct sk_buff *skb;
1177 u16 i = rx_ring->next_to_use;
1178
1179 /* do nothing if no valid netdev defined */
1180 if (!rx_ring->netdev)
1181 return;
1182
1183 while (cleaned_count--) {
1184 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1185 bi = &rx_ring->rx_buffer_info[i];
1186 skb = bi->skb;
1187
1188 if (!skb) {
1189 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1190 rx_ring->rx_buf_len);
1191 if (!skb) {
1192 rx_ring->rx_stats.alloc_rx_buff_failed++;
1193 goto no_buffers;
1194 }
1195 /* initialize queue mapping */
1196 skb_record_rx_queue(skb, rx_ring->queue_index);
1197 bi->skb = skb;
1198 }
1199
1200 if (!bi->dma) {
1201 bi->dma = dma_map_single(rx_ring->dev,
1202 skb->data,
1203 rx_ring->rx_buf_len,
1204 DMA_FROM_DEVICE);
1205 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1206 rx_ring->rx_stats.alloc_rx_buff_failed++;
1207 bi->dma = 0;
1208 goto no_buffers;
1209 }
1210 }
1211
1212 if (ring_is_ps_enabled(rx_ring)) {
1213 if (!bi->page) {
1214 bi->page = netdev_alloc_page(rx_ring->netdev);
1215 if (!bi->page) {
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1217 goto no_buffers;
1218 }
1219 }
1220
1221 if (!bi->page_dma) {
1222 /* use a half page if we're re-using */
1223 bi->page_offset ^= PAGE_SIZE / 2;
1224 bi->page_dma = dma_map_page(rx_ring->dev,
1225 bi->page,
1226 bi->page_offset,
1227 PAGE_SIZE / 2,
1228 DMA_FROM_DEVICE);
1229 if (dma_mapping_error(rx_ring->dev,
1230 bi->page_dma)) {
1231 rx_ring->rx_stats.alloc_rx_page_failed++;
1232 bi->page_dma = 0;
1233 goto no_buffers;
1234 }
1235 }
1236
1237 /* Refresh the desc even if buffer_addrs didn't change
1238 * because each write-back erases this info. */
1239 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1240 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1241 } else {
1242 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1243 rx_desc->read.hdr_addr = 0;
1244 }
1245
1246 i++;
1247 if (i == rx_ring->count)
1248 i = 0;
1249 }
1250
1251 no_buffers:
1252 if (rx_ring->next_to_use != i) {
1253 rx_ring->next_to_use = i;
1254 ixgbe_release_rx_desc(rx_ring, i);
1255 }
1256 }
1257
1258 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1259 {
1260 /* HW will not DMA in data larger than the given buffer, even if it
1261 * parses the (NFS, of course) header to be larger. In that case, it
1262 * fills the header buffer and spills the rest into the page.
1263 */
1264 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1265 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1266 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1267 if (hlen > IXGBE_RX_HDR_SIZE)
1268 hlen = IXGBE_RX_HDR_SIZE;
1269 return hlen;
1270 }
1271
1272 /**
1273 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1274 * @skb: pointer to the last skb in the rsc queue
1275 *
1276 * This function changes a queue full of hw rsc buffers into a completed
1277 * packet. It uses the ->prev pointers to find the first packet and then
1278 * turns it into the frag list owner.
1279 **/
1280 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1281 {
1282 unsigned int frag_list_size = 0;
1283 unsigned int skb_cnt = 1;
1284
1285 while (skb->prev) {
1286 struct sk_buff *prev = skb->prev;
1287 frag_list_size += skb->len;
1288 skb->prev = NULL;
1289 skb = prev;
1290 skb_cnt++;
1291 }
1292
1293 skb_shinfo(skb)->frag_list = skb->next;
1294 skb->next = NULL;
1295 skb->len += frag_list_size;
1296 skb->data_len += frag_list_size;
1297 skb->truesize += frag_list_size;
1298 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1299
1300 return skb;
1301 }
1302
1303 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1304 {
1305 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1306 IXGBE_RXDADV_RSCCNT_MASK);
1307 }
1308
1309 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1310 struct ixgbe_ring *rx_ring,
1311 int *work_done, int work_to_do)
1312 {
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
1314 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1315 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1316 struct sk_buff *skb;
1317 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1318 const int current_node = numa_node_id();
1319 #ifdef IXGBE_FCOE
1320 int ddp_bytes = 0;
1321 #endif /* IXGBE_FCOE */
1322 u32 staterr;
1323 u16 i;
1324 u16 cleaned_count = 0;
1325 bool pkt_is_rsc = false;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1330
1331 while (staterr & IXGBE_RXD_STAT_DD) {
1332 u32 upper_len = 0;
1333
1334 rmb(); /* read descriptor and rx_buffer_info after status DD */
1335
1336 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1337
1338 skb = rx_buffer_info->skb;
1339 rx_buffer_info->skb = NULL;
1340 prefetch(skb->data);
1341
1342 if (ring_is_rsc_enabled(rx_ring))
1343 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1344
1345 /* if this is a skb from previous receive DMA will be 0 */
1346 if (rx_buffer_info->dma) {
1347 u16 hlen;
1348 if (pkt_is_rsc &&
1349 !(staterr & IXGBE_RXD_STAT_EOP) &&
1350 !skb->prev) {
1351 /*
1352 * When HWRSC is enabled, delay unmapping
1353 * of the first packet. It carries the
1354 * header information, HW may still
1355 * access the header after the writeback.
1356 * Only unmap it when EOP is reached
1357 */
1358 IXGBE_RSC_CB(skb)->delay_unmap = true;
1359 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1360 } else {
1361 dma_unmap_single(rx_ring->dev,
1362 rx_buffer_info->dma,
1363 rx_ring->rx_buf_len,
1364 DMA_FROM_DEVICE);
1365 }
1366 rx_buffer_info->dma = 0;
1367
1368 if (ring_is_ps_enabled(rx_ring)) {
1369 hlen = ixgbe_get_hlen(rx_desc);
1370 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1371 } else {
1372 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1373 }
1374
1375 skb_put(skb, hlen);
1376 } else {
1377 /* assume packet split since header is unmapped */
1378 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1379 }
1380
1381 if (upper_len) {
1382 dma_unmap_page(rx_ring->dev,
1383 rx_buffer_info->page_dma,
1384 PAGE_SIZE / 2,
1385 DMA_FROM_DEVICE);
1386 rx_buffer_info->page_dma = 0;
1387 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1388 rx_buffer_info->page,
1389 rx_buffer_info->page_offset,
1390 upper_len);
1391
1392 if ((page_count(rx_buffer_info->page) == 1) &&
1393 (page_to_nid(rx_buffer_info->page) == current_node))
1394 get_page(rx_buffer_info->page);
1395 else
1396 rx_buffer_info->page = NULL;
1397
1398 skb->len += upper_len;
1399 skb->data_len += upper_len;
1400 skb->truesize += upper_len;
1401 }
1402
1403 i++;
1404 if (i == rx_ring->count)
1405 i = 0;
1406
1407 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1408 prefetch(next_rxd);
1409 cleaned_count++;
1410
1411 if (pkt_is_rsc) {
1412 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1413 IXGBE_RXDADV_NEXTP_SHIFT;
1414 next_buffer = &rx_ring->rx_buffer_info[nextp];
1415 } else {
1416 next_buffer = &rx_ring->rx_buffer_info[i];
1417 }
1418
1419 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1420 if (ring_is_ps_enabled(rx_ring)) {
1421 rx_buffer_info->skb = next_buffer->skb;
1422 rx_buffer_info->dma = next_buffer->dma;
1423 next_buffer->skb = skb;
1424 next_buffer->dma = 0;
1425 } else {
1426 skb->next = next_buffer->skb;
1427 skb->next->prev = skb;
1428 }
1429 rx_ring->rx_stats.non_eop_descs++;
1430 goto next_desc;
1431 }
1432
1433 if (skb->prev) {
1434 skb = ixgbe_transform_rsc_queue(skb);
1435 /* if we got here without RSC the packet is invalid */
1436 if (!pkt_is_rsc) {
1437 __pskb_trim(skb, 0);
1438 rx_buffer_info->skb = skb;
1439 goto next_desc;
1440 }
1441 }
1442
1443 if (ring_is_rsc_enabled(rx_ring)) {
1444 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1445 dma_unmap_single(rx_ring->dev,
1446 IXGBE_RSC_CB(skb)->dma,
1447 rx_ring->rx_buf_len,
1448 DMA_FROM_DEVICE);
1449 IXGBE_RSC_CB(skb)->dma = 0;
1450 IXGBE_RSC_CB(skb)->delay_unmap = false;
1451 }
1452 }
1453 if (pkt_is_rsc) {
1454 if (ring_is_ps_enabled(rx_ring))
1455 rx_ring->rx_stats.rsc_count +=
1456 skb_shinfo(skb)->nr_frags;
1457 else
1458 rx_ring->rx_stats.rsc_count +=
1459 IXGBE_RSC_CB(skb)->skb_cnt;
1460 rx_ring->rx_stats.rsc_flush++;
1461 }
1462
1463 /* ERR_MASK will only have valid bits if EOP set */
1464 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1465 dev_kfree_skb_any(skb);
1466 goto next_desc;
1467 }
1468
1469 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1470 if (adapter->netdev->features & NETIF_F_RXHASH)
1471 ixgbe_rx_hash(rx_desc, skb);
1472
1473 /* probably a little skewed due to removing CRC */
1474 total_rx_bytes += skb->len;
1475 total_rx_packets++;
1476
1477 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1478 #ifdef IXGBE_FCOE
1479 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1480 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1481 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1482 staterr);
1483 if (!ddp_bytes)
1484 goto next_desc;
1485 }
1486 #endif /* IXGBE_FCOE */
1487 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1488
1489 next_desc:
1490 rx_desc->wb.upper.status_error = 0;
1491
1492 (*work_done)++;
1493 if (*work_done >= work_to_do)
1494 break;
1495
1496 /* return some buffers to hardware, one at a time is too slow */
1497 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1498 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1499 cleaned_count = 0;
1500 }
1501
1502 /* use prefetched values */
1503 rx_desc = next_rxd;
1504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1505 }
1506
1507 rx_ring->next_to_clean = i;
1508 cleaned_count = ixgbe_desc_unused(rx_ring);
1509
1510 if (cleaned_count)
1511 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1512
1513 #ifdef IXGBE_FCOE
1514 /* include DDPed FCoE data */
1515 if (ddp_bytes > 0) {
1516 unsigned int mss;
1517
1518 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1519 sizeof(struct fc_frame_header) -
1520 sizeof(struct fcoe_crc_eof);
1521 if (mss > 512)
1522 mss &= ~511;
1523 total_rx_bytes += ddp_bytes;
1524 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1525 }
1526 #endif /* IXGBE_FCOE */
1527
1528 u64_stats_update_begin(&rx_ring->syncp);
1529 rx_ring->stats.packets += total_rx_packets;
1530 rx_ring->stats.bytes += total_rx_bytes;
1531 u64_stats_update_end(&rx_ring->syncp);
1532 q_vector->rx.total_packets += total_rx_packets;
1533 q_vector->rx.total_bytes += total_rx_bytes;
1534 }
1535
1536 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1537 /**
1538 * ixgbe_configure_msix - Configure MSI-X hardware
1539 * @adapter: board private structure
1540 *
1541 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1542 * interrupts.
1543 **/
1544 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1545 {
1546 struct ixgbe_q_vector *q_vector;
1547 int i, q_vectors, v_idx, r_idx;
1548 u32 mask;
1549
1550 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1551
1552 /*
1553 * Populate the IVAR table and set the ITR values to the
1554 * corresponding register.
1555 */
1556 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1557 q_vector = adapter->q_vector[v_idx];
1558 /* XXX for_each_set_bit(...) */
1559 r_idx = find_first_bit(q_vector->rx.idx,
1560 adapter->num_rx_queues);
1561
1562 for (i = 0; i < q_vector->rx.count; i++) {
1563 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1564 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1565 r_idx = find_next_bit(q_vector->rx.idx,
1566 adapter->num_rx_queues,
1567 r_idx + 1);
1568 }
1569 r_idx = find_first_bit(q_vector->tx.idx,
1570 adapter->num_tx_queues);
1571
1572 for (i = 0; i < q_vector->tx.count; i++) {
1573 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1574 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1575 r_idx = find_next_bit(q_vector->tx.idx,
1576 adapter->num_tx_queues,
1577 r_idx + 1);
1578 }
1579
1580 if (q_vector->tx.count && !q_vector->rx.count)
1581 /* tx only */
1582 q_vector->eitr = adapter->tx_eitr_param;
1583 else if (q_vector->rx.count)
1584 /* rx or mixed */
1585 q_vector->eitr = adapter->rx_eitr_param;
1586
1587 ixgbe_write_eitr(q_vector);
1588 /* If ATR is enabled, set interrupt affinity */
1589 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1590 /*
1591 * Allocate the affinity_hint cpumask, assign the mask
1592 * for this vector, and set our affinity_hint for
1593 * this irq.
1594 */
1595 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1596 GFP_KERNEL))
1597 return;
1598 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1599 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1600 q_vector->affinity_mask);
1601 }
1602 }
1603
1604 switch (adapter->hw.mac.type) {
1605 case ixgbe_mac_82598EB:
1606 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1607 v_idx);
1608 break;
1609 case ixgbe_mac_82599EB:
1610 case ixgbe_mac_X540:
1611 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1612 break;
1613
1614 default:
1615 break;
1616 }
1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1618
1619 /* set up to autoclear timer, and the vectors */
1620 mask = IXGBE_EIMS_ENABLE_MASK;
1621 if (adapter->num_vfs)
1622 mask &= ~(IXGBE_EIMS_OTHER |
1623 IXGBE_EIMS_MAILBOX |
1624 IXGBE_EIMS_LSC);
1625 else
1626 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1628 }
1629
1630 enum latency_range {
1631 lowest_latency = 0,
1632 low_latency = 1,
1633 bulk_latency = 2,
1634 latency_invalid = 255
1635 };
1636
1637 /**
1638 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1639 * @q_vector: structure containing interrupt and ring information
1640 * @ring_container: structure containing ring performance data
1641 *
1642 * Stores a new ITR value based on packets and byte
1643 * counts during the last interrupt. The advantage of per interrupt
1644 * computation is faster updates and more accurate ITR for the current
1645 * traffic pattern. Constants in this function were computed
1646 * based on theoretical maximum wire speed and thresholds were set based
1647 * on testing data as well as attempting to minimize response time
1648 * while increasing bulk throughput.
1649 * this functionality is controlled by the InterruptThrottleRate module
1650 * parameter (see ixgbe_param.c)
1651 **/
1652 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1653 struct ixgbe_ring_container *ring_container)
1654 {
1655 u64 bytes_perint;
1656 struct ixgbe_adapter *adapter = q_vector->adapter;
1657 int bytes = ring_container->total_bytes;
1658 int packets = ring_container->total_packets;
1659 u32 timepassed_us;
1660 u8 itr_setting = ring_container->itr;
1661
1662 if (packets == 0)
1663 return;
1664
1665 /* simple throttlerate management
1666 * 0-20MB/s lowest (100000 ints/s)
1667 * 20-100MB/s low (20000 ints/s)
1668 * 100-1249MB/s bulk (8000 ints/s)
1669 */
1670 /* what was last interrupt timeslice? */
1671 timepassed_us = 1000000/q_vector->eitr;
1672 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1673
1674 switch (itr_setting) {
1675 case lowest_latency:
1676 if (bytes_perint > adapter->eitr_low)
1677 itr_setting = low_latency;
1678 break;
1679 case low_latency:
1680 if (bytes_perint > adapter->eitr_high)
1681 itr_setting = bulk_latency;
1682 else if (bytes_perint <= adapter->eitr_low)
1683 itr_setting = lowest_latency;
1684 break;
1685 case bulk_latency:
1686 if (bytes_perint <= adapter->eitr_high)
1687 itr_setting = low_latency;
1688 break;
1689 }
1690
1691 /* clear work counters since we have the values we need */
1692 ring_container->total_bytes = 0;
1693 ring_container->total_packets = 0;
1694
1695 /* write updated itr to ring container */
1696 ring_container->itr = itr_setting;
1697 }
1698
1699 /**
1700 * ixgbe_write_eitr - write EITR register in hardware specific way
1701 * @q_vector: structure containing interrupt and ring information
1702 *
1703 * This function is made to be called by ethtool and by the driver
1704 * when it needs to update EITR registers at runtime. Hardware
1705 * specific quirks/differences are taken care of here.
1706 */
1707 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1708 {
1709 struct ixgbe_adapter *adapter = q_vector->adapter;
1710 struct ixgbe_hw *hw = &adapter->hw;
1711 int v_idx = q_vector->v_idx;
1712 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1713
1714 switch (adapter->hw.mac.type) {
1715 case ixgbe_mac_82598EB:
1716 /* must write high and low 16 bits to reset counter */
1717 itr_reg |= (itr_reg << 16);
1718 break;
1719 case ixgbe_mac_82599EB:
1720 case ixgbe_mac_X540:
1721 /*
1722 * 82599 and X540 can support a value of zero, so allow it for
1723 * max interrupt rate, but there is an errata where it can
1724 * not be zero with RSC
1725 */
1726 if (itr_reg == 8 &&
1727 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1728 itr_reg = 0;
1729
1730 /*
1731 * set the WDIS bit to not clear the timer bits and cause an
1732 * immediate assertion of the interrupt
1733 */
1734 itr_reg |= IXGBE_EITR_CNT_WDIS;
1735 break;
1736 default:
1737 break;
1738 }
1739 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1740 }
1741
1742 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1743 {
1744 u32 new_itr = q_vector->eitr;
1745 u8 current_itr;
1746
1747 ixgbe_update_itr(q_vector, &q_vector->tx);
1748 ixgbe_update_itr(q_vector, &q_vector->rx);
1749
1750 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1751
1752 switch (current_itr) {
1753 /* counts and packets in update_itr are dependent on these numbers */
1754 case lowest_latency:
1755 new_itr = 100000;
1756 break;
1757 case low_latency:
1758 new_itr = 20000; /* aka hwitr = ~200 */
1759 break;
1760 case bulk_latency:
1761 new_itr = 8000;
1762 break;
1763 default:
1764 break;
1765 }
1766
1767 if (new_itr != q_vector->eitr) {
1768 /* do an exponential smoothing */
1769 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1770
1771 /* save the algorithm value here */
1772 q_vector->eitr = new_itr;
1773
1774 ixgbe_write_eitr(q_vector);
1775 }
1776 }
1777
1778 /**
1779 * ixgbe_check_overtemp_subtask - check for over tempurature
1780 * @adapter: pointer to adapter
1781 **/
1782 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1783 {
1784 struct ixgbe_hw *hw = &adapter->hw;
1785 u32 eicr = adapter->interrupt_event;
1786
1787 if (test_bit(__IXGBE_DOWN, &adapter->state))
1788 return;
1789
1790 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1791 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1792 return;
1793
1794 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1795
1796 switch (hw->device_id) {
1797 case IXGBE_DEV_ID_82599_T3_LOM:
1798 /*
1799 * Since the warning interrupt is for both ports
1800 * we don't have to check if:
1801 * - This interrupt wasn't for our port.
1802 * - We may have missed the interrupt so always have to
1803 * check if we got a LSC
1804 */
1805 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1806 !(eicr & IXGBE_EICR_LSC))
1807 return;
1808
1809 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1810 u32 autoneg;
1811 bool link_up = false;
1812
1813 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1814
1815 if (link_up)
1816 return;
1817 }
1818
1819 /* Check if this is not due to overtemp */
1820 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1821 return;
1822
1823 break;
1824 default:
1825 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1826 return;
1827 break;
1828 }
1829 e_crit(drv,
1830 "Network adapter has been stopped because it has over heated. "
1831 "Restart the computer. If the problem persists, "
1832 "power off the system and replace the adapter\n");
1833
1834 adapter->interrupt_event = 0;
1835 }
1836
1837 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1838 {
1839 struct ixgbe_hw *hw = &adapter->hw;
1840
1841 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1842 (eicr & IXGBE_EICR_GPI_SDP1)) {
1843 e_crit(probe, "Fan has stopped, replace the adapter\n");
1844 /* write to clear the interrupt */
1845 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1846 }
1847 }
1848
1849 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1850 {
1851 struct ixgbe_hw *hw = &adapter->hw;
1852
1853 if (eicr & IXGBE_EICR_GPI_SDP2) {
1854 /* Clear the interrupt */
1855 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1856 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1857 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1858 ixgbe_service_event_schedule(adapter);
1859 }
1860 }
1861
1862 if (eicr & IXGBE_EICR_GPI_SDP1) {
1863 /* Clear the interrupt */
1864 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1865 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1866 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1867 ixgbe_service_event_schedule(adapter);
1868 }
1869 }
1870 }
1871
1872 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1873 {
1874 struct ixgbe_hw *hw = &adapter->hw;
1875
1876 adapter->lsc_int++;
1877 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1878 adapter->link_check_timeout = jiffies;
1879 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1880 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1881 IXGBE_WRITE_FLUSH(hw);
1882 ixgbe_service_event_schedule(adapter);
1883 }
1884 }
1885
1886 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1887 {
1888 struct ixgbe_adapter *adapter = data;
1889 struct ixgbe_hw *hw = &adapter->hw;
1890 u32 eicr;
1891
1892 /*
1893 * Workaround for Silicon errata. Use clear-by-write instead
1894 * of clear-by-read. Reading with EICS will return the
1895 * interrupt causes without clearing, which later be done
1896 * with the write to EICR.
1897 */
1898 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1899 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1900
1901 if (eicr & IXGBE_EICR_LSC)
1902 ixgbe_check_lsc(adapter);
1903
1904 if (eicr & IXGBE_EICR_MAILBOX)
1905 ixgbe_msg_task(adapter);
1906
1907 switch (hw->mac.type) {
1908 case ixgbe_mac_82599EB:
1909 case ixgbe_mac_X540:
1910 /* Handle Flow Director Full threshold interrupt */
1911 if (eicr & IXGBE_EICR_FLOW_DIR) {
1912 int reinit_count = 0;
1913 int i;
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *ring = adapter->tx_ring[i];
1916 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1917 &ring->state))
1918 reinit_count++;
1919 }
1920 if (reinit_count) {
1921 /* no more flow director interrupts until after init */
1922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1923 eicr &= ~IXGBE_EICR_FLOW_DIR;
1924 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1925 ixgbe_service_event_schedule(adapter);
1926 }
1927 }
1928 ixgbe_check_sfp_event(adapter, eicr);
1929 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1930 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1931 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1932 adapter->interrupt_event = eicr;
1933 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1934 ixgbe_service_event_schedule(adapter);
1935 }
1936 }
1937 break;
1938 default:
1939 break;
1940 }
1941
1942 ixgbe_check_fan_failure(adapter, eicr);
1943
1944 /* re-enable the original interrupt state, no lsc, no queues */
1945 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1946 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1947 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1948
1949 return IRQ_HANDLED;
1950 }
1951
1952 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1953 u64 qmask)
1954 {
1955 u32 mask;
1956 struct ixgbe_hw *hw = &adapter->hw;
1957
1958 switch (hw->mac.type) {
1959 case ixgbe_mac_82598EB:
1960 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1961 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1962 break;
1963 case ixgbe_mac_82599EB:
1964 case ixgbe_mac_X540:
1965 mask = (qmask & 0xFFFFFFFF);
1966 if (mask)
1967 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1968 mask = (qmask >> 32);
1969 if (mask)
1970 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1971 break;
1972 default:
1973 break;
1974 }
1975 /* skip the flush */
1976 }
1977
1978 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1979 u64 qmask)
1980 {
1981 u32 mask;
1982 struct ixgbe_hw *hw = &adapter->hw;
1983
1984 switch (hw->mac.type) {
1985 case ixgbe_mac_82598EB:
1986 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1987 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1988 break;
1989 case ixgbe_mac_82599EB:
1990 case ixgbe_mac_X540:
1991 mask = (qmask & 0xFFFFFFFF);
1992 if (mask)
1993 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1994 mask = (qmask >> 32);
1995 if (mask)
1996 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1997 break;
1998 default:
1999 break;
2000 }
2001 /* skip the flush */
2002 }
2003
2004 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2005 {
2006 struct ixgbe_q_vector *q_vector = data;
2007 struct ixgbe_adapter *adapter = q_vector->adapter;
2008 struct ixgbe_ring *tx_ring;
2009 int i, r_idx;
2010
2011 if (!q_vector->tx.count)
2012 return IRQ_HANDLED;
2013
2014 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2015 for (i = 0; i < q_vector->tx.count; i++) {
2016 tx_ring = adapter->tx_ring[r_idx];
2017 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2018 r_idx + 1);
2019 }
2020
2021 /* EIAM disabled interrupts (on this vector) for us */
2022 napi_schedule(&q_vector->napi);
2023
2024 return IRQ_HANDLED;
2025 }
2026
2027 /**
2028 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2029 * @irq: unused
2030 * @data: pointer to our q_vector struct for this interrupt vector
2031 **/
2032 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2033 {
2034 struct ixgbe_q_vector *q_vector = data;
2035 struct ixgbe_adapter *adapter = q_vector->adapter;
2036 struct ixgbe_ring *rx_ring;
2037 int r_idx;
2038 int i;
2039
2040 #ifdef CONFIG_IXGBE_DCA
2041 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2042 ixgbe_update_dca(q_vector);
2043 #endif
2044
2045 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2046 for (i = 0; i < q_vector->rx.count; i++) {
2047 rx_ring = adapter->rx_ring[r_idx];
2048 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2049 r_idx + 1);
2050 }
2051
2052 if (!q_vector->rx.count)
2053 return IRQ_HANDLED;
2054
2055 /* EIAM disabled interrupts (on this vector) for us */
2056 napi_schedule(&q_vector->napi);
2057
2058 return IRQ_HANDLED;
2059 }
2060
2061 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2062 {
2063 struct ixgbe_q_vector *q_vector = data;
2064 struct ixgbe_adapter *adapter = q_vector->adapter;
2065 struct ixgbe_ring *ring;
2066 int r_idx;
2067 int i;
2068
2069 if (!q_vector->tx.count && !q_vector->rx.count)
2070 return IRQ_HANDLED;
2071
2072 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2073 for (i = 0; i < q_vector->tx.count; i++) {
2074 ring = adapter->tx_ring[r_idx];
2075 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2076 r_idx + 1);
2077 }
2078
2079 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2080 for (i = 0; i < q_vector->rx.count; i++) {
2081 ring = adapter->rx_ring[r_idx];
2082 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2083 r_idx + 1);
2084 }
2085
2086 /* EIAM disabled interrupts (on this vector) for us */
2087 napi_schedule(&q_vector->napi);
2088
2089 return IRQ_HANDLED;
2090 }
2091
2092 /**
2093 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2094 * @napi: napi struct with our devices info in it
2095 * @budget: amount of work driver is allowed to do this pass, in packets
2096 *
2097 * This function is optimized for cleaning one queue only on a single
2098 * q_vector!!!
2099 **/
2100 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2101 {
2102 struct ixgbe_q_vector *q_vector =
2103 container_of(napi, struct ixgbe_q_vector, napi);
2104 struct ixgbe_adapter *adapter = q_vector->adapter;
2105 struct ixgbe_ring *rx_ring = NULL;
2106 int work_done = 0;
2107 long r_idx;
2108
2109 #ifdef CONFIG_IXGBE_DCA
2110 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2111 ixgbe_update_dca(q_vector);
2112 #endif
2113
2114 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2115 rx_ring = adapter->rx_ring[r_idx];
2116
2117 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2118
2119 /* If all Rx work done, exit the polling mode */
2120 if (work_done < budget) {
2121 napi_complete(napi);
2122 if (adapter->rx_itr_setting & 1)
2123 ixgbe_set_itr(q_vector);
2124 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2125 ixgbe_irq_enable_queues(adapter,
2126 ((u64)1 << q_vector->v_idx));
2127 }
2128
2129 return work_done;
2130 }
2131
2132 /**
2133 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2134 * @napi: napi struct with our devices info in it
2135 * @budget: amount of work driver is allowed to do this pass, in packets
2136 *
2137 * This function will clean more than one rx queue associated with a
2138 * q_vector.
2139 **/
2140 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2141 {
2142 struct ixgbe_q_vector *q_vector =
2143 container_of(napi, struct ixgbe_q_vector, napi);
2144 struct ixgbe_adapter *adapter = q_vector->adapter;
2145 struct ixgbe_ring *ring = NULL;
2146 int work_done = 0, i;
2147 long r_idx;
2148 bool tx_clean_complete = true;
2149
2150 #ifdef CONFIG_IXGBE_DCA
2151 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2152 ixgbe_update_dca(q_vector);
2153 #endif
2154
2155 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2156 for (i = 0; i < q_vector->tx.count; i++) {
2157 ring = adapter->tx_ring[r_idx];
2158 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2159 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2160 r_idx + 1);
2161 }
2162
2163 /* attempt to distribute budget to each queue fairly, but don't allow
2164 * the budget to go below 1 because we'll exit polling */
2165 budget /= (q_vector->rx.count ?: 1);
2166 budget = max(budget, 1);
2167 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2168 for (i = 0; i < q_vector->rx.count; i++) {
2169 ring = adapter->rx_ring[r_idx];
2170 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2171 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2172 r_idx + 1);
2173 }
2174
2175 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2176 ring = adapter->rx_ring[r_idx];
2177 /* If all Rx work done, exit the polling mode */
2178 if (work_done < budget) {
2179 napi_complete(napi);
2180 if (adapter->rx_itr_setting & 1)
2181 ixgbe_set_itr(q_vector);
2182 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2183 ixgbe_irq_enable_queues(adapter,
2184 ((u64)1 << q_vector->v_idx));
2185 return 0;
2186 }
2187
2188 return work_done;
2189 }
2190
2191 /**
2192 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2193 * @napi: napi struct with our devices info in it
2194 * @budget: amount of work driver is allowed to do this pass, in packets
2195 *
2196 * This function is optimized for cleaning one queue only on a single
2197 * q_vector!!!
2198 **/
2199 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2200 {
2201 struct ixgbe_q_vector *q_vector =
2202 container_of(napi, struct ixgbe_q_vector, napi);
2203 struct ixgbe_adapter *adapter = q_vector->adapter;
2204 struct ixgbe_ring *tx_ring = NULL;
2205 int work_done = 0;
2206 long r_idx;
2207
2208 #ifdef CONFIG_IXGBE_DCA
2209 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2210 ixgbe_update_dca(q_vector);
2211 #endif
2212
2213 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2214 tx_ring = adapter->tx_ring[r_idx];
2215
2216 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2217 work_done = budget;
2218
2219 /* If all Tx work done, exit the polling mode */
2220 if (work_done < budget) {
2221 napi_complete(napi);
2222 if (adapter->tx_itr_setting & 1)
2223 ixgbe_set_itr(q_vector);
2224 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2225 ixgbe_irq_enable_queues(adapter,
2226 ((u64)1 << q_vector->v_idx));
2227 }
2228
2229 return work_done;
2230 }
2231
2232 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2233 int r_idx)
2234 {
2235 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2236 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2237
2238 set_bit(r_idx, q_vector->rx.idx);
2239 q_vector->rx.count++;
2240 rx_ring->q_vector = q_vector;
2241 }
2242
2243 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2244 int t_idx)
2245 {
2246 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2247 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2248
2249 set_bit(t_idx, q_vector->tx.idx);
2250 q_vector->tx.count++;
2251 tx_ring->q_vector = q_vector;
2252 q_vector->tx.work_limit = a->tx_work_limit;
2253 }
2254
2255 /**
2256 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2257 * @adapter: board private structure to initialize
2258 *
2259 * This function maps descriptor rings to the queue-specific vectors
2260 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2261 * one vector per ring/queue, but on a constrained vector budget, we
2262 * group the rings as "efficiently" as possible. You would add new
2263 * mapping configurations in here.
2264 **/
2265 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2266 {
2267 int q_vectors;
2268 int v_start = 0;
2269 int rxr_idx = 0, txr_idx = 0;
2270 int rxr_remaining = adapter->num_rx_queues;
2271 int txr_remaining = adapter->num_tx_queues;
2272 int i, j;
2273 int rqpv, tqpv;
2274 int err = 0;
2275
2276 /* No mapping required if MSI-X is disabled. */
2277 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2278 goto out;
2279
2280 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2281
2282 /*
2283 * The ideal configuration...
2284 * We have enough vectors to map one per queue.
2285 */
2286 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2287 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2288 map_vector_to_rxq(adapter, v_start, rxr_idx);
2289
2290 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2291 map_vector_to_txq(adapter, v_start, txr_idx);
2292
2293 goto out;
2294 }
2295
2296 /*
2297 * If we don't have enough vectors for a 1-to-1
2298 * mapping, we'll have to group them so there are
2299 * multiple queues per vector.
2300 */
2301 /* Re-adjusting *qpv takes care of the remainder. */
2302 for (i = v_start; i < q_vectors; i++) {
2303 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2304 for (j = 0; j < rqpv; j++) {
2305 map_vector_to_rxq(adapter, i, rxr_idx);
2306 rxr_idx++;
2307 rxr_remaining--;
2308 }
2309 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2310 for (j = 0; j < tqpv; j++) {
2311 map_vector_to_txq(adapter, i, txr_idx);
2312 txr_idx++;
2313 txr_remaining--;
2314 }
2315 }
2316 out:
2317 return err;
2318 }
2319
2320 /**
2321 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2322 * @adapter: board private structure
2323 *
2324 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2325 * interrupts from the kernel.
2326 **/
2327 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2328 {
2329 struct net_device *netdev = adapter->netdev;
2330 irqreturn_t (*handler)(int, void *);
2331 int i, vector, q_vectors, err;
2332 int ri = 0, ti = 0;
2333
2334 /* Decrement for Other and TCP Timer vectors */
2335 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2336
2337 err = ixgbe_map_rings_to_vectors(adapter);
2338 if (err)
2339 return err;
2340
2341 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2342 ? &ixgbe_msix_clean_many : \
2343 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2344 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2345 NULL)
2346 for (vector = 0; vector < q_vectors; vector++) {
2347 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2348 handler = SET_HANDLER(q_vector);
2349
2350 if (handler == &ixgbe_msix_clean_rx) {
2351 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2352 "%s-%s-%d", netdev->name, "rx", ri++);
2353 } else if (handler == &ixgbe_msix_clean_tx) {
2354 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2355 "%s-%s-%d", netdev->name, "tx", ti++);
2356 } else if (handler == &ixgbe_msix_clean_many) {
2357 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2358 "%s-%s-%d", netdev->name, "TxRx", ri++);
2359 ti++;
2360 } else {
2361 /* skip this unused q_vector */
2362 continue;
2363 }
2364 err = request_irq(adapter->msix_entries[vector].vector,
2365 handler, 0, q_vector->name,
2366 q_vector);
2367 if (err) {
2368 e_err(probe, "request_irq failed for MSIX interrupt "
2369 "Error: %d\n", err);
2370 goto free_queue_irqs;
2371 }
2372 }
2373
2374 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2375 err = request_irq(adapter->msix_entries[vector].vector,
2376 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2377 if (err) {
2378 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2379 goto free_queue_irqs;
2380 }
2381
2382 return 0;
2383
2384 free_queue_irqs:
2385 for (i = vector - 1; i >= 0; i--)
2386 free_irq(adapter->msix_entries[--vector].vector,
2387 adapter->q_vector[i]);
2388 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2389 pci_disable_msix(adapter->pdev);
2390 kfree(adapter->msix_entries);
2391 adapter->msix_entries = NULL;
2392 return err;
2393 }
2394
2395 /**
2396 * ixgbe_irq_enable - Enable default interrupt generation settings
2397 * @adapter: board private structure
2398 **/
2399 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2400 bool flush)
2401 {
2402 u32 mask;
2403
2404 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2405 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2406 mask |= IXGBE_EIMS_GPI_SDP0;
2407 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2408 mask |= IXGBE_EIMS_GPI_SDP1;
2409 switch (adapter->hw.mac.type) {
2410 case ixgbe_mac_82599EB:
2411 case ixgbe_mac_X540:
2412 mask |= IXGBE_EIMS_ECC;
2413 mask |= IXGBE_EIMS_GPI_SDP1;
2414 mask |= IXGBE_EIMS_GPI_SDP2;
2415 if (adapter->num_vfs)
2416 mask |= IXGBE_EIMS_MAILBOX;
2417 break;
2418 default:
2419 break;
2420 }
2421 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2422 mask |= IXGBE_EIMS_FLOW_DIR;
2423
2424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2425 if (queues)
2426 ixgbe_irq_enable_queues(adapter, ~0);
2427 if (flush)
2428 IXGBE_WRITE_FLUSH(&adapter->hw);
2429
2430 if (adapter->num_vfs > 32) {
2431 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2432 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2433 }
2434 }
2435
2436 /**
2437 * ixgbe_intr - legacy mode Interrupt Handler
2438 * @irq: interrupt number
2439 * @data: pointer to a network interface device structure
2440 **/
2441 static irqreturn_t ixgbe_intr(int irq, void *data)
2442 {
2443 struct ixgbe_adapter *adapter = data;
2444 struct ixgbe_hw *hw = &adapter->hw;
2445 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2446 u32 eicr;
2447
2448 /*
2449 * Workaround for silicon errata on 82598. Mask the interrupts
2450 * before the read of EICR.
2451 */
2452 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2453
2454 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2455 * therefore no explict interrupt disable is necessary */
2456 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2457 if (!eicr) {
2458 /*
2459 * shared interrupt alert!
2460 * make sure interrupts are enabled because the read will
2461 * have disabled interrupts due to EIAM
2462 * finish the workaround of silicon errata on 82598. Unmask
2463 * the interrupt that we masked before the EICR read.
2464 */
2465 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2466 ixgbe_irq_enable(adapter, true, true);
2467 return IRQ_NONE; /* Not our interrupt */
2468 }
2469
2470 if (eicr & IXGBE_EICR_LSC)
2471 ixgbe_check_lsc(adapter);
2472
2473 switch (hw->mac.type) {
2474 case ixgbe_mac_82599EB:
2475 ixgbe_check_sfp_event(adapter, eicr);
2476 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2477 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2478 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2479 adapter->interrupt_event = eicr;
2480 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2481 ixgbe_service_event_schedule(adapter);
2482 }
2483 }
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 ixgbe_check_fan_failure(adapter, eicr);
2490
2491 if (napi_schedule_prep(&(q_vector->napi))) {
2492 /* would disable interrupts here but EIAM disabled it */
2493 __napi_schedule(&(q_vector->napi));
2494 }
2495
2496 /*
2497 * re-enable link(maybe) and non-queue interrupts, no flush.
2498 * ixgbe_poll will re-enable the queue interrupts
2499 */
2500
2501 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2502 ixgbe_irq_enable(adapter, false, false);
2503
2504 return IRQ_HANDLED;
2505 }
2506
2507 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2508 {
2509 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2510
2511 for (i = 0; i < q_vectors; i++) {
2512 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2513 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2514 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2515 q_vector->rx.count = 0;
2516 q_vector->tx.count = 0;
2517 }
2518 }
2519
2520 /**
2521 * ixgbe_request_irq - initialize interrupts
2522 * @adapter: board private structure
2523 *
2524 * Attempts to configure interrupts using the best available
2525 * capabilities of the hardware and kernel.
2526 **/
2527 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2528 {
2529 struct net_device *netdev = adapter->netdev;
2530 int err;
2531
2532 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2533 err = ixgbe_request_msix_irqs(adapter);
2534 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2535 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2536 netdev->name, adapter);
2537 } else {
2538 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2539 netdev->name, adapter);
2540 }
2541
2542 if (err)
2543 e_err(probe, "request_irq failed, Error %d\n", err);
2544
2545 return err;
2546 }
2547
2548 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2549 {
2550 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2551 int i, q_vectors;
2552
2553 q_vectors = adapter->num_msix_vectors;
2554
2555 i = q_vectors - 1;
2556 free_irq(adapter->msix_entries[i].vector, adapter);
2557
2558 i--;
2559 for (; i >= 0; i--) {
2560 /* free only the irqs that were actually requested */
2561 if (!adapter->q_vector[i]->rx.count &&
2562 !adapter->q_vector[i]->tx.count)
2563 continue;
2564
2565 free_irq(adapter->msix_entries[i].vector,
2566 adapter->q_vector[i]);
2567 }
2568
2569 ixgbe_reset_q_vectors(adapter);
2570 } else {
2571 free_irq(adapter->pdev->irq, adapter);
2572 }
2573 }
2574
2575 /**
2576 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2577 * @adapter: board private structure
2578 **/
2579 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2580 {
2581 switch (adapter->hw.mac.type) {
2582 case ixgbe_mac_82598EB:
2583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2584 break;
2585 case ixgbe_mac_82599EB:
2586 case ixgbe_mac_X540:
2587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2590 if (adapter->num_vfs > 32)
2591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2592 break;
2593 default:
2594 break;
2595 }
2596 IXGBE_WRITE_FLUSH(&adapter->hw);
2597 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2598 int i;
2599 for (i = 0; i < adapter->num_msix_vectors; i++)
2600 synchronize_irq(adapter->msix_entries[i].vector);
2601 } else {
2602 synchronize_irq(adapter->pdev->irq);
2603 }
2604 }
2605
2606 /**
2607 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2608 *
2609 **/
2610 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2611 {
2612 struct ixgbe_hw *hw = &adapter->hw;
2613
2614 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2615 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2616
2617 ixgbe_set_ivar(adapter, 0, 0, 0);
2618 ixgbe_set_ivar(adapter, 1, 0, 0);
2619
2620 map_vector_to_rxq(adapter, 0, 0);
2621 map_vector_to_txq(adapter, 0, 0);
2622
2623 e_info(hw, "Legacy interrupt IVAR setup done\n");
2624 }
2625
2626 /**
2627 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2628 * @adapter: board private structure
2629 * @ring: structure containing ring specific data
2630 *
2631 * Configure the Tx descriptor ring after a reset.
2632 **/
2633 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2634 struct ixgbe_ring *ring)
2635 {
2636 struct ixgbe_hw *hw = &adapter->hw;
2637 u64 tdba = ring->dma;
2638 int wait_loop = 10;
2639 u32 txdctl;
2640 u8 reg_idx = ring->reg_idx;
2641
2642 /* disable queue to avoid issues while updating state */
2643 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2644 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2645 txdctl & ~IXGBE_TXDCTL_ENABLE);
2646 IXGBE_WRITE_FLUSH(hw);
2647
2648 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2649 (tdba & DMA_BIT_MASK(32)));
2650 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2651 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2652 ring->count * sizeof(union ixgbe_adv_tx_desc));
2653 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2654 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2655 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2656
2657 /* configure fetching thresholds */
2658 if (adapter->rx_itr_setting == 0) {
2659 /* cannot set wthresh when itr==0 */
2660 txdctl &= ~0x007F0000;
2661 } else {
2662 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2663 txdctl |= (8 << 16);
2664 }
2665 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2666 /* PThresh workaround for Tx hang with DFP enabled. */
2667 txdctl |= 32;
2668 }
2669
2670 /* reinitialize flowdirector state */
2671 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2672 adapter->atr_sample_rate) {
2673 ring->atr_sample_rate = adapter->atr_sample_rate;
2674 ring->atr_count = 0;
2675 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2676 } else {
2677 ring->atr_sample_rate = 0;
2678 }
2679
2680 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2681
2682 /* enable queue */
2683 txdctl |= IXGBE_TXDCTL_ENABLE;
2684 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2685
2686 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2687 if (hw->mac.type == ixgbe_mac_82598EB &&
2688 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2689 return;
2690
2691 /* poll to verify queue is enabled */
2692 do {
2693 usleep_range(1000, 2000);
2694 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2695 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2696 if (!wait_loop)
2697 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2698 }
2699
2700 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2701 {
2702 struct ixgbe_hw *hw = &adapter->hw;
2703 u32 rttdcs;
2704 u32 reg;
2705 u8 tcs = netdev_get_num_tc(adapter->netdev);
2706
2707 if (hw->mac.type == ixgbe_mac_82598EB)
2708 return;
2709
2710 /* disable the arbiter while setting MTQC */
2711 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2712 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2713 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2714
2715 /* set transmit pool layout */
2716 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2717 case (IXGBE_FLAG_SRIOV_ENABLED):
2718 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2719 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2720 break;
2721 default:
2722 if (!tcs)
2723 reg = IXGBE_MTQC_64Q_1PB;
2724 else if (tcs <= 4)
2725 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2726 else
2727 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2728
2729 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2730
2731 /* Enable Security TX Buffer IFG for multiple pb */
2732 if (tcs) {
2733 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2734 reg |= IXGBE_SECTX_DCB;
2735 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2736 }
2737 break;
2738 }
2739
2740 /* re-enable the arbiter */
2741 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2742 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2743 }
2744
2745 /**
2746 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2747 * @adapter: board private structure
2748 *
2749 * Configure the Tx unit of the MAC after a reset.
2750 **/
2751 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2752 {
2753 struct ixgbe_hw *hw = &adapter->hw;
2754 u32 dmatxctl;
2755 u32 i;
2756
2757 ixgbe_setup_mtqc(adapter);
2758
2759 if (hw->mac.type != ixgbe_mac_82598EB) {
2760 /* DMATXCTL.EN must be before Tx queues are enabled */
2761 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2762 dmatxctl |= IXGBE_DMATXCTL_TE;
2763 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2764 }
2765
2766 /* Setup the HW Tx Head and Tail descriptor pointers */
2767 for (i = 0; i < adapter->num_tx_queues; i++)
2768 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2769 }
2770
2771 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2772
2773 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2774 struct ixgbe_ring *rx_ring)
2775 {
2776 u32 srrctl;
2777 u8 reg_idx = rx_ring->reg_idx;
2778
2779 switch (adapter->hw.mac.type) {
2780 case ixgbe_mac_82598EB: {
2781 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2782 const int mask = feature[RING_F_RSS].mask;
2783 reg_idx = reg_idx & mask;
2784 }
2785 break;
2786 case ixgbe_mac_82599EB:
2787 case ixgbe_mac_X540:
2788 default:
2789 break;
2790 }
2791
2792 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2793
2794 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2795 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2796 if (adapter->num_vfs)
2797 srrctl |= IXGBE_SRRCTL_DROP_EN;
2798
2799 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2800 IXGBE_SRRCTL_BSIZEHDR_MASK;
2801
2802 if (ring_is_ps_enabled(rx_ring)) {
2803 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2804 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2805 #else
2806 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2807 #endif
2808 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2809 } else {
2810 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2811 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2812 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2813 }
2814
2815 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2816 }
2817
2818 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2819 {
2820 struct ixgbe_hw *hw = &adapter->hw;
2821 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2822 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2823 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2824 u32 mrqc = 0, reta = 0;
2825 u32 rxcsum;
2826 int i, j;
2827 u8 tcs = netdev_get_num_tc(adapter->netdev);
2828 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2829
2830 if (tcs)
2831 maxq = min(maxq, adapter->num_tx_queues / tcs);
2832
2833 /* Fill out hash function seeds */
2834 for (i = 0; i < 10; i++)
2835 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2836
2837 /* Fill out redirection table */
2838 for (i = 0, j = 0; i < 128; i++, j++) {
2839 if (j == maxq)
2840 j = 0;
2841 /* reta = 4-byte sliding window of
2842 * 0x00..(indices-1)(indices-1)00..etc. */
2843 reta = (reta << 8) | (j * 0x11);
2844 if ((i & 3) == 3)
2845 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2846 }
2847
2848 /* Disable indicating checksum in descriptor, enables RSS hash */
2849 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2850 rxcsum |= IXGBE_RXCSUM_PCSD;
2851 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2852
2853 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2854 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2855 mrqc = IXGBE_MRQC_RSSEN;
2856 } else {
2857 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2858 | IXGBE_FLAG_SRIOV_ENABLED);
2859
2860 switch (mask) {
2861 case (IXGBE_FLAG_RSS_ENABLED):
2862 if (!tcs)
2863 mrqc = IXGBE_MRQC_RSSEN;
2864 else if (tcs <= 4)
2865 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2866 else
2867 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2868 break;
2869 case (IXGBE_FLAG_SRIOV_ENABLED):
2870 mrqc = IXGBE_MRQC_VMDQEN;
2871 break;
2872 default:
2873 break;
2874 }
2875 }
2876
2877 /* Perform hash on these packet types */
2878 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2879 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2880 | IXGBE_MRQC_RSS_FIELD_IPV6
2881 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2882
2883 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2884 }
2885
2886 /**
2887 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2888 * @adapter: address of board private structure
2889 * @index: index of ring to set
2890 **/
2891 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2892 struct ixgbe_ring *ring)
2893 {
2894 struct ixgbe_hw *hw = &adapter->hw;
2895 u32 rscctrl;
2896 int rx_buf_len;
2897 u8 reg_idx = ring->reg_idx;
2898
2899 if (!ring_is_rsc_enabled(ring))
2900 return;
2901
2902 rx_buf_len = ring->rx_buf_len;
2903 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2904 rscctrl |= IXGBE_RSCCTL_RSCEN;
2905 /*
2906 * we must limit the number of descriptors so that the
2907 * total size of max desc * buf_len is not greater
2908 * than 65535
2909 */
2910 if (ring_is_ps_enabled(ring)) {
2911 #if (MAX_SKB_FRAGS > 16)
2912 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2913 #elif (MAX_SKB_FRAGS > 8)
2914 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2915 #elif (MAX_SKB_FRAGS > 4)
2916 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2917 #else
2918 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2919 #endif
2920 } else {
2921 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2922 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2923 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2924 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2925 else
2926 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2927 }
2928 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2929 }
2930
2931 /**
2932 * ixgbe_set_uta - Set unicast filter table address
2933 * @adapter: board private structure
2934 *
2935 * The unicast table address is a register array of 32-bit registers.
2936 * The table is meant to be used in a way similar to how the MTA is used
2937 * however due to certain limitations in the hardware it is necessary to
2938 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2939 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2940 **/
2941 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2942 {
2943 struct ixgbe_hw *hw = &adapter->hw;
2944 int i;
2945
2946 /* The UTA table only exists on 82599 hardware and newer */
2947 if (hw->mac.type < ixgbe_mac_82599EB)
2948 return;
2949
2950 /* we only need to do this if VMDq is enabled */
2951 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2952 return;
2953
2954 for (i = 0; i < 128; i++)
2955 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2956 }
2957
2958 #define IXGBE_MAX_RX_DESC_POLL 10
2959 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2960 struct ixgbe_ring *ring)
2961 {
2962 struct ixgbe_hw *hw = &adapter->hw;
2963 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2964 u32 rxdctl;
2965 u8 reg_idx = ring->reg_idx;
2966
2967 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2968 if (hw->mac.type == ixgbe_mac_82598EB &&
2969 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2970 return;
2971
2972 do {
2973 usleep_range(1000, 2000);
2974 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2975 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2976
2977 if (!wait_loop) {
2978 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2979 "the polling period\n", reg_idx);
2980 }
2981 }
2982
2983 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2984 struct ixgbe_ring *ring)
2985 {
2986 struct ixgbe_hw *hw = &adapter->hw;
2987 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2988 u32 rxdctl;
2989 u8 reg_idx = ring->reg_idx;
2990
2991 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2992 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2993
2994 /* write value back with RXDCTL.ENABLE bit cleared */
2995 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2996
2997 if (hw->mac.type == ixgbe_mac_82598EB &&
2998 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2999 return;
3000
3001 /* the hardware may take up to 100us to really disable the rx queue */
3002 do {
3003 udelay(10);
3004 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3005 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3006
3007 if (!wait_loop) {
3008 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3009 "the polling period\n", reg_idx);
3010 }
3011 }
3012
3013 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3014 struct ixgbe_ring *ring)
3015 {
3016 struct ixgbe_hw *hw = &adapter->hw;
3017 u64 rdba = ring->dma;
3018 u32 rxdctl;
3019 u8 reg_idx = ring->reg_idx;
3020
3021 /* disable queue to avoid issues while updating state */
3022 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3023 ixgbe_disable_rx_queue(adapter, ring);
3024
3025 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3026 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3027 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3028 ring->count * sizeof(union ixgbe_adv_rx_desc));
3029 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3030 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3031 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3032
3033 ixgbe_configure_srrctl(adapter, ring);
3034 ixgbe_configure_rscctl(adapter, ring);
3035
3036 /* If operating in IOV mode set RLPML for X540 */
3037 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3038 hw->mac.type == ixgbe_mac_X540) {
3039 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3040 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3041 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3042 }
3043
3044 if (hw->mac.type == ixgbe_mac_82598EB) {
3045 /*
3046 * enable cache line friendly hardware writes:
3047 * PTHRESH=32 descriptors (half the internal cache),
3048 * this also removes ugly rx_no_buffer_count increment
3049 * HTHRESH=4 descriptors (to minimize latency on fetch)
3050 * WTHRESH=8 burst writeback up to two cache lines
3051 */
3052 rxdctl &= ~0x3FFFFF;
3053 rxdctl |= 0x080420;
3054 }
3055
3056 /* enable receive descriptor ring */
3057 rxdctl |= IXGBE_RXDCTL_ENABLE;
3058 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3059
3060 ixgbe_rx_desc_queue_enable(adapter, ring);
3061 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3062 }
3063
3064 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3065 {
3066 struct ixgbe_hw *hw = &adapter->hw;
3067 int p;
3068
3069 /* PSRTYPE must be initialized in non 82598 adapters */
3070 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3071 IXGBE_PSRTYPE_UDPHDR |
3072 IXGBE_PSRTYPE_IPV4HDR |
3073 IXGBE_PSRTYPE_L2HDR |
3074 IXGBE_PSRTYPE_IPV6HDR;
3075
3076 if (hw->mac.type == ixgbe_mac_82598EB)
3077 return;
3078
3079 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3080 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3081
3082 for (p = 0; p < adapter->num_rx_pools; p++)
3083 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3084 psrtype);
3085 }
3086
3087 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3088 {
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 gcr_ext;
3091 u32 vt_reg_bits;
3092 u32 reg_offset, vf_shift;
3093 u32 vmdctl;
3094
3095 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3096 return;
3097
3098 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3099 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3100 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3101 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3102
3103 vf_shift = adapter->num_vfs % 32;
3104 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3105
3106 /* Enable only the PF's pool for Tx/Rx */
3107 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3108 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3109 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3110 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3111 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3112
3113 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3114 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3115
3116 /*
3117 * Set up VF register offsets for selected VT Mode,
3118 * i.e. 32 or 64 VFs for SR-IOV
3119 */
3120 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3121 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3122 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3123 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3124
3125 /* enable Tx loopback for VF/PF communication */
3126 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3127 /* Enable MAC Anti-Spoofing */
3128 hw->mac.ops.set_mac_anti_spoofing(hw,
3129 (adapter->antispoofing_enabled =
3130 (adapter->num_vfs != 0)),
3131 adapter->num_vfs);
3132 }
3133
3134 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3135 {
3136 struct ixgbe_hw *hw = &adapter->hw;
3137 struct net_device *netdev = adapter->netdev;
3138 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3139 int rx_buf_len;
3140 struct ixgbe_ring *rx_ring;
3141 int i;
3142 u32 mhadd, hlreg0;
3143
3144 /* Decide whether to use packet split mode or not */
3145 /* On by default */
3146 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3147
3148 /* Do not use packet split if we're in SR-IOV Mode */
3149 if (adapter->num_vfs)
3150 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3151
3152 /* Disable packet split due to 82599 erratum #45 */
3153 if (hw->mac.type == ixgbe_mac_82599EB)
3154 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3155
3156 /* Set the RX buffer length according to the mode */
3157 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3158 rx_buf_len = IXGBE_RX_HDR_SIZE;
3159 } else {
3160 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3161 (netdev->mtu <= ETH_DATA_LEN))
3162 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3163 else
3164 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3165 }
3166
3167 #ifdef IXGBE_FCOE
3168 /* adjust max frame to be able to do baby jumbo for FCoE */
3169 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3170 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3171 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3172
3173 #endif /* IXGBE_FCOE */
3174 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3175 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3176 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3177 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3178
3179 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3180 }
3181
3182 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3183 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3184 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3185 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3186
3187 /*
3188 * Setup the HW Rx Head and Tail Descriptor Pointers and
3189 * the Base and Length of the Rx Descriptor Ring
3190 */
3191 for (i = 0; i < adapter->num_rx_queues; i++) {
3192 rx_ring = adapter->rx_ring[i];
3193 rx_ring->rx_buf_len = rx_buf_len;
3194
3195 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3196 set_ring_ps_enabled(rx_ring);
3197 else
3198 clear_ring_ps_enabled(rx_ring);
3199
3200 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3201 set_ring_rsc_enabled(rx_ring);
3202 else
3203 clear_ring_rsc_enabled(rx_ring);
3204
3205 #ifdef IXGBE_FCOE
3206 if (netdev->features & NETIF_F_FCOE_MTU) {
3207 struct ixgbe_ring_feature *f;
3208 f = &adapter->ring_feature[RING_F_FCOE];
3209 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3210 clear_ring_ps_enabled(rx_ring);
3211 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3212 rx_ring->rx_buf_len =
3213 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3214 } else if (!ring_is_rsc_enabled(rx_ring) &&
3215 !ring_is_ps_enabled(rx_ring)) {
3216 rx_ring->rx_buf_len =
3217 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3218 }
3219 }
3220 #endif /* IXGBE_FCOE */
3221 }
3222 }
3223
3224 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3225 {
3226 struct ixgbe_hw *hw = &adapter->hw;
3227 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3228
3229 switch (hw->mac.type) {
3230 case ixgbe_mac_82598EB:
3231 /*
3232 * For VMDq support of different descriptor types or
3233 * buffer sizes through the use of multiple SRRCTL
3234 * registers, RDRXCTL.MVMEN must be set to 1
3235 *
3236 * also, the manual doesn't mention it clearly but DCA hints
3237 * will only use queue 0's tags unless this bit is set. Side
3238 * effects of setting this bit are only that SRRCTL must be
3239 * fully programmed [0..15]
3240 */
3241 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3242 break;
3243 case ixgbe_mac_82599EB:
3244 case ixgbe_mac_X540:
3245 /* Disable RSC for ACK packets */
3246 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3247 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3248 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3249 /* hardware requires some bits to be set by default */
3250 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3251 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3252 break;
3253 default:
3254 /* We should do nothing since we don't know this hardware */
3255 return;
3256 }
3257
3258 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3259 }
3260
3261 /**
3262 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3263 * @adapter: board private structure
3264 *
3265 * Configure the Rx unit of the MAC after a reset.
3266 **/
3267 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3268 {
3269 struct ixgbe_hw *hw = &adapter->hw;
3270 int i;
3271 u32 rxctrl;
3272
3273 /* disable receives while setting up the descriptors */
3274 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3275 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3276
3277 ixgbe_setup_psrtype(adapter);
3278 ixgbe_setup_rdrxctl(adapter);
3279
3280 /* Program registers for the distribution of queues */
3281 ixgbe_setup_mrqc(adapter);
3282
3283 ixgbe_set_uta(adapter);
3284
3285 /* set_rx_buffer_len must be called before ring initialization */
3286 ixgbe_set_rx_buffer_len(adapter);
3287
3288 /*
3289 * Setup the HW Rx Head and Tail Descriptor Pointers and
3290 * the Base and Length of the Rx Descriptor Ring
3291 */
3292 for (i = 0; i < adapter->num_rx_queues; i++)
3293 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3294
3295 /* disable drop enable for 82598 parts */
3296 if (hw->mac.type == ixgbe_mac_82598EB)
3297 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3298
3299 /* enable all receives */
3300 rxctrl |= IXGBE_RXCTRL_RXEN;
3301 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3302 }
3303
3304 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3305 {
3306 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3307 struct ixgbe_hw *hw = &adapter->hw;
3308 int pool_ndx = adapter->num_vfs;
3309
3310 /* add VID to filter table */
3311 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3312 set_bit(vid, adapter->active_vlans);
3313 }
3314
3315 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3316 {
3317 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3318 struct ixgbe_hw *hw = &adapter->hw;
3319 int pool_ndx = adapter->num_vfs;
3320
3321 /* remove VID from filter table */
3322 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3323 clear_bit(vid, adapter->active_vlans);
3324 }
3325
3326 /**
3327 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3328 * @adapter: driver data
3329 */
3330 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3331 {
3332 struct ixgbe_hw *hw = &adapter->hw;
3333 u32 vlnctrl;
3334
3335 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3336 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3337 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3338 }
3339
3340 /**
3341 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3342 * @adapter: driver data
3343 */
3344 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3345 {
3346 struct ixgbe_hw *hw = &adapter->hw;
3347 u32 vlnctrl;
3348
3349 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3350 vlnctrl |= IXGBE_VLNCTRL_VFE;
3351 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3352 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3353 }
3354
3355 /**
3356 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3357 * @adapter: driver data
3358 */
3359 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3360 {
3361 struct ixgbe_hw *hw = &adapter->hw;
3362 u32 vlnctrl;
3363 int i, j;
3364
3365 switch (hw->mac.type) {
3366 case ixgbe_mac_82598EB:
3367 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3368 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3369 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3370 break;
3371 case ixgbe_mac_82599EB:
3372 case ixgbe_mac_X540:
3373 for (i = 0; i < adapter->num_rx_queues; i++) {
3374 j = adapter->rx_ring[i]->reg_idx;
3375 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3376 vlnctrl &= ~IXGBE_RXDCTL_VME;
3377 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3378 }
3379 break;
3380 default:
3381 break;
3382 }
3383 }
3384
3385 /**
3386 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3387 * @adapter: driver data
3388 */
3389 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3390 {
3391 struct ixgbe_hw *hw = &adapter->hw;
3392 u32 vlnctrl;
3393 int i, j;
3394
3395 switch (hw->mac.type) {
3396 case ixgbe_mac_82598EB:
3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl |= IXGBE_VLNCTRL_VME;
3399 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3400 break;
3401 case ixgbe_mac_82599EB:
3402 case ixgbe_mac_X540:
3403 for (i = 0; i < adapter->num_rx_queues; i++) {
3404 j = adapter->rx_ring[i]->reg_idx;
3405 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3406 vlnctrl |= IXGBE_RXDCTL_VME;
3407 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3408 }
3409 break;
3410 default:
3411 break;
3412 }
3413 }
3414
3415 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3416 {
3417 u16 vid;
3418
3419 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3420
3421 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3422 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3423 }
3424
3425 /**
3426 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3427 * @netdev: network interface device structure
3428 *
3429 * Writes unicast address list to the RAR table.
3430 * Returns: -ENOMEM on failure/insufficient address space
3431 * 0 on no addresses written
3432 * X on writing X addresses to the RAR table
3433 **/
3434 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3435 {
3436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3437 struct ixgbe_hw *hw = &adapter->hw;
3438 unsigned int vfn = adapter->num_vfs;
3439 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3440 int count = 0;
3441
3442 /* return ENOMEM indicating insufficient memory for addresses */
3443 if (netdev_uc_count(netdev) > rar_entries)
3444 return -ENOMEM;
3445
3446 if (!netdev_uc_empty(netdev) && rar_entries) {
3447 struct netdev_hw_addr *ha;
3448 /* return error if we do not support writing to RAR table */
3449 if (!hw->mac.ops.set_rar)
3450 return -ENOMEM;
3451
3452 netdev_for_each_uc_addr(ha, netdev) {
3453 if (!rar_entries)
3454 break;
3455 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3456 vfn, IXGBE_RAH_AV);
3457 count++;
3458 }
3459 }
3460 /* write the addresses in reverse order to avoid write combining */
3461 for (; rar_entries > 0 ; rar_entries--)
3462 hw->mac.ops.clear_rar(hw, rar_entries);
3463
3464 return count;
3465 }
3466
3467 /**
3468 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3469 * @netdev: network interface device structure
3470 *
3471 * The set_rx_method entry point is called whenever the unicast/multicast
3472 * address list or the network interface flags are updated. This routine is
3473 * responsible for configuring the hardware for proper unicast, multicast and
3474 * promiscuous mode.
3475 **/
3476 void ixgbe_set_rx_mode(struct net_device *netdev)
3477 {
3478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3479 struct ixgbe_hw *hw = &adapter->hw;
3480 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3481 int count;
3482
3483 /* Check for Promiscuous and All Multicast modes */
3484
3485 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3486
3487 /* set all bits that we expect to always be set */
3488 fctrl |= IXGBE_FCTRL_BAM;
3489 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3490 fctrl |= IXGBE_FCTRL_PMCF;
3491
3492 /* clear the bits we are changing the status of */
3493 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3494
3495 if (netdev->flags & IFF_PROMISC) {
3496 hw->addr_ctrl.user_set_promisc = true;
3497 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3498 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3499 /* don't hardware filter vlans in promisc mode */
3500 ixgbe_vlan_filter_disable(adapter);
3501 } else {
3502 if (netdev->flags & IFF_ALLMULTI) {
3503 fctrl |= IXGBE_FCTRL_MPE;
3504 vmolr |= IXGBE_VMOLR_MPE;
3505 } else {
3506 /*
3507 * Write addresses to the MTA, if the attempt fails
3508 * then we should just turn on promiscuous mode so
3509 * that we can at least receive multicast traffic
3510 */
3511 hw->mac.ops.update_mc_addr_list(hw, netdev);
3512 vmolr |= IXGBE_VMOLR_ROMPE;
3513 }
3514 ixgbe_vlan_filter_enable(adapter);
3515 hw->addr_ctrl.user_set_promisc = false;
3516 /*
3517 * Write addresses to available RAR registers, if there is not
3518 * sufficient space to store all the addresses then enable
3519 * unicast promiscuous mode
3520 */
3521 count = ixgbe_write_uc_addr_list(netdev);
3522 if (count < 0) {
3523 fctrl |= IXGBE_FCTRL_UPE;
3524 vmolr |= IXGBE_VMOLR_ROPE;
3525 }
3526 }
3527
3528 if (adapter->num_vfs) {
3529 ixgbe_restore_vf_multicasts(adapter);
3530 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3531 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3532 IXGBE_VMOLR_ROPE);
3533 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3534 }
3535
3536 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3537
3538 if (netdev->features & NETIF_F_HW_VLAN_RX)
3539 ixgbe_vlan_strip_enable(adapter);
3540 else
3541 ixgbe_vlan_strip_disable(adapter);
3542 }
3543
3544 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3545 {
3546 int q_idx;
3547 struct ixgbe_q_vector *q_vector;
3548 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3549
3550 /* legacy and MSI only use one vector */
3551 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3552 q_vectors = 1;
3553
3554 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3555 struct napi_struct *napi;
3556 q_vector = adapter->q_vector[q_idx];
3557 napi = &q_vector->napi;
3558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3559 if (!q_vector->rx.count || !q_vector->tx.count) {
3560 if (q_vector->tx.count == 1)
3561 napi->poll = &ixgbe_clean_txonly;
3562 else if (q_vector->rx.count == 1)
3563 napi->poll = &ixgbe_clean_rxonly;
3564 }
3565 }
3566
3567 napi_enable(napi);
3568 }
3569 }
3570
3571 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3572 {
3573 int q_idx;
3574 struct ixgbe_q_vector *q_vector;
3575 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3576
3577 /* legacy and MSI only use one vector */
3578 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3579 q_vectors = 1;
3580
3581 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3582 q_vector = adapter->q_vector[q_idx];
3583 napi_disable(&q_vector->napi);
3584 }
3585 }
3586
3587 #ifdef CONFIG_IXGBE_DCB
3588 /*
3589 * ixgbe_configure_dcb - Configure DCB hardware
3590 * @adapter: ixgbe adapter struct
3591 *
3592 * This is called by the driver on open to configure the DCB hardware.
3593 * This is also called by the gennetlink interface when reconfiguring
3594 * the DCB state.
3595 */
3596 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3597 {
3598 struct ixgbe_hw *hw = &adapter->hw;
3599 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3600
3601 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 netif_set_gso_max_size(adapter->netdev, 65536);
3604 return;
3605 }
3606
3607 if (hw->mac.type == ixgbe_mac_82598EB)
3608 netif_set_gso_max_size(adapter->netdev, 32768);
3609
3610
3611 /* Enable VLAN tag insert/strip */
3612 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3613
3614 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3615
3616 /* reconfigure the hardware */
3617 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3618 #ifdef IXGBE_FCOE
3619 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3620 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3621 #endif
3622 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3623 DCB_TX_CONFIG);
3624 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3625 DCB_RX_CONFIG);
3626 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3627 } else {
3628 struct net_device *dev = adapter->netdev;
3629
3630 if (adapter->ixgbe_ieee_ets)
3631 dev->dcbnl_ops->ieee_setets(dev,
3632 adapter->ixgbe_ieee_ets);
3633 if (adapter->ixgbe_ieee_pfc)
3634 dev->dcbnl_ops->ieee_setpfc(dev,
3635 adapter->ixgbe_ieee_pfc);
3636 }
3637
3638 /* Enable RSS Hash per TC */
3639 if (hw->mac.type != ixgbe_mac_82598EB) {
3640 int i;
3641 u32 reg = 0;
3642
3643 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3644 u8 msb = 0;
3645 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3646
3647 while (cnt >>= 1)
3648 msb++;
3649
3650 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3651 }
3652 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3653 }
3654 }
3655
3656 #endif
3657
3658 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3659 {
3660 int hdrm = 0;
3661 int num_tc = netdev_get_num_tc(adapter->netdev);
3662 struct ixgbe_hw *hw = &adapter->hw;
3663
3664 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3665 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3666 hdrm = 64 << adapter->fdir_pballoc;
3667
3668 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3669 }
3670
3671 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3672 {
3673 struct ixgbe_hw *hw = &adapter->hw;
3674 struct hlist_node *node, *node2;
3675 struct ixgbe_fdir_filter *filter;
3676
3677 spin_lock(&adapter->fdir_perfect_lock);
3678
3679 if (!hlist_empty(&adapter->fdir_filter_list))
3680 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3681
3682 hlist_for_each_entry_safe(filter, node, node2,
3683 &adapter->fdir_filter_list, fdir_node) {
3684 ixgbe_fdir_write_perfect_filter_82599(hw,
3685 &filter->filter,
3686 filter->sw_idx,
3687 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3688 IXGBE_FDIR_DROP_QUEUE :
3689 adapter->rx_ring[filter->action]->reg_idx);
3690 }
3691
3692 spin_unlock(&adapter->fdir_perfect_lock);
3693 }
3694
3695 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3696 {
3697 struct net_device *netdev = adapter->netdev;
3698 struct ixgbe_hw *hw = &adapter->hw;
3699 int i;
3700
3701 ixgbe_configure_pb(adapter);
3702 #ifdef CONFIG_IXGBE_DCB
3703 ixgbe_configure_dcb(adapter);
3704 #endif
3705
3706 ixgbe_set_rx_mode(netdev);
3707 ixgbe_restore_vlan(adapter);
3708
3709 #ifdef IXGBE_FCOE
3710 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3711 ixgbe_configure_fcoe(adapter);
3712
3713 #endif /* IXGBE_FCOE */
3714 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3715 for (i = 0; i < adapter->num_tx_queues; i++)
3716 adapter->tx_ring[i]->atr_sample_rate =
3717 adapter->atr_sample_rate;
3718 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3719 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3720 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3721 adapter->fdir_pballoc);
3722 ixgbe_fdir_filter_restore(adapter);
3723 }
3724 ixgbe_configure_virtualization(adapter);
3725
3726 ixgbe_configure_tx(adapter);
3727 ixgbe_configure_rx(adapter);
3728 }
3729
3730 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3731 {
3732 switch (hw->phy.type) {
3733 case ixgbe_phy_sfp_avago:
3734 case ixgbe_phy_sfp_ftl:
3735 case ixgbe_phy_sfp_intel:
3736 case ixgbe_phy_sfp_unknown:
3737 case ixgbe_phy_sfp_passive_tyco:
3738 case ixgbe_phy_sfp_passive_unknown:
3739 case ixgbe_phy_sfp_active_unknown:
3740 case ixgbe_phy_sfp_ftl_active:
3741 return true;
3742 default:
3743 return false;
3744 }
3745 }
3746
3747 /**
3748 * ixgbe_sfp_link_config - set up SFP+ link
3749 * @adapter: pointer to private adapter struct
3750 **/
3751 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3752 {
3753 /*
3754 * We are assuming the worst case scenerio here, and that
3755 * is that an SFP was inserted/removed after the reset
3756 * but before SFP detection was enabled. As such the best
3757 * solution is to just start searching as soon as we start
3758 */
3759 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3760 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3761
3762 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3763 }
3764
3765 /**
3766 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3767 * @hw: pointer to private hardware struct
3768 *
3769 * Returns 0 on success, negative on failure
3770 **/
3771 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3772 {
3773 u32 autoneg;
3774 bool negotiation, link_up = false;
3775 u32 ret = IXGBE_ERR_LINK_SETUP;
3776
3777 if (hw->mac.ops.check_link)
3778 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3779
3780 if (ret)
3781 goto link_cfg_out;
3782
3783 autoneg = hw->phy.autoneg_advertised;
3784 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3785 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3786 &negotiation);
3787 if (ret)
3788 goto link_cfg_out;
3789
3790 if (hw->mac.ops.setup_link)
3791 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3792 link_cfg_out:
3793 return ret;
3794 }
3795
3796 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3797 {
3798 struct ixgbe_hw *hw = &adapter->hw;
3799 u32 gpie = 0;
3800
3801 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3802 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3803 IXGBE_GPIE_OCD;
3804 gpie |= IXGBE_GPIE_EIAME;
3805 /*
3806 * use EIAM to auto-mask when MSI-X interrupt is asserted
3807 * this saves a register write for every interrupt
3808 */
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3812 break;
3813 case ixgbe_mac_82599EB:
3814 case ixgbe_mac_X540:
3815 default:
3816 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3817 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3818 break;
3819 }
3820 } else {
3821 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3822 * specifically only auto mask tx and rx interrupts */
3823 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3824 }
3825
3826 /* XXX: to interrupt immediately for EICS writes, enable this */
3827 /* gpie |= IXGBE_GPIE_EIMEN; */
3828
3829 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3830 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3831 gpie |= IXGBE_GPIE_VTMODE_64;
3832 }
3833
3834 /* Enable fan failure interrupt */
3835 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3836 gpie |= IXGBE_SDP1_GPIEN;
3837
3838 if (hw->mac.type == ixgbe_mac_82599EB) {
3839 gpie |= IXGBE_SDP1_GPIEN;
3840 gpie |= IXGBE_SDP2_GPIEN;
3841 }
3842
3843 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3844 }
3845
3846 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3847 {
3848 struct ixgbe_hw *hw = &adapter->hw;
3849 int err;
3850 u32 ctrl_ext;
3851
3852 ixgbe_get_hw_control(adapter);
3853 ixgbe_setup_gpie(adapter);
3854
3855 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3856 ixgbe_configure_msix(adapter);
3857 else
3858 ixgbe_configure_msi_and_legacy(adapter);
3859
3860 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3861 if (hw->mac.ops.enable_tx_laser &&
3862 ((hw->phy.multispeed_fiber) ||
3863 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3864 (hw->mac.type == ixgbe_mac_82599EB))))
3865 hw->mac.ops.enable_tx_laser(hw);
3866
3867 clear_bit(__IXGBE_DOWN, &adapter->state);
3868 ixgbe_napi_enable_all(adapter);
3869
3870 if (ixgbe_is_sfp(hw)) {
3871 ixgbe_sfp_link_config(adapter);
3872 } else {
3873 err = ixgbe_non_sfp_link_config(hw);
3874 if (err)
3875 e_err(probe, "link_config FAILED %d\n", err);
3876 }
3877
3878 /* clear any pending interrupts, may auto mask */
3879 IXGBE_READ_REG(hw, IXGBE_EICR);
3880 ixgbe_irq_enable(adapter, true, true);
3881
3882 /*
3883 * If this adapter has a fan, check to see if we had a failure
3884 * before we enabled the interrupt.
3885 */
3886 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3887 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3888 if (esdp & IXGBE_ESDP_SDP1)
3889 e_crit(drv, "Fan has stopped, replace the adapter\n");
3890 }
3891
3892 /* enable transmits */
3893 netif_tx_start_all_queues(adapter->netdev);
3894
3895 /* bring the link up in the watchdog, this could race with our first
3896 * link up interrupt but shouldn't be a problem */
3897 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3898 adapter->link_check_timeout = jiffies;
3899 mod_timer(&adapter->service_timer, jiffies);
3900
3901 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3902 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3903 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3904 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3905
3906 return 0;
3907 }
3908
3909 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3910 {
3911 WARN_ON(in_interrupt());
3912 /* put off any impending NetWatchDogTimeout */
3913 adapter->netdev->trans_start = jiffies;
3914
3915 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3916 usleep_range(1000, 2000);
3917 ixgbe_down(adapter);
3918 /*
3919 * If SR-IOV enabled then wait a bit before bringing the adapter
3920 * back up to give the VFs time to respond to the reset. The
3921 * two second wait is based upon the watchdog timer cycle in
3922 * the VF driver.
3923 */
3924 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3925 msleep(2000);
3926 ixgbe_up(adapter);
3927 clear_bit(__IXGBE_RESETTING, &adapter->state);
3928 }
3929
3930 int ixgbe_up(struct ixgbe_adapter *adapter)
3931 {
3932 /* hardware has been reset, we need to reload some things */
3933 ixgbe_configure(adapter);
3934
3935 return ixgbe_up_complete(adapter);
3936 }
3937
3938 void ixgbe_reset(struct ixgbe_adapter *adapter)
3939 {
3940 struct ixgbe_hw *hw = &adapter->hw;
3941 int err;
3942
3943 /* lock SFP init bit to prevent race conditions with the watchdog */
3944 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3945 usleep_range(1000, 2000);
3946
3947 /* clear all SFP and link config related flags while holding SFP_INIT */
3948 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3949 IXGBE_FLAG2_SFP_NEEDS_RESET);
3950 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3951
3952 err = hw->mac.ops.init_hw(hw);
3953 switch (err) {
3954 case 0:
3955 case IXGBE_ERR_SFP_NOT_PRESENT:
3956 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3957 break;
3958 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3959 e_dev_err("master disable timed out\n");
3960 break;
3961 case IXGBE_ERR_EEPROM_VERSION:
3962 /* We are running on a pre-production device, log a warning */
3963 e_dev_warn("This device is a pre-production adapter/LOM. "
3964 "Please be aware there may be issuesassociated with "
3965 "your hardware. If you are experiencing problems "
3966 "please contact your Intel or hardware "
3967 "representative who provided you with this "
3968 "hardware.\n");
3969 break;
3970 default:
3971 e_dev_err("Hardware Error: %d\n", err);
3972 }
3973
3974 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3975
3976 /* reprogram the RAR[0] in case user changed it. */
3977 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3978 IXGBE_RAH_AV);
3979 }
3980
3981 /**
3982 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3983 * @rx_ring: ring to free buffers from
3984 **/
3985 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3986 {
3987 struct device *dev = rx_ring->dev;
3988 unsigned long size;
3989 u16 i;
3990
3991 /* ring already cleared, nothing to do */
3992 if (!rx_ring->rx_buffer_info)
3993 return;
3994
3995 /* Free all the Rx ring sk_buffs */
3996 for (i = 0; i < rx_ring->count; i++) {
3997 struct ixgbe_rx_buffer *rx_buffer_info;
3998
3999 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4000 if (rx_buffer_info->dma) {
4001 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4002 rx_ring->rx_buf_len,
4003 DMA_FROM_DEVICE);
4004 rx_buffer_info->dma = 0;
4005 }
4006 if (rx_buffer_info->skb) {
4007 struct sk_buff *skb = rx_buffer_info->skb;
4008 rx_buffer_info->skb = NULL;
4009 do {
4010 struct sk_buff *this = skb;
4011 if (IXGBE_RSC_CB(this)->delay_unmap) {
4012 dma_unmap_single(dev,
4013 IXGBE_RSC_CB(this)->dma,
4014 rx_ring->rx_buf_len,
4015 DMA_FROM_DEVICE);
4016 IXGBE_RSC_CB(this)->dma = 0;
4017 IXGBE_RSC_CB(skb)->delay_unmap = false;
4018 }
4019 skb = skb->prev;
4020 dev_kfree_skb(this);
4021 } while (skb);
4022 }
4023 if (!rx_buffer_info->page)
4024 continue;
4025 if (rx_buffer_info->page_dma) {
4026 dma_unmap_page(dev, rx_buffer_info->page_dma,
4027 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4028 rx_buffer_info->page_dma = 0;
4029 }
4030 put_page(rx_buffer_info->page);
4031 rx_buffer_info->page = NULL;
4032 rx_buffer_info->page_offset = 0;
4033 }
4034
4035 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4036 memset(rx_ring->rx_buffer_info, 0, size);
4037
4038 /* Zero out the descriptor ring */
4039 memset(rx_ring->desc, 0, rx_ring->size);
4040
4041 rx_ring->next_to_clean = 0;
4042 rx_ring->next_to_use = 0;
4043 }
4044
4045 /**
4046 * ixgbe_clean_tx_ring - Free Tx Buffers
4047 * @tx_ring: ring to be cleaned
4048 **/
4049 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4050 {
4051 struct ixgbe_tx_buffer *tx_buffer_info;
4052 unsigned long size;
4053 u16 i;
4054
4055 /* ring already cleared, nothing to do */
4056 if (!tx_ring->tx_buffer_info)
4057 return;
4058
4059 /* Free all the Tx ring sk_buffs */
4060 for (i = 0; i < tx_ring->count; i++) {
4061 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4062 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4063 }
4064
4065 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4066 memset(tx_ring->tx_buffer_info, 0, size);
4067
4068 /* Zero out the descriptor ring */
4069 memset(tx_ring->desc, 0, tx_ring->size);
4070
4071 tx_ring->next_to_use = 0;
4072 tx_ring->next_to_clean = 0;
4073 }
4074
4075 /**
4076 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4077 * @adapter: board private structure
4078 **/
4079 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4080 {
4081 int i;
4082
4083 for (i = 0; i < adapter->num_rx_queues; i++)
4084 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4085 }
4086
4087 /**
4088 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4089 * @adapter: board private structure
4090 **/
4091 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4092 {
4093 int i;
4094
4095 for (i = 0; i < adapter->num_tx_queues; i++)
4096 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4097 }
4098
4099 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4100 {
4101 struct hlist_node *node, *node2;
4102 struct ixgbe_fdir_filter *filter;
4103
4104 spin_lock(&adapter->fdir_perfect_lock);
4105
4106 hlist_for_each_entry_safe(filter, node, node2,
4107 &adapter->fdir_filter_list, fdir_node) {
4108 hlist_del(&filter->fdir_node);
4109 kfree(filter);
4110 }
4111 adapter->fdir_filter_count = 0;
4112
4113 spin_unlock(&adapter->fdir_perfect_lock);
4114 }
4115
4116 void ixgbe_down(struct ixgbe_adapter *adapter)
4117 {
4118 struct net_device *netdev = adapter->netdev;
4119 struct ixgbe_hw *hw = &adapter->hw;
4120 u32 rxctrl;
4121 int i;
4122 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4123
4124 /* signal that we are down to the interrupt handler */
4125 set_bit(__IXGBE_DOWN, &adapter->state);
4126
4127 /* disable receives */
4128 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4129 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4130
4131 /* disable all enabled rx queues */
4132 for (i = 0; i < adapter->num_rx_queues; i++)
4133 /* this call also flushes the previous write */
4134 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4135
4136 usleep_range(10000, 20000);
4137
4138 netif_tx_stop_all_queues(netdev);
4139
4140 /* call carrier off first to avoid false dev_watchdog timeouts */
4141 netif_carrier_off(netdev);
4142 netif_tx_disable(netdev);
4143
4144 ixgbe_irq_disable(adapter);
4145
4146 ixgbe_napi_disable_all(adapter);
4147
4148 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4149 IXGBE_FLAG2_RESET_REQUESTED);
4150 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4151
4152 del_timer_sync(&adapter->service_timer);
4153
4154 /* disable receive for all VFs and wait one second */
4155 if (adapter->num_vfs) {
4156 /* ping all the active vfs to let them know we are going down */
4157 ixgbe_ping_all_vfs(adapter);
4158
4159 /* Disable all VFTE/VFRE TX/RX */
4160 ixgbe_disable_tx_rx(adapter);
4161
4162 /* Mark all the VFs as inactive */
4163 for (i = 0 ; i < adapter->num_vfs; i++)
4164 adapter->vfinfo[i].clear_to_send = 0;
4165 }
4166
4167 /* Cleanup the affinity_hint CPU mask memory and callback */
4168 for (i = 0; i < num_q_vectors; i++) {
4169 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4170 /* clear the affinity_mask in the IRQ descriptor */
4171 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4172 /* release the CPU mask memory */
4173 free_cpumask_var(q_vector->affinity_mask);
4174 }
4175
4176 /* disable transmits in the hardware now that interrupts are off */
4177 for (i = 0; i < adapter->num_tx_queues; i++) {
4178 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4179 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4180 }
4181
4182 /* Disable the Tx DMA engine on 82599 and X540 */
4183 switch (hw->mac.type) {
4184 case ixgbe_mac_82599EB:
4185 case ixgbe_mac_X540:
4186 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4187 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4188 ~IXGBE_DMATXCTL_TE));
4189 break;
4190 default:
4191 break;
4192 }
4193
4194 if (!pci_channel_offline(adapter->pdev))
4195 ixgbe_reset(adapter);
4196
4197 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4198 if (hw->mac.ops.disable_tx_laser &&
4199 ((hw->phy.multispeed_fiber) ||
4200 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4201 (hw->mac.type == ixgbe_mac_82599EB))))
4202 hw->mac.ops.disable_tx_laser(hw);
4203
4204 ixgbe_clean_all_tx_rings(adapter);
4205 ixgbe_clean_all_rx_rings(adapter);
4206
4207 #ifdef CONFIG_IXGBE_DCA
4208 /* since we reset the hardware DCA settings were cleared */
4209 ixgbe_setup_dca(adapter);
4210 #endif
4211 }
4212
4213 /**
4214 * ixgbe_poll - NAPI Rx polling callback
4215 * @napi: structure for representing this polling device
4216 * @budget: how many packets driver is allowed to clean
4217 *
4218 * This function is used for legacy and MSI, NAPI mode
4219 **/
4220 static int ixgbe_poll(struct napi_struct *napi, int budget)
4221 {
4222 struct ixgbe_q_vector *q_vector =
4223 container_of(napi, struct ixgbe_q_vector, napi);
4224 struct ixgbe_adapter *adapter = q_vector->adapter;
4225 int tx_clean_complete, work_done = 0;
4226
4227 #ifdef CONFIG_IXGBE_DCA
4228 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4229 ixgbe_update_dca(q_vector);
4230 #endif
4231
4232 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4233 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4234
4235 if (!tx_clean_complete)
4236 work_done = budget;
4237
4238 /* If budget not fully consumed, exit the polling mode */
4239 if (work_done < budget) {
4240 napi_complete(napi);
4241 if (adapter->rx_itr_setting & 1)
4242 ixgbe_set_itr(q_vector);
4243 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4244 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4245 }
4246 return work_done;
4247 }
4248
4249 /**
4250 * ixgbe_tx_timeout - Respond to a Tx Hang
4251 * @netdev: network interface device structure
4252 **/
4253 static void ixgbe_tx_timeout(struct net_device *netdev)
4254 {
4255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4256
4257 /* Do the reset outside of interrupt context */
4258 ixgbe_tx_timeout_reset(adapter);
4259 }
4260
4261 /**
4262 * ixgbe_set_rss_queues: Allocate queues for RSS
4263 * @adapter: board private structure to initialize
4264 *
4265 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4266 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4267 *
4268 **/
4269 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4270 {
4271 bool ret = false;
4272 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4273
4274 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4275 f->mask = 0xF;
4276 adapter->num_rx_queues = f->indices;
4277 adapter->num_tx_queues = f->indices;
4278 ret = true;
4279 } else {
4280 ret = false;
4281 }
4282
4283 return ret;
4284 }
4285
4286 /**
4287 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4288 * @adapter: board private structure to initialize
4289 *
4290 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4291 * to the original CPU that initiated the Tx session. This runs in addition
4292 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4293 * Rx load across CPUs using RSS.
4294 *
4295 **/
4296 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4297 {
4298 bool ret = false;
4299 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4300
4301 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4302 f_fdir->mask = 0;
4303
4304 /* Flow Director must have RSS enabled */
4305 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4306 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4307 adapter->num_tx_queues = f_fdir->indices;
4308 adapter->num_rx_queues = f_fdir->indices;
4309 ret = true;
4310 } else {
4311 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4312 }
4313 return ret;
4314 }
4315
4316 #ifdef IXGBE_FCOE
4317 /**
4318 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4319 * @adapter: board private structure to initialize
4320 *
4321 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4322 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4323 * rx queues out of the max number of rx queues, instead, it is used as the
4324 * index of the first rx queue used by FCoE.
4325 *
4326 **/
4327 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4328 {
4329 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4330
4331 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4332 return false;
4333
4334 f->indices = min((int)num_online_cpus(), f->indices);
4335
4336 adapter->num_rx_queues = 1;
4337 adapter->num_tx_queues = 1;
4338
4339 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4340 e_info(probe, "FCoE enabled with RSS\n");
4341 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4342 ixgbe_set_fdir_queues(adapter);
4343 else
4344 ixgbe_set_rss_queues(adapter);
4345 }
4346
4347 /* adding FCoE rx rings to the end */
4348 f->mask = adapter->num_rx_queues;
4349 adapter->num_rx_queues += f->indices;
4350 adapter->num_tx_queues += f->indices;
4351
4352 return true;
4353 }
4354 #endif /* IXGBE_FCOE */
4355
4356 /* Artificial max queue cap per traffic class in DCB mode */
4357 #define DCB_QUEUE_CAP 8
4358
4359 #ifdef CONFIG_IXGBE_DCB
4360 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4361 {
4362 int per_tc_q, q, i, offset = 0;
4363 struct net_device *dev = adapter->netdev;
4364 int tcs = netdev_get_num_tc(dev);
4365
4366 if (!tcs)
4367 return false;
4368
4369 /* Map queue offset and counts onto allocated tx queues */
4370 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4371 q = min((int)num_online_cpus(), per_tc_q);
4372
4373 for (i = 0; i < tcs; i++) {
4374 netdev_set_prio_tc_map(dev, i, i);
4375 netdev_set_tc_queue(dev, i, q, offset);
4376 offset += q;
4377 }
4378
4379 adapter->num_tx_queues = q * tcs;
4380 adapter->num_rx_queues = q * tcs;
4381
4382 #ifdef IXGBE_FCOE
4383 /* FCoE enabled queues require special configuration indexed
4384 * by feature specific indices and mask. Here we map FCoE
4385 * indices onto the DCB queue pairs allowing FCoE to own
4386 * configuration later.
4387 */
4388 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4389 int tc;
4390 struct ixgbe_ring_feature *f =
4391 &adapter->ring_feature[RING_F_FCOE];
4392
4393 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4394 f->indices = dev->tc_to_txq[tc].count;
4395 f->mask = dev->tc_to_txq[tc].offset;
4396 }
4397 #endif
4398
4399 return true;
4400 }
4401 #endif
4402
4403 /**
4404 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4405 * @adapter: board private structure to initialize
4406 *
4407 * IOV doesn't actually use anything, so just NAK the
4408 * request for now and let the other queue routines
4409 * figure out what to do.
4410 */
4411 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4412 {
4413 return false;
4414 }
4415
4416 /*
4417 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4418 * @adapter: board private structure to initialize
4419 *
4420 * This is the top level queue allocation routine. The order here is very
4421 * important, starting with the "most" number of features turned on at once,
4422 * and ending with the smallest set of features. This way large combinations
4423 * can be allocated if they're turned on, and smaller combinations are the
4424 * fallthrough conditions.
4425 *
4426 **/
4427 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4428 {
4429 /* Start with base case */
4430 adapter->num_rx_queues = 1;
4431 adapter->num_tx_queues = 1;
4432 adapter->num_rx_pools = adapter->num_rx_queues;
4433 adapter->num_rx_queues_per_pool = 1;
4434
4435 if (ixgbe_set_sriov_queues(adapter))
4436 goto done;
4437
4438 #ifdef CONFIG_IXGBE_DCB
4439 if (ixgbe_set_dcb_queues(adapter))
4440 goto done;
4441
4442 #endif
4443 #ifdef IXGBE_FCOE
4444 if (ixgbe_set_fcoe_queues(adapter))
4445 goto done;
4446
4447 #endif /* IXGBE_FCOE */
4448 if (ixgbe_set_fdir_queues(adapter))
4449 goto done;
4450
4451 if (ixgbe_set_rss_queues(adapter))
4452 goto done;
4453
4454 /* fallback to base case */
4455 adapter->num_rx_queues = 1;
4456 adapter->num_tx_queues = 1;
4457
4458 done:
4459 /* Notify the stack of the (possibly) reduced queue counts. */
4460 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4461 return netif_set_real_num_rx_queues(adapter->netdev,
4462 adapter->num_rx_queues);
4463 }
4464
4465 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4466 int vectors)
4467 {
4468 int err, vector_threshold;
4469
4470 /* We'll want at least 3 (vector_threshold):
4471 * 1) TxQ[0] Cleanup
4472 * 2) RxQ[0] Cleanup
4473 * 3) Other (Link Status Change, etc.)
4474 * 4) TCP Timer (optional)
4475 */
4476 vector_threshold = MIN_MSIX_COUNT;
4477
4478 /* The more we get, the more we will assign to Tx/Rx Cleanup
4479 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4480 * Right now, we simply care about how many we'll get; we'll
4481 * set them up later while requesting irq's.
4482 */
4483 while (vectors >= vector_threshold) {
4484 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4485 vectors);
4486 if (!err) /* Success in acquiring all requested vectors. */
4487 break;
4488 else if (err < 0)
4489 vectors = 0; /* Nasty failure, quit now */
4490 else /* err == number of vectors we should try again with */
4491 vectors = err;
4492 }
4493
4494 if (vectors < vector_threshold) {
4495 /* Can't allocate enough MSI-X interrupts? Oh well.
4496 * This just means we'll go with either a single MSI
4497 * vector or fall back to legacy interrupts.
4498 */
4499 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4500 "Unable to allocate MSI-X interrupts\n");
4501 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4502 kfree(adapter->msix_entries);
4503 adapter->msix_entries = NULL;
4504 } else {
4505 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4506 /*
4507 * Adjust for only the vectors we'll use, which is minimum
4508 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4509 * vectors we were allocated.
4510 */
4511 adapter->num_msix_vectors = min(vectors,
4512 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4513 }
4514 }
4515
4516 /**
4517 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4518 * @adapter: board private structure to initialize
4519 *
4520 * Cache the descriptor ring offsets for RSS to the assigned rings.
4521 *
4522 **/
4523 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4524 {
4525 int i;
4526
4527 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4528 return false;
4529
4530 for (i = 0; i < adapter->num_rx_queues; i++)
4531 adapter->rx_ring[i]->reg_idx = i;
4532 for (i = 0; i < adapter->num_tx_queues; i++)
4533 adapter->tx_ring[i]->reg_idx = i;
4534
4535 return true;
4536 }
4537
4538 #ifdef CONFIG_IXGBE_DCB
4539
4540 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4541 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4542 unsigned int *tx, unsigned int *rx)
4543 {
4544 struct net_device *dev = adapter->netdev;
4545 struct ixgbe_hw *hw = &adapter->hw;
4546 u8 num_tcs = netdev_get_num_tc(dev);
4547
4548 *tx = 0;
4549 *rx = 0;
4550
4551 switch (hw->mac.type) {
4552 case ixgbe_mac_82598EB:
4553 *tx = tc << 2;
4554 *rx = tc << 3;
4555 break;
4556 case ixgbe_mac_82599EB:
4557 case ixgbe_mac_X540:
4558 if (num_tcs == 8) {
4559 if (tc < 3) {
4560 *tx = tc << 5;
4561 *rx = tc << 4;
4562 } else if (tc < 5) {
4563 *tx = ((tc + 2) << 4);
4564 *rx = tc << 4;
4565 } else if (tc < num_tcs) {
4566 *tx = ((tc + 8) << 3);
4567 *rx = tc << 4;
4568 }
4569 } else if (num_tcs == 4) {
4570 *rx = tc << 5;
4571 switch (tc) {
4572 case 0:
4573 *tx = 0;
4574 break;
4575 case 1:
4576 *tx = 64;
4577 break;
4578 case 2:
4579 *tx = 96;
4580 break;
4581 case 3:
4582 *tx = 112;
4583 break;
4584 default:
4585 break;
4586 }
4587 }
4588 break;
4589 default:
4590 break;
4591 }
4592 }
4593
4594 /**
4595 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4596 * @adapter: board private structure to initialize
4597 *
4598 * Cache the descriptor ring offsets for DCB to the assigned rings.
4599 *
4600 **/
4601 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4602 {
4603 struct net_device *dev = adapter->netdev;
4604 int i, j, k;
4605 u8 num_tcs = netdev_get_num_tc(dev);
4606
4607 if (!num_tcs)
4608 return false;
4609
4610 for (i = 0, k = 0; i < num_tcs; i++) {
4611 unsigned int tx_s, rx_s;
4612 u16 count = dev->tc_to_txq[i].count;
4613
4614 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4615 for (j = 0; j < count; j++, k++) {
4616 adapter->tx_ring[k]->reg_idx = tx_s + j;
4617 adapter->rx_ring[k]->reg_idx = rx_s + j;
4618 adapter->tx_ring[k]->dcb_tc = i;
4619 adapter->rx_ring[k]->dcb_tc = i;
4620 }
4621 }
4622
4623 return true;
4624 }
4625 #endif
4626
4627 /**
4628 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4629 * @adapter: board private structure to initialize
4630 *
4631 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4632 *
4633 **/
4634 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4635 {
4636 int i;
4637 bool ret = false;
4638
4639 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4640 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4641 for (i = 0; i < adapter->num_rx_queues; i++)
4642 adapter->rx_ring[i]->reg_idx = i;
4643 for (i = 0; i < adapter->num_tx_queues; i++)
4644 adapter->tx_ring[i]->reg_idx = i;
4645 ret = true;
4646 }
4647
4648 return ret;
4649 }
4650
4651 #ifdef IXGBE_FCOE
4652 /**
4653 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4654 * @adapter: board private structure to initialize
4655 *
4656 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4657 *
4658 */
4659 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4660 {
4661 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4662 int i;
4663 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4664
4665 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4666 return false;
4667
4668 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4669 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4670 ixgbe_cache_ring_fdir(adapter);
4671 else
4672 ixgbe_cache_ring_rss(adapter);
4673
4674 fcoe_rx_i = f->mask;
4675 fcoe_tx_i = f->mask;
4676 }
4677 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4678 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4679 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4680 }
4681 return true;
4682 }
4683
4684 #endif /* IXGBE_FCOE */
4685 /**
4686 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4687 * @adapter: board private structure to initialize
4688 *
4689 * SR-IOV doesn't use any descriptor rings but changes the default if
4690 * no other mapping is used.
4691 *
4692 */
4693 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4694 {
4695 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4696 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4697 if (adapter->num_vfs)
4698 return true;
4699 else
4700 return false;
4701 }
4702
4703 /**
4704 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4705 * @adapter: board private structure to initialize
4706 *
4707 * Once we know the feature-set enabled for the device, we'll cache
4708 * the register offset the descriptor ring is assigned to.
4709 *
4710 * Note, the order the various feature calls is important. It must start with
4711 * the "most" features enabled at the same time, then trickle down to the
4712 * least amount of features turned on at once.
4713 **/
4714 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4715 {
4716 /* start with default case */
4717 adapter->rx_ring[0]->reg_idx = 0;
4718 adapter->tx_ring[0]->reg_idx = 0;
4719
4720 if (ixgbe_cache_ring_sriov(adapter))
4721 return;
4722
4723 #ifdef CONFIG_IXGBE_DCB
4724 if (ixgbe_cache_ring_dcb(adapter))
4725 return;
4726 #endif
4727
4728 #ifdef IXGBE_FCOE
4729 if (ixgbe_cache_ring_fcoe(adapter))
4730 return;
4731 #endif /* IXGBE_FCOE */
4732
4733 if (ixgbe_cache_ring_fdir(adapter))
4734 return;
4735
4736 if (ixgbe_cache_ring_rss(adapter))
4737 return;
4738 }
4739
4740 /**
4741 * ixgbe_alloc_queues - Allocate memory for all rings
4742 * @adapter: board private structure to initialize
4743 *
4744 * We allocate one ring per queue at run-time since we don't know the
4745 * number of queues at compile-time. The polling_netdev array is
4746 * intended for Multiqueue, but should work fine with a single queue.
4747 **/
4748 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4749 {
4750 int rx = 0, tx = 0, nid = adapter->node;
4751
4752 if (nid < 0 || !node_online(nid))
4753 nid = first_online_node;
4754
4755 for (; tx < adapter->num_tx_queues; tx++) {
4756 struct ixgbe_ring *ring;
4757
4758 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4759 if (!ring)
4760 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4761 if (!ring)
4762 goto err_allocation;
4763 ring->count = adapter->tx_ring_count;
4764 ring->queue_index = tx;
4765 ring->numa_node = nid;
4766 ring->dev = &adapter->pdev->dev;
4767 ring->netdev = adapter->netdev;
4768
4769 adapter->tx_ring[tx] = ring;
4770 }
4771
4772 for (; rx < adapter->num_rx_queues; rx++) {
4773 struct ixgbe_ring *ring;
4774
4775 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4776 if (!ring)
4777 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4778 if (!ring)
4779 goto err_allocation;
4780 ring->count = adapter->rx_ring_count;
4781 ring->queue_index = rx;
4782 ring->numa_node = nid;
4783 ring->dev = &adapter->pdev->dev;
4784 ring->netdev = adapter->netdev;
4785
4786 adapter->rx_ring[rx] = ring;
4787 }
4788
4789 ixgbe_cache_ring_register(adapter);
4790
4791 return 0;
4792
4793 err_allocation:
4794 while (tx)
4795 kfree(adapter->tx_ring[--tx]);
4796
4797 while (rx)
4798 kfree(adapter->rx_ring[--rx]);
4799 return -ENOMEM;
4800 }
4801
4802 /**
4803 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4804 * @adapter: board private structure to initialize
4805 *
4806 * Attempt to configure the interrupts using the best available
4807 * capabilities of the hardware and the kernel.
4808 **/
4809 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4810 {
4811 struct ixgbe_hw *hw = &adapter->hw;
4812 int err = 0;
4813 int vector, v_budget;
4814
4815 /*
4816 * It's easy to be greedy for MSI-X vectors, but it really
4817 * doesn't do us much good if we have a lot more vectors
4818 * than CPU's. So let's be conservative and only ask for
4819 * (roughly) the same number of vectors as there are CPU's.
4820 */
4821 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4822 (int)num_online_cpus()) + NON_Q_VECTORS;
4823
4824 /*
4825 * At the same time, hardware can only support a maximum of
4826 * hw.mac->max_msix_vectors vectors. With features
4827 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4828 * descriptor queues supported by our device. Thus, we cap it off in
4829 * those rare cases where the cpu count also exceeds our vector limit.
4830 */
4831 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4832
4833 /* A failure in MSI-X entry allocation isn't fatal, but it does
4834 * mean we disable MSI-X capabilities of the adapter. */
4835 adapter->msix_entries = kcalloc(v_budget,
4836 sizeof(struct msix_entry), GFP_KERNEL);
4837 if (adapter->msix_entries) {
4838 for (vector = 0; vector < v_budget; vector++)
4839 adapter->msix_entries[vector].entry = vector;
4840
4841 ixgbe_acquire_msix_vectors(adapter, v_budget);
4842
4843 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4844 goto out;
4845 }
4846
4847 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4848 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4849 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4850 e_err(probe,
4851 "ATR is not supported while multiple "
4852 "queues are disabled. Disabling Flow Director\n");
4853 }
4854 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4855 adapter->atr_sample_rate = 0;
4856 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4857 ixgbe_disable_sriov(adapter);
4858
4859 err = ixgbe_set_num_queues(adapter);
4860 if (err)
4861 return err;
4862
4863 err = pci_enable_msi(adapter->pdev);
4864 if (!err) {
4865 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4866 } else {
4867 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4868 "Unable to allocate MSI interrupt, "
4869 "falling back to legacy. Error: %d\n", err);
4870 /* reset err */
4871 err = 0;
4872 }
4873
4874 out:
4875 return err;
4876 }
4877
4878 /**
4879 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4880 * @adapter: board private structure to initialize
4881 *
4882 * We allocate one q_vector per queue interrupt. If allocation fails we
4883 * return -ENOMEM.
4884 **/
4885 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4886 {
4887 int q_idx, num_q_vectors;
4888 struct ixgbe_q_vector *q_vector;
4889 int (*poll)(struct napi_struct *, int);
4890
4891 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4892 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4893 poll = &ixgbe_clean_rxtx_many;
4894 } else {
4895 num_q_vectors = 1;
4896 poll = &ixgbe_poll;
4897 }
4898
4899 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4900 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4901 GFP_KERNEL, adapter->node);
4902 if (!q_vector)
4903 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4904 GFP_KERNEL);
4905 if (!q_vector)
4906 goto err_out;
4907 q_vector->adapter = adapter;
4908 if (q_vector->tx.count && !q_vector->rx.count)
4909 q_vector->eitr = adapter->tx_eitr_param;
4910 else
4911 q_vector->eitr = adapter->rx_eitr_param;
4912 q_vector->v_idx = q_idx;
4913 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4914 adapter->q_vector[q_idx] = q_vector;
4915 }
4916
4917 return 0;
4918
4919 err_out:
4920 while (q_idx) {
4921 q_idx--;
4922 q_vector = adapter->q_vector[q_idx];
4923 netif_napi_del(&q_vector->napi);
4924 kfree(q_vector);
4925 adapter->q_vector[q_idx] = NULL;
4926 }
4927 return -ENOMEM;
4928 }
4929
4930 /**
4931 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4932 * @adapter: board private structure to initialize
4933 *
4934 * This function frees the memory allocated to the q_vectors. In addition if
4935 * NAPI is enabled it will delete any references to the NAPI struct prior
4936 * to freeing the q_vector.
4937 **/
4938 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4939 {
4940 int q_idx, num_q_vectors;
4941
4942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4944 else
4945 num_q_vectors = 1;
4946
4947 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4948 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4949 adapter->q_vector[q_idx] = NULL;
4950 netif_napi_del(&q_vector->napi);
4951 kfree(q_vector);
4952 }
4953 }
4954
4955 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4956 {
4957 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4958 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4959 pci_disable_msix(adapter->pdev);
4960 kfree(adapter->msix_entries);
4961 adapter->msix_entries = NULL;
4962 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4963 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4964 pci_disable_msi(adapter->pdev);
4965 }
4966 }
4967
4968 /**
4969 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4970 * @adapter: board private structure to initialize
4971 *
4972 * We determine which interrupt scheme to use based on...
4973 * - Kernel support (MSI, MSI-X)
4974 * - which can be user-defined (via MODULE_PARAM)
4975 * - Hardware queue count (num_*_queues)
4976 * - defined by miscellaneous hardware support/features (RSS, etc.)
4977 **/
4978 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4979 {
4980 int err;
4981
4982 /* Number of supported queues */
4983 err = ixgbe_set_num_queues(adapter);
4984 if (err)
4985 return err;
4986
4987 err = ixgbe_set_interrupt_capability(adapter);
4988 if (err) {
4989 e_dev_err("Unable to setup interrupt capabilities\n");
4990 goto err_set_interrupt;
4991 }
4992
4993 err = ixgbe_alloc_q_vectors(adapter);
4994 if (err) {
4995 e_dev_err("Unable to allocate memory for queue vectors\n");
4996 goto err_alloc_q_vectors;
4997 }
4998
4999 err = ixgbe_alloc_queues(adapter);
5000 if (err) {
5001 e_dev_err("Unable to allocate memory for queues\n");
5002 goto err_alloc_queues;
5003 }
5004
5005 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5006 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5007 adapter->num_rx_queues, adapter->num_tx_queues);
5008
5009 set_bit(__IXGBE_DOWN, &adapter->state);
5010
5011 return 0;
5012
5013 err_alloc_queues:
5014 ixgbe_free_q_vectors(adapter);
5015 err_alloc_q_vectors:
5016 ixgbe_reset_interrupt_capability(adapter);
5017 err_set_interrupt:
5018 return err;
5019 }
5020
5021 /**
5022 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5023 * @adapter: board private structure to clear interrupt scheme on
5024 *
5025 * We go through and clear interrupt specific resources and reset the structure
5026 * to pre-load conditions
5027 **/
5028 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5029 {
5030 int i;
5031
5032 for (i = 0; i < adapter->num_tx_queues; i++) {
5033 kfree(adapter->tx_ring[i]);
5034 adapter->tx_ring[i] = NULL;
5035 }
5036 for (i = 0; i < adapter->num_rx_queues; i++) {
5037 struct ixgbe_ring *ring = adapter->rx_ring[i];
5038
5039 /* ixgbe_get_stats64() might access this ring, we must wait
5040 * a grace period before freeing it.
5041 */
5042 kfree_rcu(ring, rcu);
5043 adapter->rx_ring[i] = NULL;
5044 }
5045
5046 adapter->num_tx_queues = 0;
5047 adapter->num_rx_queues = 0;
5048
5049 ixgbe_free_q_vectors(adapter);
5050 ixgbe_reset_interrupt_capability(adapter);
5051 }
5052
5053 /**
5054 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5055 * @adapter: board private structure to initialize
5056 *
5057 * ixgbe_sw_init initializes the Adapter private data structure.
5058 * Fields are initialized based on PCI device information and
5059 * OS network device settings (MTU size).
5060 **/
5061 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5062 {
5063 struct ixgbe_hw *hw = &adapter->hw;
5064 struct pci_dev *pdev = adapter->pdev;
5065 struct net_device *dev = adapter->netdev;
5066 unsigned int rss;
5067 #ifdef CONFIG_IXGBE_DCB
5068 int j;
5069 struct tc_configuration *tc;
5070 #endif
5071 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5072
5073 /* PCI config space info */
5074
5075 hw->vendor_id = pdev->vendor;
5076 hw->device_id = pdev->device;
5077 hw->revision_id = pdev->revision;
5078 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5079 hw->subsystem_device_id = pdev->subsystem_device;
5080
5081 /* Set capability flags */
5082 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5083 adapter->ring_feature[RING_F_RSS].indices = rss;
5084 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5085 switch (hw->mac.type) {
5086 case ixgbe_mac_82598EB:
5087 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5088 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5089 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5090 break;
5091 case ixgbe_mac_82599EB:
5092 case ixgbe_mac_X540:
5093 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5094 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5095 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5096 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5097 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5098 /* Flow Director hash filters enabled */
5099 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5100 adapter->atr_sample_rate = 20;
5101 adapter->ring_feature[RING_F_FDIR].indices =
5102 IXGBE_MAX_FDIR_INDICES;
5103 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5104 #ifdef IXGBE_FCOE
5105 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5106 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5107 adapter->ring_feature[RING_F_FCOE].indices = 0;
5108 #ifdef CONFIG_IXGBE_DCB
5109 /* Default traffic class to use for FCoE */
5110 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5111 #endif
5112 #endif /* IXGBE_FCOE */
5113 break;
5114 default:
5115 break;
5116 }
5117
5118 /* n-tuple support exists, always init our spinlock */
5119 spin_lock_init(&adapter->fdir_perfect_lock);
5120
5121 #ifdef CONFIG_IXGBE_DCB
5122 /* Configure DCB traffic classes */
5123 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5124 tc = &adapter->dcb_cfg.tc_config[j];
5125 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5126 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5127 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5128 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5129 tc->dcb_pfc = pfc_disabled;
5130 }
5131 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5132 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5133 adapter->dcb_cfg.pfc_mode_enable = false;
5134 adapter->dcb_set_bitmap = 0x00;
5135 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5136 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5137 MAX_TRAFFIC_CLASS);
5138
5139 #endif
5140
5141 /* default flow control settings */
5142 hw->fc.requested_mode = ixgbe_fc_full;
5143 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5144 #ifdef CONFIG_DCB
5145 adapter->last_lfc_mode = hw->fc.current_mode;
5146 #endif
5147 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5148 hw->fc.low_water = FC_LOW_WATER(max_frame);
5149 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5150 hw->fc.send_xon = true;
5151 hw->fc.disable_fc_autoneg = false;
5152
5153 /* enable itr by default in dynamic mode */
5154 adapter->rx_itr_setting = 1;
5155 adapter->rx_eitr_param = 20000;
5156 adapter->tx_itr_setting = 1;
5157 adapter->tx_eitr_param = 10000;
5158
5159 /* set defaults for eitr in MegaBytes */
5160 adapter->eitr_low = 10;
5161 adapter->eitr_high = 20;
5162
5163 /* set default ring sizes */
5164 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5165 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5166
5167 /* set default work limits */
5168 adapter->tx_work_limit = adapter->tx_ring_count;
5169
5170 /* initialize eeprom parameters */
5171 if (ixgbe_init_eeprom_params_generic(hw)) {
5172 e_dev_err("EEPROM initialization failed\n");
5173 return -EIO;
5174 }
5175
5176 /* enable rx csum by default */
5177 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5178
5179 /* get assigned NUMA node */
5180 adapter->node = dev_to_node(&pdev->dev);
5181
5182 set_bit(__IXGBE_DOWN, &adapter->state);
5183
5184 return 0;
5185 }
5186
5187 /**
5188 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5189 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5190 *
5191 * Return 0 on success, negative on failure
5192 **/
5193 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5194 {
5195 struct device *dev = tx_ring->dev;
5196 int size;
5197
5198 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5199 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5200 if (!tx_ring->tx_buffer_info)
5201 tx_ring->tx_buffer_info = vzalloc(size);
5202 if (!tx_ring->tx_buffer_info)
5203 goto err;
5204
5205 /* round up to nearest 4K */
5206 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5207 tx_ring->size = ALIGN(tx_ring->size, 4096);
5208
5209 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5210 &tx_ring->dma, GFP_KERNEL);
5211 if (!tx_ring->desc)
5212 goto err;
5213
5214 tx_ring->next_to_use = 0;
5215 tx_ring->next_to_clean = 0;
5216 return 0;
5217
5218 err:
5219 vfree(tx_ring->tx_buffer_info);
5220 tx_ring->tx_buffer_info = NULL;
5221 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5222 return -ENOMEM;
5223 }
5224
5225 /**
5226 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5227 * @adapter: board private structure
5228 *
5229 * If this function returns with an error, then it's possible one or
5230 * more of the rings is populated (while the rest are not). It is the
5231 * callers duty to clean those orphaned rings.
5232 *
5233 * Return 0 on success, negative on failure
5234 **/
5235 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5236 {
5237 int i, err = 0;
5238
5239 for (i = 0; i < adapter->num_tx_queues; i++) {
5240 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5241 if (!err)
5242 continue;
5243 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5244 break;
5245 }
5246
5247 return err;
5248 }
5249
5250 /**
5251 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5252 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5253 *
5254 * Returns 0 on success, negative on failure
5255 **/
5256 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5257 {
5258 struct device *dev = rx_ring->dev;
5259 int size;
5260
5261 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5262 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5263 if (!rx_ring->rx_buffer_info)
5264 rx_ring->rx_buffer_info = vzalloc(size);
5265 if (!rx_ring->rx_buffer_info)
5266 goto err;
5267
5268 /* Round up to nearest 4K */
5269 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5270 rx_ring->size = ALIGN(rx_ring->size, 4096);
5271
5272 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5273 &rx_ring->dma, GFP_KERNEL);
5274
5275 if (!rx_ring->desc)
5276 goto err;
5277
5278 rx_ring->next_to_clean = 0;
5279 rx_ring->next_to_use = 0;
5280
5281 return 0;
5282 err:
5283 vfree(rx_ring->rx_buffer_info);
5284 rx_ring->rx_buffer_info = NULL;
5285 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5286 return -ENOMEM;
5287 }
5288
5289 /**
5290 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5291 * @adapter: board private structure
5292 *
5293 * If this function returns with an error, then it's possible one or
5294 * more of the rings is populated (while the rest are not). It is the
5295 * callers duty to clean those orphaned rings.
5296 *
5297 * Return 0 on success, negative on failure
5298 **/
5299 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5300 {
5301 int i, err = 0;
5302
5303 for (i = 0; i < adapter->num_rx_queues; i++) {
5304 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5305 if (!err)
5306 continue;
5307 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5308 break;
5309 }
5310
5311 return err;
5312 }
5313
5314 /**
5315 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5316 * @tx_ring: Tx descriptor ring for a specific queue
5317 *
5318 * Free all transmit software resources
5319 **/
5320 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5321 {
5322 ixgbe_clean_tx_ring(tx_ring);
5323
5324 vfree(tx_ring->tx_buffer_info);
5325 tx_ring->tx_buffer_info = NULL;
5326
5327 /* if not set, then don't free */
5328 if (!tx_ring->desc)
5329 return;
5330
5331 dma_free_coherent(tx_ring->dev, tx_ring->size,
5332 tx_ring->desc, tx_ring->dma);
5333
5334 tx_ring->desc = NULL;
5335 }
5336
5337 /**
5338 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5339 * @adapter: board private structure
5340 *
5341 * Free all transmit software resources
5342 **/
5343 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5344 {
5345 int i;
5346
5347 for (i = 0; i < adapter->num_tx_queues; i++)
5348 if (adapter->tx_ring[i]->desc)
5349 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5350 }
5351
5352 /**
5353 * ixgbe_free_rx_resources - Free Rx Resources
5354 * @rx_ring: ring to clean the resources from
5355 *
5356 * Free all receive software resources
5357 **/
5358 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5359 {
5360 ixgbe_clean_rx_ring(rx_ring);
5361
5362 vfree(rx_ring->rx_buffer_info);
5363 rx_ring->rx_buffer_info = NULL;
5364
5365 /* if not set, then don't free */
5366 if (!rx_ring->desc)
5367 return;
5368
5369 dma_free_coherent(rx_ring->dev, rx_ring->size,
5370 rx_ring->desc, rx_ring->dma);
5371
5372 rx_ring->desc = NULL;
5373 }
5374
5375 /**
5376 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5377 * @adapter: board private structure
5378 *
5379 * Free all receive software resources
5380 **/
5381 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5382 {
5383 int i;
5384
5385 for (i = 0; i < adapter->num_rx_queues; i++)
5386 if (adapter->rx_ring[i]->desc)
5387 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5388 }
5389
5390 /**
5391 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5392 * @netdev: network interface device structure
5393 * @new_mtu: new value for maximum frame size
5394 *
5395 * Returns 0 on success, negative on failure
5396 **/
5397 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5398 {
5399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5400 struct ixgbe_hw *hw = &adapter->hw;
5401 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5402
5403 /* MTU < 68 is an error and causes problems on some kernels */
5404 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5405 hw->mac.type != ixgbe_mac_X540) {
5406 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5407 return -EINVAL;
5408 } else {
5409 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5410 return -EINVAL;
5411 }
5412
5413 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5414 /* must set new MTU before calling down or up */
5415 netdev->mtu = new_mtu;
5416
5417 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5418 hw->fc.low_water = FC_LOW_WATER(max_frame);
5419
5420 if (netif_running(netdev))
5421 ixgbe_reinit_locked(adapter);
5422
5423 return 0;
5424 }
5425
5426 /**
5427 * ixgbe_open - Called when a network interface is made active
5428 * @netdev: network interface device structure
5429 *
5430 * Returns 0 on success, negative value on failure
5431 *
5432 * The open entry point is called when a network interface is made
5433 * active by the system (IFF_UP). At this point all resources needed
5434 * for transmit and receive operations are allocated, the interrupt
5435 * handler is registered with the OS, the watchdog timer is started,
5436 * and the stack is notified that the interface is ready.
5437 **/
5438 static int ixgbe_open(struct net_device *netdev)
5439 {
5440 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5441 int err;
5442
5443 /* disallow open during test */
5444 if (test_bit(__IXGBE_TESTING, &adapter->state))
5445 return -EBUSY;
5446
5447 netif_carrier_off(netdev);
5448
5449 /* allocate transmit descriptors */
5450 err = ixgbe_setup_all_tx_resources(adapter);
5451 if (err)
5452 goto err_setup_tx;
5453
5454 /* allocate receive descriptors */
5455 err = ixgbe_setup_all_rx_resources(adapter);
5456 if (err)
5457 goto err_setup_rx;
5458
5459 ixgbe_configure(adapter);
5460
5461 err = ixgbe_request_irq(adapter);
5462 if (err)
5463 goto err_req_irq;
5464
5465 err = ixgbe_up_complete(adapter);
5466 if (err)
5467 goto err_up;
5468
5469 netif_tx_start_all_queues(netdev);
5470
5471 return 0;
5472
5473 err_up:
5474 ixgbe_release_hw_control(adapter);
5475 ixgbe_free_irq(adapter);
5476 err_req_irq:
5477 err_setup_rx:
5478 ixgbe_free_all_rx_resources(adapter);
5479 err_setup_tx:
5480 ixgbe_free_all_tx_resources(adapter);
5481 ixgbe_reset(adapter);
5482
5483 return err;
5484 }
5485
5486 /**
5487 * ixgbe_close - Disables a network interface
5488 * @netdev: network interface device structure
5489 *
5490 * Returns 0, this is not allowed to fail
5491 *
5492 * The close entry point is called when an interface is de-activated
5493 * by the OS. The hardware is still under the drivers control, but
5494 * needs to be disabled. A global MAC reset is issued to stop the
5495 * hardware, and all transmit and receive resources are freed.
5496 **/
5497 static int ixgbe_close(struct net_device *netdev)
5498 {
5499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5500
5501 ixgbe_down(adapter);
5502 ixgbe_free_irq(adapter);
5503
5504 ixgbe_fdir_filter_exit(adapter);
5505
5506 ixgbe_free_all_tx_resources(adapter);
5507 ixgbe_free_all_rx_resources(adapter);
5508
5509 ixgbe_release_hw_control(adapter);
5510
5511 return 0;
5512 }
5513
5514 #ifdef CONFIG_PM
5515 static int ixgbe_resume(struct pci_dev *pdev)
5516 {
5517 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5518 struct net_device *netdev = adapter->netdev;
5519 u32 err;
5520
5521 pci_set_power_state(pdev, PCI_D0);
5522 pci_restore_state(pdev);
5523 /*
5524 * pci_restore_state clears dev->state_saved so call
5525 * pci_save_state to restore it.
5526 */
5527 pci_save_state(pdev);
5528
5529 err = pci_enable_device_mem(pdev);
5530 if (err) {
5531 e_dev_err("Cannot enable PCI device from suspend\n");
5532 return err;
5533 }
5534 pci_set_master(pdev);
5535
5536 pci_wake_from_d3(pdev, false);
5537
5538 err = ixgbe_init_interrupt_scheme(adapter);
5539 if (err) {
5540 e_dev_err("Cannot initialize interrupts for device\n");
5541 return err;
5542 }
5543
5544 ixgbe_reset(adapter);
5545
5546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5547
5548 if (netif_running(netdev)) {
5549 err = ixgbe_open(netdev);
5550 if (err)
5551 return err;
5552 }
5553
5554 netif_device_attach(netdev);
5555
5556 return 0;
5557 }
5558 #endif /* CONFIG_PM */
5559
5560 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5561 {
5562 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5563 struct net_device *netdev = adapter->netdev;
5564 struct ixgbe_hw *hw = &adapter->hw;
5565 u32 ctrl, fctrl;
5566 u32 wufc = adapter->wol;
5567 #ifdef CONFIG_PM
5568 int retval = 0;
5569 #endif
5570
5571 netif_device_detach(netdev);
5572
5573 if (netif_running(netdev)) {
5574 ixgbe_down(adapter);
5575 ixgbe_free_irq(adapter);
5576 ixgbe_free_all_tx_resources(adapter);
5577 ixgbe_free_all_rx_resources(adapter);
5578 }
5579
5580 ixgbe_clear_interrupt_scheme(adapter);
5581 #ifdef CONFIG_DCB
5582 kfree(adapter->ixgbe_ieee_pfc);
5583 kfree(adapter->ixgbe_ieee_ets);
5584 #endif
5585
5586 #ifdef CONFIG_PM
5587 retval = pci_save_state(pdev);
5588 if (retval)
5589 return retval;
5590
5591 #endif
5592 if (wufc) {
5593 ixgbe_set_rx_mode(netdev);
5594
5595 /* turn on all-multi mode if wake on multicast is enabled */
5596 if (wufc & IXGBE_WUFC_MC) {
5597 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5598 fctrl |= IXGBE_FCTRL_MPE;
5599 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5600 }
5601
5602 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5603 ctrl |= IXGBE_CTRL_GIO_DIS;
5604 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5605
5606 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5607 } else {
5608 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5609 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5610 }
5611
5612 switch (hw->mac.type) {
5613 case ixgbe_mac_82598EB:
5614 pci_wake_from_d3(pdev, false);
5615 break;
5616 case ixgbe_mac_82599EB:
5617 case ixgbe_mac_X540:
5618 pci_wake_from_d3(pdev, !!wufc);
5619 break;
5620 default:
5621 break;
5622 }
5623
5624 *enable_wake = !!wufc;
5625
5626 ixgbe_release_hw_control(adapter);
5627
5628 pci_disable_device(pdev);
5629
5630 return 0;
5631 }
5632
5633 #ifdef CONFIG_PM
5634 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5635 {
5636 int retval;
5637 bool wake;
5638
5639 retval = __ixgbe_shutdown(pdev, &wake);
5640 if (retval)
5641 return retval;
5642
5643 if (wake) {
5644 pci_prepare_to_sleep(pdev);
5645 } else {
5646 pci_wake_from_d3(pdev, false);
5647 pci_set_power_state(pdev, PCI_D3hot);
5648 }
5649
5650 return 0;
5651 }
5652 #endif /* CONFIG_PM */
5653
5654 static void ixgbe_shutdown(struct pci_dev *pdev)
5655 {
5656 bool wake;
5657
5658 __ixgbe_shutdown(pdev, &wake);
5659
5660 if (system_state == SYSTEM_POWER_OFF) {
5661 pci_wake_from_d3(pdev, wake);
5662 pci_set_power_state(pdev, PCI_D3hot);
5663 }
5664 }
5665
5666 /**
5667 * ixgbe_update_stats - Update the board statistics counters.
5668 * @adapter: board private structure
5669 **/
5670 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5671 {
5672 struct net_device *netdev = adapter->netdev;
5673 struct ixgbe_hw *hw = &adapter->hw;
5674 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5675 u64 total_mpc = 0;
5676 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5677 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5678 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5679 u64 bytes = 0, packets = 0;
5680
5681 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5682 test_bit(__IXGBE_RESETTING, &adapter->state))
5683 return;
5684
5685 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5686 u64 rsc_count = 0;
5687 u64 rsc_flush = 0;
5688 for (i = 0; i < 16; i++)
5689 adapter->hw_rx_no_dma_resources +=
5690 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5691 for (i = 0; i < adapter->num_rx_queues; i++) {
5692 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5693 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5694 }
5695 adapter->rsc_total_count = rsc_count;
5696 adapter->rsc_total_flush = rsc_flush;
5697 }
5698
5699 for (i = 0; i < adapter->num_rx_queues; i++) {
5700 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5701 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5702 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5703 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5704 bytes += rx_ring->stats.bytes;
5705 packets += rx_ring->stats.packets;
5706 }
5707 adapter->non_eop_descs = non_eop_descs;
5708 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5709 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5710 netdev->stats.rx_bytes = bytes;
5711 netdev->stats.rx_packets = packets;
5712
5713 bytes = 0;
5714 packets = 0;
5715 /* gather some stats to the adapter struct that are per queue */
5716 for (i = 0; i < adapter->num_tx_queues; i++) {
5717 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5718 restart_queue += tx_ring->tx_stats.restart_queue;
5719 tx_busy += tx_ring->tx_stats.tx_busy;
5720 bytes += tx_ring->stats.bytes;
5721 packets += tx_ring->stats.packets;
5722 }
5723 adapter->restart_queue = restart_queue;
5724 adapter->tx_busy = tx_busy;
5725 netdev->stats.tx_bytes = bytes;
5726 netdev->stats.tx_packets = packets;
5727
5728 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5729 for (i = 0; i < 8; i++) {
5730 /* for packet buffers not used, the register should read 0 */
5731 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5732 missed_rx += mpc;
5733 hwstats->mpc[i] += mpc;
5734 total_mpc += hwstats->mpc[i];
5735 if (hw->mac.type == ixgbe_mac_82598EB)
5736 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5737 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5738 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5739 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5740 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5741 switch (hw->mac.type) {
5742 case ixgbe_mac_82598EB:
5743 hwstats->pxonrxc[i] +=
5744 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5745 break;
5746 case ixgbe_mac_82599EB:
5747 case ixgbe_mac_X540:
5748 hwstats->pxonrxc[i] +=
5749 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5750 break;
5751 default:
5752 break;
5753 }
5754 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5755 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5756 }
5757 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5758 /* work around hardware counting issue */
5759 hwstats->gprc -= missed_rx;
5760
5761 ixgbe_update_xoff_received(adapter);
5762
5763 /* 82598 hardware only has a 32 bit counter in the high register */
5764 switch (hw->mac.type) {
5765 case ixgbe_mac_82598EB:
5766 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5767 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5768 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5769 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5770 break;
5771 case ixgbe_mac_X540:
5772 /* OS2BMC stats are X540 only*/
5773 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5774 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5775 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5776 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5777 case ixgbe_mac_82599EB:
5778 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5779 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5780 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5781 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5782 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5783 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5784 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5785 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5786 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5787 #ifdef IXGBE_FCOE
5788 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5789 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5790 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5791 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5792 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5793 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5794 #endif /* IXGBE_FCOE */
5795 break;
5796 default:
5797 break;
5798 }
5799 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5800 hwstats->bprc += bprc;
5801 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5802 if (hw->mac.type == ixgbe_mac_82598EB)
5803 hwstats->mprc -= bprc;
5804 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5805 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5806 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5807 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5808 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5809 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5810 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5811 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5812 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5813 hwstats->lxontxc += lxon;
5814 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5815 hwstats->lxofftxc += lxoff;
5816 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5817 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5818 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5819 /*
5820 * 82598 errata - tx of flow control packets is included in tx counters
5821 */
5822 xon_off_tot = lxon + lxoff;
5823 hwstats->gptc -= xon_off_tot;
5824 hwstats->mptc -= xon_off_tot;
5825 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5826 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5827 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5828 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5829 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5830 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5831 hwstats->ptc64 -= xon_off_tot;
5832 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5833 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5834 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5835 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5836 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5837 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5838
5839 /* Fill out the OS statistics structure */
5840 netdev->stats.multicast = hwstats->mprc;
5841
5842 /* Rx Errors */
5843 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5844 netdev->stats.rx_dropped = 0;
5845 netdev->stats.rx_length_errors = hwstats->rlec;
5846 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5847 netdev->stats.rx_missed_errors = total_mpc;
5848 }
5849
5850 /**
5851 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5852 * @adapter - pointer to the device adapter structure
5853 **/
5854 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5855 {
5856 struct ixgbe_hw *hw = &adapter->hw;
5857 int i;
5858
5859 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5860 return;
5861
5862 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5863
5864 /* if interface is down do nothing */
5865 if (test_bit(__IXGBE_DOWN, &adapter->state))
5866 return;
5867
5868 /* do nothing if we are not using signature filters */
5869 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5870 return;
5871
5872 adapter->fdir_overflow++;
5873
5874 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5875 for (i = 0; i < adapter->num_tx_queues; i++)
5876 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5877 &(adapter->tx_ring[i]->state));
5878 /* re-enable flow director interrupts */
5879 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5880 } else {
5881 e_err(probe, "failed to finish FDIR re-initialization, "
5882 "ignored adding FDIR ATR filters\n");
5883 }
5884 }
5885
5886 /**
5887 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5888 * @adapter - pointer to the device adapter structure
5889 *
5890 * This function serves two purposes. First it strobes the interrupt lines
5891 * in order to make certain interrupts are occuring. Secondly it sets the
5892 * bits needed to check for TX hangs. As a result we should immediately
5893 * determine if a hang has occured.
5894 */
5895 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5896 {
5897 struct ixgbe_hw *hw = &adapter->hw;
5898 u64 eics = 0;
5899 int i;
5900
5901 /* If we're down or resetting, just bail */
5902 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5903 test_bit(__IXGBE_RESETTING, &adapter->state))
5904 return;
5905
5906 /* Force detection of hung controller */
5907 if (netif_carrier_ok(adapter->netdev)) {
5908 for (i = 0; i < adapter->num_tx_queues; i++)
5909 set_check_for_tx_hang(adapter->tx_ring[i]);
5910 }
5911
5912 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5913 /*
5914 * for legacy and MSI interrupts don't set any bits
5915 * that are enabled for EIAM, because this operation
5916 * would set *both* EIMS and EICS for any bit in EIAM
5917 */
5918 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5919 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5920 } else {
5921 /* get one bit for every active tx/rx interrupt vector */
5922 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5923 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5924 if (qv->rx.count || qv->tx.count)
5925 eics |= ((u64)1 << i);
5926 }
5927 }
5928
5929 /* Cause software interrupt to ensure rings are cleaned */
5930 ixgbe_irq_rearm_queues(adapter, eics);
5931
5932 }
5933
5934 /**
5935 * ixgbe_watchdog_update_link - update the link status
5936 * @adapter - pointer to the device adapter structure
5937 * @link_speed - pointer to a u32 to store the link_speed
5938 **/
5939 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5940 {
5941 struct ixgbe_hw *hw = &adapter->hw;
5942 u32 link_speed = adapter->link_speed;
5943 bool link_up = adapter->link_up;
5944 int i;
5945
5946 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5947 return;
5948
5949 if (hw->mac.ops.check_link) {
5950 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5951 } else {
5952 /* always assume link is up, if no check link function */
5953 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5954 link_up = true;
5955 }
5956 if (link_up) {
5957 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5958 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5959 hw->mac.ops.fc_enable(hw, i);
5960 } else {
5961 hw->mac.ops.fc_enable(hw, 0);
5962 }
5963 }
5964
5965 if (link_up ||
5966 time_after(jiffies, (adapter->link_check_timeout +
5967 IXGBE_TRY_LINK_TIMEOUT))) {
5968 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5969 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5970 IXGBE_WRITE_FLUSH(hw);
5971 }
5972
5973 adapter->link_up = link_up;
5974 adapter->link_speed = link_speed;
5975 }
5976
5977 /**
5978 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5979 * print link up message
5980 * @adapter - pointer to the device adapter structure
5981 **/
5982 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5983 {
5984 struct net_device *netdev = adapter->netdev;
5985 struct ixgbe_hw *hw = &adapter->hw;
5986 u32 link_speed = adapter->link_speed;
5987 bool flow_rx, flow_tx;
5988
5989 /* only continue if link was previously down */
5990 if (netif_carrier_ok(netdev))
5991 return;
5992
5993 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5994
5995 switch (hw->mac.type) {
5996 case ixgbe_mac_82598EB: {
5997 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5998 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5999 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6000 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6001 }
6002 break;
6003 case ixgbe_mac_X540:
6004 case ixgbe_mac_82599EB: {
6005 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6006 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6007 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6008 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6009 }
6010 break;
6011 default:
6012 flow_tx = false;
6013 flow_rx = false;
6014 break;
6015 }
6016 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6017 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6018 "10 Gbps" :
6019 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6020 "1 Gbps" :
6021 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6022 "100 Mbps" :
6023 "unknown speed"))),
6024 ((flow_rx && flow_tx) ? "RX/TX" :
6025 (flow_rx ? "RX" :
6026 (flow_tx ? "TX" : "None"))));
6027
6028 netif_carrier_on(netdev);
6029 ixgbe_check_vf_rate_limit(adapter);
6030 }
6031
6032 /**
6033 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6034 * print link down message
6035 * @adapter - pointer to the adapter structure
6036 **/
6037 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6038 {
6039 struct net_device *netdev = adapter->netdev;
6040 struct ixgbe_hw *hw = &adapter->hw;
6041
6042 adapter->link_up = false;
6043 adapter->link_speed = 0;
6044
6045 /* only continue if link was up previously */
6046 if (!netif_carrier_ok(netdev))
6047 return;
6048
6049 /* poll for SFP+ cable when link is down */
6050 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6051 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6052
6053 e_info(drv, "NIC Link is Down\n");
6054 netif_carrier_off(netdev);
6055 }
6056
6057 /**
6058 * ixgbe_watchdog_flush_tx - flush queues on link down
6059 * @adapter - pointer to the device adapter structure
6060 **/
6061 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6062 {
6063 int i;
6064 int some_tx_pending = 0;
6065
6066 if (!netif_carrier_ok(adapter->netdev)) {
6067 for (i = 0; i < adapter->num_tx_queues; i++) {
6068 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6069 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6070 some_tx_pending = 1;
6071 break;
6072 }
6073 }
6074
6075 if (some_tx_pending) {
6076 /* We've lost link, so the controller stops DMA,
6077 * but we've got queued Tx work that's never going
6078 * to get done, so reset controller to flush Tx.
6079 * (Do the reset outside of interrupt context).
6080 */
6081 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6082 }
6083 }
6084 }
6085
6086 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6087 {
6088 u32 ssvpc;
6089
6090 /* Do not perform spoof check for 82598 */
6091 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6092 return;
6093
6094 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6095
6096 /*
6097 * ssvpc register is cleared on read, if zero then no
6098 * spoofed packets in the last interval.
6099 */
6100 if (!ssvpc)
6101 return;
6102
6103 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6104 }
6105
6106 /**
6107 * ixgbe_watchdog_subtask - check and bring link up
6108 * @adapter - pointer to the device adapter structure
6109 **/
6110 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6111 {
6112 /* if interface is down do nothing */
6113 if (test_bit(__IXGBE_DOWN, &adapter->state))
6114 return;
6115
6116 ixgbe_watchdog_update_link(adapter);
6117
6118 if (adapter->link_up)
6119 ixgbe_watchdog_link_is_up(adapter);
6120 else
6121 ixgbe_watchdog_link_is_down(adapter);
6122
6123 ixgbe_spoof_check(adapter);
6124 ixgbe_update_stats(adapter);
6125
6126 ixgbe_watchdog_flush_tx(adapter);
6127 }
6128
6129 /**
6130 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6131 * @adapter - the ixgbe adapter structure
6132 **/
6133 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6134 {
6135 struct ixgbe_hw *hw = &adapter->hw;
6136 s32 err;
6137
6138 /* not searching for SFP so there is nothing to do here */
6139 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6140 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6141 return;
6142
6143 /* someone else is in init, wait until next service event */
6144 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6145 return;
6146
6147 err = hw->phy.ops.identify_sfp(hw);
6148 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6149 goto sfp_out;
6150
6151 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6152 /* If no cable is present, then we need to reset
6153 * the next time we find a good cable. */
6154 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6155 }
6156
6157 /* exit on error */
6158 if (err)
6159 goto sfp_out;
6160
6161 /* exit if reset not needed */
6162 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6163 goto sfp_out;
6164
6165 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6166
6167 /*
6168 * A module may be identified correctly, but the EEPROM may not have
6169 * support for that module. setup_sfp() will fail in that case, so
6170 * we should not allow that module to load.
6171 */
6172 if (hw->mac.type == ixgbe_mac_82598EB)
6173 err = hw->phy.ops.reset(hw);
6174 else
6175 err = hw->mac.ops.setup_sfp(hw);
6176
6177 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6178 goto sfp_out;
6179
6180 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6181 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6182
6183 sfp_out:
6184 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6185
6186 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6187 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6188 e_dev_err("failed to initialize because an unsupported "
6189 "SFP+ module type was detected.\n");
6190 e_dev_err("Reload the driver after installing a "
6191 "supported module.\n");
6192 unregister_netdev(adapter->netdev);
6193 }
6194 }
6195
6196 /**
6197 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6198 * @adapter - the ixgbe adapter structure
6199 **/
6200 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6201 {
6202 struct ixgbe_hw *hw = &adapter->hw;
6203 u32 autoneg;
6204 bool negotiation;
6205
6206 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6207 return;
6208
6209 /* someone else is in init, wait until next service event */
6210 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6211 return;
6212
6213 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6214
6215 autoneg = hw->phy.autoneg_advertised;
6216 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6217 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6218 hw->mac.autotry_restart = false;
6219 if (hw->mac.ops.setup_link)
6220 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6221
6222 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6223 adapter->link_check_timeout = jiffies;
6224 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6225 }
6226
6227 /**
6228 * ixgbe_service_timer - Timer Call-back
6229 * @data: pointer to adapter cast into an unsigned long
6230 **/
6231 static void ixgbe_service_timer(unsigned long data)
6232 {
6233 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6234 unsigned long next_event_offset;
6235
6236 /* poll faster when waiting for link */
6237 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6238 next_event_offset = HZ / 10;
6239 else
6240 next_event_offset = HZ * 2;
6241
6242 /* Reset the timer */
6243 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6244
6245 ixgbe_service_event_schedule(adapter);
6246 }
6247
6248 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6249 {
6250 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6251 return;
6252
6253 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6254
6255 /* If we're already down or resetting, just bail */
6256 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6257 test_bit(__IXGBE_RESETTING, &adapter->state))
6258 return;
6259
6260 ixgbe_dump(adapter);
6261 netdev_err(adapter->netdev, "Reset adapter\n");
6262 adapter->tx_timeout_count++;
6263
6264 ixgbe_reinit_locked(adapter);
6265 }
6266
6267 /**
6268 * ixgbe_service_task - manages and runs subtasks
6269 * @work: pointer to work_struct containing our data
6270 **/
6271 static void ixgbe_service_task(struct work_struct *work)
6272 {
6273 struct ixgbe_adapter *adapter = container_of(work,
6274 struct ixgbe_adapter,
6275 service_task);
6276
6277 ixgbe_reset_subtask(adapter);
6278 ixgbe_sfp_detection_subtask(adapter);
6279 ixgbe_sfp_link_config_subtask(adapter);
6280 ixgbe_check_overtemp_subtask(adapter);
6281 ixgbe_watchdog_subtask(adapter);
6282 ixgbe_fdir_reinit_subtask(adapter);
6283 ixgbe_check_hang_subtask(adapter);
6284
6285 ixgbe_service_event_complete(adapter);
6286 }
6287
6288 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6289 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6290 {
6291 struct ixgbe_adv_tx_context_desc *context_desc;
6292 u16 i = tx_ring->next_to_use;
6293
6294 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6295
6296 i++;
6297 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6298
6299 /* set bits to identify this as an advanced context descriptor */
6300 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6301
6302 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6303 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6304 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6305 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6306 }
6307
6308 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6309 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6310 {
6311 int err;
6312 u32 vlan_macip_lens, type_tucmd;
6313 u32 mss_l4len_idx, l4len;
6314
6315 if (!skb_is_gso(skb))
6316 return 0;
6317
6318 if (skb_header_cloned(skb)) {
6319 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6320 if (err)
6321 return err;
6322 }
6323
6324 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6325 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6326
6327 if (protocol == __constant_htons(ETH_P_IP)) {
6328 struct iphdr *iph = ip_hdr(skb);
6329 iph->tot_len = 0;
6330 iph->check = 0;
6331 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6332 iph->daddr, 0,
6333 IPPROTO_TCP,
6334 0);
6335 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6336 } else if (skb_is_gso_v6(skb)) {
6337 ipv6_hdr(skb)->payload_len = 0;
6338 tcp_hdr(skb)->check =
6339 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6340 &ipv6_hdr(skb)->daddr,
6341 0, IPPROTO_TCP, 0);
6342 }
6343
6344 l4len = tcp_hdrlen(skb);
6345 *hdr_len = skb_transport_offset(skb) + l4len;
6346
6347 /* mss_l4len_id: use 1 as index for TSO */
6348 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6349 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6350 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6351
6352 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6353 vlan_macip_lens = skb_network_header_len(skb);
6354 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6355 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6356
6357 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6358 mss_l4len_idx);
6359
6360 return 1;
6361 }
6362
6363 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6364 struct sk_buff *skb, u32 tx_flags,
6365 __be16 protocol)
6366 {
6367 u32 vlan_macip_lens = 0;
6368 u32 mss_l4len_idx = 0;
6369 u32 type_tucmd = 0;
6370
6371 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6372 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN))
6373 return false;
6374 } else {
6375 u8 l4_hdr = 0;
6376 switch (protocol) {
6377 case __constant_htons(ETH_P_IP):
6378 vlan_macip_lens |= skb_network_header_len(skb);
6379 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6380 l4_hdr = ip_hdr(skb)->protocol;
6381 break;
6382 case __constant_htons(ETH_P_IPV6):
6383 vlan_macip_lens |= skb_network_header_len(skb);
6384 l4_hdr = ipv6_hdr(skb)->nexthdr;
6385 break;
6386 default:
6387 if (unlikely(net_ratelimit())) {
6388 dev_warn(tx_ring->dev,
6389 "partial checksum but proto=%x!\n",
6390 skb->protocol);
6391 }
6392 break;
6393 }
6394
6395 switch (l4_hdr) {
6396 case IPPROTO_TCP:
6397 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6398 mss_l4len_idx = tcp_hdrlen(skb) <<
6399 IXGBE_ADVTXD_L4LEN_SHIFT;
6400 break;
6401 case IPPROTO_SCTP:
6402 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6403 mss_l4len_idx = sizeof(struct sctphdr) <<
6404 IXGBE_ADVTXD_L4LEN_SHIFT;
6405 break;
6406 case IPPROTO_UDP:
6407 mss_l4len_idx = sizeof(struct udphdr) <<
6408 IXGBE_ADVTXD_L4LEN_SHIFT;
6409 break;
6410 default:
6411 if (unlikely(net_ratelimit())) {
6412 dev_warn(tx_ring->dev,
6413 "partial checksum but l4 proto=%x!\n",
6414 skb->protocol);
6415 }
6416 break;
6417 }
6418 }
6419
6420 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6421 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6422
6423 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6424 type_tucmd, mss_l4len_idx);
6425
6426 return (skb->ip_summed == CHECKSUM_PARTIAL);
6427 }
6428
6429 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6430 {
6431 /* set type for advanced descriptor with frame checksum insertion */
6432 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6433 IXGBE_ADVTXD_DCMD_IFCS |
6434 IXGBE_ADVTXD_DCMD_DEXT);
6435
6436 /* set HW vlan bit if vlan is present */
6437 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6438 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6439
6440 /* set segmentation enable bits for TSO/FSO */
6441 #ifdef IXGBE_FCOE
6442 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6443 #else
6444 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6445 #endif
6446 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6447
6448 return cmd_type;
6449 }
6450
6451 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6452 {
6453 __le32 olinfo_status =
6454 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6455
6456 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6457 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6458 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6459 /* enble IPv4 checksum for TSO */
6460 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6461 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6462 }
6463
6464 /* enable L4 checksum for TSO and TX checksum offload */
6465 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6466 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6467
6468 #ifdef IXGBE_FCOE
6469 /* use index 1 context for FCOE/FSO */
6470 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6471 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6472 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6473
6474 #endif
6475 return olinfo_status;
6476 }
6477
6478 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6479 IXGBE_TXD_CMD_RS)
6480
6481 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6482 struct sk_buff *skb,
6483 struct ixgbe_tx_buffer *first,
6484 u32 tx_flags,
6485 const u8 hdr_len)
6486 {
6487 struct device *dev = tx_ring->dev;
6488 struct ixgbe_tx_buffer *tx_buffer_info;
6489 union ixgbe_adv_tx_desc *tx_desc;
6490 dma_addr_t dma;
6491 __le32 cmd_type, olinfo_status;
6492 struct skb_frag_struct *frag;
6493 unsigned int f = 0;
6494 unsigned int data_len = skb->data_len;
6495 unsigned int size = skb_headlen(skb);
6496 u32 offset = 0;
6497 u32 paylen = skb->len - hdr_len;
6498 u16 i = tx_ring->next_to_use;
6499 u16 gso_segs;
6500
6501 #ifdef IXGBE_FCOE
6502 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6503 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6504 data_len -= sizeof(struct fcoe_crc_eof);
6505 } else {
6506 size -= sizeof(struct fcoe_crc_eof) - data_len;
6507 data_len = 0;
6508 }
6509 }
6510
6511 #endif
6512 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6513 if (dma_mapping_error(dev, dma))
6514 goto dma_error;
6515
6516 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6517 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6518
6519 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6520
6521 for (;;) {
6522 while (size > IXGBE_MAX_DATA_PER_TXD) {
6523 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6524 tx_desc->read.cmd_type_len =
6525 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6526 tx_desc->read.olinfo_status = olinfo_status;
6527
6528 offset += IXGBE_MAX_DATA_PER_TXD;
6529 size -= IXGBE_MAX_DATA_PER_TXD;
6530
6531 tx_desc++;
6532 i++;
6533 if (i == tx_ring->count) {
6534 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6535 i = 0;
6536 }
6537 }
6538
6539 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6540 tx_buffer_info->length = offset + size;
6541 tx_buffer_info->tx_flags = tx_flags;
6542 tx_buffer_info->dma = dma;
6543
6544 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6545 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6546 tx_desc->read.olinfo_status = olinfo_status;
6547
6548 if (!data_len)
6549 break;
6550
6551 frag = &skb_shinfo(skb)->frags[f];
6552 #ifdef IXGBE_FCOE
6553 size = min_t(unsigned int, data_len, frag->size);
6554 #else
6555 size = frag->size;
6556 #endif
6557 data_len -= size;
6558 f++;
6559
6560 offset = 0;
6561 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6562
6563 dma = dma_map_page(dev, frag->page, frag->page_offset,
6564 size, DMA_TO_DEVICE);
6565 if (dma_mapping_error(dev, dma))
6566 goto dma_error;
6567
6568 tx_desc++;
6569 i++;
6570 if (i == tx_ring->count) {
6571 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6572 i = 0;
6573 }
6574 }
6575
6576 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6577
6578 i++;
6579 if (i == tx_ring->count)
6580 i = 0;
6581
6582 tx_ring->next_to_use = i;
6583
6584 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6585 gso_segs = skb_shinfo(skb)->gso_segs;
6586 #ifdef IXGBE_FCOE
6587 /* adjust for FCoE Sequence Offload */
6588 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6589 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6590 skb_shinfo(skb)->gso_size);
6591 #endif /* IXGBE_FCOE */
6592 else
6593 gso_segs = 1;
6594
6595 /* multiply data chunks by size of headers */
6596 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6597 tx_buffer_info->gso_segs = gso_segs;
6598 tx_buffer_info->skb = skb;
6599
6600 /* set the timestamp */
6601 first->time_stamp = jiffies;
6602
6603 /*
6604 * Force memory writes to complete before letting h/w
6605 * know there are new descriptors to fetch. (Only
6606 * applicable for weak-ordered memory model archs,
6607 * such as IA-64).
6608 */
6609 wmb();
6610
6611 /* set next_to_watch value indicating a packet is present */
6612 first->next_to_watch = tx_desc;
6613
6614 /* notify HW of packet */
6615 writel(i, tx_ring->tail);
6616
6617 return;
6618 dma_error:
6619 dev_err(dev, "TX DMA map failed\n");
6620
6621 /* clear dma mappings for failed tx_buffer_info map */
6622 for (;;) {
6623 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6624 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6625 if (tx_buffer_info == first)
6626 break;
6627 if (i == 0)
6628 i = tx_ring->count;
6629 i--;
6630 }
6631
6632 dev_kfree_skb_any(skb);
6633
6634 tx_ring->next_to_use = i;
6635 }
6636
6637 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6638 u32 tx_flags, __be16 protocol)
6639 {
6640 struct ixgbe_q_vector *q_vector = ring->q_vector;
6641 union ixgbe_atr_hash_dword input = { .dword = 0 };
6642 union ixgbe_atr_hash_dword common = { .dword = 0 };
6643 union {
6644 unsigned char *network;
6645 struct iphdr *ipv4;
6646 struct ipv6hdr *ipv6;
6647 } hdr;
6648 struct tcphdr *th;
6649 __be16 vlan_id;
6650
6651 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6652 if (!q_vector)
6653 return;
6654
6655 /* do nothing if sampling is disabled */
6656 if (!ring->atr_sample_rate)
6657 return;
6658
6659 ring->atr_count++;
6660
6661 /* snag network header to get L4 type and address */
6662 hdr.network = skb_network_header(skb);
6663
6664 /* Currently only IPv4/IPv6 with TCP is supported */
6665 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6666 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6667 (protocol != __constant_htons(ETH_P_IP) ||
6668 hdr.ipv4->protocol != IPPROTO_TCP))
6669 return;
6670
6671 th = tcp_hdr(skb);
6672
6673 /* skip this packet since it is invalid or the socket is closing */
6674 if (!th || th->fin)
6675 return;
6676
6677 /* sample on all syn packets or once every atr sample count */
6678 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6679 return;
6680
6681 /* reset sample count */
6682 ring->atr_count = 0;
6683
6684 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6685
6686 /*
6687 * src and dst are inverted, think how the receiver sees them
6688 *
6689 * The input is broken into two sections, a non-compressed section
6690 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6691 * is XORed together and stored in the compressed dword.
6692 */
6693 input.formatted.vlan_id = vlan_id;
6694
6695 /*
6696 * since src port and flex bytes occupy the same word XOR them together
6697 * and write the value to source port portion of compressed dword
6698 */
6699 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6700 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6701 else
6702 common.port.src ^= th->dest ^ protocol;
6703 common.port.dst ^= th->source;
6704
6705 if (protocol == __constant_htons(ETH_P_IP)) {
6706 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6707 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6708 } else {
6709 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6710 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6711 hdr.ipv6->saddr.s6_addr32[1] ^
6712 hdr.ipv6->saddr.s6_addr32[2] ^
6713 hdr.ipv6->saddr.s6_addr32[3] ^
6714 hdr.ipv6->daddr.s6_addr32[0] ^
6715 hdr.ipv6->daddr.s6_addr32[1] ^
6716 hdr.ipv6->daddr.s6_addr32[2] ^
6717 hdr.ipv6->daddr.s6_addr32[3];
6718 }
6719
6720 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6721 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6722 input, common, ring->queue_index);
6723 }
6724
6725 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6726 {
6727 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6728 /* Herbert's original patch had:
6729 * smp_mb__after_netif_stop_queue();
6730 * but since that doesn't exist yet, just open code it. */
6731 smp_mb();
6732
6733 /* We need to check again in a case another CPU has just
6734 * made room available. */
6735 if (likely(ixgbe_desc_unused(tx_ring) < size))
6736 return -EBUSY;
6737
6738 /* A reprieve! - use start_queue because it doesn't call schedule */
6739 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6740 ++tx_ring->tx_stats.restart_queue;
6741 return 0;
6742 }
6743
6744 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6745 {
6746 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6747 return 0;
6748 return __ixgbe_maybe_stop_tx(tx_ring, size);
6749 }
6750
6751 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6752 {
6753 struct ixgbe_adapter *adapter = netdev_priv(dev);
6754 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6755 smp_processor_id();
6756 #ifdef IXGBE_FCOE
6757 __be16 protocol = vlan_get_protocol(skb);
6758
6759 if (((protocol == htons(ETH_P_FCOE)) ||
6760 (protocol == htons(ETH_P_FIP))) &&
6761 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6762 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6763 txq += adapter->ring_feature[RING_F_FCOE].mask;
6764 return txq;
6765 }
6766 #endif
6767
6768 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6769 while (unlikely(txq >= dev->real_num_tx_queues))
6770 txq -= dev->real_num_tx_queues;
6771 return txq;
6772 }
6773
6774 return skb_tx_hash(dev, skb);
6775 }
6776
6777 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6778 struct ixgbe_adapter *adapter,
6779 struct ixgbe_ring *tx_ring)
6780 {
6781 struct ixgbe_tx_buffer *first;
6782 int tso;
6783 u32 tx_flags = 0;
6784 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6785 unsigned short f;
6786 #endif
6787 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6788 __be16 protocol = skb->protocol;
6789 u8 hdr_len = 0;
6790
6791 /*
6792 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6793 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6794 * + 2 desc gap to keep tail from touching head,
6795 * + 1 desc for context descriptor,
6796 * otherwise try next time
6797 */
6798 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6799 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6800 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6801 #else
6802 count += skb_shinfo(skb)->nr_frags;
6803 #endif
6804 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6805 tx_ring->tx_stats.tx_busy++;
6806 return NETDEV_TX_BUSY;
6807 }
6808
6809 /* if we have a HW VLAN tag being added default to the HW one */
6810 if (vlan_tx_tag_present(skb)) {
6811 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6812 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6813 /* else if it is a SW VLAN check the next protocol and store the tag */
6814 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6815 struct vlan_hdr *vhdr, _vhdr;
6816 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6817 if (!vhdr)
6818 goto out_drop;
6819
6820 protocol = vhdr->h_vlan_encapsulated_proto;
6821 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6822 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6823 }
6824
6825 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6826 skb->priority != TC_PRIO_CONTROL) {
6827 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6828 tx_flags |= tx_ring->dcb_tc <<
6829 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6830 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6831 struct vlan_ethhdr *vhdr;
6832 if (skb_header_cloned(skb) &&
6833 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6834 goto out_drop;
6835 vhdr = (struct vlan_ethhdr *)skb->data;
6836 vhdr->h_vlan_TCI = htons(tx_flags >>
6837 IXGBE_TX_FLAGS_VLAN_SHIFT);
6838 } else {
6839 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6840 }
6841 }
6842
6843 /* record the location of the first descriptor for this packet */
6844 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6845
6846 #ifdef IXGBE_FCOE
6847 /* setup tx offload for FCoE */
6848 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6849 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6850 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6851 if (tso < 0)
6852 goto out_drop;
6853 else if (tso)
6854 tx_flags |= IXGBE_TX_FLAGS_FSO |
6855 IXGBE_TX_FLAGS_FCOE;
6856 else
6857 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6858
6859 goto xmit_fcoe;
6860 }
6861
6862 #endif /* IXGBE_FCOE */
6863 /* setup IPv4/IPv6 offloads */
6864 if (protocol == __constant_htons(ETH_P_IP))
6865 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6866
6867 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6868 if (tso < 0)
6869 goto out_drop;
6870 else if (tso)
6871 tx_flags |= IXGBE_TX_FLAGS_TSO;
6872 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6873 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6874
6875 /* add the ATR filter if ATR is on */
6876 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6877 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6878
6879 #ifdef IXGBE_FCOE
6880 xmit_fcoe:
6881 #endif /* IXGBE_FCOE */
6882 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6883
6884 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6885
6886 return NETDEV_TX_OK;
6887
6888 out_drop:
6889 dev_kfree_skb_any(skb);
6890 return NETDEV_TX_OK;
6891 }
6892
6893 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6894 {
6895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6896 struct ixgbe_ring *tx_ring;
6897
6898 tx_ring = adapter->tx_ring[skb->queue_mapping];
6899 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6900 }
6901
6902 /**
6903 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6904 * @netdev: network interface device structure
6905 * @p: pointer to an address structure
6906 *
6907 * Returns 0 on success, negative on failure
6908 **/
6909 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6910 {
6911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6912 struct ixgbe_hw *hw = &adapter->hw;
6913 struct sockaddr *addr = p;
6914
6915 if (!is_valid_ether_addr(addr->sa_data))
6916 return -EADDRNOTAVAIL;
6917
6918 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6919 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6920
6921 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6922 IXGBE_RAH_AV);
6923
6924 return 0;
6925 }
6926
6927 static int
6928 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6929 {
6930 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6931 struct ixgbe_hw *hw = &adapter->hw;
6932 u16 value;
6933 int rc;
6934
6935 if (prtad != hw->phy.mdio.prtad)
6936 return -EINVAL;
6937 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6938 if (!rc)
6939 rc = value;
6940 return rc;
6941 }
6942
6943 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6944 u16 addr, u16 value)
6945 {
6946 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6947 struct ixgbe_hw *hw = &adapter->hw;
6948
6949 if (prtad != hw->phy.mdio.prtad)
6950 return -EINVAL;
6951 return hw->phy.ops.write_reg(hw, addr, devad, value);
6952 }
6953
6954 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6955 {
6956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6957
6958 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6959 }
6960
6961 /**
6962 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6963 * netdev->dev_addrs
6964 * @netdev: network interface device structure
6965 *
6966 * Returns non-zero on failure
6967 **/
6968 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6969 {
6970 int err = 0;
6971 struct ixgbe_adapter *adapter = netdev_priv(dev);
6972 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6973
6974 if (is_valid_ether_addr(mac->san_addr)) {
6975 rtnl_lock();
6976 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6977 rtnl_unlock();
6978 }
6979 return err;
6980 }
6981
6982 /**
6983 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6984 * netdev->dev_addrs
6985 * @netdev: network interface device structure
6986 *
6987 * Returns non-zero on failure
6988 **/
6989 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6990 {
6991 int err = 0;
6992 struct ixgbe_adapter *adapter = netdev_priv(dev);
6993 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6994
6995 if (is_valid_ether_addr(mac->san_addr)) {
6996 rtnl_lock();
6997 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6998 rtnl_unlock();
6999 }
7000 return err;
7001 }
7002
7003 #ifdef CONFIG_NET_POLL_CONTROLLER
7004 /*
7005 * Polling 'interrupt' - used by things like netconsole to send skbs
7006 * without having to re-enable interrupts. It's not called while
7007 * the interrupt routine is executing.
7008 */
7009 static void ixgbe_netpoll(struct net_device *netdev)
7010 {
7011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7012 int i;
7013
7014 /* if interface is down do nothing */
7015 if (test_bit(__IXGBE_DOWN, &adapter->state))
7016 return;
7017
7018 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7019 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7020 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7021 for (i = 0; i < num_q_vectors; i++) {
7022 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7023 ixgbe_msix_clean_many(0, q_vector);
7024 }
7025 } else {
7026 ixgbe_intr(adapter->pdev->irq, netdev);
7027 }
7028 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7029 }
7030 #endif
7031
7032 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7033 struct rtnl_link_stats64 *stats)
7034 {
7035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7036 int i;
7037
7038 rcu_read_lock();
7039 for (i = 0; i < adapter->num_rx_queues; i++) {
7040 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7041 u64 bytes, packets;
7042 unsigned int start;
7043
7044 if (ring) {
7045 do {
7046 start = u64_stats_fetch_begin_bh(&ring->syncp);
7047 packets = ring->stats.packets;
7048 bytes = ring->stats.bytes;
7049 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7050 stats->rx_packets += packets;
7051 stats->rx_bytes += bytes;
7052 }
7053 }
7054
7055 for (i = 0; i < adapter->num_tx_queues; i++) {
7056 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7057 u64 bytes, packets;
7058 unsigned int start;
7059
7060 if (ring) {
7061 do {
7062 start = u64_stats_fetch_begin_bh(&ring->syncp);
7063 packets = ring->stats.packets;
7064 bytes = ring->stats.bytes;
7065 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7066 stats->tx_packets += packets;
7067 stats->tx_bytes += bytes;
7068 }
7069 }
7070 rcu_read_unlock();
7071 /* following stats updated by ixgbe_watchdog_task() */
7072 stats->multicast = netdev->stats.multicast;
7073 stats->rx_errors = netdev->stats.rx_errors;
7074 stats->rx_length_errors = netdev->stats.rx_length_errors;
7075 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7076 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7077 return stats;
7078 }
7079
7080 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7081 * #adapter: pointer to ixgbe_adapter
7082 * @tc: number of traffic classes currently enabled
7083 *
7084 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7085 * 802.1Q priority maps to a packet buffer that exists.
7086 */
7087 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7088 {
7089 struct ixgbe_hw *hw = &adapter->hw;
7090 u32 reg, rsave;
7091 int i;
7092
7093 /* 82598 have a static priority to TC mapping that can not
7094 * be changed so no validation is needed.
7095 */
7096 if (hw->mac.type == ixgbe_mac_82598EB)
7097 return;
7098
7099 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7100 rsave = reg;
7101
7102 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7103 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7104
7105 /* If up2tc is out of bounds default to zero */
7106 if (up2tc > tc)
7107 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7108 }
7109
7110 if (reg != rsave)
7111 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7112
7113 return;
7114 }
7115
7116
7117 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7118 * classes.
7119 *
7120 * @netdev: net device to configure
7121 * @tc: number of traffic classes to enable
7122 */
7123 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7124 {
7125 struct ixgbe_adapter *adapter = netdev_priv(dev);
7126 struct ixgbe_hw *hw = &adapter->hw;
7127
7128 /* If DCB is anabled do not remove traffic classes, multiple
7129 * traffic classes are required to implement DCB
7130 */
7131 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7132 return 0;
7133
7134 /* Hardware supports up to 8 traffic classes */
7135 if (tc > MAX_TRAFFIC_CLASS ||
7136 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7137 return -EINVAL;
7138
7139 /* Hardware has to reinitialize queues and interrupts to
7140 * match packet buffer alignment. Unfortunantly, the
7141 * hardware is not flexible enough to do this dynamically.
7142 */
7143 if (netif_running(dev))
7144 ixgbe_close(dev);
7145 ixgbe_clear_interrupt_scheme(adapter);
7146
7147 if (tc)
7148 netdev_set_num_tc(dev, tc);
7149 else
7150 netdev_reset_tc(dev);
7151
7152 ixgbe_init_interrupt_scheme(adapter);
7153 ixgbe_validate_rtr(adapter, tc);
7154 if (netif_running(dev))
7155 ixgbe_open(dev);
7156
7157 return 0;
7158 }
7159
7160 void ixgbe_do_reset(struct net_device *netdev)
7161 {
7162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7163
7164 if (netif_running(netdev))
7165 ixgbe_reinit_locked(adapter);
7166 else
7167 ixgbe_reset(adapter);
7168 }
7169
7170 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7171 {
7172 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7173
7174 #ifdef CONFIG_DCB
7175 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7176 data &= ~NETIF_F_HW_VLAN_RX;
7177 #endif
7178
7179 /* return error if RXHASH is being enabled when RSS is not supported */
7180 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7181 data &= ~NETIF_F_RXHASH;
7182
7183 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7184 if (!(data & NETIF_F_RXCSUM))
7185 data &= ~NETIF_F_LRO;
7186
7187 /* Turn off LRO if not RSC capable or invalid ITR settings */
7188 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7189 data &= ~NETIF_F_LRO;
7190 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7191 (adapter->rx_itr_setting != 1 &&
7192 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7193 data &= ~NETIF_F_LRO;
7194 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7195 }
7196
7197 return data;
7198 }
7199
7200 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7201 {
7202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7203 bool need_reset = false;
7204
7205 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7206 if (!(data & NETIF_F_RXCSUM))
7207 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7208 else
7209 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7210
7211 /* Make sure RSC matches LRO, reset if change */
7212 if (!!(data & NETIF_F_LRO) !=
7213 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7214 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7215 switch (adapter->hw.mac.type) {
7216 case ixgbe_mac_X540:
7217 case ixgbe_mac_82599EB:
7218 need_reset = true;
7219 break;
7220 default:
7221 break;
7222 }
7223 }
7224
7225 /*
7226 * Check if Flow Director n-tuple support was enabled or disabled. If
7227 * the state changed, we need to reset.
7228 */
7229 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7230 /* turn off ATR, enable perfect filters and reset */
7231 if (data & NETIF_F_NTUPLE) {
7232 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7233 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7234 need_reset = true;
7235 }
7236 } else if (!(data & NETIF_F_NTUPLE)) {
7237 /* turn off Flow Director, set ATR and reset */
7238 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7239 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7240 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7241 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7242 need_reset = true;
7243 }
7244
7245 if (need_reset)
7246 ixgbe_do_reset(netdev);
7247
7248 return 0;
7249
7250 }
7251
7252 static const struct net_device_ops ixgbe_netdev_ops = {
7253 .ndo_open = ixgbe_open,
7254 .ndo_stop = ixgbe_close,
7255 .ndo_start_xmit = ixgbe_xmit_frame,
7256 .ndo_select_queue = ixgbe_select_queue,
7257 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7258 .ndo_validate_addr = eth_validate_addr,
7259 .ndo_set_mac_address = ixgbe_set_mac,
7260 .ndo_change_mtu = ixgbe_change_mtu,
7261 .ndo_tx_timeout = ixgbe_tx_timeout,
7262 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7263 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7264 .ndo_do_ioctl = ixgbe_ioctl,
7265 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7266 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7267 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7268 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7269 .ndo_get_stats64 = ixgbe_get_stats64,
7270 .ndo_setup_tc = ixgbe_setup_tc,
7271 #ifdef CONFIG_NET_POLL_CONTROLLER
7272 .ndo_poll_controller = ixgbe_netpoll,
7273 #endif
7274 #ifdef IXGBE_FCOE
7275 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7276 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7277 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7278 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7279 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7280 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7281 #endif /* IXGBE_FCOE */
7282 .ndo_set_features = ixgbe_set_features,
7283 .ndo_fix_features = ixgbe_fix_features,
7284 };
7285
7286 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7287 const struct ixgbe_info *ii)
7288 {
7289 #ifdef CONFIG_PCI_IOV
7290 struct ixgbe_hw *hw = &adapter->hw;
7291 int err;
7292 int num_vf_macvlans, i;
7293 struct vf_macvlans *mv_list;
7294
7295 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7296 return;
7297
7298 /* The 82599 supports up to 64 VFs per physical function
7299 * but this implementation limits allocation to 63 so that
7300 * basic networking resources are still available to the
7301 * physical function
7302 */
7303 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7304 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7305 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7306 if (err) {
7307 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7308 goto err_novfs;
7309 }
7310
7311 num_vf_macvlans = hw->mac.num_rar_entries -
7312 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7313
7314 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7315 sizeof(struct vf_macvlans),
7316 GFP_KERNEL);
7317 if (mv_list) {
7318 /* Initialize list of VF macvlans */
7319 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7320 for (i = 0; i < num_vf_macvlans; i++) {
7321 mv_list->vf = -1;
7322 mv_list->free = true;
7323 mv_list->rar_entry = hw->mac.num_rar_entries -
7324 (i + adapter->num_vfs + 1);
7325 list_add(&mv_list->l, &adapter->vf_mvs.l);
7326 mv_list++;
7327 }
7328 }
7329
7330 /* If call to enable VFs succeeded then allocate memory
7331 * for per VF control structures.
7332 */
7333 adapter->vfinfo =
7334 kcalloc(adapter->num_vfs,
7335 sizeof(struct vf_data_storage), GFP_KERNEL);
7336 if (adapter->vfinfo) {
7337 /* Now that we're sure SR-IOV is enabled
7338 * and memory allocated set up the mailbox parameters
7339 */
7340 ixgbe_init_mbx_params_pf(hw);
7341 memcpy(&hw->mbx.ops, ii->mbx_ops,
7342 sizeof(hw->mbx.ops));
7343
7344 /* Disable RSC when in SR-IOV mode */
7345 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7346 IXGBE_FLAG2_RSC_ENABLED);
7347 return;
7348 }
7349
7350 /* Oh oh */
7351 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7352 "SRIOV disabled\n");
7353 pci_disable_sriov(adapter->pdev);
7354
7355 err_novfs:
7356 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7357 adapter->num_vfs = 0;
7358 #endif /* CONFIG_PCI_IOV */
7359 }
7360
7361 /**
7362 * ixgbe_probe - Device Initialization Routine
7363 * @pdev: PCI device information struct
7364 * @ent: entry in ixgbe_pci_tbl
7365 *
7366 * Returns 0 on success, negative on failure
7367 *
7368 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7369 * The OS initialization, configuring of the adapter private structure,
7370 * and a hardware reset occur.
7371 **/
7372 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7373 const struct pci_device_id *ent)
7374 {
7375 struct net_device *netdev;
7376 struct ixgbe_adapter *adapter = NULL;
7377 struct ixgbe_hw *hw;
7378 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7379 static int cards_found;
7380 int i, err, pci_using_dac;
7381 u8 part_str[IXGBE_PBANUM_LENGTH];
7382 unsigned int indices = num_possible_cpus();
7383 #ifdef IXGBE_FCOE
7384 u16 device_caps;
7385 #endif
7386 u32 eec;
7387
7388 /* Catch broken hardware that put the wrong VF device ID in
7389 * the PCIe SR-IOV capability.
7390 */
7391 if (pdev->is_virtfn) {
7392 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7393 pci_name(pdev), pdev->vendor, pdev->device);
7394 return -EINVAL;
7395 }
7396
7397 err = pci_enable_device_mem(pdev);
7398 if (err)
7399 return err;
7400
7401 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7402 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7403 pci_using_dac = 1;
7404 } else {
7405 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7406 if (err) {
7407 err = dma_set_coherent_mask(&pdev->dev,
7408 DMA_BIT_MASK(32));
7409 if (err) {
7410 dev_err(&pdev->dev,
7411 "No usable DMA configuration, aborting\n");
7412 goto err_dma;
7413 }
7414 }
7415 pci_using_dac = 0;
7416 }
7417
7418 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7419 IORESOURCE_MEM), ixgbe_driver_name);
7420 if (err) {
7421 dev_err(&pdev->dev,
7422 "pci_request_selected_regions failed 0x%x\n", err);
7423 goto err_pci_reg;
7424 }
7425
7426 pci_enable_pcie_error_reporting(pdev);
7427
7428 pci_set_master(pdev);
7429 pci_save_state(pdev);
7430
7431 #ifdef CONFIG_IXGBE_DCB
7432 indices *= MAX_TRAFFIC_CLASS;
7433 #endif
7434
7435 if (ii->mac == ixgbe_mac_82598EB)
7436 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7437 else
7438 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7439
7440 #ifdef IXGBE_FCOE
7441 indices += min_t(unsigned int, num_possible_cpus(),
7442 IXGBE_MAX_FCOE_INDICES);
7443 #endif
7444 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7445 if (!netdev) {
7446 err = -ENOMEM;
7447 goto err_alloc_etherdev;
7448 }
7449
7450 SET_NETDEV_DEV(netdev, &pdev->dev);
7451
7452 adapter = netdev_priv(netdev);
7453 pci_set_drvdata(pdev, adapter);
7454
7455 adapter->netdev = netdev;
7456 adapter->pdev = pdev;
7457 hw = &adapter->hw;
7458 hw->back = adapter;
7459 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7460
7461 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7462 pci_resource_len(pdev, 0));
7463 if (!hw->hw_addr) {
7464 err = -EIO;
7465 goto err_ioremap;
7466 }
7467
7468 for (i = 1; i <= 5; i++) {
7469 if (pci_resource_len(pdev, i) == 0)
7470 continue;
7471 }
7472
7473 netdev->netdev_ops = &ixgbe_netdev_ops;
7474 ixgbe_set_ethtool_ops(netdev);
7475 netdev->watchdog_timeo = 5 * HZ;
7476 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7477
7478 adapter->bd_number = cards_found;
7479
7480 /* Setup hw api */
7481 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7482 hw->mac.type = ii->mac;
7483
7484 /* EEPROM */
7485 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7486 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7487 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7488 if (!(eec & (1 << 8)))
7489 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7490
7491 /* PHY */
7492 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7493 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7494 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7495 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7496 hw->phy.mdio.mmds = 0;
7497 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7498 hw->phy.mdio.dev = netdev;
7499 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7500 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7501
7502 ii->get_invariants(hw);
7503
7504 /* setup the private structure */
7505 err = ixgbe_sw_init(adapter);
7506 if (err)
7507 goto err_sw_init;
7508
7509 /* Make it possible the adapter to be woken up via WOL */
7510 switch (adapter->hw.mac.type) {
7511 case ixgbe_mac_82599EB:
7512 case ixgbe_mac_X540:
7513 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7514 break;
7515 default:
7516 break;
7517 }
7518
7519 /*
7520 * If there is a fan on this device and it has failed log the
7521 * failure.
7522 */
7523 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7524 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7525 if (esdp & IXGBE_ESDP_SDP1)
7526 e_crit(probe, "Fan has stopped, replace the adapter\n");
7527 }
7528
7529 /* reset_hw fills in the perm_addr as well */
7530 hw->phy.reset_if_overtemp = true;
7531 err = hw->mac.ops.reset_hw(hw);
7532 hw->phy.reset_if_overtemp = false;
7533 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7534 hw->mac.type == ixgbe_mac_82598EB) {
7535 err = 0;
7536 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7537 e_dev_err("failed to load because an unsupported SFP+ "
7538 "module type was detected.\n");
7539 e_dev_err("Reload the driver after installing a supported "
7540 "module.\n");
7541 goto err_sw_init;
7542 } else if (err) {
7543 e_dev_err("HW Init failed: %d\n", err);
7544 goto err_sw_init;
7545 }
7546
7547 ixgbe_probe_vf(adapter, ii);
7548
7549 netdev->features = NETIF_F_SG |
7550 NETIF_F_IP_CSUM |
7551 NETIF_F_IPV6_CSUM |
7552 NETIF_F_HW_VLAN_TX |
7553 NETIF_F_HW_VLAN_RX |
7554 NETIF_F_HW_VLAN_FILTER |
7555 NETIF_F_TSO |
7556 NETIF_F_TSO6 |
7557 NETIF_F_GRO |
7558 NETIF_F_RXHASH |
7559 NETIF_F_RXCSUM;
7560
7561 netdev->hw_features = netdev->features;
7562
7563 switch (adapter->hw.mac.type) {
7564 case ixgbe_mac_82599EB:
7565 case ixgbe_mac_X540:
7566 netdev->features |= NETIF_F_SCTP_CSUM;
7567 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7568 NETIF_F_NTUPLE;
7569 break;
7570 default:
7571 break;
7572 }
7573
7574 netdev->vlan_features |= NETIF_F_TSO;
7575 netdev->vlan_features |= NETIF_F_TSO6;
7576 netdev->vlan_features |= NETIF_F_IP_CSUM;
7577 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7578 netdev->vlan_features |= NETIF_F_SG;
7579
7580 netdev->priv_flags |= IFF_UNICAST_FLT;
7581
7582 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7583 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7584 IXGBE_FLAG_DCB_ENABLED);
7585
7586 #ifdef CONFIG_IXGBE_DCB
7587 netdev->dcbnl_ops = &dcbnl_ops;
7588 #endif
7589
7590 #ifdef IXGBE_FCOE
7591 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7592 if (hw->mac.ops.get_device_caps) {
7593 hw->mac.ops.get_device_caps(hw, &device_caps);
7594 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7595 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7596 }
7597 }
7598 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7599 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7600 netdev->vlan_features |= NETIF_F_FSO;
7601 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7602 }
7603 #endif /* IXGBE_FCOE */
7604 if (pci_using_dac) {
7605 netdev->features |= NETIF_F_HIGHDMA;
7606 netdev->vlan_features |= NETIF_F_HIGHDMA;
7607 }
7608
7609 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7610 netdev->hw_features |= NETIF_F_LRO;
7611 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7612 netdev->features |= NETIF_F_LRO;
7613
7614 /* make sure the EEPROM is good */
7615 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7616 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7617 err = -EIO;
7618 goto err_eeprom;
7619 }
7620
7621 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7622 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7623
7624 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7625 e_dev_err("invalid MAC address\n");
7626 err = -EIO;
7627 goto err_eeprom;
7628 }
7629
7630 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7631 if (hw->mac.ops.disable_tx_laser &&
7632 ((hw->phy.multispeed_fiber) ||
7633 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7634 (hw->mac.type == ixgbe_mac_82599EB))))
7635 hw->mac.ops.disable_tx_laser(hw);
7636
7637 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7638 (unsigned long) adapter);
7639
7640 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7641 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7642
7643 err = ixgbe_init_interrupt_scheme(adapter);
7644 if (err)
7645 goto err_sw_init;
7646
7647 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7648 netdev->hw_features &= ~NETIF_F_RXHASH;
7649 netdev->features &= ~NETIF_F_RXHASH;
7650 }
7651
7652 switch (pdev->device) {
7653 case IXGBE_DEV_ID_82599_SFP:
7654 /* Only this subdevice supports WOL */
7655 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7656 adapter->wol = IXGBE_WUFC_MAG;
7657 break;
7658 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7659 /* All except this subdevice support WOL */
7660 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7661 adapter->wol = IXGBE_WUFC_MAG;
7662 break;
7663 case IXGBE_DEV_ID_82599_KX4:
7664 adapter->wol = IXGBE_WUFC_MAG;
7665 break;
7666 default:
7667 adapter->wol = 0;
7668 break;
7669 }
7670 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7671
7672 /* pick up the PCI bus settings for reporting later */
7673 hw->mac.ops.get_bus_info(hw);
7674
7675 /* print bus type/speed/width info */
7676 e_dev_info("(PCI Express:%s:%s) %pM\n",
7677 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7678 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7679 "Unknown"),
7680 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7681 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7682 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7683 "Unknown"),
7684 netdev->dev_addr);
7685
7686 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7687 if (err)
7688 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7689 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7690 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7691 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7692 part_str);
7693 else
7694 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7695 hw->mac.type, hw->phy.type, part_str);
7696
7697 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7698 e_dev_warn("PCI-Express bandwidth available for this card is "
7699 "not sufficient for optimal performance.\n");
7700 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7701 "is required.\n");
7702 }
7703
7704 /* save off EEPROM version number */
7705 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7706
7707 /* reset the hardware with the new settings */
7708 err = hw->mac.ops.start_hw(hw);
7709
7710 if (err == IXGBE_ERR_EEPROM_VERSION) {
7711 /* We are running on a pre-production device, log a warning */
7712 e_dev_warn("This device is a pre-production adapter/LOM. "
7713 "Please be aware there may be issues associated "
7714 "with your hardware. If you are experiencing "
7715 "problems please contact your Intel or hardware "
7716 "representative who provided you with this "
7717 "hardware.\n");
7718 }
7719 strcpy(netdev->name, "eth%d");
7720 err = register_netdev(netdev);
7721 if (err)
7722 goto err_register;
7723
7724 /* carrier off reporting is important to ethtool even BEFORE open */
7725 netif_carrier_off(netdev);
7726
7727 #ifdef CONFIG_IXGBE_DCA
7728 if (dca_add_requester(&pdev->dev) == 0) {
7729 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7730 ixgbe_setup_dca(adapter);
7731 }
7732 #endif
7733 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7734 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7735 for (i = 0; i < adapter->num_vfs; i++)
7736 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7737 }
7738
7739 /* Inform firmware of driver version */
7740 if (hw->mac.ops.set_fw_drv_ver)
7741 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7742 FW_CEM_UNUSED_VER);
7743
7744 /* add san mac addr to netdev */
7745 ixgbe_add_sanmac_netdev(netdev);
7746
7747 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7748 cards_found++;
7749 return 0;
7750
7751 err_register:
7752 ixgbe_release_hw_control(adapter);
7753 ixgbe_clear_interrupt_scheme(adapter);
7754 err_sw_init:
7755 err_eeprom:
7756 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7757 ixgbe_disable_sriov(adapter);
7758 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7759 iounmap(hw->hw_addr);
7760 err_ioremap:
7761 free_netdev(netdev);
7762 err_alloc_etherdev:
7763 pci_release_selected_regions(pdev,
7764 pci_select_bars(pdev, IORESOURCE_MEM));
7765 err_pci_reg:
7766 err_dma:
7767 pci_disable_device(pdev);
7768 return err;
7769 }
7770
7771 /**
7772 * ixgbe_remove - Device Removal Routine
7773 * @pdev: PCI device information struct
7774 *
7775 * ixgbe_remove is called by the PCI subsystem to alert the driver
7776 * that it should release a PCI device. The could be caused by a
7777 * Hot-Plug event, or because the driver is going to be removed from
7778 * memory.
7779 **/
7780 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7781 {
7782 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7783 struct net_device *netdev = adapter->netdev;
7784
7785 set_bit(__IXGBE_DOWN, &adapter->state);
7786 cancel_work_sync(&adapter->service_task);
7787
7788 #ifdef CONFIG_IXGBE_DCA
7789 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7790 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7791 dca_remove_requester(&pdev->dev);
7792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7793 }
7794
7795 #endif
7796 #ifdef IXGBE_FCOE
7797 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7798 ixgbe_cleanup_fcoe(adapter);
7799
7800 #endif /* IXGBE_FCOE */
7801
7802 /* remove the added san mac */
7803 ixgbe_del_sanmac_netdev(netdev);
7804
7805 if (netdev->reg_state == NETREG_REGISTERED)
7806 unregister_netdev(netdev);
7807
7808 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7809 ixgbe_disable_sriov(adapter);
7810
7811 ixgbe_clear_interrupt_scheme(adapter);
7812
7813 ixgbe_release_hw_control(adapter);
7814
7815 iounmap(adapter->hw.hw_addr);
7816 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7817 IORESOURCE_MEM));
7818
7819 e_dev_info("complete\n");
7820
7821 free_netdev(netdev);
7822
7823 pci_disable_pcie_error_reporting(pdev);
7824
7825 pci_disable_device(pdev);
7826 }
7827
7828 /**
7829 * ixgbe_io_error_detected - called when PCI error is detected
7830 * @pdev: Pointer to PCI device
7831 * @state: The current pci connection state
7832 *
7833 * This function is called after a PCI bus error affecting
7834 * this device has been detected.
7835 */
7836 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7837 pci_channel_state_t state)
7838 {
7839 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7840 struct net_device *netdev = adapter->netdev;
7841
7842 netif_device_detach(netdev);
7843
7844 if (state == pci_channel_io_perm_failure)
7845 return PCI_ERS_RESULT_DISCONNECT;
7846
7847 if (netif_running(netdev))
7848 ixgbe_down(adapter);
7849 pci_disable_device(pdev);
7850
7851 /* Request a slot reset. */
7852 return PCI_ERS_RESULT_NEED_RESET;
7853 }
7854
7855 /**
7856 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7857 * @pdev: Pointer to PCI device
7858 *
7859 * Restart the card from scratch, as if from a cold-boot.
7860 */
7861 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7862 {
7863 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7864 pci_ers_result_t result;
7865 int err;
7866
7867 if (pci_enable_device_mem(pdev)) {
7868 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7869 result = PCI_ERS_RESULT_DISCONNECT;
7870 } else {
7871 pci_set_master(pdev);
7872 pci_restore_state(pdev);
7873 pci_save_state(pdev);
7874
7875 pci_wake_from_d3(pdev, false);
7876
7877 ixgbe_reset(adapter);
7878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7879 result = PCI_ERS_RESULT_RECOVERED;
7880 }
7881
7882 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7883 if (err) {
7884 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7885 "failed 0x%0x\n", err);
7886 /* non-fatal, continue */
7887 }
7888
7889 return result;
7890 }
7891
7892 /**
7893 * ixgbe_io_resume - called when traffic can start flowing again.
7894 * @pdev: Pointer to PCI device
7895 *
7896 * This callback is called when the error recovery driver tells us that
7897 * its OK to resume normal operation.
7898 */
7899 static void ixgbe_io_resume(struct pci_dev *pdev)
7900 {
7901 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7902 struct net_device *netdev = adapter->netdev;
7903
7904 if (netif_running(netdev)) {
7905 if (ixgbe_up(adapter)) {
7906 e_info(probe, "ixgbe_up failed after reset\n");
7907 return;
7908 }
7909 }
7910
7911 netif_device_attach(netdev);
7912 }
7913
7914 static struct pci_error_handlers ixgbe_err_handler = {
7915 .error_detected = ixgbe_io_error_detected,
7916 .slot_reset = ixgbe_io_slot_reset,
7917 .resume = ixgbe_io_resume,
7918 };
7919
7920 static struct pci_driver ixgbe_driver = {
7921 .name = ixgbe_driver_name,
7922 .id_table = ixgbe_pci_tbl,
7923 .probe = ixgbe_probe,
7924 .remove = __devexit_p(ixgbe_remove),
7925 #ifdef CONFIG_PM
7926 .suspend = ixgbe_suspend,
7927 .resume = ixgbe_resume,
7928 #endif
7929 .shutdown = ixgbe_shutdown,
7930 .err_handler = &ixgbe_err_handler
7931 };
7932
7933 /**
7934 * ixgbe_init_module - Driver Registration Routine
7935 *
7936 * ixgbe_init_module is the first routine called when the driver is
7937 * loaded. All it does is register with the PCI subsystem.
7938 **/
7939 static int __init ixgbe_init_module(void)
7940 {
7941 int ret;
7942 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7943 pr_info("%s\n", ixgbe_copyright);
7944
7945 #ifdef CONFIG_IXGBE_DCA
7946 dca_register_notify(&dca_notifier);
7947 #endif
7948
7949 ret = pci_register_driver(&ixgbe_driver);
7950 return ret;
7951 }
7952
7953 module_init(ixgbe_init_module);
7954
7955 /**
7956 * ixgbe_exit_module - Driver Exit Cleanup Routine
7957 *
7958 * ixgbe_exit_module is called just before the driver is removed
7959 * from memory.
7960 **/
7961 static void __exit ixgbe_exit_module(void)
7962 {
7963 #ifdef CONFIG_IXGBE_DCA
7964 dca_unregister_notify(&dca_notifier);
7965 #endif
7966 pci_unregister_driver(&ixgbe_driver);
7967 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7968 }
7969
7970 #ifdef CONFIG_IXGBE_DCA
7971 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7972 void *p)
7973 {
7974 int ret_val;
7975
7976 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7977 __ixgbe_notify_dca);
7978
7979 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7980 }
7981
7982 #endif /* CONFIG_IXGBE_DCA */
7983
7984 module_exit(ixgbe_exit_module);
7985
7986 /* ixgbe_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree