drivers/staging/gma500/mdfld_dsi_output.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  * jim liu <jim.liu@intel.com>
  25  * Jackie Li<yaodong.li@intel.com>
  26  */
  27
  28 #ifndef __MDFLD_DSI_OUTPUT_H__
  29 #define __MDFLD_DSI_OUTPUT_H__
  30
  31 #include <linux/backlight.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include "psb_drv.h"
  38 #include "psb_intel_drv.h"
  39 #include "psb_intel_reg.h"
  40 #include "power.h"
  41 #include "mdfld_output.h"
  42
  43 #include <asm/mrst.h>
  44
  45 #define DRM_MODE_ENCODER_MIPI  5
  46
  47 /* Medfield DSI controller registers */
  48
  49 #define MIPIA_DEVICE_READY_REG                          0xb000
  50 #define MIPIA_INTR_STAT_REG                             0xb004
  51 #define MIPIA_INTR_EN_REG                               0xb008
  52 #define MIPIA_DSI_FUNC_PRG_REG                          0xb00c
  53 #define MIPIA_HS_TX_TIMEOUT_REG                         0xb010
  54 #define MIPIA_LP_RX_TIMEOUT_REG                         0xb014
  55 #define MIPIA_TURN_AROUND_TIMEOUT_REG                   0xb018
  56 #define MIPIA_DEVICE_RESET_TIMER_REG                    0xb01c
  57 #define MIPIA_DPI_RESOLUTION_REG                        0xb020
  58 #define MIPIA_DBI_FIFO_THROTTLE_REG                     0xb024
  59 #define MIPIA_HSYNC_COUNT_REG                           0xb028
  60 #define MIPIA_HBP_COUNT_REG                             0xb02c
  61 #define MIPIA_HFP_COUNT_REG                             0xb030
  62 #define MIPIA_HACTIVE_COUNT_REG                         0xb034
  63 #define MIPIA_VSYNC_COUNT_REG                           0xb038
  64 #define MIPIA_VBP_COUNT_REG                             0xb03c
  65 #define MIPIA_VFP_COUNT_REG                             0xb040
  66 #define MIPIA_HIGH_LOW_SWITCH_COUNT_REG                 0xb044
  67 #define MIPIA_DPI_CONTROL_REG                           0xb048
  68 #define MIPIA_DPI_DATA_REG                              0xb04c
  69 #define MIPIA_INIT_COUNT_REG                            0xb050
  70 #define MIPIA_MAX_RETURN_PACK_SIZE_REG                  0xb054
  71 #define MIPIA_VIDEO_MODE_FORMAT_REG                     0xb058
  72 #define MIPIA_EOT_DISABLE_REG                           0xb05c
  73 #define MIPIA_LP_BYTECLK_REG                            0xb060
  74 #define MIPIA_LP_GEN_DATA_REG                           0xb064
  75 #define MIPIA_HS_GEN_DATA_REG                           0xb068
  76 #define MIPIA_LP_GEN_CTRL_REG                           0xb06c
  77 #define MIPIA_HS_GEN_CTRL_REG                           0xb070
  78 #define MIPIA_GEN_FIFO_STAT_REG                         0xb074
  79 #define MIPIA_HS_LS_DBI_ENABLE_REG                      0xb078
  80 #define MIPIA_DPHY_PARAM_REG                            0xb080
  81 #define MIPIA_DBI_BW_CTRL_REG                           0xb084
  82 #define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG              0xb088
  83
  84 #define DSI_DEVICE_READY                                (0x1)
  85 #define DSI_POWER_STATE_ULPS_ENTER                      (0x2 << 1)
  86 #define DSI_POWER_STATE_ULPS_EXIT                       (0x1 << 1)
  87 #define DSI_POWER_STATE_ULPS_OFFSET                     (0x1)
  88
  89
  90 #define DSI_ONE_DATA_LANE                               (0x1)
  91 #define DSI_TWO_DATA_LANE                               (0x2)
  92 #define DSI_THREE_DATA_LANE                             (0X3)
  93 #define DSI_FOUR_DATA_LANE                              (0x4)
  94 #define DSI_DPI_VIRT_CHANNEL_OFFSET                     (0x3)
  95 #define DSI_DBI_VIRT_CHANNEL_OFFSET                     (0x5)
  96 #define DSI_DPI_COLOR_FORMAT_RGB565                     (0x01 << 7)
  97 #define DSI_DPI_COLOR_FORMAT_RGB666                     (0x02 << 7)
  98 #define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK              (0x03 << 7)
  99 #define DSI_DPI_COLOR_FORMAT_RGB888                     (0x04 << 7)
 100 #define DSI_DBI_COLOR_FORMAT_OPTION2                    (0x05 << 13)
 101
 102 #define DSI_INTR_STATE_RXSOTERROR                       1
 103
 104 #define DSI_INTR_STATE_SPL_PKG_SENT                     (1 << 30)
 105 #define DSI_INTR_STATE_TE                               (1 << 31)
 106
 107 #define DSI_HS_TX_TIMEOUT_MASK                          (0xffffff)
 108
 109 #define DSI_LP_RX_TIMEOUT_MASK                          (0xffffff)
 110
 111 #define DSI_TURN_AROUND_TIMEOUT_MASK                    (0x3f)
 112
 113 #define DSI_RESET_TIMER_MASK                            (0xffff)
 114
 115 #define DSI_DBI_FIFO_WM_HALF                            (0x0)
 116 #define DSI_DBI_FIFO_WM_QUARTER                         (0x1)
 117 #define DSI_DBI_FIFO_WM_LOW                             (0x2)
 118
 119 #define DSI_DPI_TIMING_MASK                             (0xffff)
 120
 121 #define DSI_INIT_TIMER_MASK                             (0xffff)
 122
 123 #define DSI_DBI_RETURN_PACK_SIZE_MASK                   (0x3ff)
 124
 125 #define DSI_LP_BYTECLK_MASK                             (0x0ffff)
 126
 127 #define DSI_HS_CTRL_GEN_SHORT_W0                        (0x03)
 128 #define DSI_HS_CTRL_GEN_SHORT_W1                        (0x13)
 129 #define DSI_HS_CTRL_GEN_SHORT_W2                        (0x23)
 130 #define DSI_HS_CTRL_GEN_R0                              (0x04)
 131 #define DSI_HS_CTRL_GEN_R1                              (0x14)
 132 #define DSI_HS_CTRL_GEN_R2                              (0x24)
 133 #define DSI_HS_CTRL_GEN_LONG_W                          (0x29)
 134 #define DSI_HS_CTRL_MCS_SHORT_W0                        (0x05)
 135 #define DSI_HS_CTRL_MCS_SHORT_W1                        (0x15)
 136 #define DSI_HS_CTRL_MCS_R0                              (0x06)
 137 #define DSI_HS_CTRL_MCS_LONG_W                          (0x39)
 138 #define DSI_HS_CTRL_VC_OFFSET                           (0x06)
 139 #define DSI_HS_CTRL_WC_OFFSET                           (0x08)
 140
 141 #define DSI_FIFO_GEN_HS_DATA_FULL                       (1 << 0)
 142 #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY                 (1 << 1)
 143 #define DSI_FIFO_GEN_HS_DATA_EMPTY                      (1 << 2)
 144 #define DSI_FIFO_GEN_LP_DATA_FULL                       (1 << 8)
 145 #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY                 (1 << 9)
 146 #define DSI_FIFO_GEN_LP_DATA_EMPTY                      (1 << 10)
 147 #define DSI_FIFO_GEN_HS_CTRL_FULL                       (1 << 16)
 148 #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY                 (1 << 17)
 149 #define DSI_FIFO_GEN_HS_CTRL_EMPTY                      (1 << 18)
 150 #define DSI_FIFO_GEN_LP_CTRL_FULL                       (1 << 24)
 151 #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY                 (1 << 25)
 152 #define DSI_FIFO_GEN_LP_CTRL_EMPTY                      (1 << 26)
 153 #define DSI_FIFO_DBI_EMPTY                              (1 << 27)
 154 #define DSI_FIFO_DPI_EMPTY                              (1 << 28)
 155
 156 #define DSI_DBI_HS_LP_SWITCH_MASK                       (0x1)
 157
 158 #define DSI_HS_LP_SWITCH_COUNTER_OFFSET                 (0x0)
 159 #define DSI_LP_HS_SWITCH_COUNTER_OFFSET                 (0x16)
 160
 161 #define DSI_DPI_CTRL_HS_SHUTDOWN                        (0x00000001)
 162 #define DSI_DPI_CTRL_HS_TURN_ON                         (0x00000002)
 163
 164 /* Medfield DSI adapter registers */
 165 #define MIPIA_CONTROL_REG                               0xb104
 166 #define MIPIA_DATA_ADD_REG                              0xb108
 167 #define MIPIA_DATA_LEN_REG                              0xb10c
 168 #define MIPIA_CMD_ADD_REG                               0xb110
 169 #define MIPIA_CMD_LEN_REG                               0xb114
 170
 171 enum {
 172         MDFLD_DSI_ENCODER_DBI = 0,
 173         MDFLD_DSI_ENCODER_DPI,
 174 };
 175
 176 enum {
 177         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
 178         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
 179         MDFLD_DSI_VIDEO_BURST_MODE = 3,
 180 };
 181
 182 #define DSI_DPI_COMPLETE_LAST_LINE                      (1 << 2)
 183 #define DSI_DPI_DISABLE_BTA                             (1 << 3)
 184
 185 struct mdfld_dsi_connector_state {
 186         u32 mipi_ctrl_reg;
 187 };
 188
 189 struct mdfld_dsi_encoder_state {
 190
 191 };
 192
 193 struct mdfld_dsi_connector {
 194         /*
 195          * This is ugly, but I have to use connector in it! :-(
 196          * FIXME: use drm_connector instead.
 197          */
 198         struct psb_intel_output base;
 199
 200         int pipe;
 201         void *private;
 202         void *pkg_sender;
 203 };
 204
 205 struct mdfld_dsi_encoder {
 206         struct drm_encoder base;
 207         void *private;
 208 };
 209
 210 /*
 211  * DSI config, consists of one DSI connector, two DSI encoders.
 212  * DRM will pick up on DSI encoder basing on differents configs.
 213  */
 214 struct mdfld_dsi_config {
 215         struct drm_device *dev;
 216         struct drm_display_mode *fixed_mode;
 217         struct drm_display_mode *mode;
 218
 219         struct mdfld_dsi_connector *connector;
 220         struct mdfld_dsi_encoder *encoders[DRM_CONNECTOR_MAX_ENCODER];
 221         struct mdfld_dsi_encoder *encoder;
 222
 223         int changed;
 224
 225         int bpp;
 226         int type;
 227         int lane_count;
 228         /*Virtual channel number for this encoder*/
 229         int channel_num;
 230         /*video mode configure*/
 231         int video_mode;
 232
 233         int dvr_ic_inited;
 234 };
 235
 236 #define MDFLD_DSI_CONNECTOR(psb_output) \
 237                 (container_of(psb_output, struct mdfld_dsi_connector, base))
 238
 239 #define MDFLD_DSI_ENCODER(encoder) \
 240                 (container_of(encoder, struct mdfld_dsi_encoder, base))
 241
 242 static inline struct mdfld_dsi_config *
 243         mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
 244 {
 245         if (!connector)
 246                 return NULL;
 247         return (struct mdfld_dsi_config *)connector->private;
 248 }
 249
 250 static inline void *mdfld_dsi_get_pkg_sender(struct mdfld_dsi_config *config)
 251 {
 252         struct mdfld_dsi_connector *dsi_connector;
 253
 254         if (!config)
 255                 return NULL;
 256
 257         dsi_connector = config->connector;
 258
 259         if (!dsi_connector)
 260                 return NULL;
 261
 262         return dsi_connector->pkg_sender;
 263 }
 264
 265 static inline struct mdfld_dsi_config *
 266         mdfld_dsi_encoder_get_config(struct mdfld_dsi_encoder *encoder)
 267 {
 268         if (!encoder)
 269                 return NULL;
 270         return (struct mdfld_dsi_config *)encoder->private;
 271 }
 272
 273 static inline struct mdfld_dsi_connector *
 274         mdfld_dsi_encoder_get_connector(struct mdfld_dsi_encoder *encoder)
 275 {
 276         struct mdfld_dsi_config *config;
 277
 278         if (!encoder)
 279                 return NULL;
 280
 281         config = mdfld_dsi_encoder_get_config(encoder);
 282         if (!config)
 283                 return NULL;
 284
 285         return config->connector;
 286 }
 287
 288 static inline void *mdfld_dsi_encoder_get_pkg_sender(
 289         struct mdfld_dsi_encoder *encoder)
 290 {
 291         struct mdfld_dsi_config *dsi_config;
 292
 293         dsi_config = mdfld_dsi_encoder_get_config(encoder);
 294         if (!dsi_config)
 295                 return NULL;
 296
 297         return mdfld_dsi_get_pkg_sender(dsi_config);
 298 }
 299
 300 static inline int mdfld_dsi_encoder_get_pipe(struct mdfld_dsi_encoder *encoder)
 301 {
 302         struct mdfld_dsi_connector *connector;
 303
 304         if (!encoder)
 305                 return -1;
 306
 307         connector = mdfld_dsi_encoder_get_connector(encoder);
 308         if (!connector)
 309                 return -1;
 310
 311         return connector->pipe;
 312 }
 313
 314 extern void mdfld_dsi_gen_fifo_ready(struct drm_device *dev,
 315                                 u32 gen_fifo_stat_reg, u32 fifo_stat);
 316 extern void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config,
 317                                 int pipe);
 318 extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
 319                                 int level);
 320 extern void mdfld_dsi_output_init(struct drm_device *dev, int pipe,
 321                                 struct mdfld_dsi_config *config,
 322                                 struct panel_funcs *p_cmd_funcs,
 323                                 struct panel_funcs *p_vid_funcs);
 324 extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
 325                                 int pipe);
 326
 327 #endif /*__MDFLD_DSI_OUTPUT_H__*/