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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / sh_mobile_hdmi.c
blobe7594e145c96561ef221165f8ff9a6862d7dfd2a
1 /*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28
29 #include <video/sh_mobile_hdmi.h>
30 #include <video/sh_mobile_lcdc.h>
31
32 #include "sh_mobile_lcdcfb.h"
33
34 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
36 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
40 bits 19..16 of Internal CTS */
41 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
42 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
43 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
44 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
45 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
46 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
47 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
48 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
49 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
50 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
51 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
52 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
55 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
57 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
58 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
59 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
60
61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
63
64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
65 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
66 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
67 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
68 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
69 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
70 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
71 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
72 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
73 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
74 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
75 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
76 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
77 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
78 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
80 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
81 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
82 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
83 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
84 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
98 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
133 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
134 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
135 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
136 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
137 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
138 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
139 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
140 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
141 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
142 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
144 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
145 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
146 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
147 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
148 #define HDMI_SHA0 0xB9 /* sha0 */
149 #define HDMI_SHA1 0xBA /* sha1 */
150 #define HDMI_SHA2 0xBB /* sha2 */
151 #define HDMI_SHA3 0xBC /* sha3 */
152 #define HDMI_SHA4 0xBD /* sha4 */
153 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
154 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
155 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
156 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
157 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
158 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
159 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
160 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
161 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
162 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
163 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
164 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
165 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
166 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
167 #define HDMI_AN_SEED 0xCC /* An seed */
168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
171 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
172 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
174 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
175 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
176 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
177 #define HDMI_PJ 0xD7 /* Pj */
178 #define HDMI_SHA_RD 0xD8 /* sha_rd */
179 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
180 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
181 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
182 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
183 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
184 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
185 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
186 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
187 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
188 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
189 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
190 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
191 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
192 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
193 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
194 #define HDMI_AN_23_16 0xEA /* An [23:16] */
195 #define HDMI_AN_31_24 0xEB /* An [31:24] */
196 #define HDMI_AN_39_32 0xEC /* An [39:32] */
197 #define HDMI_AN_47_40 0xED /* An [47:40] */
198 #define HDMI_AN_55_48 0xEE /* An [55:48] */
199 #define HDMI_AN_63_56 0xEF /* An [63:56] */
200 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
201 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
202 #define HDMI_TEST_MODE 0xFE /* Test mode */
203
204 enum hotplug_state {
205 HDMI_HOTPLUG_DISCONNECTED,
206 HDMI_HOTPLUG_CONNECTED,
207 HDMI_HOTPLUG_EDID_DONE,
208 };
209
210 struct sh_hdmi {
211 void __iomem *base;
212 enum hotplug_state hp_state; /* hot-plug status */
213 u8 preprogrammed_vic; /* use a pre-programmed VIC or
214 the external mode */
215 u8 edid_block_addr;
216 u8 edid_segment_nr;
217 u8 edid_blocks;
218 struct clk *hdmi_clk;
219 struct device *dev;
220 struct fb_info *info;
221 struct mutex mutex; /* Protect the info pointer */
222 struct delayed_work edid_work;
223 struct fb_var_screeninfo var;
224 struct fb_monspecs monspec;
225 };
226
227 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
228 {
229 iowrite8(data, hdmi->base + reg);
230 }
231
232 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
233 {
234 return ioread8(hdmi->base + reg);
235 }
236
237 /*
238 * HDMI sound
239 */
240 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
241 unsigned int reg)
242 {
243 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
244
245 return hdmi_read(hdmi, reg);
246 }
247
248 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
249 unsigned int reg,
250 unsigned int value)
251 {
252 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
253
254 hdmi_write(hdmi, value, reg);
255 return 0;
256 }
257
258 static struct snd_soc_dai_driver sh_hdmi_dai = {
259 .name = "sh_mobile_hdmi-hifi",
260 .playback = {
261 .stream_name = "Playback",
262 .channels_min = 2,
263 .channels_max = 8,
264 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
265 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
266 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
267 SNDRV_PCM_RATE_192000,
268 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
269 },
270 };
271
272 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
273 {
274 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
275
276 return 0;
277 }
278
279 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
280 .probe = sh_hdmi_snd_probe,
281 .read = sh_hdmi_snd_read,
282 .write = sh_hdmi_snd_write,
283 };
284
285 /*
286 * HDMI video
287 */
288
289 /* External video parameter settings */
290 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
291 {
292 struct fb_var_screeninfo *var = &hdmi->var;
293 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
294 u8 sync = 0;
295
296 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
297
298 hdelay = var->hsync_len + var->left_margin;
299 hblank = var->right_margin + hdelay;
300
301 /*
302 * Vertical timing looks a bit different in Figure 18,
303 * but let's try the same first by setting offset = 0
304 */
305 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
306
307 vdelay = var->vsync_len + var->upper_margin;
308 vblank = var->lower_margin + vdelay;
309 voffset = min(var->upper_margin / 2, 6U);
310
311 /*
312 * [3]: VSYNC polarity: Positive
313 * [2]: HSYNC polarity: Positive
314 * [1]: Interlace/Progressive: Progressive
315 * [0]: External video settings enable: used.
316 */
317 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
318 sync |= 4;
319 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
320 sync |= 8;
321
322 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
323 htotal, hblank, hdelay, var->hsync_len,
324 vtotal, vblank, vdelay, var->vsync_len, sync);
325
326 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
327
328 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
329 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
330
331 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
332 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
333
334 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
335 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
336
337 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
338 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
339
340 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
341 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
342
343 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
344
345 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
346
347 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
348
349 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
350 if (!hdmi->preprogrammed_vic)
351 hdmi_write(hdmi, sync | 1 | (voffset << 4),
352 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
353 }
354
355 /**
356 * sh_hdmi_video_config()
357 */
358 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
359 {
360 /*
361 * [7:4]: Audio sampling frequency: 48kHz
362 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
363 * [0]: Internal/External DE select: internal
364 */
365 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
366
367 /*
368 * [7:6]: Video output format: RGB 4:4:4
369 * [5:4]: Input video data width: 8 bit
370 * [3:1]: EAV/SAV location: channel 1
371 * [0]: Video input color space: RGB
372 */
373 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
374
375 /*
376 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
377 * left at 0 by default, this configures 24bpp and sets the Color Depth
378 * (CD) field in the General Control Packet
379 */
380 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
381 }
382
383 /**
384 * sh_hdmi_audio_config()
385 */
386 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
387 {
388 u8 data;
389 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
390
391 /*
392 * [7:4] L/R data swap control
393 * [3:0] appropriate N[19:16]
394 */
395 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
396 /* appropriate N[15:8] */
397 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
398 /* appropriate N[7:0] */
399 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
400
401 /* [7:4] 48 kHz SPDIF not used */
402 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
403
404 /*
405 * [6:5] set required down sampling rate if required
406 * [4:3] set required audio source
407 */
408 switch (pdata->flags & HDMI_SND_SRC_MASK) {
409 default:
410 /* fall through */
411 case HDMI_SND_SRC_I2S:
412 data = 0x0 << 3;
413 break;
414 case HDMI_SND_SRC_SPDIF:
415 data = 0x1 << 3;
416 break;
417 case HDMI_SND_SRC_DSD:
418 data = 0x2 << 3;
419 break;
420 case HDMI_SND_SRC_HBR:
421 data = 0x3 << 3;
422 break;
423 }
424 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
425
426 /* [3:0] set sending channel number for channel status */
427 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
428
429 /*
430 * [5:2] set valid I2S source input pin
431 * [1:0] set input I2S source mode
432 */
433 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
434
435 /* [7:4] set valid DSD source input pin */
436 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
437
438 /* [7:0] set appropriate I2S input pin swap settings if required */
439 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
440
441 /*
442 * [7] set validity bit for channel status
443 * [3:0] set original sample frequency for channel status
444 */
445 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
446
447 /*
448 * [7] set value for channel status
449 * [6] set value for channel status
450 * [5] set copyright bit for channel status
451 * [4:2] set additional information for channel status
452 * [1:0] set clock accuracy for channel status
453 */
454 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
455
456 /* [7:0] set category code for channel status */
457 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
458
459 /*
460 * [7:4] set source number for channel status
461 * [3:0] set word length for channel status
462 */
463 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
464
465 /* [7:4] set sample frequency for channel status */
466 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
467 }
468
469 /**
470 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
471 */
472 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
473 {
474 if (hdmi->var.pixclock < 10000) {
475 /* for 1080p8bit 148MHz */
476 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
477 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
478 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
479 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
480 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
481 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
482 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
483 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
484 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
485 } else if (hdmi->var.pixclock < 30000) {
486 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
487 /*
488 * [1:0] Speed_A
489 * [3:2] Speed_B
490 * [4] PLLA_Bypass
491 * [6] DRV_TEST_EN
492 * [7] DRV_TEST_IN
493 */
494 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
495 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
496 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
497 /*
498 * [2:0] BGR_I_OFFSET
499 * [6:4] BGR_V_OFFSET
500 */
501 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
502 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
503 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
504 /*
505 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
506 * LPF capacitance, LPF resistance[1]
507 */
508 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
509 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
510 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
511 /*
512 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
513 * LPF capacitance, LPF resistance[1]
514 */
515 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
516 /* DRV_CONFIG, PE_CONFIG */
517 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
518 /*
519 * [2:0] AMON_SEL (4 == LPF voltage)
520 * [4] PLLA_CONFIG[16]
521 * [5] PLLB_CONFIG[16]
522 */
523 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
524 } else {
525 /* for 480p8bit 27MHz */
526 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
527 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
528 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
529 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
530 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
531 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
532 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
533 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
534 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
535 }
536 }
537
538 /**
539 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
540 */
541 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
542 {
543 u8 vic;
544
545 /* AVI InfoFrame */
546 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
547
548 /* Packet Type = 0x82 */
549 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
550
551 /* Version = 0x02 */
552 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
553
554 /* Length = 13 (0x0D) */
555 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
556
557 /* N. A. Checksum */
558 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
559
560 /*
561 * Y = RGB
562 * A0 = No Data
563 * B = Bar Data not valid
564 * S = No Data
565 */
566 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
567
568 /*
569 * [7:6] C = Colorimetry: no data
570 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
571 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
572 */
573 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
574
575 /*
576 * ITC = No Data
577 * EC = xvYCC601
578 * Q = Default (depends on video format)
579 * SC = No Known non_uniform Scaling
580 */
581 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
582
583 /*
584 * VIC should be ignored if external config is used, so, we could just use 0,
585 * but play safe and use a valid value in any case just in case
586 */
587 if (hdmi->preprogrammed_vic)
588 vic = hdmi->preprogrammed_vic;
589 else
590 vic = 4;
591 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
592
593 /* PR = No Repetition */
594 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
595
596 /* Line Number of End of Top Bar (lower 8 bits) */
597 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
598
599 /* Line Number of End of Top Bar (upper 8 bits) */
600 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
601
602 /* Line Number of Start of Bottom Bar (lower 8 bits) */
603 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
604
605 /* Line Number of Start of Bottom Bar (upper 8 bits) */
606 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
607
608 /* Pixel Number of End of Left Bar (lower 8 bits) */
609 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
610
611 /* Pixel Number of End of Left Bar (upper 8 bits) */
612 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
613
614 /* Pixel Number of Start of Right Bar (lower 8 bits) */
615 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
616
617 /* Pixel Number of Start of Right Bar (upper 8 bits) */
618 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
619 }
620
621 /**
622 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
623 */
624 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
625 {
626 /* Audio InfoFrame */
627 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
628
629 /* Packet Type = 0x84 */
630 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
631
632 /* Version Number = 0x01 */
633 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
634
635 /* 0 Length = 10 (0x0A) */
636 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
637
638 /* n. a. Checksum */
639 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
640
641 /* Audio Channel Count = Refer to Stream Header */
642 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
643
644 /* Refer to Stream Header */
645 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
646
647 /* Format depends on coding type (i.e. CT0...CT3) */
648 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
649
650 /* Speaker Channel Allocation = Front Right + Front Left */
651 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
652
653 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
654 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
655
656 /* Reserved (0) */
657 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
658 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
659 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
660 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
661 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
662 }
663
664 /**
665 * sh_hdmi_configure() - Initialise HDMI for output
666 */
667 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
668 {
669 /* Configure video format */
670 sh_hdmi_video_config(hdmi);
671
672 /* Configure audio format */
673 sh_hdmi_audio_config(hdmi);
674
675 /* Configure PHY */
676 sh_hdmi_phy_config(hdmi);
677
678 /* Auxiliary Video Information (AVI) InfoFrame */
679 sh_hdmi_avi_infoframe_setup(hdmi);
680
681 /* Audio InfoFrame */
682 sh_hdmi_audio_infoframe_setup(hdmi);
683
684 /*
685 * Control packet auto send with VSYNC control: auto send
686 * General control, Gamut metadata, ISRC, and ACP packets
687 */
688 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
689
690 /* FIXME */
691 msleep(10);
692
693 /* PS mode b->d, reset PLLA and PLLB */
694 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
695
696 udelay(10);
697
698 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
699 }
700
701 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
702 const struct fb_videomode *mode,
703 unsigned long *hdmi_rate, unsigned long *parent_rate)
704 {
705 unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
706 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
707
708 *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
709 if ((long)*hdmi_rate < 0)
710 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
711
712 rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
713 if (rate_error && pdata->clk_optimize_parent)
714 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
715 else if (clk_get_parent(hdmi->hdmi_clk))
716 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
717
718 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
719 mode->left_margin, mode->xres,
720 mode->right_margin, mode->hsync_len,
721 mode->upper_margin, mode->yres,
722 mode->lower_margin, mode->vsync_len);
723
724 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
725 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
726 mode->refresh, *parent_rate);
727
728 return rate_error;
729 }
730
731 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
732 unsigned long *parent_rate)
733 {
734 struct fb_var_screeninfo tmpvar;
735 struct fb_var_screeninfo *var = &tmpvar;
736 const struct fb_videomode *mode, *found = NULL;
737 struct fb_info *info = hdmi->info;
738 struct fb_modelist *modelist = NULL;
739 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
740 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
741 bool exact_match = false;
742 u8 edid[128];
743 char *forced;
744 int i;
745
746 /* Read EDID */
747 dev_dbg(hdmi->dev, "Read back EDID code:");
748 for (i = 0; i < 128; i++) {
749 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
750 #ifdef DEBUG
751 if ((i % 16) == 0) {
752 printk(KERN_CONT "\n");
753 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
754 } else {
755 printk(KERN_CONT " %02X", edid[i]);
756 }
757 #endif
758 }
759 #ifdef DEBUG
760 printk(KERN_CONT "\n");
761 #endif
762
763 if (!hdmi->edid_blocks) {
764 fb_edid_to_monspecs(edid, &hdmi->monspec);
765 hdmi->edid_blocks = edid[126] + 1;
766
767 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
768 hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
769 } else {
770 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
771 edid[0], edid[2]);
772 fb_edid_add_monspecs(edid, &hdmi->monspec);
773 }
774
775 if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
776 (hdmi->edid_block_addr >> 7) + 1) {
777 /* More blocks to read */
778 if (hdmi->edid_block_addr) {
779 hdmi->edid_block_addr = 0;
780 hdmi->edid_segment_nr++;
781 } else {
782 hdmi->edid_block_addr = 0x80;
783 }
784 /* Set EDID word address */
785 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
786 /* Enable EDID interrupt */
787 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
788 /* Set EDID segment pointer - starts reading EDID */
789 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
790 return -EAGAIN;
791 }
792
793 /* All E-EDID blocks ready */
794 dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
795
796 fb_get_options("sh_mobile_lcdc", &forced);
797 if (forced && *forced) {
798 /* Only primitive parsing so far */
799 i = sscanf(forced, "%ux%u@%u",
800 &f_width, &f_height, &f_refresh);
801 if (i < 2) {
802 f_width = 0;
803 f_height = 0;
804 }
805 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
806 f_width, f_height, f_refresh);
807 }
808
809 /* Walk monitor modes to find the best or the exact match */
810 for (i = 0, mode = hdmi->monspec.modedb;
811 f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
812 i++, mode++) {
813 unsigned long rate_error;
814
815 /* No interest in unmatching modes */
816 if (f_width != mode->xres || f_height != mode->yres)
817 continue;
818
819 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
820
821 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
822 /*
823 * Exact match if either the refresh rate matches or it
824 * hasn't been specified and we've found a mode, for
825 * which we can configure the clock precisely
826 */
827 exact_match = true;
828 else if (found && found_rate_error <= rate_error)
829 /*
830 * We otherwise search for the closest matching clock
831 * rate - either if no refresh rate has been specified
832 * or we cannot find an exactly matching one
833 */
834 continue;
835
836 /* Check if supported: sufficient fb memory, supported clock-rate */
837 fb_videomode_to_var(var, mode);
838
839 if (info && info->fbops->fb_check_var &&
840 info->fbops->fb_check_var(var, info)) {
841 exact_match = false;
842 continue;
843 }
844
845 found = mode;
846 found_rate_error = rate_error;
847 }
848
849 hdmi->var.width = hdmi->monspec.max_x * 10;
850 hdmi->var.height = hdmi->monspec.max_y * 10;
851
852 /*
853 * TODO 1: if no ->info is present, postpone running the config until
854 * after ->info first gets registered.
855 * TODO 2: consider registering the HDMI platform device from the LCDC
856 * driver, and passing ->info with HDMI platform data.
857 */
858 if (info && !found) {
859 modelist = hdmi->info->modelist.next &&
860 !list_empty(&hdmi->info->modelist) ?
861 list_entry(hdmi->info->modelist.next,
862 struct fb_modelist, list) :
863 NULL;
864
865 if (modelist) {
866 found = &modelist->mode;
867 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
868 }
869 }
870
871 /* No cookie today */
872 if (!found)
873 return -ENXIO;
874
875 if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
876 hdmi->preprogrammed_vic = 1;
877 else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
878 hdmi->preprogrammed_vic = 2;
879 else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
880 hdmi->preprogrammed_vic = 17;
881 else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
882 hdmi->preprogrammed_vic = 4;
883 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
884 hdmi->preprogrammed_vic = 32;
885 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
886 hdmi->preprogrammed_vic = 31;
887 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
888 hdmi->preprogrammed_vic = 16;
889 else
890 hdmi->preprogrammed_vic = 0;
891
892 dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
893 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
894 found->xres, found->yres, found->refresh,
895 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
896
897 fb_videomode_to_var(&hdmi->var, found);
898 sh_hdmi_external_video_param(hdmi);
899
900 return 0;
901 }
902
903 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
904 {
905 struct sh_hdmi *hdmi = dev_id;
906 u8 status1, status2, mask1, mask2;
907
908 /* mode_b and PLLA and PLLB reset */
909 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
910
911 /* How long shall reset be held? */
912 udelay(10);
913
914 /* mode_b and PLLA and PLLB reset release */
915 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
916
917 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
918 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
919
920 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
921 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
922
923 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
924 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
925 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
926
927 if (printk_ratelimit())
928 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
929 irq, status1, mask1, status2, mask2);
930
931 if (!((status1 & mask1) | (status2 & mask2))) {
932 return IRQ_NONE;
933 } else if (status1 & 0xc0) {
934 u8 msens;
935
936 /* Datasheet specifies 10ms... */
937 udelay(500);
938
939 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
940 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
941 /* Check, if hot plug & MSENS pin status are both high */
942 if ((msens & 0xC0) == 0xC0) {
943 /* Display plug in */
944 hdmi->edid_segment_nr = 0;
945 hdmi->edid_block_addr = 0;
946 hdmi->edid_blocks = 0;
947 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
948
949 /* Set EDID word address */
950 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
951 /* Enable EDID interrupt */
952 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
953 /* Set EDID segment pointer - starts reading EDID */
954 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
955 } else if (!(status1 & 0x80)) {
956 /* Display unplug, beware multiple interrupts */
957 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
958 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
959 schedule_delayed_work(&hdmi->edid_work, 0);
960 }
961 /* display_off will switch back to mode_a */
962 }
963 } else if (status1 & 2) {
964 /* EDID error interrupt: retry */
965 /* Set EDID word address */
966 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
967 /* Set EDID segment pointer */
968 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
969 } else if (status1 & 4) {
970 /* Disable EDID interrupt */
971 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
972 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
973 }
974
975 return IRQ_HANDLED;
976 }
977
978 /* locking: called with info->lock held, or before register_framebuffer() */
979 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
980 {
981 /*
982 * info is guaranteed to be valid, when we are called, because our
983 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
984 */
985 struct sh_hdmi *hdmi = arg;
986 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
987 struct sh_mobile_lcdc_chan *ch = info->par;
988
989 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
990 pdata->lcd_dev, info->state);
991
992 /* No need to lock */
993 hdmi->info = info;
994
995 /*
996 * hp_state can be set to
997 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
998 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
999 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
1000 */
1001 switch (hdmi->hp_state) {
1002 case HDMI_HOTPLUG_EDID_DONE:
1003 /* PS mode d->e. All functions are active */
1004 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
1005 dev_dbg(hdmi->dev, "HDMI running\n");
1006 break;
1007 case HDMI_HOTPLUG_DISCONNECTED:
1008 info->state = FBINFO_STATE_SUSPENDED;
1009 default:
1010 hdmi->var = ch->display_var;
1011 }
1012 }
1013
1014 /* locking: called with info->lock held */
1015 static void sh_hdmi_display_off(void *arg)
1016 {
1017 struct sh_hdmi *hdmi = arg;
1018 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1019
1020 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
1021 /* PS mode e->a */
1022 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1023 }
1024
1025 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1026 {
1027 struct fb_info *info = hdmi->info;
1028 struct sh_mobile_lcdc_chan *ch = info->par;
1029 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1030 struct fb_videomode mode1, mode2;
1031
1032 fb_var_to_videomode(&mode1, old_var);
1033 fb_var_to_videomode(&mode2, new_var);
1034
1035 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1036 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1037
1038 if (fb_mode_is_equal(&mode1, &mode2)) {
1039 /* It can be a different monitor with an equal video-mode */
1040 old_var->width = new_var->width;
1041 old_var->height = new_var->height;
1042 return false;
1043 }
1044
1045 dev_dbg(info->dev, "Switching %u -> %u lines\n",
1046 mode1.yres, mode2.yres);
1047 *old_var = *new_var;
1048
1049 return true;
1050 }
1051
1052 /**
1053 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1054 * @hdmi: driver context
1055 * @hdmi_rate: HDMI clock frequency in Hz
1056 * @parent_rate: if != 0 - set parent clock rate for optimal precision
1057 * return: configured positive rate if successful
1058 * 0 if couldn't set the rate, but managed to enable the
1059 * clock, negative error, if couldn't enable the clock
1060 */
1061 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1062 unsigned long parent_rate)
1063 {
1064 int ret;
1065
1066 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1067 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1068 if (ret < 0) {
1069 dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1070 hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1071 } else {
1072 dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1073 }
1074 }
1075
1076 ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1077 if (ret < 0) {
1078 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1079 hdmi_rate = 0;
1080 } else {
1081 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1082 }
1083
1084 return hdmi_rate;
1085 }
1086
1087 /* Hotplug interrupt occurred, read EDID */
1088 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1089 {
1090 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1091 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1092 struct sh_mobile_lcdc_chan *ch;
1093 int ret;
1094
1095 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1096 pdata->lcd_dev, hdmi->hp_state);
1097
1098 if (!pdata->lcd_dev)
1099 return;
1100
1101 mutex_lock(&hdmi->mutex);
1102
1103 if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1104 unsigned long parent_rate = 0, hdmi_rate;
1105
1106 /* A device has been plugged in */
1107 pm_runtime_get_sync(hdmi->dev);
1108
1109 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1110 if (ret < 0)
1111 goto out;
1112
1113 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1114
1115 /* Reconfigure the clock */
1116 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1117 if (ret < 0)
1118 goto out;
1119
1120 msleep(10);
1121 sh_hdmi_configure(hdmi);
1122 /* Switched to another (d) power-save mode */
1123 msleep(10);
1124
1125 if (!hdmi->info)
1126 goto out;
1127
1128 ch = hdmi->info->par;
1129
1130 acquire_console_sem();
1131
1132 /* HDMI plug in */
1133 if (!sh_hdmi_must_reconfigure(hdmi) &&
1134 hdmi->info->state == FBINFO_STATE_RUNNING) {
1135 /*
1136 * First activation with the default monitor - just turn
1137 * on, if we run a resume here, the logo disappears
1138 */
1139 if (lock_fb_info(hdmi->info)) {
1140 struct fb_info *info = hdmi->info;
1141 info->var.width = hdmi->var.width;
1142 info->var.height = hdmi->var.height;
1143 sh_hdmi_display_on(hdmi, info);
1144 unlock_fb_info(info);
1145 }
1146 } else {
1147 /* New monitor or have to wake up */
1148 fb_set_suspend(hdmi->info, 0);
1149 }
1150
1151 release_console_sem();
1152 } else {
1153 ret = 0;
1154 if (!hdmi->info)
1155 goto out;
1156
1157 hdmi->monspec.modedb_len = 0;
1158 fb_destroy_modedb(hdmi->monspec.modedb);
1159 hdmi->monspec.modedb = NULL;
1160
1161 acquire_console_sem();
1162
1163 /* HDMI disconnect */
1164 fb_set_suspend(hdmi->info, 1);
1165
1166 release_console_sem();
1167 pm_runtime_put(hdmi->dev);
1168 }
1169
1170 out:
1171 if (ret < 0 && ret != -EAGAIN)
1172 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1173 mutex_unlock(&hdmi->mutex);
1174
1175 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1176 }
1177
1178 static int sh_hdmi_notify(struct notifier_block *nb,
1179 unsigned long action, void *data);
1180
1181 static struct notifier_block sh_hdmi_notifier = {
1182 .notifier_call = sh_hdmi_notify,
1183 };
1184
1185 static int sh_hdmi_notify(struct notifier_block *nb,
1186 unsigned long action, void *data)
1187 {
1188 struct fb_event *event = data;
1189 struct fb_info *info = event->info;
1190 struct sh_mobile_lcdc_chan *ch = info->par;
1191 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1192 struct sh_hdmi *hdmi = board_cfg->board_data;
1193
1194 if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1195 return NOTIFY_DONE;
1196
1197 switch(action) {
1198 case FB_EVENT_FB_REGISTERED:
1199 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1200 break;
1201 case FB_EVENT_FB_UNREGISTERED:
1202 /*
1203 * We are called from unregister_framebuffer() with the
1204 * info->lock held. This is bad for us, because we can race with
1205 * the scheduled work, which has to call fb_set_suspend(), which
1206 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1207 * cannot take and hold info->lock for the whole function
1208 * duration. Using an additional lock creates a classical AB-BA
1209 * lock up. Therefore, we have to release the info->lock
1210 * temporarily, synchronise with the work queue and re-acquire
1211 * the info->lock.
1212 */
1213 unlock_fb_info(hdmi->info);
1214 mutex_lock(&hdmi->mutex);
1215 hdmi->info = NULL;
1216 mutex_unlock(&hdmi->mutex);
1217 lock_fb_info(hdmi->info);
1218 return NOTIFY_OK;
1219 }
1220 return NOTIFY_DONE;
1221 }
1222
1223 static int __init sh_hdmi_probe(struct platform_device *pdev)
1224 {
1225 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1226 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227 struct sh_mobile_lcdc_board_cfg *board_cfg;
1228 int irq = platform_get_irq(pdev, 0), ret;
1229 struct sh_hdmi *hdmi;
1230 long rate;
1231
1232 if (!res || !pdata || irq < 0)
1233 return -ENODEV;
1234
1235 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1236 if (!hdmi) {
1237 dev_err(&pdev->dev, "Cannot allocate device data\n");
1238 return -ENOMEM;
1239 }
1240
1241 mutex_init(&hdmi->mutex);
1242
1243 hdmi->dev = &pdev->dev;
1244
1245 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1246 if (IS_ERR(hdmi->hdmi_clk)) {
1247 ret = PTR_ERR(hdmi->hdmi_clk);
1248 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1249 goto egetclk;
1250 }
1251
1252 /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1253 rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1254 if (rate > 0)
1255 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1256
1257 if (rate < 0) {
1258 ret = rate;
1259 goto erate;
1260 }
1261
1262 ret = clk_enable(hdmi->hdmi_clk);
1263 if (ret < 0) {
1264 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1265 goto erate;
1266 }
1267
1268 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1269
1270 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1271 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1272 ret = -EBUSY;
1273 goto ereqreg;
1274 }
1275
1276 hdmi->base = ioremap(res->start, resource_size(res));
1277 if (!hdmi->base) {
1278 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1279 ret = -ENOMEM;
1280 goto emap;
1281 }
1282
1283 platform_set_drvdata(pdev, hdmi);
1284
1285 /* Set up LCDC callbacks */
1286 board_cfg = &pdata->lcd_chan->board_cfg;
1287 board_cfg->owner = THIS_MODULE;
1288 board_cfg->board_data = hdmi;
1289 board_cfg->display_on = sh_hdmi_display_on;
1290 board_cfg->display_off = sh_hdmi_display_off;
1291
1292 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1293
1294 pm_runtime_enable(&pdev->dev);
1295 pm_runtime_resume(&pdev->dev);
1296
1297 /* Product and revision IDs are 0 in sh-mobile version */
1298 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1299 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1300
1301 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1302 dev_name(&pdev->dev), hdmi);
1303 if (ret < 0) {
1304 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1305 goto ereqirq;
1306 }
1307
1308 ret = snd_soc_register_codec(&pdev->dev,
1309 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1310 if (ret < 0) {
1311 dev_err(&pdev->dev, "codec registration failed\n");
1312 goto ecodec;
1313 }
1314
1315 return 0;
1316
1317 ecodec:
1318 free_irq(irq, hdmi);
1319 ereqirq:
1320 pm_runtime_disable(&pdev->dev);
1321 iounmap(hdmi->base);
1322 emap:
1323 release_mem_region(res->start, resource_size(res));
1324 ereqreg:
1325 clk_disable(hdmi->hdmi_clk);
1326 erate:
1327 clk_put(hdmi->hdmi_clk);
1328 egetclk:
1329 mutex_destroy(&hdmi->mutex);
1330 kfree(hdmi);
1331
1332 return ret;
1333 }
1334
1335 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1336 {
1337 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1338 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1339 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1340 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1341 int irq = platform_get_irq(pdev, 0);
1342
1343 snd_soc_unregister_codec(&pdev->dev);
1344
1345 board_cfg->display_on = NULL;
1346 board_cfg->display_off = NULL;
1347 board_cfg->board_data = NULL;
1348 board_cfg->owner = NULL;
1349
1350 /* No new work will be scheduled, wait for running ISR */
1351 free_irq(irq, hdmi);
1352 /* Wait for already scheduled work */
1353 cancel_delayed_work_sync(&hdmi->edid_work);
1354 pm_runtime_disable(&pdev->dev);
1355 clk_disable(hdmi->hdmi_clk);
1356 clk_put(hdmi->hdmi_clk);
1357 iounmap(hdmi->base);
1358 release_mem_region(res->start, resource_size(res));
1359 mutex_destroy(&hdmi->mutex);
1360 kfree(hdmi);
1361
1362 return 0;
1363 }
1364
1365 static struct platform_driver sh_hdmi_driver = {
1366 .remove = __exit_p(sh_hdmi_remove),
1367 .driver = {
1368 .name = "sh-mobile-hdmi",
1369 },
1370 };
1371
1372 static int __init sh_hdmi_init(void)
1373 {
1374 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1375 }
1376 module_init(sh_hdmi_init);
1377
1378 static void __exit sh_hdmi_exit(void)
1379 {
1380 platform_driver_unregister(&sh_hdmi_driver);
1381 }
1382 module_exit(sh_hdmi_exit);
1383
1384 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1385 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1386 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree