drivers/staging/brcm80211/include/pci_core.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _PCI_CORE_H_
  18 #define _PCI_CORE_H_
  19
  20 #ifndef _LANGUAGE_ASSEMBLY
  21
  22 /* cpp contortions to concatenate w/arg prescan */
  23 #ifndef PAD
  24 #define _PADLINE(line)  pad ## line
  25 #define _XSTR(line)     _PADLINE(line)
  26 #define PAD             _XSTR(__LINE__)
  27 #endif
  28
  29 /* Sonics side: PCI core and host control registers */
  30 typedef struct sbpciregs {
  31         u32 control;            /* PCI control */
  32         u32 PAD[3];
  33         u32 arbcontrol; /* PCI arbiter control */
  34         u32 clkrun;             /* Clkrun Control (>=rev11) */
  35         u32 PAD[2];
  36         u32 intstatus;  /* Interrupt status */
  37         u32 intmask;            /* Interrupt mask */
  38         u32 sbtopcimailbox;     /* Sonics to PCI mailbox */
  39         u32 PAD[9];
  40         u32 bcastaddr;  /* Sonics broadcast address */
  41         u32 bcastdata;  /* Sonics broadcast data */
  42         u32 PAD[2];
  43         u32 gpioin;             /* ro: gpio input (>=rev2) */
  44         u32 gpioout;            /* rw: gpio output (>=rev2) */
  45         u32 gpioouten;  /* rw: gpio output enable (>= rev2) */
  46         u32 gpiocontrol;        /* rw: gpio control (>= rev2) */
  47         u32 PAD[36];
  48         u32 sbtopci0;   /* Sonics to PCI translation 0 */
  49         u32 sbtopci1;   /* Sonics to PCI translation 1 */
  50         u32 sbtopci2;   /* Sonics to PCI translation 2 */
  51         u32 PAD[189];
  52         u32 pcicfg[4][64];      /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
  53         u16 sprom[36];  /* SPROM shadow Area */
  54         u32 PAD[46];
  55 } sbpciregs_t;
  56
  57 #endif                          /* _LANGUAGE_ASSEMBLY */
  58
  59 /* PCI control */
  60 #define PCI_RST_OE      0x01    /* When set, drives PCI_RESET out to pin */
  61 #define PCI_RST         0x02    /* Value driven out to pin */
  62 #define PCI_CLK_OE      0x04    /* When set, drives clock as gated by PCI_CLK out to pin */
  63 #define PCI_CLK         0x08    /* Gate for clock driven out to pin */
  64
  65 /* PCI arbiter control */
  66 #define PCI_INT_ARB     0x01    /* When set, use an internal arbiter */
  67 #define PCI_EXT_ARB     0x02    /* When set, use an external arbiter */
  68 /* ParkID - for PCI corerev >= 8 */
  69 #define PCI_PARKID_MASK         0x1c    /* Selects which agent is parked on an idle bus */
  70 #define PCI_PARKID_SHIFT        2
  71 #define PCI_PARKID_EXT0         0       /* External master 0 */
  72 #define PCI_PARKID_EXT1         1       /* External master 1 */
  73 #define PCI_PARKID_EXT2         2       /* External master 2 */
  74 #define PCI_PARKID_EXT3         3       /* External master 3 (rev >= 11) */
  75 #define PCI_PARKID_INT          3       /* Internal master (rev < 11) */
  76 #define PCI11_PARKID_INT        4       /* Internal master (rev >= 11) */
  77 #define PCI_PARKID_LAST         4       /* Last active master (rev < 11) */
  78 #define PCI11_PARKID_LAST       5       /* Last active master (rev >= 11) */
  79
  80 #define PCI_CLKRUN_DSBL 0x8000  /* Bit 15 forceClkrun */
  81
  82 /* Interrupt status/mask */
  83 #define PCI_INTA        0x01    /* PCI INTA# is asserted */
  84 #define PCI_INTB        0x02    /* PCI INTB# is asserted */
  85 #define PCI_SERR        0x04    /* PCI SERR# has been asserted (write one to clear) */
  86 #define PCI_PERR        0x08    /* PCI PERR# has been asserted (write one to clear) */
  87 #define PCI_PME         0x10    /* PCI PME# is asserted */
  88
  89 /* (General) PCI/SB mailbox interrupts, two bits per pci function */
  90 #define MAILBOX_F0_0    0x100   /* function 0, int 0 */
  91 #define MAILBOX_F0_1    0x200   /* function 0, int 1 */
  92 #define MAILBOX_F1_0    0x400   /* function 1, int 0 */
  93 #define MAILBOX_F1_1    0x800   /* function 1, int 1 */
  94 #define MAILBOX_F2_0    0x1000  /* function 2, int 0 */
  95 #define MAILBOX_F2_1    0x2000  /* function 2, int 1 */
  96 #define MAILBOX_F3_0    0x4000  /* function 3, int 0 */
  97 #define MAILBOX_F3_1    0x8000  /* function 3, int 1 */
  98
  99 /* Sonics broadcast address */
 100 #define BCAST_ADDR_MASK 0xff    /* Broadcast register address */
 101
 102 /* Sonics to PCI translation types */
 103 #define SBTOPCI0_MASK   0xfc000000
 104 #define SBTOPCI1_MASK   0xfc000000
 105 #define SBTOPCI2_MASK   0xc0000000
 106 #define SBTOPCI_MEM     0
 107 #define SBTOPCI_IO      1
 108 #define SBTOPCI_CFG0    2
 109 #define SBTOPCI_CFG1    3
 110 #define SBTOPCI_PREF    0x4     /* prefetch enable */
 111 #define SBTOPCI_BURST   0x8     /* burst enable */
 112 #define SBTOPCI_RC_MASK         0x30    /* read command (>= rev11) */
 113 #define SBTOPCI_RC_READ         0x00    /* memory read */
 114 #define SBTOPCI_RC_READLINE     0x10    /* memory read line */
 115 #define SBTOPCI_RC_READMULTI    0x20    /* memory read multiple */
 116
 117 /* PCI core index in SROM shadow area */
 118 #define SRSH_PI_OFFSET  0       /* first word */
 119 #define SRSH_PI_MASK    0xf000  /* bit 15:12 */
 120 #define SRSH_PI_SHIFT   12      /* bit 15:12 */
 121
 122 #endif                          /* _PCI_CORE_H_ */