2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
41 #include <asm/processor.h>
45 #include "mce-internal.h"
47 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
49 #define rcu_dereference_check_mce(p) \
50 rcu_dereference_index_check((p), \
51 rcu_read_lock_sched_held() || \
52 lockdep_is_held(&mce_chrdev_read_mutex))
54 #define CREATE_TRACE_POINTS
55 #include <trace/events/mce.h>
57 int mce_disabled __read_mostly
;
59 #define MISC_MCELOG_MINOR 227
61 #define SPINUNIT 100 /* 100ns */
65 DEFINE_PER_CPU(unsigned, mce_exception_count
);
69 * 0: always panic on uncorrected errors, log corrected errors
70 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
71 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
72 * 3: never panic or SIGBUS, log all errors (for testing only)
74 static int tolerant __read_mostly
= 1;
75 static int banks __read_mostly
;
76 static int rip_msr __read_mostly
;
77 static int mce_bootlog __read_mostly
= -1;
78 static int monarch_timeout __read_mostly
= -1;
79 static int mce_panic_timeout __read_mostly
;
80 static int mce_dont_log_ce __read_mostly
;
81 int mce_cmci_disabled __read_mostly
;
82 int mce_ignore_ce __read_mostly
;
83 int mce_ser __read_mostly
;
85 struct mce_bank
*mce_banks __read_mostly
;
87 /* User mode helper program triggered by machine check event */
88 static unsigned long mce_need_notify
;
89 static char mce_helper
[128];
90 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
92 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
94 static DEFINE_PER_CPU(struct mce
, mces_seen
);
95 static int cpu_missing
;
98 * CPU/chipset specific EDAC code can register a notifier call here to print
99 * MCE errors in a human-readable form.
101 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
102 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain
);
104 /* MCA banks polled by the period polling timer for corrected events */
105 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
106 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
109 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce
*m
)
114 memset(m
, 0, sizeof(struct mce
));
115 m
->cpu
= m
->extcpu
= smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m
->time
= get_seconds();
119 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
120 m
->cpuid
= cpuid_eax(1);
122 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
124 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
125 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
128 DEFINE_PER_CPU(struct mce
, injectm
);
129 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
132 * Lockless MCE logging infrastructure.
133 * This avoids deadlocks on printk locks without having to break locks. Also
134 * separate MCEs from kernel messages to avoid bogus bug reports.
137 static struct mce_log mcelog
= {
138 .signature
= MCE_LOG_SIGNATURE
,
140 .recordlen
= sizeof(struct mce
),
143 void mce_log(struct mce
*mce
)
145 unsigned next
, entry
;
148 /* Emit the trace record: */
149 trace_mce_record(mce
);
151 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
152 if (ret
== NOTIFY_STOP
)
158 entry
= rcu_dereference_check_mce(mcelog
.next
);
162 * When the buffer fills up discard new entries.
163 * Assume that the earlier errors are the more
166 if (entry
>= MCE_LOG_LEN
) {
167 set_bit(MCE_OVERFLOW
,
168 (unsigned long *)&mcelog
.flags
);
171 /* Old left over entry. Skip: */
172 if (mcelog
.entry
[entry
].finished
) {
180 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
183 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
185 mcelog
.entry
[entry
].finished
= 1;
189 set_bit(0, &mce_need_notify
);
192 static void print_mce(struct mce
*m
)
196 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
197 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
200 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
201 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
204 if (m
->cs
== __KERNEL_CS
)
205 print_symbol("{%s}", m
->ip
);
209 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
211 pr_cont("ADDR %llx ", m
->addr
);
213 pr_cont("MISC %llx ", m
->misc
);
217 * Note this output is parsed by external tools and old fields
218 * should not be changed.
220 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
221 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
222 cpu_data(m
->extcpu
).microcode
);
225 * Print out human-readable details about the MCE error,
226 * (if the CPU has an implementation for that)
228 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
229 if (ret
== NOTIFY_STOP
)
232 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
235 #define PANIC_TIMEOUT 5 /* 5 seconds */
237 static atomic_t mce_paniced
;
239 static int fake_panic
;
240 static atomic_t mce_fake_paniced
;
242 /* Panic in progress. Enable interrupts and wait for final IPI */
243 static void wait_for_panic(void)
245 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
249 while (timeout
-- > 0)
251 if (panic_timeout
== 0)
252 panic_timeout
= mce_panic_timeout
;
253 panic("Panicing machine check CPU died");
256 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
262 * Make sure only one CPU runs in machine check panic
264 if (atomic_inc_return(&mce_paniced
) > 1)
271 /* Don't log too much for fake panic */
272 if (atomic_inc_return(&mce_fake_paniced
) > 1)
275 /* First print corrected ones that are still unlogged */
276 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
277 struct mce
*m
= &mcelog
.entry
[i
];
278 if (!(m
->status
& MCI_STATUS_VAL
))
280 if (!(m
->status
& MCI_STATUS_UC
)) {
283 apei_err
= apei_write_mce(m
);
286 /* Now print uncorrected but with the final one last */
287 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
288 struct mce
*m
= &mcelog
.entry
[i
];
289 if (!(m
->status
& MCI_STATUS_VAL
))
291 if (!(m
->status
& MCI_STATUS_UC
))
293 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
296 apei_err
= apei_write_mce(m
);
302 apei_err
= apei_write_mce(final
);
305 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
307 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
309 if (panic_timeout
== 0)
310 panic_timeout
= mce_panic_timeout
;
313 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
316 /* Support code for software error injection */
318 static int msr_to_offset(u32 msr
)
320 unsigned bank
= __this_cpu_read(injectm
.bank
);
323 return offsetof(struct mce
, ip
);
324 if (msr
== MSR_IA32_MCx_STATUS(bank
))
325 return offsetof(struct mce
, status
);
326 if (msr
== MSR_IA32_MCx_ADDR(bank
))
327 return offsetof(struct mce
, addr
);
328 if (msr
== MSR_IA32_MCx_MISC(bank
))
329 return offsetof(struct mce
, misc
);
330 if (msr
== MSR_IA32_MCG_STATUS
)
331 return offsetof(struct mce
, mcgstatus
);
335 /* MSR access wrappers used for error injection */
336 static u64
mce_rdmsrl(u32 msr
)
340 if (__this_cpu_read(injectm
.finished
)) {
341 int offset
= msr_to_offset(msr
);
345 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
348 if (rdmsrl_safe(msr
, &v
)) {
349 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
351 * Return zero in case the access faulted. This should
352 * not happen normally but can happen if the CPU does
353 * something weird, or if the code is buggy.
361 static void mce_wrmsrl(u32 msr
, u64 v
)
363 if (__this_cpu_read(injectm
.finished
)) {
364 int offset
= msr_to_offset(msr
);
367 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
374 * Collect all global (w.r.t. this processor) status about this machine
375 * check into our "mce" struct so that we can use it later to assess
376 * the severity of the problem as we read per-bank specific details.
378 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
382 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
385 * Get the address of the instruction at the time of
386 * the machine check error.
388 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
392 /* Use accurate RIP reporting if available. */
394 m
->ip
= mce_rdmsrl(rip_msr
);
399 * Simple lockless ring to communicate PFNs from the exception handler with the
400 * process context work function. This is vastly simplified because there's
401 * only a single reader and a single writer.
403 #define MCE_RING_SIZE 16 /* we use one entry less */
406 unsigned short start
;
408 unsigned long ring
[MCE_RING_SIZE
];
410 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
412 /* Runs with CPU affinity in workqueue */
413 static int mce_ring_empty(void)
415 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
417 return r
->start
== r
->end
;
420 static int mce_ring_get(unsigned long *pfn
)
427 r
= &__get_cpu_var(mce_ring
);
428 if (r
->start
== r
->end
)
430 *pfn
= r
->ring
[r
->start
];
431 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
438 /* Always runs in MCE context with preempt off */
439 static int mce_ring_add(unsigned long pfn
)
441 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
444 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
445 if (next
== r
->start
)
447 r
->ring
[r
->end
] = pfn
;
453 int mce_available(struct cpuinfo_x86
*c
)
457 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
460 static void mce_schedule_work(void)
462 if (!mce_ring_empty()) {
463 struct work_struct
*work
= &__get_cpu_var(mce_work
);
464 if (!work_pending(work
))
469 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
471 static void mce_irq_work_cb(struct irq_work
*entry
)
477 static void mce_report_event(struct pt_regs
*regs
)
479 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
482 * Triggering the work queue here is just an insurance
483 * policy in case the syscall exit notify handler
484 * doesn't run soon enough or ends up running on the
485 * wrong CPU (can happen when audit sleeps)
491 irq_work_queue(&__get_cpu_var(mce_irq_work
));
494 DEFINE_PER_CPU(unsigned, mce_poll_count
);
497 * Poll for corrected events or events that happened before reset.
498 * Those are just logged through /dev/mcelog.
500 * This is executed in standard interrupt context.
502 * Note: spec recommends to panic for fatal unsignalled
503 * errors here. However this would be quite problematic --
504 * we would need to reimplement the Monarch handling and
505 * it would mess up the exclusion between exception handler
506 * and poll hander -- * so we skip this for now.
507 * These cases should not happen anyways, or only when the CPU
508 * is already totally * confused. In this case it's likely it will
509 * not fully execute the machine check handler either.
511 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
516 percpu_inc(mce_poll_count
);
518 mce_gather_info(&m
, NULL
);
520 for (i
= 0; i
< banks
; i
++) {
521 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
530 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
531 if (!(m
.status
& MCI_STATUS_VAL
))
535 * Uncorrected or signalled events are handled by the exception
536 * handler when it is enabled, so don't process those here.
538 * TBD do the same check for MCI_STATUS_EN here?
540 if (!(flags
& MCP_UC
) &&
541 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
544 if (m
.status
& MCI_STATUS_MISCV
)
545 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
546 if (m
.status
& MCI_STATUS_ADDRV
)
547 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
549 if (!(flags
& MCP_TIMESTAMP
))
552 * Don't get the IP here because it's unlikely to
553 * have anything to do with the actual error location.
555 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
559 * Clear state for this bank.
561 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
565 * Don't clear MCG_STATUS here because it's only defined for
571 EXPORT_SYMBOL_GPL(machine_check_poll
);
574 * Do a quick check if any of the events requires a panic.
575 * This decides if we keep the events around or clear them.
577 static int mce_no_way_out(struct mce
*m
, char **msg
)
581 for (i
= 0; i
< banks
; i
++) {
582 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
583 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
590 * Variable to establish order between CPUs while scanning.
591 * Each CPU spins initially until executing is equal its number.
593 static atomic_t mce_executing
;
596 * Defines order of CPUs on entry. First CPU becomes Monarch.
598 static atomic_t mce_callin
;
601 * Check if a timeout waiting for other CPUs happened.
603 static int mce_timed_out(u64
*t
)
606 * The others already did panic for some reason.
607 * Bail out like in a timeout.
608 * rmb() to tell the compiler that system_state
609 * might have been modified by someone else.
612 if (atomic_read(&mce_paniced
))
614 if (!monarch_timeout
)
616 if ((s64
)*t
< SPINUNIT
) {
617 /* CHECKME: Make panic default for 1 too? */
619 mce_panic("Timeout synchronizing machine check over CPUs",
626 touch_nmi_watchdog();
631 * The Monarch's reign. The Monarch is the CPU who entered
632 * the machine check handler first. It waits for the others to
633 * raise the exception too and then grades them. When any
634 * error is fatal panic. Only then let the others continue.
636 * The other CPUs entering the MCE handler will be controlled by the
637 * Monarch. They are called Subjects.
639 * This way we prevent any potential data corruption in a unrecoverable case
640 * and also makes sure always all CPU's errors are examined.
642 * Also this detects the case of a machine check event coming from outer
643 * space (not detected by any CPUs) In this case some external agent wants
644 * us to shut down, so panic too.
646 * The other CPUs might still decide to panic if the handler happens
647 * in a unrecoverable place, but in this case the system is in a semi-stable
648 * state and won't corrupt anything by itself. It's ok to let the others
649 * continue for a bit first.
651 * All the spin loops have timeouts; when a timeout happens a CPU
652 * typically elects itself to be Monarch.
654 static void mce_reign(void)
657 struct mce
*m
= NULL
;
658 int global_worst
= 0;
663 * This CPU is the Monarch and the other CPUs have run
664 * through their handlers.
665 * Grade the severity of the errors of all the CPUs.
667 for_each_possible_cpu(cpu
) {
668 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
670 if (severity
> global_worst
) {
672 global_worst
= severity
;
673 m
= &per_cpu(mces_seen
, cpu
);
678 * Cannot recover? Panic here then.
679 * This dumps all the mces in the log buffer and stops the
682 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
683 mce_panic("Fatal Machine check", m
, msg
);
686 * For UC somewhere we let the CPU who detects it handle it.
687 * Also must let continue the others, otherwise the handling
688 * CPU could deadlock on a lock.
692 * No machine check event found. Must be some external
693 * source or one CPU is hung. Panic.
695 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
696 mce_panic("Machine check from unknown source", NULL
, NULL
);
699 * Now clear all the mces_seen so that they don't reappear on
702 for_each_possible_cpu(cpu
)
703 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
706 static atomic_t global_nwo
;
709 * Start of Monarch synchronization. This waits until all CPUs have
710 * entered the exception handler and then determines if any of them
711 * saw a fatal event that requires panic. Then it executes them
712 * in the entry order.
713 * TBD double check parallel CPU hotunplug
715 static int mce_start(int *no_way_out
)
718 int cpus
= num_online_cpus();
719 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
724 atomic_add(*no_way_out
, &global_nwo
);
726 * global_nwo should be updated before mce_callin
729 order
= atomic_inc_return(&mce_callin
);
734 while (atomic_read(&mce_callin
) != cpus
) {
735 if (mce_timed_out(&timeout
)) {
736 atomic_set(&global_nwo
, 0);
743 * mce_callin should be read before global_nwo
749 * Monarch: Starts executing now, the others wait.
751 atomic_set(&mce_executing
, 1);
754 * Subject: Now start the scanning loop one by one in
755 * the original callin order.
756 * This way when there are any shared banks it will be
757 * only seen by one CPU before cleared, avoiding duplicates.
759 while (atomic_read(&mce_executing
) < order
) {
760 if (mce_timed_out(&timeout
)) {
761 atomic_set(&global_nwo
, 0);
769 * Cache the global no_way_out state.
771 *no_way_out
= atomic_read(&global_nwo
);
777 * Synchronize between CPUs after main scanning loop.
778 * This invokes the bulk of the Monarch processing.
780 static int mce_end(int order
)
783 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
791 * Allow others to run.
793 atomic_inc(&mce_executing
);
796 /* CHECKME: Can this race with a parallel hotplug? */
797 int cpus
= num_online_cpus();
800 * Monarch: Wait for everyone to go through their scanning
803 while (atomic_read(&mce_executing
) <= cpus
) {
804 if (mce_timed_out(&timeout
))
814 * Subject: Wait for Monarch to finish.
816 while (atomic_read(&mce_executing
) != 0) {
817 if (mce_timed_out(&timeout
))
823 * Don't reset anything. That's done by the Monarch.
829 * Reset all global state.
832 atomic_set(&global_nwo
, 0);
833 atomic_set(&mce_callin
, 0);
837 * Let others run again.
839 atomic_set(&mce_executing
, 0);
844 * Check if the address reported by the CPU is in a format we can parse.
845 * It would be possible to add code for most other cases, but all would
846 * be somewhat complicated (e.g. segment offset would require an instruction
847 * parser). So only support physical addresses up to page granuality for now.
849 static int mce_usable_address(struct mce
*m
)
851 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
853 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
855 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
860 static void mce_clear_state(unsigned long *toclear
)
864 for (i
= 0; i
< banks
; i
++) {
865 if (test_bit(i
, toclear
))
866 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
871 * The actual machine check handler. This only handles real
872 * exceptions when something got corrupted coming in through int 18.
874 * This is executed in NMI context not subject to normal locking rules. This
875 * implies that most kernel services cannot be safely used. Don't even
876 * think about putting a printk in there!
878 * On Intel systems this is entered on all CPUs in parallel through
879 * MCE broadcast. However some CPUs might be broken beyond repair,
880 * so be always careful when synchronizing with others.
882 void do_machine_check(struct pt_regs
*regs
, long error_code
)
884 struct mce m
, *final
;
889 * Establish sequential order between the CPUs entering the machine
894 * If no_way_out gets set, there is no safe way to recover from this
895 * MCE. If tolerant is cranked up, we'll try anyway.
899 * If kill_it gets set, there might be a way to recover from this
903 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
904 char *msg
= "Unknown";
906 atomic_inc(&mce_entry
);
908 percpu_inc(mce_exception_count
);
913 mce_gather_info(&m
, regs
);
915 final
= &__get_cpu_var(mces_seen
);
918 no_way_out
= mce_no_way_out(&m
, &msg
);
923 * When no restart IP must always kill or panic.
925 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
929 * Go through all the banks in exclusion of the other CPUs.
930 * This way we don't report duplicated events on shared banks
931 * because the first one to see it will clear it.
933 order
= mce_start(&no_way_out
);
934 for (i
= 0; i
< banks
; i
++) {
935 __clear_bit(i
, toclear
);
936 if (!mce_banks
[i
].ctl
)
943 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
944 if ((m
.status
& MCI_STATUS_VAL
) == 0)
948 * Non uncorrected or non signaled errors are handled by
949 * machine_check_poll. Leave them alone, unless this panics.
951 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
956 * Set taint even when machine check was not enabled.
958 add_taint(TAINT_MACHINE_CHECK
);
960 severity
= mce_severity(&m
, tolerant
, NULL
);
963 * When machine check was for corrected handler don't touch,
964 * unless we're panicing.
966 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
968 __set_bit(i
, toclear
);
969 if (severity
== MCE_NO_SEVERITY
) {
971 * Machine check event was not enabled. Clear, but
978 * Kill on action required.
980 if (severity
== MCE_AR_SEVERITY
)
983 if (m
.status
& MCI_STATUS_MISCV
)
984 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
985 if (m
.status
& MCI_STATUS_ADDRV
)
986 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
989 * Action optional error. Queue address for later processing.
990 * When the ring overflows we just ignore the AO error.
991 * RED-PEN add some logging mechanism when
992 * usable_address or mce_add_ring fails.
993 * RED-PEN don't ignore overflow for tolerant == 0
995 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
996 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1000 if (severity
> worst
) {
1007 mce_clear_state(toclear
);
1010 * Do most of the synchronization with other CPUs.
1011 * When there's any problem use only local no_way_out state.
1013 if (mce_end(order
) < 0)
1014 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1017 * If we have decided that we just CAN'T continue, and the user
1018 * has not set tolerant to an insane level, give up and die.
1020 * This is mainly used in the case when the system doesn't
1021 * support MCE broadcasting or it has been disabled.
1023 if (no_way_out
&& tolerant
< 3)
1024 mce_panic("Fatal machine check on current CPU", final
, msg
);
1027 * If the error seems to be unrecoverable, something should be
1028 * done. Try to kill as little as possible. If we can kill just
1029 * one task, do that. If the user has set the tolerance very
1030 * high, don't try to do anything at all.
1033 if (kill_it
&& tolerant
< 3)
1034 force_sig(SIGBUS
, current
);
1036 /* notify userspace ASAP */
1037 set_thread_flag(TIF_MCE_NOTIFY
);
1040 mce_report_event(regs
);
1041 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1043 atomic_dec(&mce_entry
);
1046 EXPORT_SYMBOL_GPL(do_machine_check
);
1048 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1049 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1051 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1055 * Called after mce notification in process context. This code
1056 * is allowed to sleep. Call the high level VM handler to process
1057 * any corrupted pages.
1058 * Assume that the work queue code only calls this one at a time
1060 * Note we don't disable preemption, so this code might run on the wrong
1061 * CPU. In this case the event is picked up by the scheduled work queue.
1062 * This is merely a fast path to expedite processing in some common
1065 void mce_notify_process(void)
1069 while (mce_ring_get(&pfn
))
1070 memory_failure(pfn
, MCE_VECTOR
);
1073 static void mce_process_work(struct work_struct
*dummy
)
1075 mce_notify_process();
1078 #ifdef CONFIG_X86_MCE_INTEL
1080 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1081 * @cpu: The CPU on which the event occurred.
1082 * @status: Event status information
1084 * This function should be called by the thermal interrupt after the
1085 * event has been processed and the decision was made to log the event
1088 * The status parameter will be saved to the 'status' field of 'struct mce'
1089 * and historically has been the register value of the
1090 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1092 void mce_log_therm_throt_event(__u64 status
)
1097 m
.bank
= MCE_THERMAL_BANK
;
1101 #endif /* CONFIG_X86_MCE_INTEL */
1104 * Periodic polling timer for "silent" machine check errors. If the
1105 * poller finds an MCE, poll 2x faster. When the poller finds no more
1106 * errors, poll 2x slower (up to check_interval seconds).
1108 static int check_interval
= 5 * 60; /* 5 minutes */
1110 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1111 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1113 static void mce_start_timer(unsigned long data
)
1115 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1118 WARN_ON(smp_processor_id() != data
);
1120 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1121 machine_check_poll(MCP_TIMESTAMP
,
1122 &__get_cpu_var(mce_poll_banks
));
1126 * Alert userspace if needed. If we logged an MCE, reduce the
1127 * polling interval, otherwise increase the polling interval.
1129 n
= &__get_cpu_var(mce_next_interval
);
1130 if (mce_notify_irq())
1131 *n
= max(*n
/2, HZ
/100);
1133 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1135 t
->expires
= jiffies
+ *n
;
1136 add_timer_on(t
, smp_processor_id());
1139 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1140 static void mce_timer_delete_all(void)
1144 for_each_online_cpu(cpu
)
1145 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1148 static void mce_do_trigger(struct work_struct
*work
)
1150 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1153 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1156 * Notify the user(s) about new machine check events.
1157 * Can be called from interrupt context, but not from machine check/NMI
1160 int mce_notify_irq(void)
1162 /* Not more than two messages every minute */
1163 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1165 clear_thread_flag(TIF_MCE_NOTIFY
);
1167 if (test_and_clear_bit(0, &mce_need_notify
)) {
1168 /* wake processes polling /dev/mcelog */
1169 wake_up_interruptible(&mce_chrdev_wait
);
1172 * There is no risk of missing notifications because
1173 * work_pending is always cleared before the function is
1176 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1177 schedule_work(&mce_trigger_work
);
1179 if (__ratelimit(&ratelimit
))
1180 pr_info(HW_ERR
"Machine check events logged\n");
1186 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1188 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1192 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1195 for (i
= 0; i
< banks
; i
++) {
1196 struct mce_bank
*b
= &mce_banks
[i
];
1205 * Initialize Machine Checks for a CPU.
1207 static int __cpuinit
__mcheck_cpu_cap_init(void)
1212 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1214 b
= cap
& MCG_BANKCNT_MASK
;
1216 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1218 if (b
> MAX_NR_BANKS
) {
1220 "MCE: Using only %u machine check banks out of %u\n",
1225 /* Don't support asymmetric configurations today */
1226 WARN_ON(banks
!= 0 && b
!= banks
);
1229 int err
= __mcheck_cpu_mce_banks_init();
1235 /* Use accurate RIP reporting if available. */
1236 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1237 rip_msr
= MSR_IA32_MCG_EIP
;
1239 if (cap
& MCG_SER_P
)
1245 static void __mcheck_cpu_init_generic(void)
1247 mce_banks_t all_banks
;
1252 * Log the machine checks left over from the previous reset.
1254 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1255 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1257 set_in_cr4(X86_CR4_MCE
);
1259 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1260 if (cap
& MCG_CTL_P
)
1261 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1263 for (i
= 0; i
< banks
; i
++) {
1264 struct mce_bank
*b
= &mce_banks
[i
];
1268 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1269 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1273 /* Add per CPU specific workarounds here */
1274 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1276 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1277 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1281 /* This should be disabled by the BIOS, but isn't always */
1282 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1283 if (c
->x86
== 15 && banks
> 4) {
1285 * disable GART TBL walk error reporting, which
1286 * trips off incorrectly with the IOMMU & 3ware
1289 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1291 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1293 * Lots of broken BIOS around that don't clear them
1294 * by default and leave crap in there. Don't log:
1299 * Various K7s with broken bank 0 around. Always disable
1302 if (c
->x86
== 6 && banks
> 0)
1303 mce_banks
[0].ctl
= 0;
1306 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1308 * SDM documents that on family 6 bank 0 should not be written
1309 * because it aliases to another special BIOS controlled
1311 * But it's not aliased anymore on model 0x1a+
1312 * Don't ignore bank 0 completely because there could be a
1313 * valid event later, merely don't write CTL0.
1316 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1317 mce_banks
[0].init
= 0;
1320 * All newer Intel systems support MCE broadcasting. Enable
1321 * synchronization with a one second timeout.
1323 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1324 monarch_timeout
< 0)
1325 monarch_timeout
= USEC_PER_SEC
;
1328 * There are also broken BIOSes on some Pentium M and
1331 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1334 if (monarch_timeout
< 0)
1335 monarch_timeout
= 0;
1336 if (mce_bootlog
!= 0)
1337 mce_panic_timeout
= 30;
1342 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1347 switch (c
->x86_vendor
) {
1348 case X86_VENDOR_INTEL
:
1349 intel_p5_mcheck_init(c
);
1352 case X86_VENDOR_CENTAUR
:
1353 winchip_mcheck_init(c
);
1361 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1363 switch (c
->x86_vendor
) {
1364 case X86_VENDOR_INTEL
:
1365 mce_intel_feature_init(c
);
1367 case X86_VENDOR_AMD
:
1368 mce_amd_feature_init(c
);
1375 static void __mcheck_cpu_init_timer(void)
1377 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1378 int *n
= &__get_cpu_var(mce_next_interval
);
1380 setup_timer(t
, mce_start_timer
, smp_processor_id());
1385 *n
= check_interval
* HZ
;
1388 t
->expires
= round_jiffies(jiffies
+ *n
);
1389 add_timer_on(t
, smp_processor_id());
1392 /* Handle unconfigured int18 (should never happen) */
1393 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1395 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1396 smp_processor_id());
1399 /* Call the installed machine check handler for this CPU setup. */
1400 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1401 unexpected_machine_check
;
1404 * Called for each booted CPU to set up machine checks.
1405 * Must be called with preempt off:
1407 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1412 if (__mcheck_cpu_ancient_init(c
))
1415 if (!mce_available(c
))
1418 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1423 machine_check_vector
= do_machine_check
;
1425 __mcheck_cpu_init_generic();
1426 __mcheck_cpu_init_vendor(c
);
1427 __mcheck_cpu_init_timer();
1428 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1429 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1433 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1436 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1437 static int mce_chrdev_open_count
; /* #times opened */
1438 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1440 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1442 spin_lock(&mce_chrdev_state_lock
);
1444 if (mce_chrdev_open_exclu
||
1445 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1446 spin_unlock(&mce_chrdev_state_lock
);
1451 if (file
->f_flags
& O_EXCL
)
1452 mce_chrdev_open_exclu
= 1;
1453 mce_chrdev_open_count
++;
1455 spin_unlock(&mce_chrdev_state_lock
);
1457 return nonseekable_open(inode
, file
);
1460 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1462 spin_lock(&mce_chrdev_state_lock
);
1464 mce_chrdev_open_count
--;
1465 mce_chrdev_open_exclu
= 0;
1467 spin_unlock(&mce_chrdev_state_lock
);
1472 static void collect_tscs(void *data
)
1474 unsigned long *cpu_tsc
= (unsigned long *)data
;
1476 rdtscll(cpu_tsc
[smp_processor_id()]);
1479 static int mce_apei_read_done
;
1481 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1482 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1488 if (usize
< sizeof(struct mce
))
1491 rc
= apei_read_mce(&m
, &record_id
);
1492 /* Error or no more MCE record */
1494 mce_apei_read_done
= 1;
1498 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1501 * In fact, we should have cleared the record after that has
1502 * been flushed to the disk or sent to network in
1503 * /sbin/mcelog, but we have no interface to support that now,
1504 * so just clear it to avoid duplication.
1506 rc
= apei_clear_mce(record_id
);
1508 mce_apei_read_done
= 1;
1511 *ubuf
+= sizeof(struct mce
);
1516 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1517 size_t usize
, loff_t
*off
)
1519 char __user
*buf
= ubuf
;
1520 unsigned long *cpu_tsc
;
1521 unsigned prev
, next
;
1524 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1528 mutex_lock(&mce_chrdev_read_mutex
);
1530 if (!mce_apei_read_done
) {
1531 err
= __mce_read_apei(&buf
, usize
);
1532 if (err
|| buf
!= ubuf
)
1536 next
= rcu_dereference_check_mce(mcelog
.next
);
1538 /* Only supports full reads right now */
1540 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1546 for (i
= prev
; i
< next
; i
++) {
1547 unsigned long start
= jiffies
;
1548 struct mce
*m
= &mcelog
.entry
[i
];
1550 while (!m
->finished
) {
1551 if (time_after_eq(jiffies
, start
+ 2)) {
1552 memset(m
, 0, sizeof(*m
));
1558 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1564 memset(mcelog
.entry
+ prev
, 0,
1565 (next
- prev
) * sizeof(struct mce
));
1567 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1568 } while (next
!= prev
);
1570 synchronize_sched();
1573 * Collect entries that were still getting written before the
1576 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1578 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1579 struct mce
*m
= &mcelog
.entry
[i
];
1581 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1582 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1585 memset(m
, 0, sizeof(*m
));
1593 mutex_unlock(&mce_chrdev_read_mutex
);
1596 return err
? err
: buf
- ubuf
;
1599 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1601 poll_wait(file
, &mce_chrdev_wait
, wait
);
1602 if (rcu_access_index(mcelog
.next
))
1603 return POLLIN
| POLLRDNORM
;
1604 if (!mce_apei_read_done
&& apei_check_mce())
1605 return POLLIN
| POLLRDNORM
;
1609 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1612 int __user
*p
= (int __user
*)arg
;
1614 if (!capable(CAP_SYS_ADMIN
))
1618 case MCE_GET_RECORD_LEN
:
1619 return put_user(sizeof(struct mce
), p
);
1620 case MCE_GET_LOG_LEN
:
1621 return put_user(MCE_LOG_LEN
, p
);
1622 case MCE_GETCLEAR_FLAGS
: {
1626 flags
= mcelog
.flags
;
1627 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1629 return put_user(flags
, p
);
1636 /* Modified in mce-inject.c, so not static or const */
1637 struct file_operations mce_chrdev_ops
= {
1638 .open
= mce_chrdev_open
,
1639 .release
= mce_chrdev_release
,
1640 .read
= mce_chrdev_read
,
1641 .poll
= mce_chrdev_poll
,
1642 .unlocked_ioctl
= mce_chrdev_ioctl
,
1643 .llseek
= no_llseek
,
1645 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1647 static struct miscdevice mce_chrdev_device
= {
1654 * mce=off Disables machine check
1655 * mce=no_cmci Disables CMCI
1656 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1657 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1658 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1659 * monarchtimeout is how long to wait for other CPUs on machine
1660 * check, or 0 to not wait
1661 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1662 * mce=nobootlog Don't log MCEs from before booting.
1664 static int __init
mcheck_enable(char *str
)
1672 if (!strcmp(str
, "off"))
1674 else if (!strcmp(str
, "no_cmci"))
1675 mce_cmci_disabled
= 1;
1676 else if (!strcmp(str
, "dont_log_ce"))
1677 mce_dont_log_ce
= 1;
1678 else if (!strcmp(str
, "ignore_ce"))
1680 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1681 mce_bootlog
= (str
[0] == 'b');
1682 else if (isdigit(str
[0])) {
1683 get_option(&str
, &tolerant
);
1686 get_option(&str
, &monarch_timeout
);
1689 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1695 __setup("mce", mcheck_enable
);
1697 int __init
mcheck_init(void)
1699 mcheck_intel_therm_init();
1705 * mce_syscore: PM support
1709 * Disable machine checks on suspend and shutdown. We can't really handle
1712 static int mce_disable_error_reporting(void)
1716 for (i
= 0; i
< banks
; i
++) {
1717 struct mce_bank
*b
= &mce_banks
[i
];
1720 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1725 static int mce_syscore_suspend(void)
1727 return mce_disable_error_reporting();
1730 static void mce_syscore_shutdown(void)
1732 mce_disable_error_reporting();
1736 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1737 * Only one CPU is active at this time, the others get re-added later using
1740 static void mce_syscore_resume(void)
1742 __mcheck_cpu_init_generic();
1743 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1746 static struct syscore_ops mce_syscore_ops
= {
1747 .suspend
= mce_syscore_suspend
,
1748 .shutdown
= mce_syscore_shutdown
,
1749 .resume
= mce_syscore_resume
,
1753 * mce_sysdev: Sysfs support
1756 static void mce_cpu_restart(void *data
)
1758 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1760 __mcheck_cpu_init_generic();
1761 __mcheck_cpu_init_timer();
1764 /* Reinit MCEs after user configuration changes */
1765 static void mce_restart(void)
1767 mce_timer_delete_all();
1768 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1771 /* Toggle features for corrected errors */
1772 static void mce_disable_cmci(void *data
)
1774 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1779 static void mce_enable_ce(void *all
)
1781 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1786 __mcheck_cpu_init_timer();
1789 static struct sysdev_class mce_sysdev_class
= {
1790 .name
= "machinecheck",
1793 DEFINE_PER_CPU(struct sys_device
, mce_sysdev
);
1796 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1798 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1800 return container_of(attr
, struct mce_bank
, attr
);
1803 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1806 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1809 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1810 const char *buf
, size_t size
)
1814 if (strict_strtoull(buf
, 0, &new) < 0)
1817 attr_to_bank(attr
)->ctl
= new;
1824 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1826 strcpy(buf
, mce_helper
);
1828 return strlen(mce_helper
) + 1;
1831 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1832 const char *buf
, size_t siz
)
1836 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1837 mce_helper
[sizeof(mce_helper
)-1] = 0;
1838 p
= strchr(mce_helper
, '\n');
1843 return strlen(mce_helper
) + !!p
;
1846 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1847 struct sysdev_attribute
*attr
,
1848 const char *buf
, size_t size
)
1852 if (strict_strtoull(buf
, 0, &new) < 0)
1855 if (mce_ignore_ce
^ !!new) {
1857 /* disable ce features */
1858 mce_timer_delete_all();
1859 on_each_cpu(mce_disable_cmci
, NULL
, 1);
1862 /* enable ce features */
1864 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1870 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1871 struct sysdev_attribute
*attr
,
1872 const char *buf
, size_t size
)
1876 if (strict_strtoull(buf
, 0, &new) < 0)
1879 if (mce_cmci_disabled
^ !!new) {
1882 on_each_cpu(mce_disable_cmci
, NULL
, 1);
1883 mce_cmci_disabled
= 1;
1886 mce_cmci_disabled
= 0;
1887 on_each_cpu(mce_enable_ce
, NULL
, 1);
1893 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1894 struct sysdev_attribute
*attr
,
1895 const char *buf
, size_t size
)
1897 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1902 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1903 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1904 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1905 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1907 static struct sysdev_ext_attribute attr_check_interval
= {
1908 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1909 store_int_with_restart
),
1913 static struct sysdev_ext_attribute attr_ignore_ce
= {
1914 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1918 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1919 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1923 static struct sysdev_attribute
*mce_sysdev_attrs
[] = {
1924 &attr_tolerant
.attr
,
1925 &attr_check_interval
.attr
,
1927 &attr_monarch_timeout
.attr
,
1928 &attr_dont_log_ce
.attr
,
1929 &attr_ignore_ce
.attr
,
1930 &attr_cmci_disabled
.attr
,
1934 static cpumask_var_t mce_sysdev_initialized
;
1936 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1937 static __cpuinit
int mce_sysdev_create(unsigned int cpu
)
1939 struct sys_device
*sysdev
= &per_cpu(mce_sysdev
, cpu
);
1943 if (!mce_available(&boot_cpu_data
))
1946 memset(&sysdev
->kobj
, 0, sizeof(struct kobject
));
1948 sysdev
->cls
= &mce_sysdev_class
;
1950 err
= sysdev_register(sysdev
);
1954 for (i
= 0; mce_sysdev_attrs
[i
]; i
++) {
1955 err
= sysdev_create_file(sysdev
, mce_sysdev_attrs
[i
]);
1959 for (j
= 0; j
< banks
; j
++) {
1960 err
= sysdev_create_file(sysdev
, &mce_banks
[j
].attr
);
1964 cpumask_set_cpu(cpu
, mce_sysdev_initialized
);
1969 sysdev_remove_file(sysdev
, &mce_banks
[j
].attr
);
1972 sysdev_remove_file(sysdev
, mce_sysdev_attrs
[i
]);
1974 sysdev_unregister(sysdev
);
1979 static __cpuinit
void mce_sysdev_remove(unsigned int cpu
)
1981 struct sys_device
*sysdev
= &per_cpu(mce_sysdev
, cpu
);
1984 if (!cpumask_test_cpu(cpu
, mce_sysdev_initialized
))
1987 for (i
= 0; mce_sysdev_attrs
[i
]; i
++)
1988 sysdev_remove_file(sysdev
, mce_sysdev_attrs
[i
]);
1990 for (i
= 0; i
< banks
; i
++)
1991 sysdev_remove_file(sysdev
, &mce_banks
[i
].attr
);
1993 sysdev_unregister(sysdev
);
1994 cpumask_clear_cpu(cpu
, mce_sysdev_initialized
);
1997 /* Make sure there are no machine checks on offlined CPUs. */
1998 static void __cpuinit
mce_disable_cpu(void *h
)
2000 unsigned long action
= *(unsigned long *)h
;
2003 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2006 if (!(action
& CPU_TASKS_FROZEN
))
2008 for (i
= 0; i
< banks
; i
++) {
2009 struct mce_bank
*b
= &mce_banks
[i
];
2012 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2016 static void __cpuinit
mce_reenable_cpu(void *h
)
2018 unsigned long action
= *(unsigned long *)h
;
2021 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2024 if (!(action
& CPU_TASKS_FROZEN
))
2026 for (i
= 0; i
< banks
; i
++) {
2027 struct mce_bank
*b
= &mce_banks
[i
];
2030 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2034 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2035 static int __cpuinit
2036 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2038 unsigned int cpu
= (unsigned long)hcpu
;
2039 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2043 case CPU_ONLINE_FROZEN
:
2044 mce_sysdev_create(cpu
);
2045 if (threshold_cpu_callback
)
2046 threshold_cpu_callback(action
, cpu
);
2049 case CPU_DEAD_FROZEN
:
2050 if (threshold_cpu_callback
)
2051 threshold_cpu_callback(action
, cpu
);
2052 mce_sysdev_remove(cpu
);
2054 case CPU_DOWN_PREPARE
:
2055 case CPU_DOWN_PREPARE_FROZEN
:
2057 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2059 case CPU_DOWN_FAILED
:
2060 case CPU_DOWN_FAILED_FROZEN
:
2061 if (!mce_ignore_ce
&& check_interval
) {
2062 t
->expires
= round_jiffies(jiffies
+
2063 __get_cpu_var(mce_next_interval
));
2064 add_timer_on(t
, cpu
);
2066 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2069 /* intentionally ignoring frozen here */
2070 cmci_rediscover(cpu
);
2076 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2077 .notifier_call
= mce_cpu_callback
,
2080 static __init
void mce_init_banks(void)
2084 for (i
= 0; i
< banks
; i
++) {
2085 struct mce_bank
*b
= &mce_banks
[i
];
2086 struct sysdev_attribute
*a
= &b
->attr
;
2088 sysfs_attr_init(&a
->attr
);
2089 a
->attr
.name
= b
->attrname
;
2090 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2092 a
->attr
.mode
= 0644;
2093 a
->show
= show_bank
;
2094 a
->store
= set_bank
;
2098 static __init
int mcheck_init_device(void)
2103 if (!mce_available(&boot_cpu_data
))
2106 zalloc_cpumask_var(&mce_sysdev_initialized
, GFP_KERNEL
);
2110 err
= sysdev_class_register(&mce_sysdev_class
);
2114 for_each_online_cpu(i
) {
2115 err
= mce_sysdev_create(i
);
2120 register_syscore_ops(&mce_syscore_ops
);
2121 register_hotcpu_notifier(&mce_cpu_notifier
);
2123 /* register character device /dev/mcelog */
2124 misc_register(&mce_chrdev_device
);
2128 device_initcall(mcheck_init_device
);
2131 * Old style boot options parsing. Only for compatibility.
2133 static int __init
mcheck_disable(char *str
)
2138 __setup("nomce", mcheck_disable
);
2140 #ifdef CONFIG_DEBUG_FS
2141 struct dentry
*mce_get_debugfs_dir(void)
2143 static struct dentry
*dmce
;
2146 dmce
= debugfs_create_dir("mce", NULL
);
2151 static void mce_reset(void)
2154 atomic_set(&mce_fake_paniced
, 0);
2155 atomic_set(&mce_executing
, 0);
2156 atomic_set(&mce_callin
, 0);
2157 atomic_set(&global_nwo
, 0);
2160 static int fake_panic_get(void *data
, u64
*val
)
2166 static int fake_panic_set(void *data
, u64 val
)
2173 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2174 fake_panic_set
, "%llu\n");
2176 static int __init
mcheck_debugfs_init(void)
2178 struct dentry
*dmce
, *ffake_panic
;
2180 dmce
= mce_get_debugfs_dir();
2183 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2190 late_initcall(mcheck_debugfs_init
);