drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/version.h>
  24 #include <linux/kref.h>
  25
  26 #include <drm/drmP.h>
  27 #include "drm_global.h"
  28 #include "gem_glue.h"
  29 #include "psb_drm.h"
  30 #include "psb_reg.h"
  31 #include "psb_intel_drv.h"
  32 #include "psb_gtt.h"
  33 #include "psb_powermgmt.h"
  34 #include "mrst.h"
  35
  36 /* Append new drm mode definition here, align with libdrm definition */
  37 #define DRM_MODE_SCALE_NO_SCALE   2
  38
  39 enum {
  40         CHIP_PSB_8108 = 0,              /* Poulsbo */
  41         CHIP_PSB_8109 = 1,              /* Poulsbo */
  42         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  43 };
  44
  45 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  46
  47 /*
  48  * Driver definitions
  49  */
  50
  51 #define DRIVER_NAME "gma500"
  52 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  53
  54 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  55 #define PSB_DRM_DRIVER_MAJOR 1
  56 #define PSB_DRM_DRIVER_MINOR 0
  57 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  58
  59 /*
  60  *      Hardware offsets
  61  */
  62 #define PSB_VDC_OFFSET           0x00000000
  63 #define PSB_VDC_SIZE             0x000080000
  64 #define MRST_MMIO_SIZE           0x0000C0000
  65 #define MDFLD_MMIO_SIZE          0x000100000
  66 #define PSB_SGX_SIZE             0x8000
  67 #define PSB_SGX_OFFSET           0x00040000
  68 #define MRST_SGX_OFFSET          0x00080000
  69 /*
  70  *      PCI resource identifiers
  71  */
  72 #define PSB_MMIO_RESOURCE        0
  73 #define PSB_GATT_RESOURCE        2
  74 #define PSB_GTT_RESOURCE         3
  75 /*
  76  *      PCI configuration
  77  */
  78 #define PSB_GMCH_CTRL            0x52
  79 #define PSB_BSM                  0x5C
  80 #define _PSB_GMCH_ENABLED        0x4
  81 #define PSB_PGETBL_CTL           0x2020
  82 #define _PSB_PGETBL_ENABLED      0x00000001
  83 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  84
  85 /* To get rid of */
  86 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  87 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  88
  89 /*
  90  *      SGX side MMU definitions (these can probably go)
  91  */
  92
  93 /*
  94  *      Flags for external memory type field.
  95  */
  96 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
  97 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
  98 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
  99 /*
 100  *      PTE's and PDE's
 101  */
 102 #define PSB_PDE_MASK              0x003FFFFF
 103 #define PSB_PDE_SHIFT             22
 104 #define PSB_PTE_SHIFT             12
 105 /*
 106  *      Cache control
 107  */
 108 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 109 #define PSB_PTE_WO                0x0002        /* Write only */
 110 #define PSB_PTE_RO                0x0004        /* Read only */
 111 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 112
 113 /*
 114  *      VDC registers and bits
 115  */
 116 #define PSB_MSVDX_CLOCKGATING     0x2064
 117 #define PSB_TOPAZ_CLOCKGATING     0x2068
 118 #define PSB_HWSTAM                0x2098
 119 #define PSB_INSTPM                0x20C0
 120 #define PSB_INT_IDENTITY_R        0x20A4
 121 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 122 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 123 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 124 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 125 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 126 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 127 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 128 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 129 #define _MDFLD_MIPIA_FLAG         (1<<16)
 130 #define _MDFLD_MIPIC_FLAG         (1<<17)
 131 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 132 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 133 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 134
 135 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 136 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 137                                   _MDFLD_PIPEB_EVENT_FLAG | \
 138                                   _PSB_PIPEA_EVENT_FLAG | \
 139                                   _PSB_VSYNC_PIPEA_FLAG | \
 140                                   _MDFLD_MIPIA_FLAG | \
 141                                   _MDFLD_MIPIC_FLAG)
 142 #define PSB_INT_IDENTITY_R        0x20A4
 143 #define PSB_INT_MASK_R            0x20A8
 144 #define PSB_INT_ENABLE_R          0x20A0
 145
 146 #define _PSB_MMU_ER_MASK      0x0001FF00
 147 #define _PSB_MMU_ER_HOST      (1 << 16)
 148 #define GPIOA                   0x5010
 149 #define GPIOB                   0x5014
 150 #define GPIOC                   0x5018
 151 #define GPIOD                   0x501c
 152 #define GPIOE                   0x5020
 153 #define GPIOF                   0x5024
 154 #define GPIOG                   0x5028
 155 #define GPIOH                   0x502c
 156 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 157 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 158 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 159 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 160 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 161 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 162 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 163 #define GPIO_DATA_DIR_MASK              (1 << 8)
 164 #define GPIO_DATA_DIR_IN                (0 << 9)
 165 #define GPIO_DATA_DIR_OUT               (1 << 9)
 166 #define GPIO_DATA_VAL_MASK              (1 << 10)
 167 #define GPIO_DATA_VAL_OUT               (1 << 11)
 168 #define GPIO_DATA_VAL_IN                (1 << 12)
 169 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 170
 171 #define VCLK_DIVISOR_VGA0   0x6000
 172 #define VCLK_DIVISOR_VGA1   0x6004
 173 #define VCLK_POST_DIV       0x6010
 174
 175 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 176 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 177 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 178 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 179 #define PSB_COMM_USER_IRQ (1024 >> 2)
 180 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 181 #define PSB_COMM_FW (2048 >> 2)
 182
 183 #define PSB_UIRQ_VISTEST               1
 184 #define PSB_UIRQ_OOM_REPLY             2
 185 #define PSB_UIRQ_FIRE_TA_REPLY         3
 186 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 187
 188 #define PSB_2D_SIZE (256*1024*1024)
 189 #define PSB_MAX_RELOC_PAGES 1024
 190
 191 #define PSB_LOW_REG_OFFS 0x0204
 192 #define PSB_HIGH_REG_OFFS 0x0600
 193
 194 #define PSB_NUM_VBLANKS 2
 195
 196
 197 #define PSB_2D_SIZE (256*1024*1024)
 198 #define PSB_MAX_RELOC_PAGES 1024
 199
 200 #define PSB_LOW_REG_OFFS 0x0204
 201 #define PSB_HIGH_REG_OFFS 0x0600
 202
 203 #define PSB_NUM_VBLANKS 2
 204 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 205 #define PSB_LID_DELAY (DRM_HZ / 10)
 206
 207 #define MDFLD_PNW_A0 0x00
 208 #define MDFLD_PNW_B0 0x04
 209 #define MDFLD_PNW_C0 0x08
 210
 211 #define PSB_PWR_STATE_ON                1
 212 #define PSB_PWR_STATE_OFF               2
 213
 214 #define PSB_PMPOLICY_NOPM               0
 215 #define PSB_PMPOLICY_CLOCKGATING        1
 216 #define PSB_PMPOLICY_POWERDOWN          2
 217
 218 #define PSB_PMSTATE_POWERUP             0
 219 #define PSB_PMSTATE_CLOCKGATED          1
 220 #define PSB_PMSTATE_POWERDOWN           2
 221 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 222 #define PSB_PCIx_MSI_DATA_LOC           0x98
 223
 224 struct opregion_header;
 225 struct opregion_acpi;
 226 struct opregion_swsci;
 227 struct opregion_asle;
 228
 229 struct psb_intel_opregion {
 230         struct opregion_header *header;
 231         struct opregion_acpi *acpi;
 232         struct opregion_swsci *swsci;
 233         struct opregion_asle *asle;
 234         int enabled;
 235 };
 236
 237
 238 struct drm_psb_private {
 239         struct drm_device *dev;
 240
 241         unsigned long chipset;
 242
 243         struct psb_gtt *pg;
 244
 245         /* GTT Memory manager */
 246         struct psb_gtt_mm *gtt_mm;
 247         struct page *scratch_page;
 248         u32 *gtt_map;
 249         uint32_t stolen_base;
 250         void *vram_addr;
 251         unsigned long vram_stolen_size;
 252         int gtt_initialized;
 253         u16 gmch_ctrl;          /* Saved GTT setup */
 254         u32 pge_ctl;
 255
 256         struct mutex gtt_mutex;
 257         struct resource *gtt_mem;       /* Our PCI resource */
 258
 259         struct psb_mmu_driver *mmu;
 260         struct psb_mmu_pd *pf_pd;
 261
 262         /*
 263          * Register base
 264          */
 265
 266         uint8_t *sgx_reg;
 267         uint8_t *vdc_reg;
 268         uint32_t gatt_free_offset;
 269
 270         /*
 271          * Fencing / irq.
 272          */
 273
 274         uint32_t vdc_irq_mask;
 275         uint32_t pipestat[PSB_NUM_PIPE];
 276
 277         spinlock_t irqmask_lock;
 278
 279         /*
 280          * Power
 281          */
 282
 283         bool suspended;
 284         bool display_power;
 285         int display_count;
 286
 287         /*
 288          * Modesetting
 289          */
 290         struct psb_intel_mode_device mode_dev;
 291
 292         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 293         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 294         uint32_t num_pipe;
 295
 296         /*
 297          * OSPM info (Power management base) (can go ?)
 298          */
 299         uint32_t ospm_base;
 300
 301         /*
 302          * Sizes info
 303          */
 304
 305         struct drm_psb_sizes_arg sizes;
 306
 307         u32 fuse_reg_value;
 308         u32 video_device_fuse;
 309
 310         /* PCI revision ID for B0:D2:F0 */
 311         uint8_t platform_rev_id;
 312
 313         /*
 314          * LVDS info
 315          */
 316         int backlight_duty_cycle;       /* restore backlight to this value */
 317         bool panel_wants_dither;
 318         struct drm_display_mode *panel_fixed_mode;
 319         struct drm_display_mode *lfp_lvds_vbt_mode;
 320         struct drm_display_mode *sdvo_lvds_vbt_mode;
 321
 322         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 323         struct psb_intel_i2c_chan *lvds_i2c_bus;
 324
 325         /* Feature bits from the VBIOS */
 326         unsigned int int_tv_support:1;
 327         unsigned int lvds_dither:1;
 328         unsigned int lvds_vbt:1;
 329         unsigned int int_crt_support:1;
 330         unsigned int lvds_use_ssc:1;
 331         int lvds_ssc_freq;
 332         bool is_lvds_on;
 333         bool is_mipi_on;
 334
 335         unsigned int core_freq;
 336         uint32_t iLVDS_enable;
 337
 338         /* Runtime PM state */
 339         int rpm_enabled;
 340
 341         /* Moorestown specific */
 342         struct mrst_vbt vbt_data;
 343         struct mrst_gct_data gct_data;
 344
 345         /* Moorestown pipe config register value cache */
 346         uint32_t pipeconf;
 347         uint32_t pipeconf1;
 348         uint32_t pipeconf2;
 349
 350         /* Moorestown plane control register value cache */
 351         uint32_t dspcntr;
 352         uint32_t dspcntr1;
 353         uint32_t dspcntr2;
 354
 355         /*
 356          * Register state
 357          */
 358         uint32_t saveDSPACNTR;
 359         uint32_t saveDSPBCNTR;
 360         uint32_t savePIPEACONF;
 361         uint32_t savePIPEBCONF;
 362         uint32_t savePIPEASRC;
 363         uint32_t savePIPEBSRC;
 364         uint32_t saveFPA0;
 365         uint32_t saveFPA1;
 366         uint32_t saveDPLL_A;
 367         uint32_t saveDPLL_A_MD;
 368         uint32_t saveHTOTAL_A;
 369         uint32_t saveHBLANK_A;
 370         uint32_t saveHSYNC_A;
 371         uint32_t saveVTOTAL_A;
 372         uint32_t saveVBLANK_A;
 373         uint32_t saveVSYNC_A;
 374         uint32_t saveDSPASTRIDE;
 375         uint32_t saveDSPASIZE;
 376         uint32_t saveDSPAPOS;
 377         uint32_t saveDSPABASE;
 378         uint32_t saveDSPASURF;
 379         uint32_t saveFPB0;
 380         uint32_t saveFPB1;
 381         uint32_t saveDPLL_B;
 382         uint32_t saveDPLL_B_MD;
 383         uint32_t saveHTOTAL_B;
 384         uint32_t saveHBLANK_B;
 385         uint32_t saveHSYNC_B;
 386         uint32_t saveVTOTAL_B;
 387         uint32_t saveVBLANK_B;
 388         uint32_t saveVSYNC_B;
 389         uint32_t saveDSPBSTRIDE;
 390         uint32_t saveDSPBSIZE;
 391         uint32_t saveDSPBPOS;
 392         uint32_t saveDSPBBASE;
 393         uint32_t saveDSPBSURF;
 394         uint32_t saveVCLK_DIVISOR_VGA0;
 395         uint32_t saveVCLK_DIVISOR_VGA1;
 396         uint32_t saveVCLK_POST_DIV;
 397         uint32_t saveVGACNTRL;
 398         uint32_t saveADPA;
 399         uint32_t saveLVDS;
 400         uint32_t saveDVOA;
 401         uint32_t saveDVOB;
 402         uint32_t saveDVOC;
 403         uint32_t savePP_ON;
 404         uint32_t savePP_OFF;
 405         uint32_t savePP_CONTROL;
 406         uint32_t savePP_CYCLE;
 407         uint32_t savePFIT_CONTROL;
 408         uint32_t savePaletteA[256];
 409         uint32_t savePaletteB[256];
 410         uint32_t saveBLC_PWM_CTL2;
 411         uint32_t saveBLC_PWM_CTL;
 412         uint32_t saveCLOCKGATING;
 413         uint32_t saveDSPARB;
 414         uint32_t saveDSPATILEOFF;
 415         uint32_t saveDSPBTILEOFF;
 416         uint32_t saveDSPAADDR;
 417         uint32_t saveDSPBADDR;
 418         uint32_t savePFIT_AUTO_RATIOS;
 419         uint32_t savePFIT_PGM_RATIOS;
 420         uint32_t savePP_ON_DELAYS;
 421         uint32_t savePP_OFF_DELAYS;
 422         uint32_t savePP_DIVISOR;
 423         uint32_t saveBSM;
 424         uint32_t saveVBT;
 425         uint32_t saveBCLRPAT_A;
 426         uint32_t saveBCLRPAT_B;
 427         uint32_t saveDSPALINOFF;
 428         uint32_t saveDSPBLINOFF;
 429         uint32_t savePERF_MODE;
 430         uint32_t saveDSPFW1;
 431         uint32_t saveDSPFW2;
 432         uint32_t saveDSPFW3;
 433         uint32_t saveDSPFW4;
 434         uint32_t saveDSPFW5;
 435         uint32_t saveDSPFW6;
 436         uint32_t saveCHICKENBIT;
 437         uint32_t saveDSPACURSOR_CTRL;
 438         uint32_t saveDSPBCURSOR_CTRL;
 439         uint32_t saveDSPACURSOR_BASE;
 440         uint32_t saveDSPBCURSOR_BASE;
 441         uint32_t saveDSPACURSOR_POS;
 442         uint32_t saveDSPBCURSOR_POS;
 443         uint32_t save_palette_a[256];
 444         uint32_t save_palette_b[256];
 445         uint32_t saveOV_OVADD;
 446         uint32_t saveOV_OGAMC0;
 447         uint32_t saveOV_OGAMC1;
 448         uint32_t saveOV_OGAMC2;
 449         uint32_t saveOV_OGAMC3;
 450         uint32_t saveOV_OGAMC4;
 451         uint32_t saveOV_OGAMC5;
 452         uint32_t saveOVC_OVADD;
 453         uint32_t saveOVC_OGAMC0;
 454         uint32_t saveOVC_OGAMC1;
 455         uint32_t saveOVC_OGAMC2;
 456         uint32_t saveOVC_OGAMC3;
 457         uint32_t saveOVC_OGAMC4;
 458         uint32_t saveOVC_OGAMC5;
 459
 460         /* MSI reg save */
 461         uint32_t msi_addr;
 462         uint32_t msi_data;
 463
 464         /*
 465          * LID-Switch
 466          */
 467         spinlock_t lid_lock;
 468         struct timer_list lid_timer;
 469         struct psb_intel_opregion opregion;
 470         u32 *lid_state;
 471         u32 lid_last_state;
 472
 473         /*
 474          * Watchdog
 475          */
 476
 477         uint32_t apm_reg;
 478         uint16_t apm_base;
 479
 480         /*
 481          * Used for modifying backlight from
 482          * xrandr -- consider removing and using HAL instead
 483          */
 484         struct drm_property *backlight_property;
 485         uint32_t blc_adj1;
 486         uint32_t blc_adj2;
 487
 488         void *fbdev;
 489 };
 490
 491
 492 struct psb_mmu_driver;
 493
 494 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 495 extern int drm_pick_crtcs(struct drm_device *dev);
 496
 497 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 498 {
 499         return (struct drm_psb_private *) dev->dev_private;
 500 }
 501
 502 /*
 503  * MMU stuff.
 504  */
 505
 506 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 507                                         int trap_pagefaults,
 508                                         int invalid_type,
 509                                         struct drm_psb_private *dev_priv);
 510 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 511 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 512                                                  *driver);
 513 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 514                                uint32_t gtt_start, uint32_t gtt_pages);
 515 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 516                                            int trap_pagefaults,
 517                                            int invalid_type);
 518 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 519 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 520 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 521                                         unsigned long address,
 522                                         uint32_t num_pages);
 523 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 524                                        uint32_t start_pfn,
 525                                        unsigned long address,
 526                                        uint32_t num_pages, int type);
 527 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 528                                   unsigned long *pfn);
 529
 530 /*
 531  * Enable / disable MMU for different requestors.
 532  */
 533
 534
 535 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 536 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 537                                 unsigned long address, uint32_t num_pages,
 538                                 uint32_t desired_tile_stride,
 539                                 uint32_t hw_tile_stride, int type);
 540 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 541                                  unsigned long address, uint32_t num_pages,
 542                                  uint32_t desired_tile_stride,
 543                                  uint32_t hw_tile_stride);
 544 /*
 545  *psb_irq.c
 546  */
 547
 548 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 549 extern int psb_irq_enable_dpst(struct drm_device *dev);
 550 extern int psb_irq_disable_dpst(struct drm_device *dev);
 551 extern void psb_irq_preinstall(struct drm_device *dev);
 552 extern int psb_irq_postinstall(struct drm_device *dev);
 553 extern void psb_irq_uninstall(struct drm_device *dev);
 554 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 555 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 556
 557 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 558 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 559 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 560 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 561 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 562 void
 563 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 564
 565 void
 566 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 567
 568 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 569
 570 /*
 571  * psb_opregion.c
 572  */
 573 extern int psb_intel_opregion_init(struct drm_device *dev);
 574
 575 /*
 576  *psb_fb.c
 577  */
 578 extern int psbfb_probed(struct drm_device *dev);
 579 extern int psbfb_remove(struct drm_device *dev,
 580                         struct drm_framebuffer *fb);
 581 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
 582                                struct drm_file *file_priv);
 583 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
 584                               struct drm_file *file_priv);
 585 extern void *psbfb_vdc_reg(struct drm_device* dev);
 586
 587 /*
 588  * psb_2d.c
 589  */
 590 extern void psbfb_copyarea(struct fb_info *info,
 591                                         const struct fb_copyarea *region);
 592 extern int psbfb_sync(struct fb_info *info);
 593 extern void psb_spank(struct drm_psb_private *dev_priv);
 594 extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
 595                                         unsigned size);
 596
 597 /*
 598  * psb_reset.c
 599  */
 600
 601 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 602 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 603 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 604
 605 /* modesetting */
 606 extern void psb_modeset_init(struct drm_device *dev);
 607 extern void psb_modeset_cleanup(struct drm_device *dev);
 608 extern int psb_fbdev_init(struct drm_device *dev);
 609
 610 /* psb_bl.c */
 611 int psb_backlight_init(struct drm_device *dev);
 612 void psb_backlight_exit(void);
 613 int psb_set_brightness(struct backlight_device *bd);
 614 int psb_get_brightness(struct backlight_device *bd);
 615 struct backlight_device *psb_get_backlight_device(void);
 616
 617 /* mrst_crtc.c */
 618 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 619
 620 /* mrst_lvds.c */
 621 extern void mrst_lvds_init(struct drm_device *dev,
 622                     struct psb_intel_mode_device *mode_dev);
 623
 624 /* psb_intel_lvds.c */
 625 extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
 626 extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
 627 extern const struct drm_connector_helper_funcs
 628                                         psb_intel_lvds_connector_helper_funcs;
 629 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 630
 631 /* psb_gem.c */
 632 extern int psb_gem_init_object(struct drm_gem_object *obj);
 633 extern void psb_gem_free_object(struct drm_gem_object *obj);
 634 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 635                                 struct drm_file *file);
 636 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 637                         struct drm_mode_create_dumb *args);
 638 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 639                         uint32_t handle);
 640 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 641                          uint32_t handle, uint64_t *offset);
 642 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 643
 644
 645 /*
 646  * Debug print bits setting
 647  */
 648 #define PSB_D_GENERAL (1 << 0)
 649 #define PSB_D_INIT    (1 << 1)
 650 #define PSB_D_IRQ     (1 << 2)
 651 #define PSB_D_ENTRY   (1 << 3)
 652 /* debug the get H/V BP/FP count */
 653 #define PSB_D_HV      (1 << 4)
 654 #define PSB_D_DBI_BF  (1 << 5)
 655 #define PSB_D_PM      (1 << 6)
 656 #define PSB_D_RENDER  (1 << 7)
 657 #define PSB_D_REG     (1 << 8)
 658 #define PSB_D_MSVDX   (1 << 9)
 659 #define PSB_D_TOPAZ   (1 << 10)
 660
 661 extern int drm_psb_no_fb;
 662 extern int drm_idle_check_interval;
 663
 664 /*
 665  *      Utilities
 666  */
 667
 668 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 669 {
 670         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 671         uint32_t ret_val = 0;
 672         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 673         pci_write_config_dword(pci_root, 0xD0, mcr);
 674         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 675         pci_dev_put(pci_root);
 676         return ret_val;
 677 }
 678 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 679 {
 680         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 681         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 682         pci_write_config_dword(pci_root, 0xD4, value);
 683         pci_write_config_dword(pci_root, 0xD0, mcr);
 684         pci_dev_put(pci_root);
 685 }
 686 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 687 {
 688         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 689         uint32_t ret_val = 0;
 690         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 691         pci_write_config_dword(pci_root, 0xD0, mcr);
 692         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 693         pci_dev_put(pci_root);
 694         return ret_val;
 695 }
 696 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 697 {
 698         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 699         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 700         pci_write_config_dword(pci_root, 0xD4, value);
 701         pci_write_config_dword(pci_root, 0xD0, mcr);
 702         pci_dev_put(pci_root);
 703 }
 704
 705 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 706 {
 707         struct drm_psb_private *dev_priv = dev->dev_private;
 708         return ioread32(dev_priv->vdc_reg + reg);
 709 }
 710
 711 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 712
 713 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 714                                       uint32_t val)
 715 {
 716         struct drm_psb_private *dev_priv = dev->dev_private;
 717         iowrite32((val), dev_priv->vdc_reg + (reg));
 718 }
 719
 720 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 721
 722 static inline void REGISTER_WRITE16(struct drm_device *dev,
 723                                         uint32_t reg, uint32_t val)
 724 {
 725         struct drm_psb_private *dev_priv = dev->dev_private;
 726         iowrite16((val), dev_priv->vdc_reg + (reg));
 727 }
 728
 729 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 730
 731 static inline void REGISTER_WRITE8(struct drm_device *dev,
 732                                        uint32_t reg, uint32_t val)
 733 {
 734         struct drm_psb_private *dev_priv = dev->dev_private;
 735         iowrite8((val), dev_priv->vdc_reg + (reg));
 736 }
 737
 738 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 739
 740 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 741 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 742
 743 /* #define TRAP_SGX_PM_FAULT 1 */
 744 #ifdef TRAP_SGX_PM_FAULT
 745 #define PSB_RSGX32(_offs)                                               \
 746 ({                                                                      \
 747         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 748                 printk(KERN_ERR                                         \
 749                         "access sgx when it's off!! (READ) %s, %d\n",   \
 750                __FILE__, __LINE__);                                     \
 751                 melay(1000);                                            \
 752         }                                                               \
 753         ioread32(dev_priv->sgx_reg + (_offs));                          \
 754 })
 755 #else
 756 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 757 #endif
 758 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
 759
 760 #define MSVDX_REG_DUMP 0
 761
 762 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 763 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
 764
 765 #endif