2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
13 #include <asm/processor.h>
14 #include <asm/tlbflush.h>
15 #include <asm/sections.h>
16 #include <asm/uaccess.h>
17 #include <asm/pgalloc.h>
33 within(unsigned long addr
, unsigned long start
, unsigned long end
)
35 return addr
>= start
&& addr
< end
;
43 * clflush_cache_range - flush a cache range with clflush
44 * @addr: virtual start address
45 * @size: number of bytes to flush
47 * clflush is an unordered instruction which needs fencing with mfence
48 * to avoid ordering issues.
50 void clflush_cache_range(void *vaddr
, unsigned int size
)
52 void *vend
= vaddr
+ size
- 1;
56 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
59 * Flush any possible final partial cacheline:
66 static void __cpa_flush_all(void *arg
)
68 unsigned long cache
= (unsigned long)arg
;
71 * Flush all to work around Errata in early athlons regarding
72 * large page flushing.
76 if (cache
&& boot_cpu_data
.x86_model
>= 4)
80 static void cpa_flush_all(unsigned long cache
)
82 BUG_ON(irqs_disabled());
84 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1, 1);
87 static void __cpa_flush_range(void *arg
)
90 * We could optimize that further and do individual per page
91 * tlb invalidates for a low number of pages. Caveat: we must
92 * flush the high aliases on 64bit as well.
97 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
99 unsigned int i
, level
;
102 BUG_ON(irqs_disabled());
103 WARN_ON(PAGE_ALIGN(start
) != start
);
105 on_each_cpu(__cpa_flush_range
, NULL
, 1, 1);
111 * We only need to flush on one CPU,
112 * clflush is a MESI-coherent instruction that
113 * will cause all other CPUs to flush the same
116 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
117 pte_t
*pte
= lookup_address(addr
, &level
);
120 * Only flush present addresses:
122 if (pte
&& pte_present(*pte
))
123 clflush_cache_range((void *) addr
, PAGE_SIZE
);
127 #define HIGH_MAP_START __START_KERNEL_map
128 #define HIGH_MAP_END (__START_KERNEL_map + KERNEL_TEXT_SIZE)
132 * Converts a virtual address to a X86-64 highmap address
134 static unsigned long virt_to_highmap(void *address
)
137 return __pa((unsigned long)address
) + HIGH_MAP_START
- phys_base
;
139 return (unsigned long)address
;
144 * Certain areas of memory on x86 require very specific protection flags,
145 * for example the BIOS area or kernel text. Callers don't always get this
146 * right (again, ioremap() on BIOS memory is not uncommon) so this function
147 * checks and fixes these known static required protection bits.
149 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
)
151 pgprot_t forbidden
= __pgprot(0);
154 * The BIOS area between 640k and 1Mb needs to be executable for
155 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
157 if (within(__pa(address
), BIOS_BEGIN
, BIOS_END
))
158 pgprot_val(forbidden
) |= _PAGE_NX
;
161 * The kernel text needs to be executable for obvious reasons
162 * Does not cover __inittext since that is gone later on
164 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
165 pgprot_val(forbidden
) |= _PAGE_NX
;
167 * Do the same for the x86-64 high kernel mapping
169 if (within(address
, virt_to_highmap(_text
), virt_to_highmap(_etext
)))
170 pgprot_val(forbidden
) |= _PAGE_NX
;
173 #ifdef CONFIG_DEBUG_RODATA
174 /* The .rodata section needs to be read-only */
175 if (within(address
, (unsigned long)__start_rodata
,
176 (unsigned long)__end_rodata
))
177 pgprot_val(forbidden
) |= _PAGE_RW
;
179 * Do the same for the x86-64 high kernel mapping
181 if (within(address
, virt_to_highmap(__start_rodata
),
182 virt_to_highmap(__end_rodata
)))
183 pgprot_val(forbidden
) |= _PAGE_RW
;
186 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
191 pte_t
*lookup_address(unsigned long address
, int *level
)
193 pgd_t
*pgd
= pgd_offset_k(address
);
197 *level
= PG_LEVEL_NONE
;
201 pud
= pud_offset(pgd
, address
);
204 pmd
= pmd_offset(pud
, address
);
208 *level
= PG_LEVEL_2M
;
212 *level
= PG_LEVEL_4K
;
213 return pte_offset_kernel(pmd
, address
);
216 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
219 set_pte_atomic(kpte
, pte
);
221 if (!SHARED_KERNEL_PMD
) {
224 list_for_each_entry(page
, &pgd_list
, lru
) {
229 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
230 pud
= pud_offset(pgd
, address
);
231 pmd
= pmd_offset(pud
, address
);
232 set_pte_atomic((pte_t
*)pmd
, pte
);
238 static int try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
239 struct cpa_data
*cpa
)
241 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
;
242 pte_t new_pte
, old_pte
, *tmp
;
243 pgprot_t old_prot
, new_prot
;
244 int level
, res
= CPA_SPLIT
;
246 spin_lock_irqsave(&pgd_lock
, flags
);
248 * Check for races, another CPU might have split this page
251 tmp
= lookup_address(address
, &level
);
257 psize
= LARGE_PAGE_SIZE
;
258 pmask
= LARGE_PAGE_MASK
;
267 * Calculate the number of pages, which fit into this large
268 * page starting at address:
270 nextpage_addr
= (address
+ psize
) & pmask
;
271 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
272 if (numpages
< cpa
->numpages
)
273 cpa
->numpages
= numpages
;
276 * We are safe now. Check whether the new pgprot is the same:
279 old_prot
= new_prot
= pte_pgprot(old_pte
);
281 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
282 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
283 new_prot
= static_protections(new_prot
, address
);
286 * If there are no changes, return. maxpages has been updated
289 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
295 * We need to change the attributes. Check, whether we can
296 * change the large page in one go. We request a split, when
297 * the address is not aligned and the number of pages is
298 * smaller than the number of pages in the large page. Note
299 * that we limited the number of possible pages already to
300 * the number of pages in the large page.
302 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
304 * The address is aligned and the number of pages
305 * covers the full page.
307 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
308 __set_pmd_pte(kpte
, address
, new_pte
);
314 spin_unlock_irqrestore(&pgd_lock
, flags
);
318 static int split_large_page(pte_t
*kpte
, unsigned long address
)
320 pgprot_t ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
321 gfp_t gfp_flags
= GFP_KERNEL
;
322 unsigned long flags
, addr
, pfn
;
325 unsigned int i
, level
;
327 #ifdef CONFIG_DEBUG_PAGEALLOC
328 gfp_flags
= __GFP_HIGH
| __GFP_NOFAIL
| __GFP_NOWARN
;
329 gfp_flags
= GFP_ATOMIC
| __GFP_NOWARN
;
331 base
= alloc_pages(gfp_flags
, 0);
335 spin_lock_irqsave(&pgd_lock
, flags
);
337 * Check for races, another CPU might have split this page
340 tmp
= lookup_address(address
, &level
);
346 address
= __pa(address
);
347 addr
= address
& LARGE_PAGE_MASK
;
348 pbase
= (pte_t
*)page_address(base
);
350 paravirt_alloc_pt(&init_mm
, page_to_pfn(base
));
354 * Get the target pfn from the original entry:
356 pfn
= pte_pfn(*kpte
);
357 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
++)
358 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
361 * Install the new, split up pagetable. Important detail here:
363 * On Intel the NX bit of all levels must be cleared to make a
364 * page executable. See section 4.13.2 of Intel 64 and IA-32
365 * Architectures Software Developer's Manual).
367 ref_prot
= pte_pgprot(pte_mkexec(pte_clrhuge(*kpte
)));
368 __set_pmd_pte(kpte
, address
, mk_pte(base
, ref_prot
));
372 spin_unlock_irqrestore(&pgd_lock
, flags
);
375 __free_pages(base
, 0);
380 static int __change_page_attr(unsigned long address
, struct cpa_data
*cpa
)
382 struct page
*kpte_page
;
387 kpte
= lookup_address(address
, &level
);
391 kpte_page
= virt_to_page(kpte
);
392 BUG_ON(PageLRU(kpte_page
));
393 BUG_ON(PageCompound(kpte_page
));
395 if (level
== PG_LEVEL_4K
) {
396 pte_t new_pte
, old_pte
= *kpte
;
397 pgprot_t new_prot
= pte_pgprot(old_pte
);
399 if(!pte_val(old_pte
)) {
400 printk(KERN_WARNING
"CPA: called for zero pte. "
401 "vaddr = %lx cpa->vaddr = %lx\n", address
,
407 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
408 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
410 new_prot
= static_protections(new_prot
, address
);
413 * We need to keep the pfn from the existing PTE,
414 * after all we're only going to change it's attributes
415 * not the memory it points to
417 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
420 * Do we really change anything ?
422 if (pte_val(old_pte
) != pte_val(new_pte
)) {
423 set_pte_atomic(kpte
, new_pte
);
431 * Check, whether we can keep the large page intact
432 * and just change the pte:
434 res
= try_preserve_large_page(kpte
, address
, cpa
);
439 * When the range fits into the existing large page,
440 * return. cp->numpages and cpa->tlbflush have been updated in
443 if (res
== CPA_NO_SPLIT
)
447 * We have to split the large page:
449 res
= split_large_page(kpte
, address
);
457 * change_page_attr_addr - Change page table attributes in linear mapping
458 * @address: Virtual address in linear mapping.
459 * @prot: New page table attribute (PAGE_*)
461 * Change page attributes of a page in the direct mapping. This is a variant
462 * of change_page_attr() that also works on memory holes that do not have
463 * mem_map entry (pfn_valid() is false).
465 * See change_page_attr() documentation for more details.
467 * Modules and drivers should use the set_memory_* APIs instead.
470 static int change_page_attr_addr(struct cpa_data
*cpa
)
473 unsigned long address
= cpa
->vaddr
;
476 unsigned long phys_addr
= __pa(address
);
479 * If we are inside the high mapped kernel range, then we
480 * fixup the low mapping first. __va() returns the virtual
481 * address in the linear mapping:
483 if (within(address
, HIGH_MAP_START
, HIGH_MAP_END
))
484 address
= (unsigned long) __va(phys_addr
);
487 err
= __change_page_attr(address
, cpa
);
493 * If the physical address is inside the kernel map, we need
494 * to touch the high mapped kernel as well:
496 if (within(phys_addr
, 0, KERNEL_TEXT_SIZE
)) {
498 * Calc the high mapping address. See __phys_addr()
499 * for the non obvious details.
501 * Note that NX and other required permissions are
502 * checked in static_protections().
504 address
= phys_addr
+ HIGH_MAP_START
- phys_base
;
507 * Our high aliases are imprecise, because we check
508 * everything between 0 and KERNEL_TEXT_SIZE, so do
509 * not propagate lookup failures back to users:
511 __change_page_attr(address
, cpa
);
517 static int __change_page_attr_set_clr(struct cpa_data
*cpa
)
519 int ret
, numpages
= cpa
->numpages
;
523 * Store the remaining nr of pages for the large page
524 * preservation check.
526 cpa
->numpages
= numpages
;
527 ret
= change_page_attr_addr(cpa
);
532 * Adjust the number of pages with the result of the
533 * CPA operation. Either a large page has been
534 * preserved or a single page update happened.
536 BUG_ON(cpa
->numpages
> numpages
);
537 numpages
-= cpa
->numpages
;
538 cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
543 static inline int cache_attr(pgprot_t attr
)
545 return pgprot_val(attr
) &
546 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
549 static int change_page_attr_set_clr(unsigned long addr
, int numpages
,
550 pgprot_t mask_set
, pgprot_t mask_clr
)
556 * Check, if we are requested to change a not supported
559 mask_set
= canon_pgprot(mask_set
);
560 mask_clr
= canon_pgprot(mask_clr
);
561 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
))
565 cpa
.numpages
= numpages
;
566 cpa
.mask_set
= mask_set
;
567 cpa
.mask_clr
= mask_clr
;
570 ret
= __change_page_attr_set_clr(&cpa
);
573 * Check whether we really changed something:
579 * No need to flush, when we did not set any of the caching
582 cache
= cache_attr(mask_set
);
585 * On success we use clflush, when the CPU supports it to
586 * avoid the wbindv. If the CPU does not support it and in the
587 * error case we fall back to cpa_flush_all (which uses
590 if (!ret
&& cpu_has_clflush
)
591 cpa_flush_range(addr
, numpages
, cache
);
593 cpa_flush_all(cache
);
598 static inline int change_page_attr_set(unsigned long addr
, int numpages
,
601 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0));
604 static inline int change_page_attr_clear(unsigned long addr
, int numpages
,
607 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
);
610 int set_memory_uc(unsigned long addr
, int numpages
)
612 return change_page_attr_set(addr
, numpages
,
613 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
615 EXPORT_SYMBOL(set_memory_uc
);
617 int set_memory_wb(unsigned long addr
, int numpages
)
619 return change_page_attr_clear(addr
, numpages
,
620 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
622 EXPORT_SYMBOL(set_memory_wb
);
624 int set_memory_x(unsigned long addr
, int numpages
)
626 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_NX
));
628 EXPORT_SYMBOL(set_memory_x
);
630 int set_memory_nx(unsigned long addr
, int numpages
)
632 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_NX
));
634 EXPORT_SYMBOL(set_memory_nx
);
636 int set_memory_ro(unsigned long addr
, int numpages
)
638 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_RW
));
641 int set_memory_rw(unsigned long addr
, int numpages
)
643 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_RW
));
646 int set_memory_np(unsigned long addr
, int numpages
)
648 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_PRESENT
));
651 int set_pages_uc(struct page
*page
, int numpages
)
653 unsigned long addr
= (unsigned long)page_address(page
);
655 return set_memory_uc(addr
, numpages
);
657 EXPORT_SYMBOL(set_pages_uc
);
659 int set_pages_wb(struct page
*page
, int numpages
)
661 unsigned long addr
= (unsigned long)page_address(page
);
663 return set_memory_wb(addr
, numpages
);
665 EXPORT_SYMBOL(set_pages_wb
);
667 int set_pages_x(struct page
*page
, int numpages
)
669 unsigned long addr
= (unsigned long)page_address(page
);
671 return set_memory_x(addr
, numpages
);
673 EXPORT_SYMBOL(set_pages_x
);
675 int set_pages_nx(struct page
*page
, int numpages
)
677 unsigned long addr
= (unsigned long)page_address(page
);
679 return set_memory_nx(addr
, numpages
);
681 EXPORT_SYMBOL(set_pages_nx
);
683 int set_pages_ro(struct page
*page
, int numpages
)
685 unsigned long addr
= (unsigned long)page_address(page
);
687 return set_memory_ro(addr
, numpages
);
690 int set_pages_rw(struct page
*page
, int numpages
)
692 unsigned long addr
= (unsigned long)page_address(page
);
694 return set_memory_rw(addr
, numpages
);
697 #ifdef CONFIG_DEBUG_PAGEALLOC
699 static int __set_pages_p(struct page
*page
, int numpages
)
701 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
702 .numpages
= numpages
,
703 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
704 .mask_clr
= __pgprot(0)};
706 return __change_page_attr_set_clr(&cpa
);
709 static int __set_pages_np(struct page
*page
, int numpages
)
711 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
712 .numpages
= numpages
,
713 .mask_set
= __pgprot(0),
714 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
)};
716 return __change_page_attr_set_clr(&cpa
);
719 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
721 if (PageHighMem(page
))
724 debug_check_no_locks_freed(page_address(page
),
725 numpages
* PAGE_SIZE
);
729 * If page allocator is not up yet then do not call c_p_a():
731 if (!debug_pagealloc_enabled
)
735 * The return value is ignored - the calls cannot fail,
736 * large pages are disabled at boot time:
739 __set_pages_p(page
, numpages
);
741 __set_pages_np(page
, numpages
);
744 * We should perform an IPI and flush all tlbs,
745 * but that can deadlock->flush only current cpu:
752 * The testcases use internal knowledge of the implementation that shouldn't
753 * be exposed to the rest of the kernel. Include these directly here.
755 #ifdef CONFIG_CPA_DEBUG
756 #include "pageattr-test.c"