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drm/nouveau: Kill global state in NvShadowBIOS
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
blob519faa9550455dbee8f9a0d41649b920f669b41c
1 /*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "drmP.h"
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29
30 /* these defines are made up */
31 #define NV_CIO_CRE_44_HEADA 0x0
32 #define NV_CIO_CRE_44_HEADB 0x3
33 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34 #define LEGACY_I2C_CRT 0x80
35 #define LEGACY_I2C_PANEL 0x81
36 #define LEGACY_I2C_TV 0x82
37
38 #define EDID1_LEN 128
39
40 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41 #define LOG_OLD_VALUE(x)
42
43 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
45
46 struct init_exec {
47 bool execute;
48 bool repeat;
49 };
50
51 static bool nv_cksum(const uint8_t *data, unsigned int length)
52 {
53 /*
54 * There's a few checksums in the BIOS, so here's a generic checking
55 * function.
56 */
57 int i;
58 uint8_t sum = 0;
59
60 for (i = 0; i < length; i++)
61 sum += data[i];
62
63 if (sum)
64 return true;
65
66 return false;
67 }
68
69 static int
70 score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
71 {
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
74 return 0;
75 }
76
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
81 } else
82 NV_TRACE(dev, "... appears to be valid\n");
83
84 return 3;
85 }
86
87 static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
88 {
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
91 int pcir_ptr;
92 int i;
93
94 if (dev_priv->card_type >= NV_50)
95 pci_nv_20 = 0x88050;
96 else
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
98
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
103
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
107 goto out;
108
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
116 goto out;
117
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
121 */
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
124
125 out:
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
129 }
130
131 static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
132 {
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
135 int i;
136
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
139
140 if (!vbios_vram)
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
142
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
145 }
146
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
150 goto out;
151
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
154
155 out:
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
158 }
159
160 static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
161 {
162 void __iomem *rom = NULL;
163 size_t rom_len;
164 int ret;
165
166 ret = pci_enable_rom(dev->pdev);
167 if (ret)
168 return;
169
170 rom = pci_map_rom(dev->pdev, &rom_len);
171 if (!rom)
172 goto out;
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
175
176 out:
177 pci_disable_rom(dev->pdev);
178 }
179
180 struct methods {
181 const char desc[8];
182 void (*loadbios)(struct drm_device *, uint8_t *);
183 const bool rw;
184 };
185
186 static struct methods nv04_methods[] = {
187 { "PROM", load_vbios_prom, false },
188 { "PRAMIN", load_vbios_pramin, true },
189 { "PCIROM", load_vbios_pci, true },
190 };
191
192 static struct methods nv50_methods[] = {
193 { "PRAMIN", load_vbios_pramin, true },
194 { "PROM", load_vbios_prom, false },
195 { "PCIROM", load_vbios_pci, true },
196 };
197
198 #define METHODCNT 3
199
200 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
201 {
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
203 struct methods *methods;
204 int i;
205 int testscore = 3;
206 int scores[METHODCNT];
207
208 if (nouveau_vbios) {
209 methods = nv04_methods;
210 for (i = 0; i < METHODCNT; i++)
211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
212 break;
213
214 if (i < METHODCNT) {
215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
216 methods[i].desc);
217
218 methods[i].loadbios(dev, data);
219 if (score_vbios(dev, data, methods[i].rw))
220 return true;
221 }
222
223 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
224 }
225
226 if (dev_priv->card_type < NV_50)
227 methods = nv04_methods;
228 else
229 methods = nv50_methods;
230
231 for (i = 0; i < METHODCNT; i++) {
232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
233 methods[i].desc);
234 data[0] = data[1] = 0; /* avoid reuse of previous image */
235 methods[i].loadbios(dev, data);
236 scores[i] = score_vbios(dev, data, methods[i].rw);
237 if (scores[i] == testscore)
238 return true;
239 }
240
241 while (--testscore > 0) {
242 for (i = 0; i < METHODCNT; i++) {
243 if (scores[i] == testscore) {
244 NV_TRACE(dev, "Using BIOS image from %s\n",
245 methods[i].desc);
246 methods[i].loadbios(dev, data);
247 return true;
248 }
249 }
250 }
251
252 NV_ERROR(dev, "No valid BIOS image found\n");
253 return false;
254 }
255
256 struct init_tbl_entry {
257 char *name;
258 uint8_t id;
259 int length;
260 int length_offset;
261 int length_multiplier;
262 bool (*handler)(struct nvbios *, uint16_t, struct init_exec *);
263 };
264
265 struct bit_entry {
266 uint8_t id[2];
267 uint16_t length;
268 uint16_t offset;
269 };
270
271 static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
272
273 #define MACRO_INDEX_SIZE 2
274 #define MACRO_SIZE 8
275 #define CONDITION_SIZE 12
276 #define IO_FLAG_CONDITION_SIZE 9
277 #define IO_CONDITION_SIZE 5
278 #define MEM_INIT_SIZE 66
279
280 static void still_alive(void)
281 {
282 #if 0
283 sync();
284 msleep(2);
285 #endif
286 }
287
288 static uint32_t
289 munge_reg(struct nvbios *bios, uint32_t reg)
290 {
291 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
292 struct dcb_entry *dcbent = bios->display.output;
293
294 if (dev_priv->card_type < NV_50)
295 return reg;
296
297 if (reg & 0x40000000) {
298 BUG_ON(!dcbent);
299
300 reg += (ffs(dcbent->or) - 1) * 0x800;
301 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
302 reg += 0x00000080;
303 }
304
305 reg &= ~0x60000000;
306 return reg;
307 }
308
309 static int
310 valid_reg(struct nvbios *bios, uint32_t reg)
311 {
312 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
313 struct drm_device *dev = bios->dev;
314
315 /* C51 has misaligned regs on purpose. Marvellous */
316 if (reg & 0x2 || (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) {
317 NV_ERROR(dev, "========== misaligned reg 0x%08X ==========\n",
318 reg);
319 return 0;
320 }
321 /*
322 * Warn on C51 regs that have not been verified accessible in
323 * mmiotracing
324 */
325 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
326 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
327 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
328 reg);
329
330 /* Trust the init scripts on G80 */
331 if (dev_priv->card_type >= NV_50)
332 return 1;
333
334 #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
335 if (WITHIN(reg, NV_PMC_OFFSET, NV_PMC_SIZE))
336 return 1;
337 if (WITHIN(reg, NV_PBUS_OFFSET, NV_PBUS_SIZE))
338 return 1;
339 if (WITHIN(reg, NV_PFIFO_OFFSET, NV_PFIFO_SIZE))
340 return 1;
341 if (dev_priv->VBIOS.pub.chip_version >= 0x30 &&
342 (WITHIN(reg, 0x4000, 0x600) || reg == 0x00004600))
343 return 1;
344 if (dev_priv->VBIOS.pub.chip_version >= 0x40 &&
345 WITHIN(reg, 0xc000, 0x48))
346 return 1;
347 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0000d204)
348 return 1;
349 if (dev_priv->VBIOS.pub.chip_version >= 0x40) {
350 if (reg == 0x00011014 || reg == 0x00020328)
351 return 1;
352 if (WITHIN(reg, 0x88000, NV_PBUS_SIZE)) /* new PBUS */
353 return 1;
354 }
355 if (WITHIN(reg, NV_PFB_OFFSET, NV_PFB_SIZE))
356 return 1;
357 if (WITHIN(reg, NV_PEXTDEV_OFFSET, NV_PEXTDEV_SIZE))
358 return 1;
359 if (WITHIN(reg, NV_PCRTC0_OFFSET, NV_PCRTC0_SIZE * 2))
360 return 1;
361 if (WITHIN(reg, NV_PRAMDAC0_OFFSET, NV_PRAMDAC0_SIZE * 2))
362 return 1;
363 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0070fff0)
364 return 1;
365 if (dev_priv->VBIOS.pub.chip_version == 0x51 &&
366 WITHIN(reg, NV_PRAMIN_OFFSET, NV_PRAMIN_SIZE))
367 return 1;
368 #undef WITHIN
369
370 NV_ERROR(dev, "========== unknown reg 0x%08X ==========\n", reg);
371
372 return 0;
373 }
374
375 static bool
376 valid_idx_port(struct nvbios *bios, uint16_t port)
377 {
378 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
379 struct drm_device *dev = bios->dev;
380
381 /*
382 * If adding more ports here, the read/write functions below will need
383 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
384 * used for the port in question
385 */
386 if (dev_priv->card_type < NV_50) {
387 if (port == NV_CIO_CRX__COLOR)
388 return true;
389 if (port == NV_VIO_SRX)
390 return true;
391 } else {
392 if (port == NV_CIO_CRX__COLOR)
393 return true;
394 }
395
396 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
397 port);
398
399 return false;
400 }
401
402 static bool
403 valid_port(struct nvbios *bios, uint16_t port)
404 {
405 struct drm_device *dev = bios->dev;
406
407 /*
408 * If adding more ports here, the read/write functions below will need
409 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
410 * used for the port in question
411 */
412 if (port == NV_VIO_VSE2)
413 return true;
414
415 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
416
417 return false;
418 }
419
420 static uint32_t
421 bios_rd32(struct nvbios *bios, uint32_t reg)
422 {
423 uint32_t data;
424
425 reg = munge_reg(bios, reg);
426 if (!valid_reg(bios, reg))
427 return 0;
428
429 /*
430 * C51 sometimes uses regs with bit0 set in the address. For these
431 * cases there should exist a translation in a BIOS table to an IO
432 * port address which the BIOS uses for accessing the reg
433 *
434 * These only seem to appear for the power control regs to a flat panel,
435 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
436 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
437 * suspend-resume mmio trace from a C51 will be required to see if this
438 * is true for the power microcode in 0x14.., or whether the direct IO
439 * port access method is needed
440 */
441 if (reg & 0x1)
442 reg &= ~0x1;
443
444 data = nv_rd32(bios->dev, reg);
445
446 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
447
448 return data;
449 }
450
451 static void
452 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
453 {
454 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
455
456 reg = munge_reg(bios, reg);
457 if (!valid_reg(bios, reg))
458 return;
459
460 /* see note in bios_rd32 */
461 if (reg & 0x1)
462 reg &= 0xfffffffe;
463
464 LOG_OLD_VALUE(bios_rd32(bios, reg));
465 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
466
467 if (dev_priv->VBIOS.execute) {
468 still_alive();
469 nv_wr32(bios->dev, reg, data);
470 }
471 }
472
473 static uint8_t
474 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
475 {
476 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
477 struct drm_device *dev = bios->dev;
478 uint8_t data;
479
480 if (!valid_idx_port(bios, port))
481 return 0;
482
483 if (dev_priv->card_type < NV_50) {
484 if (port == NV_VIO_SRX)
485 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
486 else /* assume NV_CIO_CRX__COLOR */
487 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
488 } else {
489 uint32_t data32;
490
491 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
492 data = (data32 >> ((index & 3) << 3)) & 0xff;
493 }
494
495 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
496 "Head: 0x%02X, Data: 0x%02X\n",
497 port, index, bios->state.crtchead, data);
498 return data;
499 }
500
501 static void
502 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
503 {
504 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
505 struct drm_device *dev = bios->dev;
506
507 if (!valid_idx_port(bios, port))
508 return;
509
510 /*
511 * The current head is maintained in the nvbios member state.crtchead.
512 * We trap changes to CR44 and update the head variable and hence the
513 * register set written.
514 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
515 * of the write, and to head1 after the write
516 */
517 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
518 data != NV_CIO_CRE_44_HEADB)
519 bios->state.crtchead = 0;
520
521 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
522 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
523 "Head: 0x%02X, Data: 0x%02X\n",
524 port, index, bios->state.crtchead, data);
525
526 if (bios->execute && dev_priv->card_type < NV_50) {
527 still_alive();
528 if (port == NV_VIO_SRX)
529 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
530 else /* assume NV_CIO_CRX__COLOR */
531 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
532 } else
533 if (bios->execute) {
534 uint32_t data32, shift = (index & 3) << 3;
535
536 still_alive();
537
538 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
539 data32 &= ~(0xff << shift);
540 data32 |= (data << shift);
541 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
542 }
543
544 if (port == NV_CIO_CRX__COLOR &&
545 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
546 bios->state.crtchead = 1;
547 }
548
549 static uint8_t
550 bios_port_rd(struct nvbios *bios, uint16_t port)
551 {
552 uint8_t data, head = bios->state.crtchead;
553
554 if (!valid_port(bios, port))
555 return 0;
556
557 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
558
559 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
560 port, head, data);
561
562 return data;
563 }
564
565 static void
566 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
567 {
568 int head = bios->state.crtchead;
569
570 if (!valid_port(bios, port))
571 return;
572
573 LOG_OLD_VALUE(bios_port_rd(bios, port));
574 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
575 port, head, data);
576
577 if (!bios->execute)
578 return;
579
580 still_alive();
581 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
582 }
583
584 static bool
585 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
586 {
587 /*
588 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
589 * for the CRTC index; 1 byte for the mask to apply to the value
590 * retrieved from the CRTC; 1 byte for the shift right to apply to the
591 * masked CRTC value; 2 bytes for the offset to the flag array, to
592 * which the shifted value is added; 1 byte for the mask applied to the
593 * value read from the flag array; and 1 byte for the value to compare
594 * against the masked byte from the flag table.
595 */
596
597 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
598 uint16_t crtcport = ROM16(bios->data[condptr]);
599 uint8_t crtcindex = bios->data[condptr + 2];
600 uint8_t mask = bios->data[condptr + 3];
601 uint8_t shift = bios->data[condptr + 4];
602 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
603 uint8_t flagarraymask = bios->data[condptr + 7];
604 uint8_t cmpval = bios->data[condptr + 8];
605 uint8_t data;
606
607 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
608 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
609 "Cmpval: 0x%02X\n",
610 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
611
612 data = bios_idxprt_rd(bios, crtcport, crtcindex);
613
614 data = bios->data[flagarray + ((data & mask) >> shift)];
615 data &= flagarraymask;
616
617 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
618 offset, data, cmpval);
619
620 return (data == cmpval);
621 }
622
623 static bool
624 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
625 {
626 /*
627 * The condition table entry has 4 bytes for the address of the
628 * register to check, 4 bytes for a mask to apply to the register and
629 * 4 for a test comparison value
630 */
631
632 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
633 uint32_t reg = ROM32(bios->data[condptr]);
634 uint32_t mask = ROM32(bios->data[condptr + 4]);
635 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
636 uint32_t data;
637
638 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
639 offset, cond, reg, mask);
640
641 data = bios_rd32(bios, reg) & mask;
642
643 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
644 offset, data, cmpval);
645
646 return (data == cmpval);
647 }
648
649 static bool
650 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
651 {
652 /*
653 * The IO condition entry has 2 bytes for the IO port address; 1 byte
654 * for the index to write to io_port; 1 byte for the mask to apply to
655 * the byte read from io_port+1; and 1 byte for the value to compare
656 * against the masked byte.
657 */
658
659 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
660 uint16_t io_port = ROM16(bios->data[condptr]);
661 uint8_t port_index = bios->data[condptr + 2];
662 uint8_t mask = bios->data[condptr + 3];
663 uint8_t cmpval = bios->data[condptr + 4];
664
665 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
666
667 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
668 offset, data, cmpval);
669
670 return (data == cmpval);
671 }
672
673 static int
674 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
675 {
676 struct drm_nouveau_private *dev_priv = dev->dev_private;
677 uint32_t reg0 = nv_rd32(dev, reg + 0);
678 uint32_t reg1 = nv_rd32(dev, reg + 4);
679 struct nouveau_pll_vals pll;
680 struct pll_lims pll_limits;
681 int ret;
682
683 ret = get_pll_limits(dev, reg, &pll_limits);
684 if (ret)
685 return ret;
686
687 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
688 if (!clk)
689 return -ERANGE;
690
691 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
692 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
693
694 if (dev_priv->VBIOS.execute) {
695 still_alive();
696 nv_wr32(dev, reg + 4, reg1);
697 nv_wr32(dev, reg + 0, reg0);
698 }
699
700 return 0;
701 }
702
703 static int
704 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
705 {
706 struct drm_device *dev = bios->dev;
707 struct drm_nouveau_private *dev_priv = dev->dev_private;
708 /* clk in kHz */
709 struct pll_lims pll_lim;
710 struct nouveau_pll_vals pllvals;
711 int ret;
712
713 if (dev_priv->card_type >= NV_50)
714 return nv50_pll_set(dev, reg, clk);
715
716 /* high regs (such as in the mac g5 table) are not -= 4 */
717 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
718 if (ret)
719 return ret;
720
721 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
722 if (!clk)
723 return -ERANGE;
724
725 if (bios->execute) {
726 still_alive();
727 nouveau_hw_setpll(dev, reg, &pllvals);
728 }
729
730 return 0;
731 }
732
733 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
734 {
735 struct drm_nouveau_private *dev_priv = dev->dev_private;
736 struct nvbios *bios = &dev_priv->VBIOS;
737
738 /*
739 * For the results of this function to be correct, CR44 must have been
740 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
741 * and the DCB table parsed, before the script calling the function is
742 * run. run_digital_op_script is example of how to do such setup
743 */
744
745 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
746
747 if (dcb_entry > bios->bdcb.dcb.entries) {
748 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
749 "(%02X)\n", dcb_entry);
750 dcb_entry = 0x7f; /* unused / invalid marker */
751 }
752
753 return dcb_entry;
754 }
755
756 static struct nouveau_i2c_chan *
757 init_i2c_device_find(struct drm_device *dev, int i2c_index)
758 {
759 struct drm_nouveau_private *dev_priv = dev->dev_private;
760 struct bios_parsed_dcb *bdcb = &dev_priv->VBIOS.bdcb;
761
762 if (i2c_index == 0xff) {
763 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
764 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
765 int default_indices = bdcb->i2c_default_indices;
766
767 if (idx != 0x7f && bdcb->dcb.entry[idx].i2c_upper_default)
768 shift = 4;
769
770 i2c_index = (default_indices >> shift) & 0xf;
771 }
772 if (i2c_index == 0x80) /* g80+ */
773 i2c_index = bdcb->i2c_default_indices & 0xf;
774
775 return nouveau_i2c_find(dev, i2c_index);
776 }
777
778 static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
779 {
780 /*
781 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
782 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
783 * CR58 for CR57 = 0 to index a table of offsets to the basic
784 * 0x6808b0 address.
785 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
786 * CR58 for CR57 = 0 to index a table of offsets to the basic
787 * 0x6808b0 address, and then flip the offset by 8.
788 */
789
790 struct drm_nouveau_private *dev_priv = dev->dev_private;
791 const int pramdac_offset[13] = {
792 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
793 const uint32_t pramdac_table[4] = {
794 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
795
796 if (mlv >= 0x80) {
797 int dcb_entry, dacoffset;
798
799 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
800 dcb_entry = dcb_entry_idx_from_crtchead(dev);
801 if (dcb_entry == 0x7f)
802 return 0;
803 dacoffset = pramdac_offset[
804 dev_priv->VBIOS.bdcb.dcb.entry[dcb_entry].or];
805 if (mlv == 0x81)
806 dacoffset ^= 8;
807 return 0x6808b0 + dacoffset;
808 } else {
809 if (mlv > ARRAY_SIZE(pramdac_table)) {
810 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
811 mlv);
812 return 0;
813 }
814 return pramdac_table[mlv];
815 }
816 }
817
818 static bool
819 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
820 struct init_exec *iexec)
821 {
822 /*
823 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
824 *
825 * offset (8 bit): opcode
826 * offset + 1 (16 bit): CRTC port
827 * offset + 3 (8 bit): CRTC index
828 * offset + 4 (8 bit): mask
829 * offset + 5 (8 bit): shift
830 * offset + 6 (8 bit): count
831 * offset + 7 (32 bit): register
832 * offset + 11 (32 bit): configuration 1
833 * ...
834 *
835 * Starting at offset + 11 there are "count" 32 bit values.
836 * To find out which value to use read index "CRTC index" on "CRTC
837 * port", AND this value with "mask" and then bit shift right "shift"
838 * bits. Read the appropriate value using this index and write to
839 * "register"
840 */
841
842 uint16_t crtcport = ROM16(bios->data[offset + 1]);
843 uint8_t crtcindex = bios->data[offset + 3];
844 uint8_t mask = bios->data[offset + 4];
845 uint8_t shift = bios->data[offset + 5];
846 uint8_t count = bios->data[offset + 6];
847 uint32_t reg = ROM32(bios->data[offset + 7]);
848 uint8_t config;
849 uint32_t configval;
850
851 if (!iexec->execute)
852 return true;
853
854 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
855 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
856 offset, crtcport, crtcindex, mask, shift, count, reg);
857
858 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
859 if (config > count) {
860 NV_ERROR(bios->dev,
861 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
862 offset, config, count);
863 return false;
864 }
865
866 configval = ROM32(bios->data[offset + 11 + config * 4]);
867
868 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
869
870 bios_wr32(bios, reg, configval);
871
872 return true;
873 }
874
875 static bool
876 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
877 {
878 /*
879 * INIT_REPEAT opcode: 0x33 ('3')
880 *
881 * offset (8 bit): opcode
882 * offset + 1 (8 bit): count
883 *
884 * Execute script following this opcode up to INIT_REPEAT_END
885 * "count" times
886 */
887
888 uint8_t count = bios->data[offset + 1];
889 uint8_t i;
890
891 /* no iexec->execute check by design */
892
893 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
894 offset, count);
895
896 iexec->repeat = true;
897
898 /*
899 * count - 1, as the script block will execute once when we leave this
900 * opcode -- this is compatible with bios behaviour as:
901 * a) the block is always executed at least once, even if count == 0
902 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
903 * while we don't
904 */
905 for (i = 0; i < count - 1; i++)
906 parse_init_table(bios, offset + 2, iexec);
907
908 iexec->repeat = false;
909
910 return true;
911 }
912
913 static bool
914 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
915 struct init_exec *iexec)
916 {
917 /*
918 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
919 *
920 * offset (8 bit): opcode
921 * offset + 1 (16 bit): CRTC port
922 * offset + 3 (8 bit): CRTC index
923 * offset + 4 (8 bit): mask
924 * offset + 5 (8 bit): shift
925 * offset + 6 (8 bit): IO flag condition index
926 * offset + 7 (8 bit): count
927 * offset + 8 (32 bit): register
928 * offset + 12 (16 bit): frequency 1
929 * ...
930 *
931 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
932 * Set PLL register "register" to coefficients for frequency n,
933 * selected by reading index "CRTC index" of "CRTC port" ANDed with
934 * "mask" and shifted right by "shift".
935 *
936 * If "IO flag condition index" > 0, and condition met, double
937 * frequency before setting it.
938 */
939
940 uint16_t crtcport = ROM16(bios->data[offset + 1]);
941 uint8_t crtcindex = bios->data[offset + 3];
942 uint8_t mask = bios->data[offset + 4];
943 uint8_t shift = bios->data[offset + 5];
944 int8_t io_flag_condition_idx = bios->data[offset + 6];
945 uint8_t count = bios->data[offset + 7];
946 uint32_t reg = ROM32(bios->data[offset + 8]);
947 uint8_t config;
948 uint16_t freq;
949
950 if (!iexec->execute)
951 return true;
952
953 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
954 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
955 "Count: 0x%02X, Reg: 0x%08X\n",
956 offset, crtcport, crtcindex, mask, shift,
957 io_flag_condition_idx, count, reg);
958
959 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
960 if (config > count) {
961 NV_ERROR(bios->dev,
962 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
963 offset, config, count);
964 return false;
965 }
966
967 freq = ROM16(bios->data[offset + 12 + config * 2]);
968
969 if (io_flag_condition_idx > 0) {
970 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
971 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
972 "frequency doubled\n", offset);
973 freq *= 2;
974 } else
975 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
976 "frequency unchanged\n", offset);
977 }
978
979 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
980 offset, reg, config, freq);
981
982 setPLL(bios, reg, freq * 10);
983
984 return true;
985 }
986
987 static bool
988 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
989 {
990 /*
991 * INIT_END_REPEAT opcode: 0x36 ('6')
992 *
993 * offset (8 bit): opcode
994 *
995 * Marks the end of the block for INIT_REPEAT to repeat
996 */
997
998 /* no iexec->execute check by design */
999
1000 /*
1001 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1002 * we're not in repeat mode
1003 */
1004 if (iexec->repeat)
1005 return false;
1006
1007 return true;
1008 }
1009
1010 static bool
1011 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1012 {
1013 /*
1014 * INIT_COPY opcode: 0x37 ('7')
1015 *
1016 * offset (8 bit): opcode
1017 * offset + 1 (32 bit): register
1018 * offset + 5 (8 bit): shift
1019 * offset + 6 (8 bit): srcmask
1020 * offset + 7 (16 bit): CRTC port
1021 * offset + 9 (8 bit): CRTC index
1022 * offset + 10 (8 bit): mask
1023 *
1024 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1025 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1026 * port
1027 */
1028
1029 uint32_t reg = ROM32(bios->data[offset + 1]);
1030 uint8_t shift = bios->data[offset + 5];
1031 uint8_t srcmask = bios->data[offset + 6];
1032 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1033 uint8_t crtcindex = bios->data[offset + 9];
1034 uint8_t mask = bios->data[offset + 10];
1035 uint32_t data;
1036 uint8_t crtcdata;
1037
1038 if (!iexec->execute)
1039 return true;
1040
1041 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1042 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1043 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1044
1045 data = bios_rd32(bios, reg);
1046
1047 if (shift < 0x80)
1048 data >>= shift;
1049 else
1050 data <<= (0x100 - shift);
1051
1052 data &= srcmask;
1053
1054 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1055 crtcdata |= (uint8_t)data;
1056 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1057
1058 return true;
1059 }
1060
1061 static bool
1062 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1063 {
1064 /*
1065 * INIT_NOT opcode: 0x38 ('8')
1066 *
1067 * offset (8 bit): opcode
1068 *
1069 * Invert the current execute / no-execute condition (i.e. "else")
1070 */
1071 if (iexec->execute)
1072 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1073 else
1074 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1075
1076 iexec->execute = !iexec->execute;
1077 return true;
1078 }
1079
1080 static bool
1081 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1082 struct init_exec *iexec)
1083 {
1084 /*
1085 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1086 *
1087 * offset (8 bit): opcode
1088 * offset + 1 (8 bit): condition number
1089 *
1090 * Check condition "condition number" in the IO flag condition table.
1091 * If condition not met skip subsequent opcodes until condition is
1092 * inverted (INIT_NOT), or we hit INIT_RESUME
1093 */
1094
1095 uint8_t cond = bios->data[offset + 1];
1096
1097 if (!iexec->execute)
1098 return true;
1099
1100 if (io_flag_condition_met(bios, offset, cond))
1101 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1102 else {
1103 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1104 iexec->execute = false;
1105 }
1106
1107 return true;
1108 }
1109
1110 static bool
1111 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1112 struct init_exec *iexec)
1113 {
1114 /*
1115 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1116 *
1117 * offset (8 bit): opcode
1118 * offset + 1 (32 bit): control register
1119 * offset + 5 (32 bit): data register
1120 * offset + 9 (32 bit): mask
1121 * offset + 13 (32 bit): data
1122 * offset + 17 (8 bit): count
1123 * offset + 18 (8 bit): address 1
1124 * offset + 19 (8 bit): data 1
1125 * ...
1126 *
1127 * For each of "count" address and data pairs, write "data n" to
1128 * "data register", read the current value of "control register",
1129 * and write it back once ANDed with "mask", ORed with "data",
1130 * and ORed with "address n"
1131 */
1132
1133 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1134 uint32_t datareg = ROM32(bios->data[offset + 5]);
1135 uint32_t mask = ROM32(bios->data[offset + 9]);
1136 uint32_t data = ROM32(bios->data[offset + 13]);
1137 uint8_t count = bios->data[offset + 17];
1138 uint32_t value;
1139 int i;
1140
1141 if (!iexec->execute)
1142 return true;
1143
1144 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1145 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1146 offset, controlreg, datareg, mask, data, count);
1147
1148 for (i = 0; i < count; i++) {
1149 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1150 uint8_t instdata = bios->data[offset + 19 + i * 2];
1151
1152 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1153 offset, instaddress, instdata);
1154
1155 bios_wr32(bios, datareg, instdata);
1156 value = bios_rd32(bios, controlreg) & mask;
1157 value |= data;
1158 value |= instaddress;
1159 bios_wr32(bios, controlreg, value);
1160 }
1161
1162 return true;
1163 }
1164
1165 static bool
1166 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1167 struct init_exec *iexec)
1168 {
1169 /*
1170 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1171 *
1172 * offset (8 bit): opcode
1173 * offset + 1 (16 bit): CRTC port
1174 * offset + 3 (8 bit): CRTC index
1175 * offset + 4 (8 bit): mask
1176 * offset + 5 (8 bit): shift
1177 * offset + 6 (8 bit): count
1178 * offset + 7 (32 bit): register
1179 * offset + 11 (32 bit): frequency 1
1180 * ...
1181 *
1182 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1183 * Set PLL register "register" to coefficients for frequency n,
1184 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1185 * "mask" and shifted right by "shift".
1186 */
1187
1188 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1189 uint8_t crtcindex = bios->data[offset + 3];
1190 uint8_t mask = bios->data[offset + 4];
1191 uint8_t shift = bios->data[offset + 5];
1192 uint8_t count = bios->data[offset + 6];
1193 uint32_t reg = ROM32(bios->data[offset + 7]);
1194 uint8_t config;
1195 uint32_t freq;
1196
1197 if (!iexec->execute)
1198 return true;
1199
1200 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1201 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1202 offset, crtcport, crtcindex, mask, shift, count, reg);
1203
1204 if (!reg)
1205 return true;
1206
1207 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1208 if (config > count) {
1209 NV_ERROR(bios->dev,
1210 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1211 offset, config, count);
1212 return false;
1213 }
1214
1215 freq = ROM32(bios->data[offset + 11 + config * 4]);
1216
1217 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1218 offset, reg, config, freq);
1219
1220 setPLL(bios, reg, freq);
1221
1222 return true;
1223 }
1224
1225 static bool
1226 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1227 {
1228 /*
1229 * INIT_PLL2 opcode: 0x4B ('K')
1230 *
1231 * offset (8 bit): opcode
1232 * offset + 1 (32 bit): register
1233 * offset + 5 (32 bit): freq
1234 *
1235 * Set PLL register "register" to coefficients for frequency "freq"
1236 */
1237
1238 uint32_t reg = ROM32(bios->data[offset + 1]);
1239 uint32_t freq = ROM32(bios->data[offset + 5]);
1240
1241 if (!iexec->execute)
1242 return true;
1243
1244 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1245 offset, reg, freq);
1246
1247 setPLL(bios, reg, freq);
1248 return true;
1249 }
1250
1251 static bool
1252 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1253 {
1254 /*
1255 * INIT_I2C_BYTE opcode: 0x4C ('L')
1256 *
1257 * offset (8 bit): opcode
1258 * offset + 1 (8 bit): DCB I2C table entry index
1259 * offset + 2 (8 bit): I2C slave address
1260 * offset + 3 (8 bit): count
1261 * offset + 4 (8 bit): I2C register 1
1262 * offset + 5 (8 bit): mask 1
1263 * offset + 6 (8 bit): data 1
1264 * ...
1265 *
1266 * For each of "count" registers given by "I2C register n" on the device
1267 * addressed by "I2C slave address" on the I2C bus given by
1268 * "DCB I2C table entry index", read the register, AND the result with
1269 * "mask n" and OR it with "data n" before writing it back to the device
1270 */
1271
1272 uint8_t i2c_index = bios->data[offset + 1];
1273 uint8_t i2c_address = bios->data[offset + 2];
1274 uint8_t count = bios->data[offset + 3];
1275 struct nouveau_i2c_chan *chan;
1276 struct i2c_msg msg;
1277 int i;
1278
1279 if (!iexec->execute)
1280 return true;
1281
1282 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1283 "Count: 0x%02X\n",
1284 offset, i2c_index, i2c_address, count);
1285
1286 chan = init_i2c_device_find(bios->dev, i2c_index);
1287 if (!chan)
1288 return false;
1289
1290 for (i = 0; i < count; i++) {
1291 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1292 uint8_t mask = bios->data[offset + 5 + i * 3];
1293 uint8_t data = bios->data[offset + 6 + i * 3];
1294 uint8_t value;
1295
1296 msg.addr = i2c_address;
1297 msg.flags = I2C_M_RD;
1298 msg.len = 1;
1299 msg.buf = &value;
1300 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1301 return false;
1302
1303 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1304 "Mask: 0x%02X, Data: 0x%02X\n",
1305 offset, i2c_reg, value, mask, data);
1306
1307 value = (value & mask) | data;
1308
1309 if (bios->execute) {
1310 msg.addr = i2c_address;
1311 msg.flags = 0;
1312 msg.len = 1;
1313 msg.buf = &value;
1314 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1315 return false;
1316 }
1317 }
1318
1319 return true;
1320 }
1321
1322 static bool
1323 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1324 {
1325 /*
1326 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1327 *
1328 * offset (8 bit): opcode
1329 * offset + 1 (8 bit): DCB I2C table entry index
1330 * offset + 2 (8 bit): I2C slave address
1331 * offset + 3 (8 bit): count
1332 * offset + 4 (8 bit): I2C register 1
1333 * offset + 5 (8 bit): data 1
1334 * ...
1335 *
1336 * For each of "count" registers given by "I2C register n" on the device
1337 * addressed by "I2C slave address" on the I2C bus given by
1338 * "DCB I2C table entry index", set the register to "data n"
1339 */
1340
1341 uint8_t i2c_index = bios->data[offset + 1];
1342 uint8_t i2c_address = bios->data[offset + 2];
1343 uint8_t count = bios->data[offset + 3];
1344 struct nouveau_i2c_chan *chan;
1345 struct i2c_msg msg;
1346 int i;
1347
1348 if (!iexec->execute)
1349 return true;
1350
1351 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1352 "Count: 0x%02X\n",
1353 offset, i2c_index, i2c_address, count);
1354
1355 chan = init_i2c_device_find(bios->dev, i2c_index);
1356 if (!chan)
1357 return false;
1358
1359 for (i = 0; i < count; i++) {
1360 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1361 uint8_t data = bios->data[offset + 5 + i * 2];
1362
1363 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1364 offset, i2c_reg, data);
1365
1366 if (bios->execute) {
1367 msg.addr = i2c_address;
1368 msg.flags = 0;
1369 msg.len = 1;
1370 msg.buf = &data;
1371 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1372 return false;
1373 }
1374 }
1375
1376 return true;
1377 }
1378
1379 static bool
1380 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1381 {
1382 /*
1383 * INIT_ZM_I2C opcode: 0x4E ('N')
1384 *
1385 * offset (8 bit): opcode
1386 * offset + 1 (8 bit): DCB I2C table entry index
1387 * offset + 2 (8 bit): I2C slave address
1388 * offset + 3 (8 bit): count
1389 * offset + 4 (8 bit): data 1
1390 * ...
1391 *
1392 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1393 * address" on the I2C bus given by "DCB I2C table entry index"
1394 */
1395
1396 uint8_t i2c_index = bios->data[offset + 1];
1397 uint8_t i2c_address = bios->data[offset + 2];
1398 uint8_t count = bios->data[offset + 3];
1399 struct nouveau_i2c_chan *chan;
1400 struct i2c_msg msg;
1401 uint8_t data[256];
1402 int i;
1403
1404 if (!iexec->execute)
1405 return true;
1406
1407 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1408 "Count: 0x%02X\n",
1409 offset, i2c_index, i2c_address, count);
1410
1411 chan = init_i2c_device_find(bios->dev, i2c_index);
1412 if (!chan)
1413 return false;
1414
1415 for (i = 0; i < count; i++) {
1416 data[i] = bios->data[offset + 4 + i];
1417
1418 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1419 }
1420
1421 if (bios->execute) {
1422 msg.addr = i2c_address;
1423 msg.flags = 0;
1424 msg.len = count;
1425 msg.buf = data;
1426 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1427 return false;
1428 }
1429
1430 return true;
1431 }
1432
1433 static bool
1434 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1435 {
1436 /*
1437 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1438 *
1439 * offset (8 bit): opcode
1440 * offset + 1 (8 bit): magic lookup value
1441 * offset + 2 (8 bit): TMDS address
1442 * offset + 3 (8 bit): mask
1443 * offset + 4 (8 bit): data
1444 *
1445 * Read the data reg for TMDS address "TMDS address", AND it with mask
1446 * and OR it with data, then write it back
1447 * "magic lookup value" determines which TMDS base address register is
1448 * used -- see get_tmds_index_reg()
1449 */
1450
1451 uint8_t mlv = bios->data[offset + 1];
1452 uint32_t tmdsaddr = bios->data[offset + 2];
1453 uint8_t mask = bios->data[offset + 3];
1454 uint8_t data = bios->data[offset + 4];
1455 uint32_t reg, value;
1456
1457 if (!iexec->execute)
1458 return true;
1459
1460 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1461 "Mask: 0x%02X, Data: 0x%02X\n",
1462 offset, mlv, tmdsaddr, mask, data);
1463
1464 reg = get_tmds_index_reg(bios->dev, mlv);
1465 if (!reg)
1466 return false;
1467
1468 bios_wr32(bios, reg,
1469 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1470 value = (bios_rd32(bios, reg + 4) & mask) | data;
1471 bios_wr32(bios, reg + 4, value);
1472 bios_wr32(bios, reg, tmdsaddr);
1473
1474 return true;
1475 }
1476
1477 static bool
1478 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1479 struct init_exec *iexec)
1480 {
1481 /*
1482 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1483 *
1484 * offset (8 bit): opcode
1485 * offset + 1 (8 bit): magic lookup value
1486 * offset + 2 (8 bit): count
1487 * offset + 3 (8 bit): addr 1
1488 * offset + 4 (8 bit): data 1
1489 * ...
1490 *
1491 * For each of "count" TMDS address and data pairs write "data n" to
1492 * "addr n". "magic lookup value" determines which TMDS base address
1493 * register is used -- see get_tmds_index_reg()
1494 */
1495
1496 uint8_t mlv = bios->data[offset + 1];
1497 uint8_t count = bios->data[offset + 2];
1498 uint32_t reg;
1499 int i;
1500
1501 if (!iexec->execute)
1502 return true;
1503
1504 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1505 offset, mlv, count);
1506
1507 reg = get_tmds_index_reg(bios->dev, mlv);
1508 if (!reg)
1509 return false;
1510
1511 for (i = 0; i < count; i++) {
1512 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1513 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1514
1515 bios_wr32(bios, reg + 4, tmdsdata);
1516 bios_wr32(bios, reg, tmdsaddr);
1517 }
1518
1519 return true;
1520 }
1521
1522 static bool
1523 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1524 struct init_exec *iexec)
1525 {
1526 /*
1527 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1528 *
1529 * offset (8 bit): opcode
1530 * offset + 1 (8 bit): CRTC index1
1531 * offset + 2 (8 bit): CRTC index2
1532 * offset + 3 (8 bit): baseaddr
1533 * offset + 4 (8 bit): count
1534 * offset + 5 (8 bit): data 1
1535 * ...
1536 *
1537 * For each of "count" address and data pairs, write "baseaddr + n" to
1538 * "CRTC index1" and "data n" to "CRTC index2"
1539 * Once complete, restore initial value read from "CRTC index1"
1540 */
1541 uint8_t crtcindex1 = bios->data[offset + 1];
1542 uint8_t crtcindex2 = bios->data[offset + 2];
1543 uint8_t baseaddr = bios->data[offset + 3];
1544 uint8_t count = bios->data[offset + 4];
1545 uint8_t oldaddr, data;
1546 int i;
1547
1548 if (!iexec->execute)
1549 return true;
1550
1551 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1552 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1553 offset, crtcindex1, crtcindex2, baseaddr, count);
1554
1555 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1556
1557 for (i = 0; i < count; i++) {
1558 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1559 baseaddr + i);
1560 data = bios->data[offset + 5 + i];
1561 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1562 }
1563
1564 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1565
1566 return true;
1567 }
1568
1569 static bool
1570 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1571 {
1572 /*
1573 * INIT_CR opcode: 0x52 ('R')
1574 *
1575 * offset (8 bit): opcode
1576 * offset + 1 (8 bit): CRTC index
1577 * offset + 2 (8 bit): mask
1578 * offset + 3 (8 bit): data
1579 *
1580 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1581 * data back to "CRTC index"
1582 */
1583
1584 uint8_t crtcindex = bios->data[offset + 1];
1585 uint8_t mask = bios->data[offset + 2];
1586 uint8_t data = bios->data[offset + 3];
1587 uint8_t value;
1588
1589 if (!iexec->execute)
1590 return true;
1591
1592 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1593 offset, crtcindex, mask, data);
1594
1595 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1596 value |= data;
1597 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1598
1599 return true;
1600 }
1601
1602 static bool
1603 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1604 {
1605 /*
1606 * INIT_ZM_CR opcode: 0x53 ('S')
1607 *
1608 * offset (8 bit): opcode
1609 * offset + 1 (8 bit): CRTC index
1610 * offset + 2 (8 bit): value
1611 *
1612 * Assign "value" to CRTC register with index "CRTC index".
1613 */
1614
1615 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1616 uint8_t data = bios->data[offset + 2];
1617
1618 if (!iexec->execute)
1619 return true;
1620
1621 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1622
1623 return true;
1624 }
1625
1626 static bool
1627 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1628 {
1629 /*
1630 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1631 *
1632 * offset (8 bit): opcode
1633 * offset + 1 (8 bit): count
1634 * offset + 2 (8 bit): CRTC index 1
1635 * offset + 3 (8 bit): value 1
1636 * ...
1637 *
1638 * For "count", assign "value n" to CRTC register with index
1639 * "CRTC index n".
1640 */
1641
1642 uint8_t count = bios->data[offset + 1];
1643 int i;
1644
1645 if (!iexec->execute)
1646 return true;
1647
1648 for (i = 0; i < count; i++)
1649 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1650
1651 return true;
1652 }
1653
1654 static bool
1655 init_condition_time(struct nvbios *bios, uint16_t offset,
1656 struct init_exec *iexec)
1657 {
1658 /*
1659 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1660 *
1661 * offset (8 bit): opcode
1662 * offset + 1 (8 bit): condition number
1663 * offset + 2 (8 bit): retries / 50
1664 *
1665 * Check condition "condition number" in the condition table.
1666 * Bios code then sleeps for 2ms if the condition is not met, and
1667 * repeats up to "retries" times, but on one C51 this has proved
1668 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1669 * this, and bail after "retries" times, or 2s, whichever is less.
1670 * If still not met after retries, clear execution flag for this table.
1671 */
1672
1673 uint8_t cond = bios->data[offset + 1];
1674 uint16_t retries = bios->data[offset + 2] * 50;
1675 unsigned cnt;
1676
1677 if (!iexec->execute)
1678 return true;
1679
1680 if (retries > 100)
1681 retries = 100;
1682
1683 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1684 offset, cond, retries);
1685
1686 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1687 retries = 1;
1688
1689 for (cnt = 0; cnt < retries; cnt++) {
1690 if (bios_condition_met(bios, offset, cond)) {
1691 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1692 offset);
1693 break;
1694 } else {
1695 BIOSLOG(bios, "0x%04X: "
1696 "Condition not met, sleeping for 20ms\n",
1697 offset);
1698 msleep(20);
1699 }
1700 }
1701
1702 if (!bios_condition_met(bios, offset, cond)) {
1703 NV_WARN(bios->dev,
1704 "0x%04X: Condition still not met after %dms, "
1705 "skipping following opcodes\n", offset, 20 * retries);
1706 iexec->execute = false;
1707 }
1708
1709 return true;
1710 }
1711
1712 static bool
1713 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1714 struct init_exec *iexec)
1715 {
1716 /*
1717 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1718 *
1719 * offset (8 bit): opcode
1720 * offset + 1 (32 bit): base register
1721 * offset + 5 (8 bit): count
1722 * offset + 6 (32 bit): value 1
1723 * ...
1724 *
1725 * Starting at offset + 6 there are "count" 32 bit values.
1726 * For "count" iterations set "base register" + 4 * current_iteration
1727 * to "value current_iteration"
1728 */
1729
1730 uint32_t basereg = ROM32(bios->data[offset + 1]);
1731 uint32_t count = bios->data[offset + 5];
1732 int i;
1733
1734 if (!iexec->execute)
1735 return true;
1736
1737 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1738 offset, basereg, count);
1739
1740 for (i = 0; i < count; i++) {
1741 uint32_t reg = basereg + i * 4;
1742 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1743
1744 bios_wr32(bios, reg, data);
1745 }
1746
1747 return true;
1748 }
1749
1750 static bool
1751 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1752 {
1753 /*
1754 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1755 *
1756 * offset (8 bit): opcode
1757 * offset + 1 (16 bit): subroutine offset (in bios)
1758 *
1759 * Calls a subroutine that will execute commands until INIT_DONE
1760 * is found.
1761 */
1762
1763 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1764
1765 if (!iexec->execute)
1766 return true;
1767
1768 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1769 offset, sub_offset);
1770
1771 parse_init_table(bios, sub_offset, iexec);
1772
1773 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1774
1775 return true;
1776 }
1777
1778 static bool
1779 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1780 {
1781 /*
1782 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1783 *
1784 * offset (8 bit): opcode
1785 * offset + 1 (32 bit): src reg
1786 * offset + 5 (8 bit): shift
1787 * offset + 6 (32 bit): src mask
1788 * offset + 10 (32 bit): xor
1789 * offset + 14 (32 bit): dst reg
1790 * offset + 18 (32 bit): dst mask
1791 *
1792 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1793 * "src mask", then XOR with "xor". Write this OR'd with
1794 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1795 */
1796
1797 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1798 uint8_t shift = bios->data[offset + 5];
1799 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1800 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1801 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1802 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1803 uint32_t srcvalue, dstvalue;
1804
1805 if (!iexec->execute)
1806 return true;
1807
1808 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1809 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1810 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1811
1812 srcvalue = bios_rd32(bios, srcreg);
1813
1814 if (shift < 0x80)
1815 srcvalue >>= shift;
1816 else
1817 srcvalue <<= (0x100 - shift);
1818
1819 srcvalue = (srcvalue & srcmask) ^ xor;
1820
1821 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1822
1823 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1824
1825 return true;
1826 }
1827
1828 static bool
1829 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1830 {
1831 /*
1832 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1833 *
1834 * offset (8 bit): opcode
1835 * offset + 1 (16 bit): CRTC port
1836 * offset + 3 (8 bit): CRTC index
1837 * offset + 4 (8 bit): data
1838 *
1839 * Write "data" to index "CRTC index" of "CRTC port"
1840 */
1841 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1842 uint8_t crtcindex = bios->data[offset + 3];
1843 uint8_t data = bios->data[offset + 4];
1844
1845 if (!iexec->execute)
1846 return true;
1847
1848 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1849
1850 return true;
1851 }
1852
1853 static bool
1854 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1855 {
1856 /*
1857 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1858 *
1859 * offset (8 bit): opcode
1860 *
1861 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1862 * that the hardware can correctly calculate how much VRAM it has
1863 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1864 *
1865 * The implementation of this opcode in general consists of two parts:
1866 * 1) determination of the memory bus width
1867 * 2) determination of how many of the card's RAM pads have ICs attached
1868 *
1869 * 1) is done by a cunning combination of writes to offsets 0x1c and
1870 * 0x3c in the framebuffer, and seeing whether the written values are
1871 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1872 *
1873 * 2) is done by a cunning combination of writes to an offset slightly
1874 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1875 * if the test pattern can be read back. This then affects bits 12-15 of
1876 * NV_PFB_CFG0
1877 *
1878 * In this context a "cunning combination" may include multiple reads
1879 * and writes to varying locations, often alternating the test pattern
1880 * and 0, doubtless to make sure buffers are filled, residual charges
1881 * on tracks are removed etc.
1882 *
1883 * Unfortunately, the "cunning combination"s mentioned above, and the
1884 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1885 * trace I have.
1886 *
1887 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1888 * we started was correct, and use that instead
1889 */
1890
1891 /* no iexec->execute check by design */
1892
1893 /*
1894 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1895 * and kmmio traces of the binary driver POSTing the card show nothing
1896 * being done for this opcode. why is it still listed in the table?!
1897 */
1898
1899 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1900
1901 if (dev_priv->card_type >= NV_50)
1902 return true;
1903
1904 /*
1905 * On every card I've seen, this step gets done for us earlier in
1906 * the init scripts
1907 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1908 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1909 */
1910
1911 /*
1912 * This also has probably been done in the scripts, but an mmio trace of
1913 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1914 */
1915 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1916
1917 /* write back the saved configuration value */
1918 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1919
1920 return true;
1921 }
1922
1923 static bool
1924 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1925 {
1926 /*
1927 * INIT_RESET opcode: 0x65 ('e')
1928 *
1929 * offset (8 bit): opcode
1930 * offset + 1 (32 bit): register
1931 * offset + 5 (32 bit): value1
1932 * offset + 9 (32 bit): value2
1933 *
1934 * Assign "value1" to "register", then assign "value2" to "register"
1935 */
1936
1937 uint32_t reg = ROM32(bios->data[offset + 1]);
1938 uint32_t value1 = ROM32(bios->data[offset + 5]);
1939 uint32_t value2 = ROM32(bios->data[offset + 9]);
1940 uint32_t pci_nv_19, pci_nv_20;
1941
1942 /* no iexec->execute check by design */
1943
1944 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
1945 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
1946 bios_wr32(bios, reg, value1);
1947
1948 udelay(10);
1949
1950 bios_wr32(bios, reg, value2);
1951 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
1952
1953 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
1954 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1955 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1956
1957 return true;
1958 }
1959
1960 static bool
1961 init_configure_mem(struct nvbios *bios, uint16_t offset,
1962 struct init_exec *iexec)
1963 {
1964 /*
1965 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1966 *
1967 * offset (8 bit): opcode
1968 *
1969 * Equivalent to INIT_DONE on bios version 3 or greater.
1970 * For early bios versions, sets up the memory registers, using values
1971 * taken from the memory init table
1972 */
1973
1974 /* no iexec->execute check by design */
1975
1976 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1977 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1978 uint32_t reg, data;
1979
1980 if (bios->major_version > 2)
1981 return false;
1982
1983 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1984 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
1985
1986 if (bios->data[meminitoffs] & 1)
1987 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1988
1989 for (reg = ROM32(bios->data[seqtbloffs]);
1990 reg != 0xffffffff;
1991 reg = ROM32(bios->data[seqtbloffs += 4])) {
1992
1993 switch (reg) {
1994 case NV_PFB_PRE:
1995 data = NV_PFB_PRE_CMD_PRECHARGE;
1996 break;
1997 case NV_PFB_PAD:
1998 data = NV_PFB_PAD_CKE_NORMAL;
1999 break;
2000 case NV_PFB_REF:
2001 data = NV_PFB_REF_CMD_REFRESH;
2002 break;
2003 default:
2004 data = ROM32(bios->data[meminitdata]);
2005 meminitdata += 4;
2006 if (data == 0xffffffff)
2007 continue;
2008 }
2009
2010 bios_wr32(bios, reg, data);
2011 }
2012
2013 return true;
2014 }
2015
2016 static bool
2017 init_configure_clk(struct nvbios *bios, uint16_t offset,
2018 struct init_exec *iexec)
2019 {
2020 /*
2021 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2022 *
2023 * offset (8 bit): opcode
2024 *
2025 * Equivalent to INIT_DONE on bios version 3 or greater.
2026 * For early bios versions, sets up the NVClk and MClk PLLs, using
2027 * values taken from the memory init table
2028 */
2029
2030 /* no iexec->execute check by design */
2031
2032 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2033 int clock;
2034
2035 if (bios->major_version > 2)
2036 return false;
2037
2038 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2039 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2040
2041 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2042 if (bios->data[meminitoffs] & 1) /* DDR */
2043 clock *= 2;
2044 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2045
2046 return true;
2047 }
2048
2049 static bool
2050 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2051 struct init_exec *iexec)
2052 {
2053 /*
2054 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2055 *
2056 * offset (8 bit): opcode
2057 *
2058 * Equivalent to INIT_DONE on bios version 3 or greater.
2059 * For early bios versions, does early init, loading ram and crystal
2060 * configuration from straps into CR3C
2061 */
2062
2063 /* no iexec->execute check by design */
2064
2065 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2066 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2067
2068 if (bios->major_version > 2)
2069 return false;
2070
2071 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2072 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2073
2074 return true;
2075 }
2076
2077 static bool
2078 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2079 {
2080 /*
2081 * INIT_IO opcode: 0x69 ('i')
2082 *
2083 * offset (8 bit): opcode
2084 * offset + 1 (16 bit): CRTC port
2085 * offset + 3 (8 bit): mask
2086 * offset + 4 (8 bit): data
2087 *
2088 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2089 */
2090
2091 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2092 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2093 uint8_t mask = bios->data[offset + 3];
2094 uint8_t data = bios->data[offset + 4];
2095
2096 if (!iexec->execute)
2097 return true;
2098
2099 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2100 offset, crtcport, mask, data);
2101
2102 /*
2103 * I have no idea what this does, but NVIDIA do this magic sequence
2104 * in the places where this INIT_IO happens..
2105 */
2106 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2107 int i;
2108
2109 bios_wr32(bios, 0x614100, (bios_rd32(
2110 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2111
2112 bios_wr32(bios, 0x00e18c, bios_rd32(
2113 bios, 0x00e18c) | 0x00020000);
2114
2115 bios_wr32(bios, 0x614900, (bios_rd32(
2116 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2117
2118 bios_wr32(bios, 0x000200, bios_rd32(
2119 bios, 0x000200) & ~0x40000000);
2120
2121 mdelay(10);
2122
2123 bios_wr32(bios, 0x00e18c, bios_rd32(
2124 bios, 0x00e18c) & ~0x00020000);
2125
2126 bios_wr32(bios, 0x000200, bios_rd32(
2127 bios, 0x000200) | 0x40000000);
2128
2129 bios_wr32(bios, 0x614100, 0x00800018);
2130 bios_wr32(bios, 0x614900, 0x00800018);
2131
2132 mdelay(10);
2133
2134 bios_wr32(bios, 0x614100, 0x10000018);
2135 bios_wr32(bios, 0x614900, 0x10000018);
2136
2137 for (i = 0; i < 3; i++)
2138 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2139 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2140
2141 for (i = 0; i < 2; i++)
2142 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2143 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2144
2145 for (i = 0; i < 3; i++)
2146 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2147 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2148
2149 for (i = 0; i < 2; i++)
2150 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2151 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2152
2153 for (i = 0; i < 2; i++)
2154 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2155 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2156 return true;
2157 }
2158
2159 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2160 data);
2161 return true;
2162 }
2163
2164 static bool
2165 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2166 {
2167 /*
2168 * INIT_SUB opcode: 0x6B ('k')
2169 *
2170 * offset (8 bit): opcode
2171 * offset + 1 (8 bit): script number
2172 *
2173 * Execute script number "script number", as a subroutine
2174 */
2175
2176 uint8_t sub = bios->data[offset + 1];
2177
2178 if (!iexec->execute)
2179 return true;
2180
2181 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2182
2183 parse_init_table(bios,
2184 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2185 iexec);
2186
2187 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2188
2189 return true;
2190 }
2191
2192 static bool
2193 init_ram_condition(struct nvbios *bios, uint16_t offset,
2194 struct init_exec *iexec)
2195 {
2196 /*
2197 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2198 *
2199 * offset (8 bit): opcode
2200 * offset + 1 (8 bit): mask
2201 * offset + 2 (8 bit): cmpval
2202 *
2203 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2204 * If condition not met skip subsequent opcodes until condition is
2205 * inverted (INIT_NOT), or we hit INIT_RESUME
2206 */
2207
2208 uint8_t mask = bios->data[offset + 1];
2209 uint8_t cmpval = bios->data[offset + 2];
2210 uint8_t data;
2211
2212 if (!iexec->execute)
2213 return true;
2214
2215 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2216
2217 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2218 offset, data, cmpval);
2219
2220 if (data == cmpval)
2221 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2222 else {
2223 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2224 iexec->execute = false;
2225 }
2226
2227 return true;
2228 }
2229
2230 static bool
2231 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2232 {
2233 /*
2234 * INIT_NV_REG opcode: 0x6E ('n')
2235 *
2236 * offset (8 bit): opcode
2237 * offset + 1 (32 bit): register
2238 * offset + 5 (32 bit): mask
2239 * offset + 9 (32 bit): data
2240 *
2241 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2242 */
2243
2244 uint32_t reg = ROM32(bios->data[offset + 1]);
2245 uint32_t mask = ROM32(bios->data[offset + 5]);
2246 uint32_t data = ROM32(bios->data[offset + 9]);
2247
2248 if (!iexec->execute)
2249 return true;
2250
2251 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2252 offset, reg, mask, data);
2253
2254 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2255
2256 return true;
2257 }
2258
2259 static bool
2260 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2261 {
2262 /*
2263 * INIT_MACRO opcode: 0x6F ('o')
2264 *
2265 * offset (8 bit): opcode
2266 * offset + 1 (8 bit): macro number
2267 *
2268 * Look up macro index "macro number" in the macro index table.
2269 * The macro index table entry has 1 byte for the index in the macro
2270 * table, and 1 byte for the number of times to repeat the macro.
2271 * The macro table entry has 4 bytes for the register address and
2272 * 4 bytes for the value to write to that register
2273 */
2274
2275 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2276 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2277 uint8_t macro_tbl_idx = bios->data[tmp];
2278 uint8_t count = bios->data[tmp + 1];
2279 uint32_t reg, data;
2280 int i;
2281
2282 if (!iexec->execute)
2283 return true;
2284
2285 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2286 "Count: 0x%02X\n",
2287 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2288
2289 for (i = 0; i < count; i++) {
2290 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2291
2292 reg = ROM32(bios->data[macroentryptr]);
2293 data = ROM32(bios->data[macroentryptr + 4]);
2294
2295 bios_wr32(bios, reg, data);
2296 }
2297
2298 return true;
2299 }
2300
2301 static bool
2302 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2303 {
2304 /*
2305 * INIT_DONE opcode: 0x71 ('q')
2306 *
2307 * offset (8 bit): opcode
2308 *
2309 * End the current script
2310 */
2311
2312 /* mild retval abuse to stop parsing this table */
2313 return false;
2314 }
2315
2316 static bool
2317 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2318 {
2319 /*
2320 * INIT_RESUME opcode: 0x72 ('r')
2321 *
2322 * offset (8 bit): opcode
2323 *
2324 * End the current execute / no-execute condition
2325 */
2326
2327 if (iexec->execute)
2328 return true;
2329
2330 iexec->execute = true;
2331 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2332
2333 return true;
2334 }
2335
2336 static bool
2337 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2338 {
2339 /*
2340 * INIT_TIME opcode: 0x74 ('t')
2341 *
2342 * offset (8 bit): opcode
2343 * offset + 1 (16 bit): time
2344 *
2345 * Sleep for "time" microseconds.
2346 */
2347
2348 unsigned time = ROM16(bios->data[offset + 1]);
2349
2350 if (!iexec->execute)
2351 return true;
2352
2353 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2354 offset, time);
2355
2356 if (time < 1000)
2357 udelay(time);
2358 else
2359 msleep((time + 900) / 1000);
2360
2361 return true;
2362 }
2363
2364 static bool
2365 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2366 {
2367 /*
2368 * INIT_CONDITION opcode: 0x75 ('u')
2369 *
2370 * offset (8 bit): opcode
2371 * offset + 1 (8 bit): condition number
2372 *
2373 * Check condition "condition number" in the condition table.
2374 * If condition not met skip subsequent opcodes until condition is
2375 * inverted (INIT_NOT), or we hit INIT_RESUME
2376 */
2377
2378 uint8_t cond = bios->data[offset + 1];
2379
2380 if (!iexec->execute)
2381 return true;
2382
2383 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2384
2385 if (bios_condition_met(bios, offset, cond))
2386 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2387 else {
2388 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2389 iexec->execute = false;
2390 }
2391
2392 return true;
2393 }
2394
2395 static bool
2396 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2397 {
2398 /*
2399 * INIT_IO_CONDITION opcode: 0x76
2400 *
2401 * offset (8 bit): opcode
2402 * offset + 1 (8 bit): condition number
2403 *
2404 * Check condition "condition number" in the io condition table.
2405 * If condition not met skip subsequent opcodes until condition is
2406 * inverted (INIT_NOT), or we hit INIT_RESUME
2407 */
2408
2409 uint8_t cond = bios->data[offset + 1];
2410
2411 if (!iexec->execute)
2412 return true;
2413
2414 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2415
2416 if (io_condition_met(bios, offset, cond))
2417 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2418 else {
2419 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2420 iexec->execute = false;
2421 }
2422
2423 return true;
2424 }
2425
2426 static bool
2427 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2428 {
2429 /*
2430 * INIT_INDEX_IO opcode: 0x78 ('x')
2431 *
2432 * offset (8 bit): opcode
2433 * offset + 1 (16 bit): CRTC port
2434 * offset + 3 (8 bit): CRTC index
2435 * offset + 4 (8 bit): mask
2436 * offset + 5 (8 bit): data
2437 *
2438 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2439 * OR with "data", write-back
2440 */
2441
2442 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2443 uint8_t crtcindex = bios->data[offset + 3];
2444 uint8_t mask = bios->data[offset + 4];
2445 uint8_t data = bios->data[offset + 5];
2446 uint8_t value;
2447
2448 if (!iexec->execute)
2449 return true;
2450
2451 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2452 "Data: 0x%02X\n",
2453 offset, crtcport, crtcindex, mask, data);
2454
2455 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2456 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2457
2458 return true;
2459 }
2460
2461 static bool
2462 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2463 {
2464 /*
2465 * INIT_PLL opcode: 0x79 ('y')
2466 *
2467 * offset (8 bit): opcode
2468 * offset + 1 (32 bit): register
2469 * offset + 5 (16 bit): freq
2470 *
2471 * Set PLL register "register" to coefficients for frequency (10kHz)
2472 * "freq"
2473 */
2474
2475 uint32_t reg = ROM32(bios->data[offset + 1]);
2476 uint16_t freq = ROM16(bios->data[offset + 5]);
2477
2478 if (!iexec->execute)
2479 return true;
2480
2481 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2482
2483 setPLL(bios, reg, freq * 10);
2484
2485 return true;
2486 }
2487
2488 static bool
2489 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2490 {
2491 /*
2492 * INIT_ZM_REG opcode: 0x7A ('z')
2493 *
2494 * offset (8 bit): opcode
2495 * offset + 1 (32 bit): register
2496 * offset + 5 (32 bit): value
2497 *
2498 * Assign "value" to "register"
2499 */
2500
2501 uint32_t reg = ROM32(bios->data[offset + 1]);
2502 uint32_t value = ROM32(bios->data[offset + 5]);
2503
2504 if (!iexec->execute)
2505 return true;
2506
2507 if (reg == 0x000200)
2508 value |= 1;
2509
2510 bios_wr32(bios, reg, value);
2511
2512 return true;
2513 }
2514
2515 static bool
2516 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2517 struct init_exec *iexec)
2518 {
2519 /*
2520 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2521 *
2522 * offset (8 bit): opcode
2523 * offset + 1 (8 bit): PLL type
2524 * offset + 2 (32 bit): frequency 0
2525 *
2526 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2527 * ram_restrict_table_ptr. The value read from there is used to select
2528 * a frequency from the table starting at 'frequency 0' to be
2529 * programmed into the PLL corresponding to 'type'.
2530 *
2531 * The PLL limits table on cards using this opcode has a mapping of
2532 * 'type' to the relevant registers.
2533 */
2534
2535 struct drm_device *dev = bios->dev;
2536 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2537 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2538 uint8_t type = bios->data[offset + 1];
2539 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2540 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2541 int i;
2542
2543 if (!iexec->execute)
2544 return true;
2545
2546 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2547 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2548 return true; /* deliberate, allow default clocks to remain */
2549 }
2550
2551 entry = pll_limits + pll_limits[1];
2552 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2553 if (entry[0] == type) {
2554 uint32_t reg = ROM32(entry[3]);
2555
2556 BIOSLOG(bios, "0x%04X: "
2557 "Type %02x Reg 0x%08x Freq %dKHz\n",
2558 offset, type, reg, freq);
2559
2560 setPLL(bios, reg, freq);
2561 return true;
2562 }
2563 }
2564
2565 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2566 return true;
2567 }
2568
2569 static bool
2570 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2571 {
2572 /*
2573 * INIT_8C opcode: 0x8C ('')
2574 *
2575 * NOP so far....
2576 *
2577 */
2578
2579 return true;
2580 }
2581
2582 static bool
2583 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2584 {
2585 /*
2586 * INIT_8D opcode: 0x8D ('')
2587 *
2588 * NOP so far....
2589 *
2590 */
2591
2592 return true;
2593 }
2594
2595 static bool
2596 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2597 {
2598 /*
2599 * INIT_GPIO opcode: 0x8E ('')
2600 *
2601 * offset (8 bit): opcode
2602 *
2603 * Loop over all entries in the DCB GPIO table, and initialise
2604 * each GPIO according to various values listed in each entry
2605 */
2606
2607 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
2608 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
2609 const uint8_t *gpio_table = &bios->data[bios->bdcb.gpio_table_ptr];
2610 const uint8_t *gpio_entry;
2611 int i;
2612
2613 if (bios->bdcb.version != 0x40) {
2614 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2615 return false;
2616 }
2617
2618 if (!bios->bdcb.gpio_table_ptr) {
2619 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
2620 return false;
2621 }
2622
2623 gpio_entry = gpio_table + gpio_table[1];
2624 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) {
2625 uint32_t entry = ROM32(gpio_entry[0]), r, s, v;
2626 int line = (entry & 0x0000001f);
2627
2628 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry);
2629
2630 if ((entry & 0x0000ff00) == 0x0000ff00)
2631 continue;
2632
2633 r = nv50_gpio_reg[line >> 3];
2634 s = (line & 0x07) << 2;
2635 v = bios_rd32(bios, r) & ~(0x00000003 << s);
2636 if (entry & 0x01000000)
2637 v |= (((entry & 0x60000000) >> 29) ^ 2) << s;
2638 else
2639 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2640 bios_wr32(bios, r, v);
2641
2642 r = nv50_gpio_ctl[line >> 4];
2643 s = (line & 0x0f);
2644 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2645 switch ((entry & 0x06000000) >> 25) {
2646 case 1:
2647 v |= (0x00000001 << s);
2648 break;
2649 case 2:
2650 v |= (0x00010000 << s);
2651 break;
2652 default:
2653 break;
2654 }
2655 bios_wr32(bios, r, v);
2656 }
2657
2658 return true;
2659 }
2660
2661 /* hack to avoid moving the itbl_entry array before this function */
2662 int init_ram_restrict_zm_reg_group_blocklen;
2663
2664 static bool
2665 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2666 struct init_exec *iexec)
2667 {
2668 /*
2669 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2670 *
2671 * offset (8 bit): opcode
2672 * offset + 1 (32 bit): reg
2673 * offset + 5 (8 bit): regincrement
2674 * offset + 6 (8 bit): count
2675 * offset + 7 (32 bit): value 1,1
2676 * ...
2677 *
2678 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2679 * ram_restrict_table_ptr. The value read from here is 'n', and
2680 * "value 1,n" gets written to "reg". This repeats "count" times and on
2681 * each iteration 'm', "reg" increases by "regincrement" and
2682 * "value m,n" is used. The extent of n is limited by a number read
2683 * from the 'M' BIT table, herein called "blocklen"
2684 */
2685
2686 uint32_t reg = ROM32(bios->data[offset + 1]);
2687 uint8_t regincrement = bios->data[offset + 5];
2688 uint8_t count = bios->data[offset + 6];
2689 uint32_t strap_ramcfg, data;
2690 uint16_t blocklen;
2691 uint8_t index;
2692 int i;
2693
2694 /* previously set by 'M' BIT table */
2695 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2696
2697 if (!iexec->execute)
2698 return true;
2699
2700 if (!blocklen) {
2701 NV_ERROR(bios->dev,
2702 "0x%04X: Zero block length - has the M table "
2703 "been parsed?\n", offset);
2704 return false;
2705 }
2706
2707 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2708 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2709
2710 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2711 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2712 offset, reg, regincrement, count, strap_ramcfg, index);
2713
2714 for (i = 0; i < count; i++) {
2715 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2716
2717 bios_wr32(bios, reg, data);
2718
2719 reg += regincrement;
2720 }
2721
2722 return true;
2723 }
2724
2725 static bool
2726 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2727 {
2728 /*
2729 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2730 *
2731 * offset (8 bit): opcode
2732 * offset + 1 (32 bit): src reg
2733 * offset + 5 (32 bit): dst reg
2734 *
2735 * Put contents of "src reg" into "dst reg"
2736 */
2737
2738 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2739 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2740
2741 if (!iexec->execute)
2742 return true;
2743
2744 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2745
2746 return true;
2747 }
2748
2749 static bool
2750 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2751 struct init_exec *iexec)
2752 {
2753 /*
2754 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2755 *
2756 * offset (8 bit): opcode
2757 * offset + 1 (32 bit): dst reg
2758 * offset + 5 (8 bit): count
2759 * offset + 6 (32 bit): data 1
2760 * ...
2761 *
2762 * For each of "count" values write "data n" to "dst reg"
2763 */
2764
2765 uint32_t reg = ROM32(bios->data[offset + 1]);
2766 uint8_t count = bios->data[offset + 5];
2767 int i;
2768
2769 if (!iexec->execute)
2770 return true;
2771
2772 for (i = 0; i < count; i++) {
2773 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2774 bios_wr32(bios, reg, data);
2775 }
2776
2777 return true;
2778 }
2779
2780 static bool
2781 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2782 {
2783 /*
2784 * INIT_RESERVED opcode: 0x92 ('')
2785 *
2786 * offset (8 bit): opcode
2787 *
2788 * Seemingly does nothing
2789 */
2790
2791 return true;
2792 }
2793
2794 static bool
2795 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2796 {
2797 /*
2798 * INIT_96 opcode: 0x96 ('')
2799 *
2800 * offset (8 bit): opcode
2801 * offset + 1 (32 bit): sreg
2802 * offset + 5 (8 bit): sshift
2803 * offset + 6 (8 bit): smask
2804 * offset + 7 (8 bit): index
2805 * offset + 8 (32 bit): reg
2806 * offset + 12 (32 bit): mask
2807 * offset + 16 (8 bit): shift
2808 *
2809 */
2810
2811 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2812 uint32_t reg = ROM32(bios->data[offset + 8]);
2813 uint32_t mask = ROM32(bios->data[offset + 12]);
2814 uint32_t val;
2815
2816 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2817 if (bios->data[offset + 5] < 0x80)
2818 val >>= bios->data[offset + 5];
2819 else
2820 val <<= (0x100 - bios->data[offset + 5]);
2821 val &= bios->data[offset + 6];
2822
2823 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2824 val <<= bios->data[offset + 16];
2825
2826 if (!iexec->execute)
2827 return true;
2828
2829 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
2830 return true;
2831 }
2832
2833 static bool
2834 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2835 {
2836 /*
2837 * INIT_97 opcode: 0x97 ('')
2838 *
2839 * offset (8 bit): opcode
2840 * offset + 1 (32 bit): register
2841 * offset + 5 (32 bit): mask
2842 * offset + 9 (32 bit): value
2843 *
2844 * Adds "value" to "register" preserving the fields specified
2845 * by "mask"
2846 */
2847
2848 uint32_t reg = ROM32(bios->data[offset + 1]);
2849 uint32_t mask = ROM32(bios->data[offset + 5]);
2850 uint32_t add = ROM32(bios->data[offset + 9]);
2851 uint32_t val;
2852
2853 val = bios_rd32(bios, reg);
2854 val = (val & mask) | ((val + add) & ~mask);
2855
2856 if (!iexec->execute)
2857 return true;
2858
2859 bios_wr32(bios, reg, val);
2860 return true;
2861 }
2862
2863 static bool
2864 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2865 {
2866 /*
2867 * INIT_AUXCH opcode: 0x98 ('')
2868 *
2869 * offset (8 bit): opcode
2870 * offset + 1 (32 bit): address
2871 * offset + 5 (8 bit): count
2872 * offset + 6 (8 bit): mask 0
2873 * offset + 7 (8 bit): data 0
2874 * ...
2875 *
2876 */
2877
2878 struct drm_device *dev = bios->dev;
2879 struct nouveau_i2c_chan *auxch;
2880 uint32_t addr = ROM32(bios->data[offset + 1]);
2881 uint8_t len = bios->data[offset + 5];
2882 int ret, i;
2883
2884 if (!bios->display.output) {
2885 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
2886 return false;
2887 }
2888
2889 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2890 if (!auxch) {
2891 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2892 bios->display.output->i2c_index);
2893 return false;
2894 }
2895
2896 if (!iexec->execute)
2897 return true;
2898
2899 offset += 6;
2900 for (i = 0; i < len; i++, offset += 2) {
2901 uint8_t data;
2902
2903 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2904 if (ret) {
2905 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
2906 return false;
2907 }
2908
2909 data &= bios->data[offset + 0];
2910 data |= bios->data[offset + 1];
2911
2912 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2913 if (ret) {
2914 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
2915 return false;
2916 }
2917 }
2918
2919 return true;
2920 }
2921
2922 static bool
2923 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2924 {
2925 /*
2926 * INIT_ZM_AUXCH opcode: 0x99 ('')
2927 *
2928 * offset (8 bit): opcode
2929 * offset + 1 (32 bit): address
2930 * offset + 5 (8 bit): count
2931 * offset + 6 (8 bit): data 0
2932 * ...
2933 *
2934 */
2935
2936 struct drm_device *dev = bios->dev;
2937 struct nouveau_i2c_chan *auxch;
2938 uint32_t addr = ROM32(bios->data[offset + 1]);
2939 uint8_t len = bios->data[offset + 5];
2940 int ret, i;
2941
2942 if (!bios->display.output) {
2943 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
2944 return false;
2945 }
2946
2947 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2948 if (!auxch) {
2949 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2950 bios->display.output->i2c_index);
2951 return false;
2952 }
2953
2954 if (!iexec->execute)
2955 return true;
2956
2957 offset += 6;
2958 for (i = 0; i < len; i++, offset++) {
2959 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2960 if (ret) {
2961 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
2962 return false;
2963 }
2964 }
2965
2966 return true;
2967 }
2968
2969 static struct init_tbl_entry itbl_entry[] = {
2970 /* command name , id , length , offset , mult , command handler */
2971 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2972 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2973 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2974 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2975 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2976 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2977 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2978 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2979 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2980 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2981 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2982 { "INIT_I2C_BYTE" , 0x4C, 4 , 3 , 3 , init_i2c_byte },
2983 { "INIT_ZM_I2C_BYTE" , 0x4D, 4 , 3 , 2 , init_zm_i2c_byte },
2984 { "INIT_ZM_I2C" , 0x4E, 4 , 3 , 1 , init_zm_i2c },
2985 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2986 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2987 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2988 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2989 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2990 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2991 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2992 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2993 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
2994 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2995 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2996 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2997 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2998 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2999 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem },
3000 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk },
3001 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit },
3002 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io },
3003 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
3004 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
3005 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
3006 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
3007 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
3008 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
3009 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3010 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
3011 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
3012 { "INIT_IO_CONDITION" , 0x76, 2 , 0 , 0 , init_io_condition },
3013 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
3014 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
3015 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
3016 /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */
3017 { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll },
3018 { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c },
3019 { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d },
3020 { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio },
3021 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
3022 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
3023 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
3024 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
3025 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
3026 { "INIT_96" , 0x96, 17 , 0 , 0 , init_96 },
3027 { "INIT_97" , 0x97, 13 , 0 , 0 , init_97 },
3028 { "INIT_AUXCH" , 0x98, 6 , 5 , 2 , init_auxch },
3029 { "INIT_ZM_AUXCH" , 0x99, 6 , 5 , 1 , init_zm_auxch },
3030 { NULL , 0 , 0 , 0 , 0 , NULL }
3031 };
3032
3033 static unsigned int get_init_table_entry_length(struct nvbios *bios, unsigned int offset, int i)
3034 {
3035 /* Calculates the length of a given init table entry. */
3036 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
3037 }
3038
3039 #define MAX_TABLE_OPS 1000
3040
3041 static int
3042 parse_init_table(struct nvbios *bios, unsigned int offset,
3043 struct init_exec *iexec)
3044 {
3045 /*
3046 * Parses all commands in an init table.
3047 *
3048 * We start out executing all commands found in the init table. Some
3049 * opcodes may change the status of iexec->execute to SKIP, which will
3050 * cause the following opcodes to perform no operation until the value
3051 * is changed back to EXECUTE.
3052 */
3053
3054 int count = 0, i;
3055 uint8_t id;
3056
3057 /*
3058 * Loop until INIT_DONE causes us to break out of the loop
3059 * (or until offset > bios length just in case... )
3060 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3061 */
3062 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3063 id = bios->data[offset];
3064
3065 /* Find matching id in itbl_entry */
3066 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3067 ;
3068
3069 if (itbl_entry[i].name) {
3070 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
3071 offset, itbl_entry[i].id, itbl_entry[i].name);
3072
3073 /* execute eventual command handler */
3074 if (itbl_entry[i].handler)
3075 if (!(*itbl_entry[i].handler)(bios, offset, iexec))
3076 break;
3077 } else {
3078 NV_ERROR(bios->dev,
3079 "0x%04X: Init table command not found: "
3080 "0x%02X\n", offset, id);
3081 return -ENOENT;
3082 }
3083
3084 /*
3085 * Add the offset of the current command including all data
3086 * of that command. The offset will then be pointing on the
3087 * next op code.
3088 */
3089 offset += get_init_table_entry_length(bios, offset, i);
3090 }
3091
3092 if (offset >= bios->length)
3093 NV_WARN(bios->dev,
3094 "Offset 0x%04X greater than known bios image length. "
3095 "Corrupt image?\n", offset);
3096 if (count >= MAX_TABLE_OPS)
3097 NV_WARN(bios->dev,
3098 "More than %d opcodes to a table is unlikely, "
3099 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3100
3101 return 0;
3102 }
3103
3104 static void
3105 parse_init_tables(struct nvbios *bios)
3106 {
3107 /* Loops and calls parse_init_table() for each present table. */
3108
3109 int i = 0;
3110 uint16_t table;
3111 struct init_exec iexec = {true, false};
3112
3113 if (bios->old_style_init) {
3114 if (bios->init_script_tbls_ptr)
3115 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3116 if (bios->extra_init_script_tbl_ptr)
3117 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3118
3119 return;
3120 }
3121
3122 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3123 NV_INFO(bios->dev,
3124 "Parsing VBIOS init table %d at offset 0x%04X\n",
3125 i / 2, table);
3126 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3127
3128 parse_init_table(bios, table, &iexec);
3129 i += 2;
3130 }
3131 }
3132
3133 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3134 {
3135 int compare_record_len, i = 0;
3136 uint16_t compareclk, scriptptr = 0;
3137
3138 if (bios->major_version < 5) /* pre BIT */
3139 compare_record_len = 3;
3140 else
3141 compare_record_len = 4;
3142
3143 do {
3144 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3145 if (pxclk >= compareclk * 10) {
3146 if (bios->major_version < 5) {
3147 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3148 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3149 } else
3150 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3151 break;
3152 }
3153 i++;
3154 } while (compareclk);
3155
3156 return scriptptr;
3157 }
3158
3159 static void
3160 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3161 struct dcb_entry *dcbent, int head, bool dl)
3162 {
3163 struct drm_nouveau_private *dev_priv = dev->dev_private;
3164 struct nvbios *bios = &dev_priv->VBIOS;
3165 struct init_exec iexec = {true, false};
3166
3167 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3168 scriptptr);
3169 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3170 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3171 /* note: if dcb entries have been merged, index may be misleading */
3172 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3173 parse_init_table(bios, scriptptr, &iexec);
3174
3175 nv04_dfp_bind_head(dev, dcbent, head, dl);
3176 }
3177
3178 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3179 {
3180 struct drm_nouveau_private *dev_priv = dev->dev_private;
3181 struct nvbios *bios = &dev_priv->VBIOS;
3182 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3183 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3184
3185 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3186 return -EINVAL;
3187
3188 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3189
3190 if (script == LVDS_PANEL_OFF) {
3191 /* off-on delay in ms */
3192 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3193 }
3194 #ifdef __powerpc__
3195 /* Powerbook specific quirks */
3196 if (script == LVDS_RESET && ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0329))
3197 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3198 if ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0189 || (dev->pci_device & 0xffff) == 0x0329) {
3199 if (script == LVDS_PANEL_ON) {
3200 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
3201 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3202 }
3203 if (script == LVDS_PANEL_OFF) {
3204 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
3205 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
3206 }
3207 }
3208 #endif
3209
3210 return 0;
3211 }
3212
3213 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3214 {
3215 /*
3216 * The BIT LVDS table's header has the information to setup the
3217 * necessary registers. Following the standard 4 byte header are:
3218 * A bitmask byte and a dual-link transition pxclk value for use in
3219 * selecting the init script when not using straps; 4 script pointers
3220 * for panel power, selected by output and on/off; and 8 table pointers
3221 * for panel init, the needed one determined by output, and bits in the
3222 * conf byte. These tables are similar to the TMDS tables, consisting
3223 * of a list of pxclks and script pointers.
3224 */
3225 struct drm_nouveau_private *dev_priv = dev->dev_private;
3226 struct nvbios *bios = &dev_priv->VBIOS;
3227 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3228 uint16_t scriptptr = 0, clktable;
3229 uint8_t clktableptr = 0;
3230
3231 /*
3232 * For now we assume version 3.0 table - g80 support will need some
3233 * changes
3234 */
3235
3236 switch (script) {
3237 case LVDS_INIT:
3238 return -ENOSYS;
3239 case LVDS_BACKLIGHT_ON:
3240 case LVDS_PANEL_ON:
3241 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3242 break;
3243 case LVDS_BACKLIGHT_OFF:
3244 case LVDS_PANEL_OFF:
3245 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3246 break;
3247 case LVDS_RESET:
3248 if (dcbent->lvdsconf.use_straps_for_mode) {
3249 if (bios->fp.dual_link)
3250 clktableptr += 2;
3251 if (bios->fp.BITbit1)
3252 clktableptr++;
3253 } else {
3254 /* using EDID */
3255 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3256 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3257
3258 if (bios->fp.dual_link) {
3259 clktableptr += 2;
3260 fallbackcmpval *= 2;
3261 }
3262 if (fallbackcmpval & fallback)
3263 clktableptr++;
3264 }
3265
3266 /* adding outputset * 8 may not be correct */
3267 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3268 if (!clktable) {
3269 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3270 return -ENOENT;
3271 }
3272 scriptptr = clkcmptable(bios, clktable, pxclk);
3273 }
3274
3275 if (!scriptptr) {
3276 NV_ERROR(dev, "LVDS output init script not found\n");
3277 return -ENOENT;
3278 }
3279 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3280
3281 return 0;
3282 }
3283
3284 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3285 {
3286 /*
3287 * LVDS operations are multiplexed in an effort to present a single API
3288 * which works with two vastly differing underlying structures.
3289 * This acts as the demux
3290 */
3291
3292 struct drm_nouveau_private *dev_priv = dev->dev_private;
3293 struct nvbios *bios = &dev_priv->VBIOS;
3294 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3295 uint32_t sel_clk_binding, sel_clk;
3296 int ret;
3297
3298 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3299 (lvds_ver >= 0x30 && script == LVDS_INIT))
3300 return 0;
3301
3302 if (!bios->fp.lvds_init_run) {
3303 bios->fp.lvds_init_run = true;
3304 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3305 }
3306
3307 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3308 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3309 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3310 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3311
3312 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3313
3314 /* don't let script change pll->head binding */
3315 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3316
3317 if (lvds_ver < 0x30)
3318 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3319 else
3320 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3321
3322 bios->fp.last_script_invoc = (script << 1 | head);
3323
3324 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3325 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3326 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3327 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3328
3329 return ret;
3330 }
3331
3332 struct lvdstableheader {
3333 uint8_t lvds_ver, headerlen, recordlen;
3334 };
3335
3336 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3337 {
3338 /*
3339 * BMP version (0xa) LVDS table has a simple header of version and
3340 * record length. The BIT LVDS table has the typical BIT table header:
3341 * version byte, header length byte, record length byte, and a byte for
3342 * the maximum number of records that can be held in the table.
3343 */
3344
3345 uint8_t lvds_ver, headerlen, recordlen;
3346
3347 memset(lth, 0, sizeof(struct lvdstableheader));
3348
3349 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3350 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3351 return -EINVAL;
3352 }
3353
3354 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3355
3356 switch (lvds_ver) {
3357 case 0x0a: /* pre NV40 */
3358 headerlen = 2;
3359 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3360 break;
3361 case 0x30: /* NV4x */
3362 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3363 if (headerlen < 0x1f) {
3364 NV_ERROR(dev, "LVDS table header not understood\n");
3365 return -EINVAL;
3366 }
3367 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3368 break;
3369 case 0x40: /* G80/G90 */
3370 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3371 if (headerlen < 0x7) {
3372 NV_ERROR(dev, "LVDS table header not understood\n");
3373 return -EINVAL;
3374 }
3375 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3376 break;
3377 default:
3378 NV_ERROR(dev,
3379 "LVDS table revision %d.%d not currently supported\n",
3380 lvds_ver >> 4, lvds_ver & 0xf);
3381 return -ENOSYS;
3382 }
3383
3384 lth->lvds_ver = lvds_ver;
3385 lth->headerlen = headerlen;
3386 lth->recordlen = recordlen;
3387
3388 return 0;
3389 }
3390
3391 static int
3392 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3393 {
3394 struct drm_nouveau_private *dev_priv = dev->dev_private;
3395
3396 /*
3397 * The fp strap is normally dictated by the "User Strap" in
3398 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3399 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3400 * by the PCI subsystem ID during POST, but not before the previous user
3401 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3402 * read and used instead
3403 */
3404
3405 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3406 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3407
3408 if (dev_priv->card_type >= NV_50)
3409 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3410 else
3411 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3412 }
3413
3414 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3415 {
3416 uint8_t *fptable;
3417 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3418 int ret, ofs, fpstrapping;
3419 struct lvdstableheader lth;
3420
3421 if (bios->fp.fptablepointer == 0x0) {
3422 /* Apple cards don't have the fp table; the laptops use DDC */
3423 /* The table is also missing on some x86 IGPs */
3424 #ifndef __powerpc__
3425 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3426 #endif
3427 bios->pub.digital_min_front_porch = 0x4b;
3428 return 0;
3429 }
3430
3431 fptable = &bios->data[bios->fp.fptablepointer];
3432 fptable_ver = fptable[0];
3433
3434 switch (fptable_ver) {
3435 /*
3436 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3437 * version field, and miss one of the spread spectrum/PWM bytes.
3438 * This could affect early GF2Go parts (not seen any appropriate ROMs
3439 * though). Here we assume that a version of 0x05 matches this case
3440 * (combining with a BMP version check would be better), as the
3441 * common case for the panel type field is 0x0005, and that is in
3442 * fact what we are reading the first byte of.
3443 */
3444 case 0x05: /* some NV10, 11, 15, 16 */
3445 recordlen = 42;
3446 ofs = -1;
3447 break;
3448 case 0x10: /* some NV15/16, and NV11+ */
3449 recordlen = 44;
3450 ofs = 0;
3451 break;
3452 case 0x20: /* NV40+ */
3453 headerlen = fptable[1];
3454 recordlen = fptable[2];
3455 fpentries = fptable[3];
3456 /*
3457 * fptable[4] is the minimum
3458 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3459 */
3460 bios->pub.digital_min_front_porch = fptable[4];
3461 ofs = -7;
3462 break;
3463 default:
3464 NV_ERROR(dev,
3465 "FP table revision %d.%d not currently supported\n",
3466 fptable_ver >> 4, fptable_ver & 0xf);
3467 return -ENOSYS;
3468 }
3469
3470 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3471 return 0;
3472
3473 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3474 if (ret)
3475 return ret;
3476
3477 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3478 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3479 lth.headerlen + 1;
3480 bios->fp.xlatwidth = lth.recordlen;
3481 }
3482 if (bios->fp.fpxlatetableptr == 0x0) {
3483 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3484 return -EINVAL;
3485 }
3486
3487 fpstrapping = get_fp_strap(dev, bios);
3488
3489 fpindex = bios->data[bios->fp.fpxlatetableptr +
3490 fpstrapping * bios->fp.xlatwidth];
3491
3492 if (fpindex > fpentries) {
3493 NV_ERROR(dev, "Bad flat panel table index\n");
3494 return -ENOENT;
3495 }
3496
3497 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3498 if (lth.lvds_ver > 0x10)
3499 bios->pub.fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
3500
3501 /*
3502 * If either the strap or xlated fpindex value are 0xf there is no
3503 * panel using a strap-derived bios mode present. this condition
3504 * includes, but is different from, the DDC panel indicator above
3505 */
3506 if (fpstrapping == 0xf || fpindex == 0xf)
3507 return 0;
3508
3509 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3510 recordlen * fpindex + ofs;
3511
3512 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3513 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3514 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3515 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3516
3517 return 0;
3518 }
3519
3520 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3521 {
3522 struct drm_nouveau_private *dev_priv = dev->dev_private;
3523 struct nvbios *bios = &dev_priv->VBIOS;
3524 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3525
3526 if (!mode) /* just checking whether we can produce a mode */
3527 return bios->fp.mode_ptr;
3528
3529 memset(mode, 0, sizeof(struct drm_display_mode));
3530 /*
3531 * For version 1.0 (version in byte 0):
3532 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3533 * single/dual link, and type (TFT etc.)
3534 * bytes 3-6 are bits per colour in RGBX
3535 */
3536 mode->clock = ROM16(mode_entry[7]) * 10;
3537 /* bytes 9-10 is HActive */
3538 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3539 /*
3540 * bytes 13-14 is HValid Start
3541 * bytes 15-16 is HValid End
3542 */
3543 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3544 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3545 mode->htotal = ROM16(mode_entry[21]) + 1;
3546 /* bytes 23-24, 27-30 similarly, but vertical */
3547 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3548 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3549 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3550 mode->vtotal = ROM16(mode_entry[35]) + 1;
3551 mode->flags |= (mode_entry[37] & 0x10) ?
3552 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3553 mode->flags |= (mode_entry[37] & 0x1) ?
3554 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3555 /*
3556 * bytes 38-39 relate to spread spectrum settings
3557 * bytes 40-43 are something to do with PWM
3558 */
3559
3560 mode->status = MODE_OK;
3561 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3562 drm_mode_set_name(mode);
3563 return bios->fp.mode_ptr;
3564 }
3565
3566 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3567 {
3568 /*
3569 * The LVDS table header is (mostly) described in
3570 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3571 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3572 * straps are not being used for the panel, this specifies the frequency
3573 * at which modes should be set up in the dual link style.
3574 *
3575 * Following the header, the BMP (ver 0xa) table has several records,
3576 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3577 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3578 * numbers for use by INIT_SUB which controlled panel init and power,
3579 * and finally a dword of ms to sleep between power off and on
3580 * operations.
3581 *
3582 * In the BIT versions, the table following the header serves as an
3583 * integrated config and xlat table: the records in the table are
3584 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3585 * two bytes - the first as a config byte, the second for indexing the
3586 * fp mode table pointed to by the BIT 'D' table
3587 *
3588 * DDC is not used until after card init, so selecting the correct table
3589 * entry and setting the dual link flag for EDID equipped panels,
3590 * requiring tests against the native-mode pixel clock, cannot be done
3591 * until later, when this function should be called with non-zero pxclk
3592 */
3593 struct drm_nouveau_private *dev_priv = dev->dev_private;
3594 struct nvbios *bios = &dev_priv->VBIOS;
3595 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3596 struct lvdstableheader lth;
3597 uint16_t lvdsofs;
3598 int ret, chip_version = bios->pub.chip_version;
3599
3600 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3601 if (ret)
3602 return ret;
3603
3604 switch (lth.lvds_ver) {
3605 case 0x0a: /* pre NV40 */
3606 lvdsmanufacturerindex = bios->data[
3607 bios->fp.fpxlatemanufacturertableptr +
3608 fpstrapping];
3609
3610 /* we're done if this isn't the EDID panel case */
3611 if (!pxclk)
3612 break;
3613
3614 if (chip_version < 0x25) {
3615 /* nv17 behaviour
3616 *
3617 * It seems the old style lvds script pointer is reused
3618 * to select 18/24 bit colour depth for EDID panels.
3619 */
3620 lvdsmanufacturerindex =
3621 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3622 2 : 0;
3623 if (pxclk >= bios->fp.duallink_transition_clk)
3624 lvdsmanufacturerindex++;
3625 } else if (chip_version < 0x30) {
3626 /* nv28 behaviour (off-chip encoder)
3627 *
3628 * nv28 does a complex dance of first using byte 121 of
3629 * the EDID to choose the lvdsmanufacturerindex, then
3630 * later attempting to match the EDID manufacturer and
3631 * product IDs in a table (signature 'pidt' (panel id
3632 * table?)), setting an lvdsmanufacturerindex of 0 and
3633 * an fp strap of the match index (or 0xf if none)
3634 */
3635 lvdsmanufacturerindex = 0;
3636 } else {
3637 /* nv31, nv34 behaviour */
3638 lvdsmanufacturerindex = 0;
3639 if (pxclk >= bios->fp.duallink_transition_clk)
3640 lvdsmanufacturerindex = 2;
3641 if (pxclk >= 140000)
3642 lvdsmanufacturerindex = 3;
3643 }
3644
3645 /*
3646 * nvidia set the high nibble of (cr57=f, cr58) to
3647 * lvdsmanufacturerindex in this case; we don't
3648 */
3649 break;
3650 case 0x30: /* NV4x */
3651 case 0x40: /* G80/G90 */
3652 lvdsmanufacturerindex = fpstrapping;
3653 break;
3654 default:
3655 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3656 return -ENOSYS;
3657 }
3658
3659 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3660 switch (lth.lvds_ver) {
3661 case 0x0a:
3662 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3663 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3664 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3665 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3666 *if_is_24bit = bios->data[lvdsofs] & 16;
3667 break;
3668 case 0x30:
3669 /*
3670 * My money would be on there being a 24 bit interface bit in
3671 * this table, but I have no example of a laptop bios with a
3672 * 24 bit panel to confirm that. Hence we shout loudly if any
3673 * bit other than bit 0 is set (I've not even seen bit 1)
3674 */
3675 if (bios->data[lvdsofs] > 1)
3676 NV_ERROR(dev,
3677 "You have a very unusual laptop display; please report it\n");
3678 /*
3679 * No sign of the "power off for reset" or "reset for panel
3680 * on" bits, but it's safer to assume we should
3681 */
3682 bios->fp.power_off_for_reset = true;
3683 bios->fp.reset_after_pclk_change = true;
3684 /*
3685 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3686 * over-written, and BITbit1 isn't used
3687 */
3688 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3689 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3690 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3691 break;
3692 case 0x40:
3693 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3694 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3695 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3696 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3697 break;
3698 }
3699
3700 /* set dual_link flag for EDID case */
3701 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3702 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3703
3704 *dl = bios->fp.dual_link;
3705
3706 return 0;
3707 }
3708
3709 static uint8_t *
3710 bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3711 uint16_t record, int record_len, int record_nr)
3712 {
3713 struct drm_nouveau_private *dev_priv = dev->dev_private;
3714 struct nvbios *bios = &dev_priv->VBIOS;
3715 uint32_t entry;
3716 uint16_t table;
3717 int i, v;
3718
3719 for (i = 0; i < record_nr; i++, record += record_len) {
3720 table = ROM16(bios->data[record]);
3721 if (!table)
3722 continue;
3723 entry = ROM32(bios->data[table]);
3724
3725 v = (entry & 0x000f0000) >> 16;
3726 if (!(v & dcbent->or))
3727 continue;
3728
3729 v = (entry & 0x000000f0) >> 4;
3730 if (v != dcbent->location)
3731 continue;
3732
3733 v = (entry & 0x0000000f);
3734 if (v != dcbent->type)
3735 continue;
3736
3737 return &bios->data[table];
3738 }
3739
3740 return NULL;
3741 }
3742
3743 void *
3744 nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3745 int *length)
3746 {
3747 struct drm_nouveau_private *dev_priv = dev->dev_private;
3748 struct nvbios *bios = &dev_priv->VBIOS;
3749 uint8_t *table;
3750
3751 if (!bios->display.dp_table_ptr) {
3752 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3753 return NULL;
3754 }
3755 table = &bios->data[bios->display.dp_table_ptr];
3756
3757 if (table[0] != 0x21) {
3758 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3759 table[0]);
3760 return NULL;
3761 }
3762
3763 *length = table[4];
3764 return bios_output_config_match(dev, dcbent,
3765 bios->display.dp_table_ptr + table[1],
3766 table[2], table[3]);
3767 }
3768
3769 int
3770 nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3771 uint32_t sub, int pxclk)
3772 {
3773 /*
3774 * The display script table is located by the BIT 'U' table.
3775 *
3776 * It contains an array of pointers to various tables describing
3777 * a particular output type. The first 32-bits of the output
3778 * tables contains similar information to a DCB entry, and is
3779 * used to decide whether that particular table is suitable for
3780 * the output you want to access.
3781 *
3782 * The "record header length" field here seems to indicate the
3783 * offset of the first configuration entry in the output tables.
3784 * This is 10 on most cards I've seen, but 12 has been witnessed
3785 * on DP cards, and there's another script pointer within the
3786 * header.
3787 *
3788 * offset + 0 ( 8 bits): version
3789 * offset + 1 ( 8 bits): header length
3790 * offset + 2 ( 8 bits): record length
3791 * offset + 3 ( 8 bits): number of records
3792 * offset + 4 ( 8 bits): record header length
3793 * offset + 5 (16 bits): pointer to first output script table
3794 */
3795
3796 struct drm_nouveau_private *dev_priv = dev->dev_private;
3797 struct init_exec iexec = {true, false};
3798 struct nvbios *bios = &dev_priv->VBIOS;
3799 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3800 uint8_t *otable = NULL;
3801 uint16_t script;
3802 int i = 0;
3803
3804 if (!bios->display.script_table_ptr) {
3805 NV_ERROR(dev, "No pointer to output script table\n");
3806 return 1;
3807 }
3808
3809 /*
3810 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3811 * so until they are, we really don't need to care.
3812 */
3813 if (table[0] < 0x20)
3814 return 1;
3815
3816 if (table[0] != 0x20 && table[0] != 0x21) {
3817 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3818 table[0]);
3819 return 1;
3820 }
3821
3822 /*
3823 * The output script tables describing a particular output type
3824 * look as follows:
3825 *
3826 * offset + 0 (32 bits): output this table matches (hash of DCB)
3827 * offset + 4 ( 8 bits): unknown
3828 * offset + 5 ( 8 bits): number of configurations
3829 * offset + 6 (16 bits): pointer to some script
3830 * offset + 8 (16 bits): pointer to some script
3831 *
3832 * headerlen == 10
3833 * offset + 10 : configuration 0
3834 *
3835 * headerlen == 12
3836 * offset + 10 : pointer to some script
3837 * offset + 12 : configuration 0
3838 *
3839 * Each config entry is as follows:
3840 *
3841 * offset + 0 (16 bits): unknown, assumed to be a match value
3842 * offset + 2 (16 bits): pointer to script table (clock set?)
3843 * offset + 4 (16 bits): pointer to script table (reset?)
3844 *
3845 * There doesn't appear to be a count value to say how many
3846 * entries exist in each script table, instead, a 0 value in
3847 * the first 16-bit word seems to indicate both the end of the
3848 * list and the default entry. The second 16-bit word in the
3849 * script tables is a pointer to the script to execute.
3850 */
3851
3852 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
3853 dcbent->type, dcbent->location, dcbent->or);
3854 otable = bios_output_config_match(dev, dcbent, table[1] +
3855 bios->display.script_table_ptr,
3856 table[2], table[3]);
3857 if (!otable) {
3858 NV_ERROR(dev, "Couldn't find matching output script table\n");
3859 return 1;
3860 }
3861
3862 if (pxclk < -2 || pxclk > 0) {
3863 /* Try to find matching script table entry */
3864 for (i = 0; i < otable[5]; i++) {
3865 if (ROM16(otable[table[4] + i*6]) == sub)
3866 break;
3867 }
3868
3869 if (i == otable[5]) {
3870 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3871 "using first\n",
3872 sub, dcbent->type, dcbent->or);
3873 i = 0;
3874 }
3875 }
3876
3877 bios->display.output = dcbent;
3878
3879 if (pxclk == 0) {
3880 script = ROM16(otable[6]);
3881 if (!script) {
3882 NV_DEBUG_KMS(dev, "output script 0 not found\n");
3883 return 1;
3884 }
3885
3886 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
3887 parse_init_table(bios, script, &iexec);
3888 } else
3889 if (pxclk == -1) {
3890 script = ROM16(otable[8]);
3891 if (!script) {
3892 NV_DEBUG_KMS(dev, "output script 1 not found\n");
3893 return 1;
3894 }
3895
3896 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
3897 parse_init_table(bios, script, &iexec);
3898 } else
3899 if (pxclk == -2) {
3900 if (table[4] >= 12)
3901 script = ROM16(otable[10]);
3902 else
3903 script = 0;
3904 if (!script) {
3905 NV_DEBUG_KMS(dev, "output script 2 not found\n");
3906 return 1;
3907 }
3908
3909 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
3910 parse_init_table(bios, script, &iexec);
3911 } else
3912 if (pxclk > 0) {
3913 script = ROM16(otable[table[4] + i*6 + 2]);
3914 if (script)
3915 script = clkcmptable(bios, script, pxclk);
3916 if (!script) {
3917 NV_ERROR(dev, "clock script 0 not found\n");
3918 return 1;
3919 }
3920
3921 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
3922 parse_init_table(bios, script, &iexec);
3923 } else
3924 if (pxclk < 0) {
3925 script = ROM16(otable[table[4] + i*6 + 4]);
3926 if (script)
3927 script = clkcmptable(bios, script, -pxclk);
3928 if (!script) {
3929 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
3930 return 1;
3931 }
3932
3933 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
3934 parse_init_table(bios, script, &iexec);
3935 }
3936
3937 return 0;
3938 }
3939
3940
3941 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
3942 {
3943 /*
3944 * the pxclk parameter is in kHz
3945 *
3946 * This runs the TMDS regs setting code found on BIT bios cards
3947 *
3948 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3949 * ffs(or) == 3, use the second.
3950 */
3951
3952 struct drm_nouveau_private *dev_priv = dev->dev_private;
3953 struct nvbios *bios = &dev_priv->VBIOS;
3954 int cv = bios->pub.chip_version;
3955 uint16_t clktable = 0, scriptptr;
3956 uint32_t sel_clk_binding, sel_clk;
3957
3958 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3959 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
3960 dcbent->location != DCB_LOC_ON_CHIP)
3961 return 0;
3962
3963 switch (ffs(dcbent->or)) {
3964 case 1:
3965 clktable = bios->tmds.output0_script_ptr;
3966 break;
3967 case 2:
3968 case 3:
3969 clktable = bios->tmds.output1_script_ptr;
3970 break;
3971 }
3972
3973 if (!clktable) {
3974 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3975 return -EINVAL;
3976 }
3977
3978 scriptptr = clkcmptable(bios, clktable, pxclk);
3979
3980 if (!scriptptr) {
3981 NV_ERROR(dev, "TMDS output init script not found\n");
3982 return -ENOENT;
3983 }
3984
3985 /* don't let script change pll->head binding */
3986 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3987 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
3988 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3989 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3990
3991 return 0;
3992 }
3993
3994 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
3995 {
3996 /*
3997 * PLL limits table
3998 *
3999 * Version 0x10: NV30, NV31
4000 * One byte header (version), one record of 24 bytes
4001 * Version 0x11: NV36 - Not implemented
4002 * Seems to have same record style as 0x10, but 3 records rather than 1
4003 * Version 0x20: Found on Geforce 6 cards
4004 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4005 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4006 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4007 * length in general, some (integrated) have an extra configuration byte
4008 * Version 0x30: Found on Geforce 8, separates the register mapping
4009 * from the limits tables.
4010 */
4011
4012 struct drm_nouveau_private *dev_priv = dev->dev_private;
4013 struct nvbios *bios = &dev_priv->VBIOS;
4014 int cv = bios->pub.chip_version, pllindex = 0;
4015 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4016 uint32_t crystal_strap_mask, crystal_straps;
4017
4018 if (!bios->pll_limit_tbl_ptr) {
4019 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4020 cv >= 0x40) {
4021 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4022 return -EINVAL;
4023 }
4024 } else
4025 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4026
4027 crystal_strap_mask = 1 << 6;
4028 /* open coded dev->twoHeads test */
4029 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4030 crystal_strap_mask |= 1 << 22;
4031 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4032 crystal_strap_mask;
4033
4034 switch (pll_lim_ver) {
4035 /*
4036 * We use version 0 to indicate a pre limit table bios (single stage
4037 * pll) and load the hard coded limits instead.
4038 */
4039 case 0:
4040 break;
4041 case 0x10:
4042 case 0x11:
4043 /*
4044 * Strictly v0x11 has 3 entries, but the last two don't seem
4045 * to get used.
4046 */
4047 headerlen = 1;
4048 recordlen = 0x18;
4049 entries = 1;
4050 pllindex = 0;
4051 break;
4052 case 0x20:
4053 case 0x21:
4054 case 0x30:
4055 case 0x40:
4056 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4057 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4058 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4059 break;
4060 default:
4061 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4062 "supported\n", pll_lim_ver);
4063 return -ENOSYS;
4064 }
4065
4066 /* initialize all members to zero */
4067 memset(pll_lim, 0, sizeof(struct pll_lims));
4068
4069 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4070 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4071
4072 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4073 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4074 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4075 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4076 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4077 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4078 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4079
4080 /* these values taken from nv30/31/36 */
4081 pll_lim->vco1.min_n = 0x1;
4082 if (cv == 0x36)
4083 pll_lim->vco1.min_n = 0x5;
4084 pll_lim->vco1.max_n = 0xff;
4085 pll_lim->vco1.min_m = 0x1;
4086 pll_lim->vco1.max_m = 0xd;
4087 pll_lim->vco2.min_n = 0x4;
4088 /*
4089 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4090 * table version (apart from nv35)), N2 is compared to
4091 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4092 * save a comparison
4093 */
4094 pll_lim->vco2.max_n = 0x28;
4095 if (cv == 0x30 || cv == 0x35)
4096 /* only 5 bits available for N2 on nv30/35 */
4097 pll_lim->vco2.max_n = 0x1f;
4098 pll_lim->vco2.min_m = 0x1;
4099 pll_lim->vco2.max_m = 0x4;
4100 pll_lim->max_log2p = 0x7;
4101 pll_lim->max_usable_log2p = 0x6;
4102 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4103 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4104 uint32_t reg = 0; /* default match */
4105 uint8_t *pll_rec;
4106 int i;
4107
4108 /*
4109 * First entry is default match, if nothing better. warn if
4110 * reg field nonzero
4111 */
4112 if (ROM32(bios->data[plloffs]))
4113 NV_WARN(dev, "Default PLL limit entry has non-zero "
4114 "register field\n");
4115
4116 if (limit_match > MAX_PLL_TYPES)
4117 /* we've been passed a reg as the match */
4118 reg = limit_match;
4119 else /* limit match is a pll type */
4120 for (i = 1; i < entries && !reg; i++) {
4121 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4122
4123 if (limit_match == NVPLL &&
4124 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4125 reg = cmpreg;
4126 if (limit_match == MPLL &&
4127 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4128 reg = cmpreg;
4129 if (limit_match == VPLL1 &&
4130 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4131 reg = cmpreg;
4132 if (limit_match == VPLL2 &&
4133 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4134 reg = cmpreg;
4135 }
4136
4137 for (i = 1; i < entries; i++)
4138 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4139 pllindex = i;
4140 break;
4141 }
4142
4143 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4144
4145 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4146 pllindex ? reg : 0);
4147
4148 /*
4149 * Frequencies are stored in tables in MHz, kHz are more
4150 * useful, so we convert.
4151 */
4152
4153 /* What output frequencies can each VCO generate? */
4154 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4155 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4156 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4157 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4158
4159 /* What input frequencies they accept (past the m-divider)? */
4160 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4161 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4162 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4163 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4164
4165 /* What values are accepted as multiplier and divider? */
4166 pll_lim->vco1.min_n = pll_rec[20];
4167 pll_lim->vco1.max_n = pll_rec[21];
4168 pll_lim->vco1.min_m = pll_rec[22];
4169 pll_lim->vco1.max_m = pll_rec[23];
4170 pll_lim->vco2.min_n = pll_rec[24];
4171 pll_lim->vco2.max_n = pll_rec[25];
4172 pll_lim->vco2.min_m = pll_rec[26];
4173 pll_lim->vco2.max_m = pll_rec[27];
4174
4175 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4176 if (pll_lim->max_log2p > 0x7)
4177 /* pll decoding in nv_hw.c assumes never > 7 */
4178 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4179 pll_lim->max_log2p);
4180 if (cv < 0x60)
4181 pll_lim->max_usable_log2p = 0x6;
4182 pll_lim->log2p_bias = pll_rec[30];
4183
4184 if (recordlen > 0x22)
4185 pll_lim->refclk = ROM32(pll_rec[31]);
4186
4187 if (recordlen > 0x23 && pll_rec[35])
4188 NV_WARN(dev,
4189 "Bits set in PLL configuration byte (%x)\n",
4190 pll_rec[35]);
4191
4192 /* C51 special not seen elsewhere */
4193 if (cv == 0x51 && !pll_lim->refclk) {
4194 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4195
4196 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4197 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4198 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4199 pll_lim->refclk = 200000;
4200 else
4201 pll_lim->refclk = 25000;
4202 }
4203 }
4204 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4205 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4206 uint8_t *record = NULL;
4207 int i;
4208
4209 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4210 limit_match);
4211
4212 for (i = 0; i < entries; i++, entry += recordlen) {
4213 if (ROM32(entry[3]) == limit_match) {
4214 record = &bios->data[ROM16(entry[1])];
4215 break;
4216 }
4217 }
4218
4219 if (!record) {
4220 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4221 "limits table", limit_match);
4222 return -ENOENT;
4223 }
4224
4225 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4226 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4227 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4228 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4229 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4230 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4231 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4232 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4233 pll_lim->vco1.min_n = record[16];
4234 pll_lim->vco1.max_n = record[17];
4235 pll_lim->vco1.min_m = record[18];
4236 pll_lim->vco1.max_m = record[19];
4237 pll_lim->vco2.min_n = record[20];
4238 pll_lim->vco2.max_n = record[21];
4239 pll_lim->vco2.min_m = record[22];
4240 pll_lim->vco2.max_m = record[23];
4241 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4242 pll_lim->log2p_bias = record[27];
4243 pll_lim->refclk = ROM32(record[28]);
4244 } else if (pll_lim_ver) { /* ver 0x40 */
4245 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4246 uint8_t *record = NULL;
4247 int i;
4248
4249 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4250 limit_match);
4251
4252 for (i = 0; i < entries; i++, entry += recordlen) {
4253 if (ROM32(entry[3]) == limit_match) {
4254 record = &bios->data[ROM16(entry[1])];
4255 break;
4256 }
4257 }
4258
4259 if (!record) {
4260 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4261 "limits table", limit_match);
4262 return -ENOENT;
4263 }
4264
4265 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4266 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4267 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4268 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4269 pll_lim->vco1.min_m = record[8];
4270 pll_lim->vco1.max_m = record[9];
4271 pll_lim->vco1.min_n = record[10];
4272 pll_lim->vco1.max_n = record[11];
4273 pll_lim->min_p = record[12];
4274 pll_lim->max_p = record[13];
4275 /* where did this go to?? */
4276 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4277 pll_lim->refclk = 27000;
4278 else
4279 pll_lim->refclk = 100000;
4280 }
4281
4282 /*
4283 * By now any valid limit table ought to have set a max frequency for
4284 * vco1, so if it's zero it's either a pre limit table bios, or one
4285 * with an empty limit table (seen on nv18)
4286 */
4287 if (!pll_lim->vco1.maxfreq) {
4288 pll_lim->vco1.minfreq = bios->fminvco;
4289 pll_lim->vco1.maxfreq = bios->fmaxvco;
4290 pll_lim->vco1.min_inputfreq = 0;
4291 pll_lim->vco1.max_inputfreq = INT_MAX;
4292 pll_lim->vco1.min_n = 0x1;
4293 pll_lim->vco1.max_n = 0xff;
4294 pll_lim->vco1.min_m = 0x1;
4295 if (crystal_straps == 0) {
4296 /* nv05 does this, nv11 doesn't, nv10 unknown */
4297 if (cv < 0x11)
4298 pll_lim->vco1.min_m = 0x7;
4299 pll_lim->vco1.max_m = 0xd;
4300 } else {
4301 if (cv < 0x11)
4302 pll_lim->vco1.min_m = 0x8;
4303 pll_lim->vco1.max_m = 0xe;
4304 }
4305 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4306 pll_lim->max_log2p = 4;
4307 else
4308 pll_lim->max_log2p = 5;
4309 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4310 }
4311
4312 if (!pll_lim->refclk)
4313 switch (crystal_straps) {
4314 case 0:
4315 pll_lim->refclk = 13500;
4316 break;
4317 case (1 << 6):
4318 pll_lim->refclk = 14318;
4319 break;
4320 case (1 << 22):
4321 pll_lim->refclk = 27000;
4322 break;
4323 case (1 << 22 | 1 << 6):
4324 pll_lim->refclk = 25000;
4325 break;
4326 }
4327
4328 #if 0 /* for easy debugging */
4329 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4330 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4331 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4332 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4333
4334 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4335 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4336 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4337 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4338
4339 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4340 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4341 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4342 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4343 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4344 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4345 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4346 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4347
4348 ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p);
4349 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4350
4351 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
4352 #endif
4353
4354 return 0;
4355 }
4356
4357 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4358 {
4359 /*
4360 * offset + 0 (8 bits): Micro version
4361 * offset + 1 (8 bits): Minor version
4362 * offset + 2 (8 bits): Chip version
4363 * offset + 3 (8 bits): Major version
4364 */
4365
4366 bios->major_version = bios->data[offset + 3];
4367 bios->pub.chip_version = bios->data[offset + 2];
4368 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4369 bios->data[offset + 3], bios->data[offset + 2],
4370 bios->data[offset + 1], bios->data[offset]);
4371 }
4372
4373 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4374 {
4375 /*
4376 * Parses the init table segment for pointers used in script execution.
4377 *
4378 * offset + 0 (16 bits): init script tables pointer
4379 * offset + 2 (16 bits): macro index table pointer
4380 * offset + 4 (16 bits): macro table pointer
4381 * offset + 6 (16 bits): condition table pointer
4382 * offset + 8 (16 bits): io condition table pointer
4383 * offset + 10 (16 bits): io flag condition table pointer
4384 * offset + 12 (16 bits): init function table pointer
4385 */
4386
4387 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4388 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4389 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4390 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4391 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4392 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4393 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4394 }
4395
4396 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4397 {
4398 /*
4399 * Parses the load detect values for g80 cards.
4400 *
4401 * offset + 0 (16 bits): loadval table pointer
4402 */
4403
4404 uint16_t load_table_ptr;
4405 uint8_t version, headerlen, entrylen, num_entries;
4406
4407 if (bitentry->length != 3) {
4408 NV_ERROR(dev, "Do not understand BIT A table\n");
4409 return -EINVAL;
4410 }
4411
4412 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4413
4414 if (load_table_ptr == 0x0) {
4415 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4416 return -EINVAL;
4417 }
4418
4419 version = bios->data[load_table_ptr];
4420
4421 if (version != 0x10) {
4422 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4423 version >> 4, version & 0xF);
4424 return -ENOSYS;
4425 }
4426
4427 headerlen = bios->data[load_table_ptr + 1];
4428 entrylen = bios->data[load_table_ptr + 2];
4429 num_entries = bios->data[load_table_ptr + 3];
4430
4431 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4432 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4433 return -EINVAL;
4434 }
4435
4436 /* First entry is normal dac, 2nd tv-out perhaps? */
4437 bios->pub.dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
4438
4439 return 0;
4440 }
4441
4442 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4443 {
4444 /*
4445 * offset + 8 (16 bits): PLL limits table pointer
4446 *
4447 * There's more in here, but that's unknown.
4448 */
4449
4450 if (bitentry->length < 10) {
4451 NV_ERROR(dev, "Do not understand BIT C table\n");
4452 return -EINVAL;
4453 }
4454
4455 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4456
4457 return 0;
4458 }
4459
4460 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4461 {
4462 /*
4463 * Parses the flat panel table segment that the bit entry points to.
4464 * Starting at bitentry->offset:
4465 *
4466 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4467 * records beginning with a freq.
4468 * offset + 2 (16 bits): mode table pointer
4469 */
4470
4471 if (bitentry->length != 4) {
4472 NV_ERROR(dev, "Do not understand BIT display table\n");
4473 return -EINVAL;
4474 }
4475
4476 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4477
4478 return 0;
4479 }
4480
4481 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4482 {
4483 /*
4484 * Parses the init table segment that the bit entry points to.
4485 *
4486 * See parse_script_table_pointers for layout
4487 */
4488
4489 if (bitentry->length < 14) {
4490 NV_ERROR(dev, "Do not understand init table\n");
4491 return -EINVAL;
4492 }
4493
4494 parse_script_table_pointers(bios, bitentry->offset);
4495
4496 if (bitentry->length >= 16)
4497 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4498 if (bitentry->length >= 18)
4499 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4500
4501 return 0;
4502 }
4503
4504 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4505 {
4506 /*
4507 * BIT 'i' (info?) table
4508 *
4509 * offset + 0 (32 bits): BIOS version dword (as in B table)
4510 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4511 * offset + 13 (16 bits): pointer to table containing DAC load
4512 * detection comparison values
4513 *
4514 * There's other things in the table, purpose unknown
4515 */
4516
4517 uint16_t daccmpoffset;
4518 uint8_t dacver, dacheaderlen;
4519
4520 if (bitentry->length < 6) {
4521 NV_ERROR(dev, "BIT i table too short for needed information\n");
4522 return -EINVAL;
4523 }
4524
4525 parse_bios_version(dev, bios, bitentry->offset);
4526
4527 /*
4528 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4529 * Quadro identity crisis), other bits possibly as for BMP feature byte
4530 */
4531 bios->feature_byte = bios->data[bitentry->offset + 5];
4532 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4533
4534 if (bitentry->length < 15) {
4535 NV_WARN(dev, "BIT i table not long enough for DAC load "
4536 "detection comparison table\n");
4537 return -EINVAL;
4538 }
4539
4540 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4541
4542 /* doesn't exist on g80 */
4543 if (!daccmpoffset)
4544 return 0;
4545
4546 /*
4547 * The first value in the table, following the header, is the
4548 * comparison value, the second entry is a comparison value for
4549 * TV load detection.
4550 */
4551
4552 dacver = bios->data[daccmpoffset];
4553 dacheaderlen = bios->data[daccmpoffset + 1];
4554
4555 if (dacver != 0x00 && dacver != 0x10) {
4556 NV_WARN(dev, "DAC load detection comparison table version "
4557 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4558 return -ENOSYS;
4559 }
4560
4561 bios->pub.dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4562 bios->pub.tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
4563
4564 return 0;
4565 }
4566
4567 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4568 {
4569 /*
4570 * Parses the LVDS table segment that the bit entry points to.
4571 * Starting at bitentry->offset:
4572 *
4573 * offset + 0 (16 bits): LVDS strap xlate table pointer
4574 */
4575
4576 if (bitentry->length != 2) {
4577 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4578 return -EINVAL;
4579 }
4580
4581 /*
4582 * No idea if it's still called the LVDS manufacturer table, but
4583 * the concept's close enough.
4584 */
4585 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4586
4587 return 0;
4588 }
4589
4590 static int
4591 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4592 struct bit_entry *bitentry)
4593 {
4594 /*
4595 * offset + 2 (8 bits): number of options in an
4596 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4597 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4598 * restrict option selection
4599 *
4600 * There's a bunch of bits in this table other than the RAM restrict
4601 * stuff that we don't use - their use currently unknown
4602 */
4603
4604 uint16_t rr_strap_xlat;
4605 uint8_t rr_group_count;
4606 int i;
4607
4608 /*
4609 * Older bios versions don't have a sufficiently long table for
4610 * what we want
4611 */
4612 if (bitentry->length < 0x5)
4613 return 0;
4614
4615 if (bitentry->id[1] < 2) {
4616 rr_group_count = bios->data[bitentry->offset + 2];
4617 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 3]);
4618 } else {
4619 rr_group_count = bios->data[bitentry->offset + 0];
4620 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 1]);
4621 }
4622
4623 /* adjust length of INIT_87 */
4624 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x87); i++);
4625 itbl_entry[i].length += rr_group_count * 4;
4626
4627 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
4628 for (; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++);
4629 itbl_entry[i].length_multiplier = rr_group_count * 4;
4630
4631 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
4632 bios->ram_restrict_tbl_ptr = rr_strap_xlat;
4633
4634 return 0;
4635 }
4636
4637 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4638 {
4639 /*
4640 * Parses the pointer to the TMDS table
4641 *
4642 * Starting at bitentry->offset:
4643 *
4644 * offset + 0 (16 bits): TMDS table pointer
4645 *
4646 * The TMDS table is typically found just before the DCB table, with a
4647 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4648 * length?)
4649 *
4650 * At offset +7 is a pointer to a script, which I don't know how to
4651 * run yet.
4652 * At offset +9 is a pointer to another script, likewise
4653 * Offset +11 has a pointer to a table where the first word is a pxclk
4654 * frequency and the second word a pointer to a script, which should be
4655 * run if the comparison pxclk frequency is less than the pxclk desired.
4656 * This repeats for decreasing comparison frequencies
4657 * Offset +13 has a pointer to a similar table
4658 * The selection of table (and possibly +7/+9 script) is dictated by
4659 * "or" from the DCB.
4660 */
4661
4662 uint16_t tmdstableptr, script1, script2;
4663
4664 if (bitentry->length != 2) {
4665 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4666 return -EINVAL;
4667 }
4668
4669 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4670
4671 if (tmdstableptr == 0x0) {
4672 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4673 return -EINVAL;
4674 }
4675
4676 /* nv50+ has v2.0, but we don't parse it atm */
4677 if (bios->data[tmdstableptr] != 0x11) {
4678 NV_WARN(dev,
4679 "TMDS table revision %d.%d not currently supported\n",
4680 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4681 return -ENOSYS;
4682 }
4683
4684 /*
4685 * These two scripts are odd: they don't seem to get run even when
4686 * they are not stubbed.
4687 */
4688 script1 = ROM16(bios->data[tmdstableptr + 7]);
4689 script2 = ROM16(bios->data[tmdstableptr + 9]);
4690 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4691 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4692
4693 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4694 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4695
4696 return 0;
4697 }
4698
4699 static int
4700 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4701 struct bit_entry *bitentry)
4702 {
4703 /*
4704 * Parses the pointer to the G80 output script tables
4705 *
4706 * Starting at bitentry->offset:
4707 *
4708 * offset + 0 (16 bits): output script table pointer
4709 */
4710
4711 uint16_t outputscripttableptr;
4712
4713 if (bitentry->length != 3) {
4714 NV_ERROR(dev, "Do not understand BIT U table\n");
4715 return -EINVAL;
4716 }
4717
4718 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4719 bios->display.script_table_ptr = outputscripttableptr;
4720 return 0;
4721 }
4722
4723 static int
4724 parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4725 struct bit_entry *bitentry)
4726 {
4727 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4728 return 0;
4729 }
4730
4731 struct bit_table {
4732 const char id;
4733 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4734 };
4735
4736 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4737
4738 static int
4739 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4740 struct bit_table *table)
4741 {
4742 struct drm_device *dev = bios->dev;
4743 uint8_t maxentries = bios->data[bitoffset + 4];
4744 int i, offset;
4745 struct bit_entry bitentry;
4746
4747 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4748 bitentry.id[0] = bios->data[offset];
4749
4750 if (bitentry.id[0] != table->id)
4751 continue;
4752
4753 bitentry.id[1] = bios->data[offset + 1];
4754 bitentry.length = ROM16(bios->data[offset + 2]);
4755 bitentry.offset = ROM16(bios->data[offset + 4]);
4756
4757 return table->parse_fn(dev, bios, &bitentry);
4758 }
4759
4760 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4761 return -ENOSYS;
4762 }
4763
4764 static int
4765 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4766 {
4767 int ret;
4768
4769 /*
4770 * The only restriction on parsing order currently is having 'i' first
4771 * for use of bios->*_version or bios->feature_byte while parsing;
4772 * functions shouldn't be actually *doing* anything apart from pulling
4773 * data from the image into the bios struct, thus no interdependencies
4774 */
4775 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4776 if (ret) /* info? */
4777 return ret;
4778 if (bios->major_version >= 0x60) /* g80+ */
4779 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4780 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4781 if (ret)
4782 return ret;
4783 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4784 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4785 if (ret)
4786 return ret;
4787 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4788 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4789 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4790 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4791 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4792
4793 return 0;
4794 }
4795
4796 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4797 {
4798 /*
4799 * Parses the BMP structure for useful things, but does not act on them
4800 *
4801 * offset + 5: BMP major version
4802 * offset + 6: BMP minor version
4803 * offset + 9: BMP feature byte
4804 * offset + 10: BCD encoded BIOS version
4805 *
4806 * offset + 18: init script table pointer (for bios versions < 5.10h)
4807 * offset + 20: extra init script table pointer (for bios
4808 * versions < 5.10h)
4809 *
4810 * offset + 24: memory init table pointer (used on early bios versions)
4811 * offset + 26: SDR memory sequencing setup data table
4812 * offset + 28: DDR memory sequencing setup data table
4813 *
4814 * offset + 54: index of I2C CRTC pair to use for CRT output
4815 * offset + 55: index of I2C CRTC pair to use for TV output
4816 * offset + 56: index of I2C CRTC pair to use for flat panel output
4817 * offset + 58: write CRTC index for I2C pair 0
4818 * offset + 59: read CRTC index for I2C pair 0
4819 * offset + 60: write CRTC index for I2C pair 1
4820 * offset + 61: read CRTC index for I2C pair 1
4821 *
4822 * offset + 67: maximum internal PLL frequency (single stage PLL)
4823 * offset + 71: minimum internal PLL frequency (single stage PLL)
4824 *
4825 * offset + 75: script table pointers, as described in
4826 * parse_script_table_pointers
4827 *
4828 * offset + 89: TMDS single link output A table pointer
4829 * offset + 91: TMDS single link output B table pointer
4830 * offset + 95: LVDS single link output A table pointer
4831 * offset + 105: flat panel timings table pointer
4832 * offset + 107: flat panel strapping translation table pointer
4833 * offset + 117: LVDS manufacturer panel config table pointer
4834 * offset + 119: LVDS manufacturer strapping translation table pointer
4835 *
4836 * offset + 142: PLL limits table pointer
4837 *
4838 * offset + 156: minimum pixel clock for LVDS dual link
4839 */
4840
4841 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4842 uint16_t bmplength;
4843 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4844
4845 /* load needed defaults in case we can't parse this info */
4846 bios->bdcb.dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4847 bios->bdcb.dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4848 bios->bdcb.dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4849 bios->bdcb.dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
4850 bios->pub.digital_min_front_porch = 0x4b;
4851 bios->fmaxvco = 256000;
4852 bios->fminvco = 128000;
4853 bios->fp.duallink_transition_clk = 90000;
4854
4855 bmp_version_major = bmp[5];
4856 bmp_version_minor = bmp[6];
4857
4858 NV_TRACE(dev, "BMP version %d.%d\n",
4859 bmp_version_major, bmp_version_minor);
4860
4861 /*
4862 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4863 * pointer on early versions
4864 */
4865 if (bmp_version_major < 5)
4866 *(uint16_t *)&bios->data[0x36] = 0;
4867
4868 /*
4869 * Seems that the minor version was 1 for all major versions prior
4870 * to 5. Version 6 could theoretically exist, but I suspect BIT
4871 * happened instead.
4872 */
4873 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4874 NV_ERROR(dev, "You have an unsupported BMP version. "
4875 "Please send in your bios\n");
4876 return -ENOSYS;
4877 }
4878
4879 if (bmp_version_major == 0)
4880 /* nothing that's currently useful in this version */
4881 return 0;
4882 else if (bmp_version_major == 1)
4883 bmplength = 44; /* exact for 1.01 */
4884 else if (bmp_version_major == 2)
4885 bmplength = 48; /* exact for 2.01 */
4886 else if (bmp_version_major == 3)
4887 bmplength = 54;
4888 /* guessed - mem init tables added in this version */
4889 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4890 /* don't know if 5.0 exists... */
4891 bmplength = 62;
4892 /* guessed - BMP I2C indices added in version 4*/
4893 else if (bmp_version_minor < 0x6)
4894 bmplength = 67; /* exact for 5.01 */
4895 else if (bmp_version_minor < 0x10)
4896 bmplength = 75; /* exact for 5.06 */
4897 else if (bmp_version_minor == 0x10)
4898 bmplength = 89; /* exact for 5.10h */
4899 else if (bmp_version_minor < 0x14)
4900 bmplength = 118; /* exact for 5.11h */
4901 else if (bmp_version_minor < 0x24)
4902 /*
4903 * Not sure of version where pll limits came in;
4904 * certainly exist by 0x24 though.
4905 */
4906 /* length not exact: this is long enough to get lvds members */
4907 bmplength = 123;
4908 else if (bmp_version_minor < 0x27)
4909 /*
4910 * Length not exact: this is long enough to get pll limit
4911 * member
4912 */
4913 bmplength = 144;
4914 else
4915 /*
4916 * Length not exact: this is long enough to get dual link
4917 * transition clock.
4918 */
4919 bmplength = 158;
4920
4921 /* checksum */
4922 if (nv_cksum(bmp, 8)) {
4923 NV_ERROR(dev, "Bad BMP checksum\n");
4924 return -EINVAL;
4925 }
4926
4927 /*
4928 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4929 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4930 * (not nv10gl), bit 5 that the flat panel tables are present, and
4931 * bit 6 a tv bios.
4932 */
4933 bios->feature_byte = bmp[9];
4934
4935 parse_bios_version(dev, bios, offset + 10);
4936
4937 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
4938 bios->old_style_init = true;
4939 legacy_scripts_offset = 18;
4940 if (bmp_version_major < 2)
4941 legacy_scripts_offset -= 4;
4942 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
4943 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
4944
4945 if (bmp_version_major > 2) { /* appears in BMP 3 */
4946 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
4947 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
4948 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
4949 }
4950
4951 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4952 if (bmplength > 61)
4953 legacy_i2c_offset = offset + 54;
4954 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4955 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4956 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
4957 bios->bdcb.dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
4958 bios->bdcb.dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
4959 bios->bdcb.dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
4960 bios->bdcb.dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
4961
4962 if (bmplength > 74) {
4963 bios->fmaxvco = ROM32(bmp[67]);
4964 bios->fminvco = ROM32(bmp[71]);
4965 }
4966 if (bmplength > 88)
4967 parse_script_table_pointers(bios, offset + 75);
4968 if (bmplength > 94) {
4969 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
4970 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
4971 /*
4972 * Never observed in use with lvds scripts, but is reused for
4973 * 18/24 bit panel interface default for EDID equipped panels
4974 * (if_is_24bit not set directly to avoid any oscillation).
4975 */
4976 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
4977 }
4978 if (bmplength > 108) {
4979 bios->fp.fptablepointer = ROM16(bmp[105]);
4980 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
4981 bios->fp.xlatwidth = 1;
4982 }
4983 if (bmplength > 120) {
4984 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
4985 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
4986 }
4987 if (bmplength > 143)
4988 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
4989
4990 if (bmplength > 157)
4991 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
4992
4993 return 0;
4994 }
4995
4996 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4997 {
4998 int i, j;
4999
5000 for (i = 0; i <= (n - len); i++) {
5001 for (j = 0; j < len; j++)
5002 if (data[i + j] != str[j])
5003 break;
5004 if (j == len)
5005 return i;
5006 }
5007
5008 return 0;
5009 }
5010
5011 static int
5012 read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
5013 {
5014 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
5015 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
5016 int recordoffset = 0, rdofs = 1, wrofs = 0;
5017 uint8_t port_type = 0;
5018
5019 if (!i2ctable)
5020 return -EINVAL;
5021
5022 if (dcb_version >= 0x30) {
5023 if (i2ctable[0] != dcb_version) /* necessary? */
5024 NV_WARN(dev,
5025 "DCB I2C table version mismatch (%02X vs %02X)\n",
5026 i2ctable[0], dcb_version);
5027 dcb_i2c_ver = i2ctable[0];
5028 headerlen = i2ctable[1];
5029 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
5030 i2c_entries = i2ctable[2];
5031 else
5032 NV_WARN(dev,
5033 "DCB I2C table has more entries than indexable "
5034 "(%d entries, max index 15)\n", i2ctable[2]);
5035 entry_len = i2ctable[3];
5036 /* [4] is i2c_default_indices, read in parse_dcb_table() */
5037 }
5038 /*
5039 * It's your own fault if you call this function on a DCB 1.1 BIOS --
5040 * the test below is for DCB 1.2
5041 */
5042 if (dcb_version < 0x14) {
5043 recordoffset = 2;
5044 rdofs = 0;
5045 wrofs = 1;
5046 }
5047
5048 if (index == 0xf)
5049 return 0;
5050 if (index > i2c_entries) {
5051 NV_ERROR(dev, "DCB I2C index too big (%d > %d)\n",
5052 index, i2ctable[2]);
5053 return -ENOENT;
5054 }
5055 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5056 NV_ERROR(dev, "DCB I2C entry invalid\n");
5057 return -EINVAL;
5058 }
5059
5060 if (dcb_i2c_ver >= 0x30) {
5061 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5062
5063 /*
5064 * Fixup for chips using same address offset for read and
5065 * write.
5066 */
5067 if (port_type == 4) /* seen on C51 */
5068 rdofs = wrofs = 1;
5069 if (port_type >= 5) /* G80+ */
5070 rdofs = wrofs = 0;
5071 }
5072
5073 if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6)
5074 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5075
5076 i2c->port_type = port_type;
5077 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5078 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5079
5080 return 0;
5081 }
5082
5083 static struct dcb_gpio_entry *
5084 new_gpio_entry(struct nvbios *bios)
5085 {
5086 struct parsed_dcb_gpio *gpio = &bios->bdcb.gpio;
5087
5088 return &gpio->entry[gpio->entries++];
5089 }
5090
5091 struct dcb_gpio_entry *
5092 nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5093 {
5094 struct drm_nouveau_private *dev_priv = dev->dev_private;
5095 struct nvbios *bios = &dev_priv->VBIOS;
5096 int i;
5097
5098 for (i = 0; i < bios->bdcb.gpio.entries; i++) {
5099 if (bios->bdcb.gpio.entry[i].tag != tag)
5100 continue;
5101
5102 return &bios->bdcb.gpio.entry[i];
5103 }
5104
5105 return NULL;
5106 }
5107
5108 static void
5109 parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5110 {
5111 struct dcb_gpio_entry *gpio;
5112 uint16_t ent = ROM16(bios->data[offset]);
5113 uint8_t line = ent & 0x1f,
5114 tag = ent >> 5 & 0x3f,
5115 flags = ent >> 11 & 0x1f;
5116
5117 if (tag == 0x3f)
5118 return;
5119
5120 gpio = new_gpio_entry(bios);
5121
5122 gpio->tag = tag;
5123 gpio->line = line;
5124 gpio->invert = flags != 4;
5125 }
5126
5127 static void
5128 parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5129 {
5130 struct dcb_gpio_entry *gpio;
5131 uint32_t ent = ROM32(bios->data[offset]);
5132 uint8_t line = ent & 0x1f,
5133 tag = ent >> 8 & 0xff;
5134
5135 if (tag == 0xff)
5136 return;
5137
5138 gpio = new_gpio_entry(bios);
5139
5140 /* Currently unused, we may need more fields parsed at some
5141 * point. */
5142 gpio->tag = tag;
5143 gpio->line = line;
5144 }
5145
5146 static void
5147 parse_dcb_gpio_table(struct nvbios *bios)
5148 {
5149 struct drm_device *dev = bios->dev;
5150 uint16_t gpio_table_ptr = bios->bdcb.gpio_table_ptr;
5151 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5152 int header_len = gpio_table[1],
5153 entries = gpio_table[2],
5154 entry_len = gpio_table[3];
5155 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5156 int i;
5157
5158 if (bios->bdcb.version >= 0x40) {
5159 if (gpio_table_ptr && entry_len != 4) {
5160 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5161 return;
5162 }
5163
5164 parse_entry = parse_dcb40_gpio_entry;
5165
5166 } else if (bios->bdcb.version >= 0x30) {
5167 if (gpio_table_ptr && entry_len != 2) {
5168 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5169 return;
5170 }
5171
5172 parse_entry = parse_dcb30_gpio_entry;
5173
5174 } else if (bios->bdcb.version >= 0x22) {
5175 /*
5176 * DCBs older than v3.0 don't really have a GPIO
5177 * table, instead they keep some GPIO info at fixed
5178 * locations.
5179 */
5180 uint16_t dcbptr = ROM16(bios->data[0x36]);
5181 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5182
5183 if (tvdac_gpio[0] & 1) {
5184 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5185
5186 gpio->tag = DCB_GPIO_TVDAC0;
5187 gpio->line = tvdac_gpio[1] >> 4;
5188 gpio->invert = tvdac_gpio[0] & 2;
5189 }
5190 }
5191
5192 if (!gpio_table_ptr)
5193 return;
5194
5195 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5196 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5197 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5198 }
5199
5200 for (i = 0; i < entries; i++)
5201 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5202 }
5203
5204 struct dcb_connector_table_entry *
5205 nouveau_bios_connector_entry(struct drm_device *dev, int index)
5206 {
5207 struct drm_nouveau_private *dev_priv = dev->dev_private;
5208 struct nvbios *bios = &dev_priv->VBIOS;
5209 struct dcb_connector_table_entry *cte;
5210
5211 if (index >= bios->bdcb.connector.entries)
5212 return NULL;
5213
5214 cte = &bios->bdcb.connector.entry[index];
5215 if (cte->type == 0xff)
5216 return NULL;
5217
5218 return cte;
5219 }
5220
5221 static void
5222 parse_dcb_connector_table(struct nvbios *bios)
5223 {
5224 struct drm_device *dev = bios->dev;
5225 struct dcb_connector_table *ct = &bios->bdcb.connector;
5226 struct dcb_connector_table_entry *cte;
5227 uint8_t *conntab = &bios->data[bios->bdcb.connector_table_ptr];
5228 uint8_t *entry;
5229 int i;
5230
5231 if (!bios->bdcb.connector_table_ptr) {
5232 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5233 return;
5234 }
5235
5236 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5237 conntab[0], conntab[1], conntab[2], conntab[3]);
5238 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5239 (conntab[3] != 2 && conntab[3] != 4)) {
5240 NV_ERROR(dev, " Unknown! Please report.\n");
5241 return;
5242 }
5243
5244 ct->entries = conntab[2];
5245
5246 entry = conntab + conntab[1];
5247 cte = &ct->entry[0];
5248 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5249 if (conntab[3] == 2)
5250 cte->entry = ROM16(entry[0]);
5251 else
5252 cte->entry = ROM32(entry[0]);
5253 cte->type = (cte->entry & 0x000000ff) >> 0;
5254 cte->index = (cte->entry & 0x00000f00) >> 8;
5255 switch (cte->entry & 0x00033000) {
5256 case 0x00001000:
5257 cte->gpio_tag = 0x07;
5258 break;
5259 case 0x00002000:
5260 cte->gpio_tag = 0x08;
5261 break;
5262 case 0x00010000:
5263 cte->gpio_tag = 0x51;
5264 break;
5265 case 0x00020000:
5266 cte->gpio_tag = 0x52;
5267 break;
5268 default:
5269 cte->gpio_tag = 0xff;
5270 break;
5271 }
5272
5273 if (cte->type == 0xff)
5274 continue;
5275
5276 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5277 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
5278 }
5279 }
5280
5281 static struct dcb_entry *new_dcb_entry(struct parsed_dcb *dcb)
5282 {
5283 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5284
5285 memset(entry, 0, sizeof(struct dcb_entry));
5286 entry->index = dcb->entries++;
5287
5288 return entry;
5289 }
5290
5291 static void fabricate_vga_output(struct parsed_dcb *dcb, int i2c, int heads)
5292 {
5293 struct dcb_entry *entry = new_dcb_entry(dcb);
5294
5295 entry->type = 0;
5296 entry->i2c_index = i2c;
5297 entry->heads = heads;
5298 entry->location = DCB_LOC_ON_CHIP;
5299 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5300 }
5301
5302 static void fabricate_dvi_i_output(struct parsed_dcb *dcb, bool twoHeads)
5303 {
5304 struct dcb_entry *entry = new_dcb_entry(dcb);
5305
5306 entry->type = 2;
5307 entry->i2c_index = LEGACY_I2C_PANEL;
5308 entry->heads = twoHeads ? 3 : 1;
5309 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5310 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5311 entry->duallink_possible = false; /* SiI164 and co. are single link */
5312
5313 #if 0
5314 /*
5315 * For dvi-a either crtc probably works, but my card appears to only
5316 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5317 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5318 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5319 * the monitor picks up the mode res ok and lights up, but no pixel
5320 * data appears, so the board manufacturer probably connected up the
5321 * sync lines, but missed the video traces / components
5322 *
5323 * with this introduction, dvi-a left as an exercise for the reader.
5324 */
5325 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5326 #endif
5327 }
5328
5329 static void fabricate_tv_output(struct parsed_dcb *dcb, bool twoHeads)
5330 {
5331 struct dcb_entry *entry = new_dcb_entry(dcb);
5332
5333 entry->type = 1;
5334 entry->i2c_index = LEGACY_I2C_TV;
5335 entry->heads = twoHeads ? 3 : 1;
5336 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5337 }
5338
5339 static bool
5340 parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5341 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5342 {
5343 entry->type = conn & 0xf;
5344 entry->i2c_index = (conn >> 4) & 0xf;
5345 entry->heads = (conn >> 8) & 0xf;
5346 if (bdcb->version >= 0x40)
5347 entry->connector = (conn >> 12) & 0xf;
5348 entry->bus = (conn >> 16) & 0xf;
5349 entry->location = (conn >> 20) & 0x3;
5350 entry->or = (conn >> 24) & 0xf;
5351 /*
5352 * Normal entries consist of a single bit, but dual link has the
5353 * next most significant bit set too
5354 */
5355 entry->duallink_possible =
5356 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5357
5358 switch (entry->type) {
5359 case OUTPUT_ANALOG:
5360 /*
5361 * Although the rest of a CRT conf dword is usually
5362 * zeros, mac biosen have stuff there so we must mask
5363 */
5364 entry->crtconf.maxfreq = (bdcb->version < 0x30) ?
5365 (conf & 0xffff) * 10 :
5366 (conf & 0xff) * 10000;
5367 break;
5368 case OUTPUT_LVDS:
5369 {
5370 uint32_t mask;
5371 if (conf & 0x1)
5372 entry->lvdsconf.use_straps_for_mode = true;
5373 if (bdcb->version < 0x22) {
5374 mask = ~0xd;
5375 /*
5376 * The laptop in bug 14567 lies and claims to not use
5377 * straps when it does, so assume all DCB 2.0 laptops
5378 * use straps, until a broken EDID using one is produced
5379 */
5380 entry->lvdsconf.use_straps_for_mode = true;
5381 /*
5382 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5383 * mean the same thing (probably wrong, but might work)
5384 */
5385 if (conf & 0x4 || conf & 0x8)
5386 entry->lvdsconf.use_power_scripts = true;
5387 } else {
5388 mask = ~0x5;
5389 if (conf & 0x4)
5390 entry->lvdsconf.use_power_scripts = true;
5391 }
5392 if (conf & mask) {
5393 /*
5394 * Until we even try to use these on G8x, it's
5395 * useless reporting unknown bits. They all are.
5396 */
5397 if (bdcb->version >= 0x40)
5398 break;
5399
5400 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5401 "please report\n");
5402 }
5403 break;
5404 }
5405 case OUTPUT_TV:
5406 {
5407 if (bdcb->version >= 0x30)
5408 entry->tvconf.has_component_output = conf & (0x8 << 4);
5409 else
5410 entry->tvconf.has_component_output = false;
5411
5412 break;
5413 }
5414 case OUTPUT_DP:
5415 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5416 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5417 switch ((conf & 0x0f000000) >> 24) {
5418 case 0xf:
5419 entry->dpconf.link_nr = 4;
5420 break;
5421 case 0x3:
5422 entry->dpconf.link_nr = 2;
5423 break;
5424 default:
5425 entry->dpconf.link_nr = 1;
5426 break;
5427 }
5428 break;
5429 case OUTPUT_TMDS:
5430 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5431 break;
5432 case 0xe:
5433 /* weird g80 mobile type that "nv" treats as a terminator */
5434 bdcb->dcb.entries--;
5435 return false;
5436 }
5437
5438 /* unsure what DCB version introduces this, 3.0? */
5439 if (conf & 0x100000)
5440 entry->i2c_upper_default = true;
5441
5442 return true;
5443 }
5444
5445 static bool
5446 parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5447 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5448 {
5449 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 &&
5450 conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 &&
5451 conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 &&
5452 conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
5453 conn != 0xf2045ff2 && conn != 0xf2045f14 && conn != 0xf207df14 &&
5454 conn != 0xf2205004 && conn != 0xf2209004) {
5455 NV_ERROR(dev, "Unknown DCB 1.5 entry, please report\n");
5456
5457 /* cause output setting to fail for !TV, so message is seen */
5458 if ((conn & 0xf) != 0x1)
5459 dcb->entries = 0;
5460
5461 return false;
5462 }
5463 /* most of the below is a "best guess" atm */
5464 entry->type = conn & 0xf;
5465 if (entry->type == 2)
5466 /* another way of specifying straps based lvds... */
5467 entry->type = OUTPUT_LVDS;
5468 if (entry->type == 4) { /* digital */
5469 if (conn & 0x10)
5470 entry->type = OUTPUT_LVDS;
5471 else
5472 entry->type = OUTPUT_TMDS;
5473 }
5474 /* what's in bits 5-13? could be some encoder maker thing, in tv case */
5475 entry->i2c_index = (conn >> 14) & 0xf;
5476 /* raw heads field is in range 0-1, so move to 1-2 */
5477 entry->heads = ((conn >> 18) & 0x7) + 1;
5478 entry->location = (conn >> 21) & 0xf;
5479 /* unused: entry->bus = (conn >> 25) & 0x7; */
5480 /* set or to be same as heads -- hopefully safe enough */
5481 entry->or = entry->heads;
5482 entry->duallink_possible = false;
5483
5484 switch (entry->type) {
5485 case OUTPUT_ANALOG:
5486 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5487 break;
5488 case OUTPUT_LVDS:
5489 /*
5490 * This is probably buried in conn's unknown bits.
5491 * This will upset EDID-ful models, if they exist
5492 */
5493 entry->lvdsconf.use_straps_for_mode = true;
5494 entry->lvdsconf.use_power_scripts = true;
5495 break;
5496 case OUTPUT_TMDS:
5497 /*
5498 * Invent a DVI-A output, by copying the fields of the DVI-D
5499 * output; reported to work by math_b on an NV20(!).
5500 */
5501 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5502 break;
5503 case OUTPUT_TV:
5504 entry->tvconf.has_component_output = false;
5505 break;
5506 }
5507
5508 return true;
5509 }
5510
5511 static bool parse_dcb_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5512 uint32_t conn, uint32_t conf)
5513 {
5514 struct dcb_entry *entry = new_dcb_entry(&bdcb->dcb);
5515 bool ret;
5516
5517 if (bdcb->version >= 0x20)
5518 ret = parse_dcb20_entry(dev, bdcb, conn, conf, entry);
5519 else
5520 ret = parse_dcb15_entry(dev, &bdcb->dcb, conn, conf, entry);
5521 if (!ret)
5522 return ret;
5523
5524 read_dcb_i2c_entry(dev, bdcb->version, bdcb->i2c_table,
5525 entry->i2c_index, &bdcb->dcb.i2c[entry->i2c_index]);
5526
5527 return true;
5528 }
5529
5530 static
5531 void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
5532 {
5533 /*
5534 * DCB v2.0 lists each output combination separately.
5535 * Here we merge compatible entries to have fewer outputs, with
5536 * more options
5537 */
5538
5539 int i, newentries = 0;
5540
5541 for (i = 0; i < dcb->entries; i++) {
5542 struct dcb_entry *ient = &dcb->entry[i];
5543 int j;
5544
5545 for (j = i + 1; j < dcb->entries; j++) {
5546 struct dcb_entry *jent = &dcb->entry[j];
5547
5548 if (jent->type == 100) /* already merged entry */
5549 continue;
5550
5551 /* merge heads field when all other fields the same */
5552 if (jent->i2c_index == ient->i2c_index &&
5553 jent->type == ient->type &&
5554 jent->location == ient->location &&
5555 jent->or == ient->or) {
5556 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5557 i, j);
5558 ient->heads |= jent->heads;
5559 jent->type = 100; /* dummy value */
5560 }
5561 }
5562 }
5563
5564 /* Compact entries merged into others out of dcb */
5565 for (i = 0; i < dcb->entries; i++) {
5566 if (dcb->entry[i].type == 100)
5567 continue;
5568
5569 if (newentries != i) {
5570 dcb->entry[newentries] = dcb->entry[i];
5571 dcb->entry[newentries].index = newentries;
5572 }
5573 newentries++;
5574 }
5575
5576 dcb->entries = newentries;
5577 }
5578
5579 static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
5580 {
5581 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5582 struct parsed_dcb *dcb;
5583 uint16_t dcbptr, i2ctabptr = 0;
5584 uint8_t *dcbtable;
5585 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5586 bool configblock = true;
5587 int recordlength = 8, confofs = 4;
5588 int i;
5589
5590 dcb = bios->pub.dcb = &bdcb->dcb;
5591 dcb->entries = 0;
5592
5593 /* get the offset from 0x36 */
5594 dcbptr = ROM16(bios->data[0x36]);
5595
5596 if (dcbptr == 0x0) {
5597 NV_WARN(dev, "No output data (DCB) found in BIOS, "
5598 "assuming a CRT output exists\n");
5599 /* this situation likely means a really old card, pre DCB */
5600 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5601
5602 if (nv04_tv_identify(dev,
5603 bios->legacy.i2c_indices.tv) >= 0)
5604 fabricate_tv_output(dcb, twoHeads);
5605
5606 return 0;
5607 }
5608
5609 dcbtable = &bios->data[dcbptr];
5610
5611 /* get DCB version */
5612 bdcb->version = dcbtable[0];
5613 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
5614 bdcb->version >> 4, bdcb->version & 0xf);
5615
5616 if (bdcb->version >= 0x20) { /* NV17+ */
5617 uint32_t sig;
5618
5619 if (bdcb->version >= 0x30) { /* NV40+ */
5620 headerlen = dcbtable[1];
5621 entries = dcbtable[2];
5622 recordlength = dcbtable[3];
5623 i2ctabptr = ROM16(dcbtable[4]);
5624 sig = ROM32(dcbtable[6]);
5625 bdcb->gpio_table_ptr = ROM16(dcbtable[10]);
5626 bdcb->connector_table_ptr = ROM16(dcbtable[20]);
5627 } else {
5628 i2ctabptr = ROM16(dcbtable[2]);
5629 sig = ROM32(dcbtable[4]);
5630 headerlen = 8;
5631 }
5632
5633 if (sig != 0x4edcbdcb) {
5634 NV_ERROR(dev, "Bad Display Configuration Block "
5635 "signature (%08X)\n", sig);
5636 return -EINVAL;
5637 }
5638 } else if (bdcb->version >= 0x15) { /* some NV11 and NV20 */
5639 char sig[8] = { 0 };
5640
5641 strncpy(sig, (char *)&dcbtable[-7], 7);
5642 i2ctabptr = ROM16(dcbtable[2]);
5643 recordlength = 10;
5644 confofs = 6;
5645
5646 if (strcmp(sig, "DEV_REC")) {
5647 NV_ERROR(dev, "Bad Display Configuration Block "
5648 "signature (%s)\n", sig);
5649 return -EINVAL;
5650 }
5651 } else {
5652 /*
5653 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5654 * has the same single (crt) entry, even when tv-out present, so
5655 * the conclusion is this version cannot really be used.
5656 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5657 * 5 entries, which are not specific to the card and so no use.
5658 * v1.2 does have an I2C table that read_dcb_i2c_table can
5659 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5660 * pointer, so use the indices parsed in parse_bmp_structure.
5661 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5662 */
5663 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5664 "adding all possible outputs\n");
5665 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5666
5667 /*
5668 * Attempt to detect TV before DVI because the test
5669 * for the former is more accurate and it rules the
5670 * latter out.
5671 */
5672 if (nv04_tv_identify(dev,
5673 bios->legacy.i2c_indices.tv) >= 0)
5674 fabricate_tv_output(dcb, twoHeads);
5675
5676 else if (bios->tmds.output0_script_ptr ||
5677 bios->tmds.output1_script_ptr)
5678 fabricate_dvi_i_output(dcb, twoHeads);
5679
5680 return 0;
5681 }
5682
5683 if (!i2ctabptr)
5684 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5685 else {
5686 bdcb->i2c_table = &bios->data[i2ctabptr];
5687 if (bdcb->version >= 0x30)
5688 bdcb->i2c_default_indices = bdcb->i2c_table[4];
5689 }
5690
5691 parse_dcb_gpio_table(bios);
5692 parse_dcb_connector_table(bios);
5693
5694 if (entries > DCB_MAX_NUM_ENTRIES)
5695 entries = DCB_MAX_NUM_ENTRIES;
5696
5697 for (i = 0; i < entries; i++) {
5698 uint32_t connection, config = 0;
5699
5700 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5701 if (configblock)
5702 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5703
5704 /* seen on an NV11 with DCB v1.5 */
5705 if (connection == 0x00000000)
5706 break;
5707
5708 /* seen on an NV17 with DCB v2.0 */
5709 if (connection == 0xffffffff)
5710 break;
5711
5712 if ((connection & 0x0000000f) == 0x0000000f)
5713 continue;
5714
5715 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5716 dcb->entries, connection, config);
5717
5718 if (!parse_dcb_entry(dev, bdcb, connection, config))
5719 break;
5720 }
5721
5722 /*
5723 * apart for v2.1+ not being known for requiring merging, this
5724 * guarantees dcbent->index is the index of the entry in the rom image
5725 */
5726 if (bdcb->version < 0x21)
5727 merge_like_dcb_entries(dev, dcb);
5728
5729 return dcb->entries ? 0 : -ENXIO;
5730 }
5731
5732 static void
5733 fixup_legacy_connector(struct nvbios *bios)
5734 {
5735 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5736 struct parsed_dcb *dcb = &bdcb->dcb;
5737 int high = 0, i;
5738
5739 /*
5740 * DCB 3.0 also has the table in most cases, but there are some cards
5741 * where the table is filled with stub entries, and the DCB entriy
5742 * indices are all 0. We don't need the connector indices on pre-G80
5743 * chips (yet?) so limit the use to DCB 4.0 and above.
5744 */
5745 if (bdcb->version >= 0x40)
5746 return;
5747
5748 /*
5749 * No known connector info before v3.0, so make it up. the rule here
5750 * is: anything on the same i2c bus is considered to be on the same
5751 * connector. any output without an associated i2c bus is assigned
5752 * its own unique connector index.
5753 */
5754 for (i = 0; i < dcb->entries; i++) {
5755 if (dcb->entry[i].i2c_index == 0xf)
5756 continue;
5757
5758 /*
5759 * Ignore the I2C index for on-chip TV-out, as there
5760 * are cards with bogus values (nv31m in bug 23212),
5761 * and it's otherwise useless.
5762 */
5763 if (dcb->entry[i].type == OUTPUT_TV &&
5764 dcb->entry[i].location == DCB_LOC_ON_CHIP) {
5765 dcb->entry[i].i2c_index = 0xf;
5766 continue;
5767 }
5768
5769 dcb->entry[i].connector = dcb->entry[i].i2c_index;
5770 if (dcb->entry[i].connector > high)
5771 high = dcb->entry[i].connector;
5772 }
5773
5774 for (i = 0; i < dcb->entries; i++) {
5775 if (dcb->entry[i].i2c_index != 0xf)
5776 continue;
5777
5778 dcb->entry[i].connector = ++high;
5779 }
5780 }
5781
5782 static void
5783 fixup_legacy_i2c(struct nvbios *bios)
5784 {
5785 struct parsed_dcb *dcb = &bios->bdcb.dcb;
5786 int i;
5787
5788 for (i = 0; i < dcb->entries; i++) {
5789 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5790 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5791 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5792 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5793 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5794 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5795 }
5796 }
5797
5798 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5799 {
5800 /*
5801 * The header following the "HWSQ" signature has the number of entries,
5802 * and the entry size
5803 *
5804 * An entry consists of a dword to write to the sequencer control reg
5805 * (0x00001304), followed by the ucode bytes, written sequentially,
5806 * starting at reg 0x00001400
5807 */
5808
5809 uint8_t bytes_to_write;
5810 uint16_t hwsq_entry_offset;
5811 int i;
5812
5813 if (bios->data[hwsq_offset] <= entry) {
5814 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5815 "requested entry\n");
5816 return -ENOENT;
5817 }
5818
5819 bytes_to_write = bios->data[hwsq_offset + 1];
5820
5821 if (bytes_to_write != 36) {
5822 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5823 return -EINVAL;
5824 }
5825
5826 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5827
5828 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5829
5830 /* set sequencer control */
5831 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5832 bytes_to_write -= 4;
5833
5834 /* write ucode */
5835 for (i = 0; i < bytes_to_write; i += 4)
5836 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5837
5838 /* twiddle NV_PBUS_DEBUG_4 */
5839 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
5840
5841 return 0;
5842 }
5843
5844 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
5845 struct nvbios *bios)
5846 {
5847 /*
5848 * BMP based cards, from NV17, need a microcode loading to correctly
5849 * control the GPIO etc for LVDS panels
5850 *
5851 * BIT based cards seem to do this directly in the init scripts
5852 *
5853 * The microcode entries are found by the "HWSQ" signature.
5854 */
5855
5856 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
5857 const int sz = sizeof(hwsq_signature);
5858 int hwsq_offset;
5859
5860 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
5861 if (!hwsq_offset)
5862 return 0;
5863
5864 /* always use entry 0? */
5865 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
5866 }
5867
5868 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5869 {
5870 struct drm_nouveau_private *dev_priv = dev->dev_private;
5871 struct nvbios *bios = &dev_priv->VBIOS;
5872 const uint8_t edid_sig[] = {
5873 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5874 uint16_t offset = 0;
5875 uint16_t newoffset;
5876 int searchlen = NV_PROM_SIZE;
5877
5878 if (bios->fp.edid)
5879 return bios->fp.edid;
5880
5881 while (searchlen) {
5882 newoffset = findstr(&bios->data[offset], searchlen,
5883 edid_sig, 8);
5884 if (!newoffset)
5885 return NULL;
5886 offset += newoffset;
5887 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
5888 break;
5889
5890 searchlen -= offset;
5891 offset++;
5892 }
5893
5894 NV_TRACE(dev, "Found EDID in BIOS\n");
5895
5896 return bios->fp.edid = &bios->data[offset];
5897 }
5898
5899 void
5900 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5901 struct dcb_entry *dcbent)
5902 {
5903 struct drm_nouveau_private *dev_priv = dev->dev_private;
5904 struct nvbios *bios = &dev_priv->VBIOS;
5905 struct init_exec iexec = { true, false };
5906
5907 bios->display.output = dcbent;
5908 parse_init_table(bios, table, &iexec);
5909 bios->display.output = NULL;
5910 }
5911
5912 static bool NVInitVBIOS(struct drm_device *dev)
5913 {
5914 struct drm_nouveau_private *dev_priv = dev->dev_private;
5915 struct nvbios *bios = &dev_priv->VBIOS;
5916
5917 memset(bios, 0, sizeof(struct nvbios));
5918 bios->dev = dev;
5919
5920 if (!NVShadowVBIOS(dev, bios->data))
5921 return false;
5922
5923 bios->length = NV_PROM_SIZE;
5924 return true;
5925 }
5926
5927 static int nouveau_parse_vbios_struct(struct drm_device *dev)
5928 {
5929 struct drm_nouveau_private *dev_priv = dev->dev_private;
5930 struct nvbios *bios = &dev_priv->VBIOS;
5931 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5932 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5933 int offset;
5934
5935 offset = findstr(bios->data, bios->length,
5936 bit_signature, sizeof(bit_signature));
5937 if (offset) {
5938 NV_TRACE(dev, "BIT BIOS found\n");
5939 return parse_bit_structure(bios, offset + 6);
5940 }
5941
5942 offset = findstr(bios->data, bios->length,
5943 bmp_signature, sizeof(bmp_signature));
5944 if (offset) {
5945 NV_TRACE(dev, "BMP BIOS found\n");
5946 return parse_bmp_structure(dev, bios, offset);
5947 }
5948
5949 NV_ERROR(dev, "No known BIOS signature found\n");
5950 return -ENODEV;
5951 }
5952
5953 int
5954 nouveau_run_vbios_init(struct drm_device *dev)
5955 {
5956 struct drm_nouveau_private *dev_priv = dev->dev_private;
5957 struct nvbios *bios = &dev_priv->VBIOS;
5958 int i, ret = 0;
5959
5960 NVLockVgaCrtcs(dev, false);
5961 if (nv_two_heads(dev))
5962 NVSetOwner(dev, bios->state.crtchead);
5963
5964 if (bios->major_version < 5) /* BMP only */
5965 load_nv17_hw_sequencer_ucode(dev, bios);
5966
5967 if (bios->execute) {
5968 bios->fp.last_script_invoc = 0;
5969 bios->fp.lvds_init_run = false;
5970 }
5971
5972 parse_init_tables(bios);
5973
5974 /*
5975 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5976 * parser will run this right after the init tables, the binary
5977 * driver appears to run it at some point later.
5978 */
5979 if (bios->some_script_ptr) {
5980 struct init_exec iexec = {true, false};
5981
5982 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
5983 bios->some_script_ptr);
5984 parse_init_table(bios, bios->some_script_ptr, &iexec);
5985 }
5986
5987 if (dev_priv->card_type >= NV_50) {
5988 for (i = 0; i < bios->bdcb.dcb.entries; i++) {
5989 nouveau_bios_run_display_table(dev,
5990 &bios->bdcb.dcb.entry[i],
5991 0, 0);
5992 }
5993 }
5994
5995 NVLockVgaCrtcs(dev, true);
5996
5997 return ret;
5998 }
5999
6000 static void
6001 nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6002 {
6003 struct drm_nouveau_private *dev_priv = dev->dev_private;
6004 struct nvbios *bios = &dev_priv->VBIOS;
6005 struct dcb_i2c_entry *entry;
6006 int i;
6007
6008 entry = &bios->bdcb.dcb.i2c[0];
6009 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6010 nouveau_i2c_fini(dev, entry);
6011 }
6012
6013 int
6014 nouveau_bios_init(struct drm_device *dev)
6015 {
6016 struct drm_nouveau_private *dev_priv = dev->dev_private;
6017 struct nvbios *bios = &dev_priv->VBIOS;
6018 uint32_t saved_nv_pextdev_boot_0;
6019 bool was_locked;
6020 int ret;
6021
6022 dev_priv->vbios = &bios->pub;
6023
6024 if (!NVInitVBIOS(dev))
6025 return -ENODEV;
6026
6027 ret = nouveau_parse_vbios_struct(dev);
6028 if (ret)
6029 return ret;
6030
6031 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6032 if (ret)
6033 return ret;
6034
6035 fixup_legacy_i2c(bios);
6036 fixup_legacy_connector(bios);
6037
6038 if (!bios->major_version) /* we don't run version 0 bios */
6039 return 0;
6040
6041 /* these will need remembering across a suspend */
6042 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6043 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6044
6045 /* init script execution disabled */
6046 bios->execute = false;
6047
6048 /* ... unless card isn't POSTed already */
6049 if (dev_priv->card_type >= NV_10 &&
6050 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6051 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6052 NV_INFO(dev, "Adaptor not initialised\n");
6053 if (dev_priv->card_type < NV_50) {
6054 NV_ERROR(dev, "Unable to POST this chipset\n");
6055 return -ENODEV;
6056 }
6057
6058 NV_INFO(dev, "Running VBIOS init tables\n");
6059 bios->execute = true;
6060 }
6061
6062 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6063
6064 ret = nouveau_run_vbios_init(dev);
6065 if (ret) {
6066 dev_priv->vbios = NULL;
6067 return ret;
6068 }
6069
6070 /* feature_byte on BMP is poor, but init always sets CR4B */
6071 was_locked = NVLockVgaCrtcs(dev, false);
6072 if (bios->major_version < 5)
6073 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6074
6075 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6076 if (bios->is_mobile || bios->major_version >= 5)
6077 ret = parse_fp_mode_table(dev, bios);
6078 NVLockVgaCrtcs(dev, was_locked);
6079
6080 /* allow subsequent scripts to execute */
6081 bios->execute = true;
6082
6083 return 0;
6084 }
6085
6086 void
6087 nouveau_bios_takedown(struct drm_device *dev)
6088 {
6089 nouveau_bios_i2c_devices_takedown(dev);
6090 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree