3 * Support for a cx23417 mpeg encoder via cx231xx host port.
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <linux/firmware.h>
34 #include <linux/smp_lock.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/cx2341x.h>
38 #include <linux/usb.h>
41 /*#include "cx23885-ioctl.h"*/
43 #define CX231xx_FIRM_IMAGE_SIZE 376836
44 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
47 #define ITVC_WRITE_DIR 0x03FDFC00
48 #define ITVC_READ_DIR 0x0001FC00
50 #define MCI_MEMORY_DATA_BYTE0 0x00
51 #define MCI_MEMORY_DATA_BYTE1 0x08
52 #define MCI_MEMORY_DATA_BYTE2 0x10
53 #define MCI_MEMORY_DATA_BYTE3 0x18
55 #define MCI_MEMORY_ADDRESS_BYTE2 0x20
56 #define MCI_MEMORY_ADDRESS_BYTE1 0x28
57 #define MCI_MEMORY_ADDRESS_BYTE0 0x30
59 #define MCI_REGISTER_DATA_BYTE0 0x40
60 #define MCI_REGISTER_DATA_BYTE1 0x48
61 #define MCI_REGISTER_DATA_BYTE2 0x50
62 #define MCI_REGISTER_DATA_BYTE3 0x58
64 #define MCI_REGISTER_ADDRESS_BYTE0 0x60
65 #define MCI_REGISTER_ADDRESS_BYTE1 0x68
67 #define MCI_REGISTER_MODE 0x70
69 /*Read and write modes
71 #define MCI_MODE_REGISTER_READ 0x000
72 #define MCI_MODE_REGISTER_WRITE 0x100
73 #define MCI_MODE_MEMORY_READ 0x000
74 #define MCI_MODE_MEMORY_WRITE 0x4000
76 static unsigned int mpegbufs
= 8;
77 module_param(mpegbufs
, int, 0644);
78 MODULE_PARM_DESC(mpegbufs
, "number of mpeg buffers, range 2-32");
79 static unsigned int mpeglines
= 128;
80 module_param(mpeglines
, int, 0644);
81 MODULE_PARM_DESC(mpeglines
, "number of lines in an MPEG buffer, range 2-32");
82 static unsigned int mpeglinesize
= 512;
83 module_param(mpeglinesize
, int, 0644);
84 MODULE_PARM_DESC(mpeglinesize
,
85 "number of bytes in each line of an MPEG buffer, range 512-1024");
87 static unsigned int v4l_debug
= 1;
88 module_param(v4l_debug
, int, 0644);
89 MODULE_PARM_DESC(v4l_debug
, "enable V4L debug messages");
90 struct cx231xx_dmaqueue
*dma_qq
;
91 #define dprintk(level, fmt, arg...)\
92 do { if (v4l_debug >= level) \
93 printk(KERN_INFO "%s: " fmt, \
94 (dev) ? dev->name : "cx231xx[?]", ## arg); \
97 static struct cx231xx_tvnorm cx231xx_tvnorms
[] = {
100 .id
= V4L2_STD_NTSC_M
,
103 .id
= V4L2_STD_NTSC_M_JP
,
106 .id
= V4L2_STD_PAL_BG
,
109 .id
= V4L2_STD_PAL_DK
,
112 .id
= V4L2_STD_PAL_I
,
115 .id
= V4L2_STD_PAL_M
,
118 .id
= V4L2_STD_PAL_N
,
121 .id
= V4L2_STD_PAL_Nc
,
124 .id
= V4L2_STD_PAL_60
,
127 .id
= V4L2_STD_SECAM_L
,
130 .id
= V4L2_STD_SECAM_DK
,
134 /* ------------------------------------------------------------------ */
135 enum cx231xx_capture_type
{
136 CX231xx_MPEG_CAPTURE
,
138 CX231xx_RAW_PASSTHRU_CAPTURE
140 enum cx231xx_capture_bits
{
141 CX231xx_RAW_BITS_NONE
= 0x00,
142 CX231xx_RAW_BITS_YUV_CAPTURE
= 0x01,
143 CX231xx_RAW_BITS_PCM_CAPTURE
= 0x02,
144 CX231xx_RAW_BITS_VBI_CAPTURE
= 0x04,
145 CX231xx_RAW_BITS_PASSTHRU_CAPTURE
= 0x08,
146 CX231xx_RAW_BITS_TO_HOST_CAPTURE
= 0x10
148 enum cx231xx_capture_end
{
149 CX231xx_END_AT_GOP
, /* stop at the end of gop, generate irq */
150 CX231xx_END_NOW
, /* stop immediately, no irq */
152 enum cx231xx_framerate
{
153 CX231xx_FRAMERATE_NTSC_30
, /* NTSC: 30fps */
154 CX231xx_FRAMERATE_PAL_25
/* PAL: 25fps */
156 enum cx231xx_stream_port
{
157 CX231xx_OUTPUT_PORT_MEMORY
,
158 CX231xx_OUTPUT_PORT_STREAMING
,
159 CX231xx_OUTPUT_PORT_SERIAL
161 enum cx231xx_data_xfer_status
{
162 CX231xx_MORE_BUFFERS_FOLLOW
,
165 enum cx231xx_picture_mask
{
166 CX231xx_PICTURE_MASK_NONE
,
167 CX231xx_PICTURE_MASK_I_FRAMES
,
168 CX231xx_PICTURE_MASK_I_P_FRAMES
= 0x3,
169 CX231xx_PICTURE_MASK_ALL_FRAMES
= 0x7,
171 enum cx231xx_vbi_mode_bits
{
172 CX231xx_VBI_BITS_SLICED
,
173 CX231xx_VBI_BITS_RAW
,
175 enum cx231xx_vbi_insertion_bits
{
176 CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA
,
177 CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS
= 0x1 << 1,
178 CX231xx_VBI_BITS_SEPARATE_STREAM
= 0x2 << 1,
179 CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA
= 0x4 << 1,
180 CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA
= 0x5 << 1,
182 enum cx231xx_dma_unit
{
186 enum cx231xx_dma_transfer_status_bits
{
187 CX231xx_DMA_TRANSFER_BITS_DONE
= 0x01,
188 CX231xx_DMA_TRANSFER_BITS_ERROR
= 0x04,
189 CX231xx_DMA_TRANSFER_BITS_LL_ERROR
= 0x10,
192 CX231xx_PAUSE_ENCODING
,
193 CX231xx_RESUME_ENCODING
,
195 enum cx231xx_copyright
{
196 CX231xx_COPYRIGHT_OFF
,
197 CX231xx_COPYRIGHT_ON
,
199 enum cx231xx_notification_type
{
200 CX231xx_NOTIFICATION_REFRESH
,
202 enum cx231xx_notification_status
{
203 CX231xx_NOTIFICATION_OFF
,
204 CX231xx_NOTIFICATION_ON
,
206 enum cx231xx_notification_mailbox
{
207 CX231xx_NOTIFICATION_NO_MAILBOX
= -1,
209 enum cx231xx_field1_lines
{
210 CX231xx_FIELD1_SAA7114
= 0x00EF, /* 239 */
211 CX231xx_FIELD1_SAA7115
= 0x00F0, /* 240 */
212 CX231xx_FIELD1_MICRONAS
= 0x0105, /* 261 */
214 enum cx231xx_field2_lines
{
215 CX231xx_FIELD2_SAA7114
= 0x00EF, /* 239 */
216 CX231xx_FIELD2_SAA7115
= 0x00F0, /* 240 */
217 CX231xx_FIELD2_MICRONAS
= 0x0106, /* 262 */
219 enum cx231xx_custom_data_type
{
220 CX231xx_CUSTOM_EXTENSION_USR_DATA
,
221 CX231xx_CUSTOM_PRIVATE_PACKET
,
227 enum cx231xx_mute_video_mask
{
228 CX231xx_MUTE_VIDEO_V_MASK
= 0x0000FF00,
229 CX231xx_MUTE_VIDEO_U_MASK
= 0x00FF0000,
230 CX231xx_MUTE_VIDEO_Y_MASK
= 0xFF000000,
232 enum cx231xx_mute_video_shift
{
233 CX231xx_MUTE_VIDEO_V_SHIFT
= 8,
234 CX231xx_MUTE_VIDEO_U_SHIFT
= 16,
235 CX231xx_MUTE_VIDEO_Y_SHIFT
= 24,
238 /* defines below are from ivtv-driver.h */
239 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
241 /* Firmware API commands */
242 #define IVTV_API_STD_TIMEOUT 500
245 /* IVTV_REG_OFFSET */
246 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
247 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
248 #define IVTV_REG_SPU (0x9050)
249 #define IVTV_REG_HW_BLOCKS (0x9054)
250 #define IVTV_REG_VPU (0x9058)
251 #define IVTV_REG_APU (0xA064)
253 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
258 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
259 +-------+-------+-------+-------+-------+-------+-------+-------+
260 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
261 +-------+-------+-------+-------+-------+-------+-------+-------+
262 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
263 +-------+-------+-------+-------+-------+-------+-------+-------+
264 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
265 +-------+-------+-------+-------+-------+-------+-------+-------+
267 #define MC417_MIWR 0x8000
268 #define MC417_MIRD 0x4000
269 #define MC417_MICS 0x2000
270 #define MC417_MIRDY 0x1000
271 #define MC417_MIADDR 0x0F00
272 #define MC417_MIDATA 0x00FF
275 /*** Bit definitions for MC417_CTL register ****
276 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
277 +--------+-------------+--------+--------------+------------+
278 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
279 +--------+-------------+--------+--------------+------------+
281 #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
282 #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
283 #define MC417_UART_GPIO_EN 0x00000001
285 /* Values for speed control */
286 #define MC417_SPD_CTL_SLOW 0x1
287 #define MC417_SPD_CTL_MEDIUM 0x0
288 #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
290 /* Values for GPIO select */
291 #define MC417_GPIO_SEL_GPIO3 0x3
292 #define MC417_GPIO_SEL_GPIO2 0x2
293 #define MC417_GPIO_SEL_GPIO1 0x1
294 #define MC417_GPIO_SEL_GPIO0 0x0
297 #define CX23417_GPIO_MASK 0xFC0003FF
298 int setITVCReg(struct cx231xx
*dev
, u32 gpio_direction
, u32 value
)
301 u32 _gpio_direction
= 0;
303 _gpio_direction
= _gpio_direction
& CX23417_GPIO_MASK
;
304 _gpio_direction
= _gpio_direction
|gpio_direction
;
305 status
= cx231xx_send_gpio_cmd(dev
, _gpio_direction
,
306 (u8
*)&value
, 4, 0, 0);
309 int getITVCReg(struct cx231xx
*dev
, u32 gpio_direction
, u32
*pValue
)
312 u32 _gpio_direction
= 0;
314 _gpio_direction
= _gpio_direction
& CX23417_GPIO_MASK
;
315 _gpio_direction
= _gpio_direction
|gpio_direction
;
317 status
= cx231xx_send_gpio_cmd(dev
, _gpio_direction
,
318 (u8
*)pValue
, 4, 0, 1);
321 int waitForMciComplete(struct cx231xx
*dev
)
324 u32 gpio_driection
= 0;
326 getITVCReg(dev
, gpio_driection
, &gpio
);
328 while (!(gpio
&0x020000)) {
331 getITVCReg(dev
, gpio_driection
, &gpio
);
334 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio
);
340 int mc417_register_write(struct cx231xx
*dev
, u16 address
, u32 value
)
345 temp
= 0x82|MCI_REGISTER_DATA_BYTE0
|((value
&0x000000FF)<<8);
347 status
= setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
350 temp
= temp
|((0x05)<<10);
351 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
353 /*write data byte 1;*/
354 temp
= 0x82|MCI_REGISTER_DATA_BYTE1
|(value
&0x0000FF00);
356 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
357 temp
= temp
|((0x05)<<10);
358 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
360 /*write data byte 2;*/
361 temp
= 0x82|MCI_REGISTER_DATA_BYTE2
|((value
&0x00FF0000)>>8);
363 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
364 temp
= temp
|((0x05)<<10);
365 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
367 /*write data byte 3;*/
368 temp
= 0x82|MCI_REGISTER_DATA_BYTE3
|((value
&0xFF000000)>>16);
370 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
371 temp
= temp
|((0x05)<<10);
372 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
374 /*write address byte 0;*/
375 temp
= 0x82|MCI_REGISTER_ADDRESS_BYTE0
|((address
&0x000000FF)<<8);
377 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
378 temp
= temp
|((0x05)<<10);
379 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
381 /*write address byte 1;*/
382 temp
= 0x82|MCI_REGISTER_ADDRESS_BYTE1
|(address
&0x0000FF00);
384 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
385 temp
= temp
|((0x05)<<10);
386 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
388 /*Write that the mode is write.*/
389 temp
= 0x82 | MCI_REGISTER_MODE
| MCI_MODE_REGISTER_WRITE
;
391 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
392 temp
= temp
|((0x05)<<10);
393 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
395 return waitForMciComplete(dev
);
400 int mc417_register_read(struct cx231xx
*dev
, u16 address
, u32
*value
)
402 /*write address byte 0;*/
404 u32 return_value
= 0;
407 temp
= 0x82|MCI_REGISTER_ADDRESS_BYTE0
|((address
&0x00FF)<<8);
409 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
410 temp
= temp
|((0x05)<<10);
411 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
413 /*write address byte 1;*/
414 temp
= 0x82|MCI_REGISTER_ADDRESS_BYTE1
|(address
&0xFF00);
416 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
417 temp
= temp
|((0x05)<<10);
418 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
420 /*write that the mode is read;*/
421 temp
= 0x82 | MCI_REGISTER_MODE
| MCI_MODE_REGISTER_READ
;
423 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
424 temp
= temp
|((0x05)<<10);
425 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
427 /*wait for the MIRDY line to be asserted ,
428 signalling that the read is done;*/
429 ret
= waitForMciComplete(dev
);
432 /*switch the DATA- GPIO to input mode;*/
434 /*Read data byte 0;*/
435 temp
= (0x82|MCI_REGISTER_DATA_BYTE0
)<<10;
436 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
437 temp
= ((0x81|MCI_REGISTER_DATA_BYTE0
)<<10);
438 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
439 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
440 return_value
|= ((temp
&0x03FC0000)>>18);
441 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
443 /* Read data byte 1;*/
444 temp
= (0x82|MCI_REGISTER_DATA_BYTE1
)<<10;
445 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
446 temp
= ((0x81|MCI_REGISTER_DATA_BYTE1
)<<10);
447 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
448 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
450 return_value
|= ((temp
&0x03FC0000)>>10);
451 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
453 /*Read data byte 2;*/
454 temp
= (0x82|MCI_REGISTER_DATA_BYTE2
)<<10;
455 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
456 temp
= ((0x81|MCI_REGISTER_DATA_BYTE2
)<<10);
457 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
458 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
459 return_value
|= ((temp
&0x03FC0000)>>2);
460 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
462 /*Read data byte 3;*/
463 temp
= (0x82|MCI_REGISTER_DATA_BYTE3
)<<10;
464 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
465 temp
= ((0x81|MCI_REGISTER_DATA_BYTE3
)<<10);
466 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
467 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
468 return_value
|= ((temp
&0x03FC0000)<<6);
469 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
471 *value
= return_value
;
477 int mc417_memory_write(struct cx231xx
*dev
, u32 address
, u32 value
)
480 /*write data byte 0;*/
485 temp
= 0x82|MCI_MEMORY_DATA_BYTE0
|((value
&0x000000FF)<<8);
487 ret
= setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
490 temp
= temp
|((0x05)<<10);
491 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
493 /*write data byte 1;*/
494 temp
= 0x82|MCI_MEMORY_DATA_BYTE1
|(value
&0x0000FF00);
496 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
497 temp
= temp
|((0x05)<<10);
498 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
500 /*write data byte 2;*/
501 temp
= 0x82|MCI_MEMORY_DATA_BYTE2
|((value
&0x00FF0000)>>8);
503 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
504 temp
= temp
|((0x05)<<10);
505 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
507 /*write data byte 3;*/
508 temp
= 0x82|MCI_MEMORY_DATA_BYTE3
|((value
&0xFF000000)>>16);
510 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
511 temp
= temp
|((0x05)<<10);
512 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
514 /* write address byte 2;*/
515 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE2
| MCI_MODE_MEMORY_WRITE
|
516 ((address
& 0x003F0000)>>8);
518 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
519 temp
= temp
|((0x05)<<10);
520 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
522 /* write address byte 1;*/
523 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE1
| (address
& 0xFF00);
525 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
526 temp
= temp
|((0x05)<<10);
527 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
529 /* write address byte 0;*/
530 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE0
|((address
& 0x00FF)<<8);
532 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
533 temp
= temp
|((0x05)<<10);
534 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
536 /*wait for MIRDY line;*/
537 waitForMciComplete(dev
);
543 int mc417_memory_read(struct cx231xx
*dev
, u32 address
, u32
*value
)
547 u32 return_value
= 0;
550 /*write address byte 2;*/
551 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE2
| MCI_MODE_MEMORY_READ
|
552 ((address
& 0x003F0000)>>8);
554 ret
= setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
557 temp
= temp
|((0x05)<<10);
558 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
560 /*write address byte 1*/
561 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE1
| (address
& 0xFF00);
563 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
564 temp
= temp
|((0x05)<<10);
565 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
567 /*write address byte 0*/
568 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE0
| ((address
& 0x00FF)<<8);
570 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
571 temp
= temp
|((0x05)<<10);
572 setITVCReg(dev
, ITVC_WRITE_DIR
, temp
);
574 /*Wait for MIRDY line*/
575 ret
= waitForMciComplete(dev
);
578 /*Read data byte 3;*/
579 temp
= (0x82|MCI_MEMORY_DATA_BYTE3
)<<10;
580 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
581 temp
= ((0x81|MCI_MEMORY_DATA_BYTE3
)<<10);
582 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
583 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
584 return_value
|= ((temp
&0x03FC0000)<<6);
585 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
587 /*Read data byte 2;*/
588 temp
= (0x82|MCI_MEMORY_DATA_BYTE2
)<<10;
589 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
590 temp
= ((0x81|MCI_MEMORY_DATA_BYTE2
)<<10);
591 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
592 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
593 return_value
|= ((temp
&0x03FC0000)>>2);
594 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
596 /* Read data byte 1;*/
597 temp
= (0x82|MCI_MEMORY_DATA_BYTE1
)<<10;
598 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
599 temp
= ((0x81|MCI_MEMORY_DATA_BYTE1
)<<10);
600 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
601 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
602 return_value
|= ((temp
&0x03FC0000)>>10);
603 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
605 /*Read data byte 0;*/
606 temp
= (0x82|MCI_MEMORY_DATA_BYTE0
)<<10;
607 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
608 temp
= ((0x81|MCI_MEMORY_DATA_BYTE0
)<<10);
609 setITVCReg(dev
, ITVC_READ_DIR
, temp
);
610 getITVCReg(dev
, ITVC_READ_DIR
, &temp
);
611 return_value
|= ((temp
&0x03FC0000)>>18);
612 setITVCReg(dev
, ITVC_READ_DIR
, (0x87<<10));
614 *value
= return_value
;
618 void mc417_gpio_set(struct cx231xx
*dev
, u32 mask
)
622 /* Set the gpio value */
623 mc417_register_read(dev
, 0x900C, &val
);
624 val
|= (mask
& 0x000ffff);
625 mc417_register_write(dev
, 0x900C, val
);
628 void mc417_gpio_clear(struct cx231xx
*dev
, u32 mask
)
632 /* Clear the gpio value */
633 mc417_register_read(dev
, 0x900C, &val
);
634 val
&= ~(mask
& 0x0000ffff);
635 mc417_register_write(dev
, 0x900C, val
);
638 void mc417_gpio_enable(struct cx231xx
*dev
, u32 mask
, int asoutput
)
642 /* Enable GPIO direction bits */
643 mc417_register_read(dev
, 0x9020, &val
);
645 val
|= (mask
& 0x0000ffff);
647 val
&= ~(mask
& 0x0000ffff);
649 mc417_register_write(dev
, 0x9020, val
);
651 /* ------------------------------------------------------------------ */
653 /* MPEG encoder API */
654 static char *cmd_to_str(int cmd
)
657 case CX2341X_ENC_PING_FW
:
659 case CX2341X_ENC_START_CAPTURE
:
660 return "START_CAPTURE";
661 case CX2341X_ENC_STOP_CAPTURE
:
662 return "STOP_CAPTURE";
663 case CX2341X_ENC_SET_AUDIO_ID
:
664 return "SET_AUDIO_ID";
665 case CX2341X_ENC_SET_VIDEO_ID
:
666 return "SET_VIDEO_ID";
667 case CX2341X_ENC_SET_PCR_ID
:
668 return "SET_PCR_PID";
669 case CX2341X_ENC_SET_FRAME_RATE
:
670 return "SET_FRAME_RATE";
671 case CX2341X_ENC_SET_FRAME_SIZE
:
672 return "SET_FRAME_SIZE";
673 case CX2341X_ENC_SET_BIT_RATE
:
674 return "SET_BIT_RATE";
675 case CX2341X_ENC_SET_GOP_PROPERTIES
:
676 return "SET_GOP_PROPERTIES";
677 case CX2341X_ENC_SET_ASPECT_RATIO
:
678 return "SET_ASPECT_RATIO";
679 case CX2341X_ENC_SET_DNR_FILTER_MODE
:
680 return "SET_DNR_FILTER_PROPS";
681 case CX2341X_ENC_SET_DNR_FILTER_PROPS
:
682 return "SET_DNR_FILTER_PROPS";
683 case CX2341X_ENC_SET_CORING_LEVELS
:
684 return "SET_CORING_LEVELS";
685 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE
:
686 return "SET_SPATIAL_FILTER_TYPE";
687 case CX2341X_ENC_SET_VBI_LINE
:
688 return "SET_VBI_LINE";
689 case CX2341X_ENC_SET_STREAM_TYPE
:
690 return "SET_STREAM_TYPE";
691 case CX2341X_ENC_SET_OUTPUT_PORT
:
692 return "SET_OUTPUT_PORT";
693 case CX2341X_ENC_SET_AUDIO_PROPERTIES
:
694 return "SET_AUDIO_PROPERTIES";
695 case CX2341X_ENC_HALT_FW
:
697 case CX2341X_ENC_GET_VERSION
:
698 return "GET_VERSION";
699 case CX2341X_ENC_SET_GOP_CLOSURE
:
700 return "SET_GOP_CLOSURE";
701 case CX2341X_ENC_GET_SEQ_END
:
702 return "GET_SEQ_END";
703 case CX2341X_ENC_SET_PGM_INDEX_INFO
:
704 return "SET_PGM_INDEX_INFO";
705 case CX2341X_ENC_SET_VBI_CONFIG
:
706 return "SET_VBI_CONFIG";
707 case CX2341X_ENC_SET_DMA_BLOCK_SIZE
:
708 return "SET_DMA_BLOCK_SIZE";
709 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10
:
710 return "GET_PREV_DMA_INFO_MB_10";
711 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
:
712 return "GET_PREV_DMA_INFO_MB_9";
713 case CX2341X_ENC_SCHED_DMA_TO_HOST
:
714 return "SCHED_DMA_TO_HOST";
715 case CX2341X_ENC_INITIALIZE_INPUT
:
716 return "INITIALIZE_INPUT";
717 case CX2341X_ENC_SET_FRAME_DROP_RATE
:
718 return "SET_FRAME_DROP_RATE";
719 case CX2341X_ENC_PAUSE_ENCODER
:
720 return "PAUSE_ENCODER";
721 case CX2341X_ENC_REFRESH_INPUT
:
722 return "REFRESH_INPUT";
723 case CX2341X_ENC_SET_COPYRIGHT
:
724 return "SET_COPYRIGHT";
725 case CX2341X_ENC_SET_EVENT_NOTIFICATION
:
726 return "SET_EVENT_NOTIFICATION";
727 case CX2341X_ENC_SET_NUM_VSYNC_LINES
:
728 return "SET_NUM_VSYNC_LINES";
729 case CX2341X_ENC_SET_PLACEHOLDER
:
730 return "SET_PLACEHOLDER";
731 case CX2341X_ENC_MUTE_VIDEO
:
733 case CX2341X_ENC_MUTE_AUDIO
:
735 case CX2341X_ENC_MISC
:
742 static int cx231xx_mbox_func(void *priv
,
746 u32 data
[CX2341X_MBOX_MAX_DATA
])
748 struct cx231xx
*dev
= priv
;
749 unsigned long timeout
;
750 u32 value
, flag
, retval
= 0;
753 dprintk(3, "%s: command(0x%X) = %s\n", __func__
, command
,
754 cmd_to_str(command
));
756 /* this may not be 100% safe if we can't read any memory location
757 without side effects */
758 mc417_memory_read(dev
, dev
->cx23417_mailbox
- 4, &value
);
759 if (value
!= 0x12345678) {
761 "Firmware and/or mailbox pointer not initialized "
762 "or corrupted, signature = 0x%x, cmd = %s\n", value
,
763 cmd_to_str(command
));
767 /* This read looks at 32 bits, but flag is only 8 bits.
768 * Seems we also bail if CMD or TIMEOUT bytes are set???
770 mc417_memory_read(dev
, dev
->cx23417_mailbox
, &flag
);
772 dprintk(3, "ERROR: Mailbox appears to be in use "
773 "(%x), cmd = %s\n", flag
, cmd_to_str(command
));
777 flag
|= 1; /* tell 'em we're working on it */
778 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
780 /* write command + args + fill remaining with zeros */
782 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 1, command
);
783 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 3,
784 IVTV_API_STD_TIMEOUT
); /* timeout */
785 for (i
= 0; i
< in
; i
++) {
786 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 4 + i
, data
[i
]);
787 dprintk(3, "API Input %d = %d\n", i
, data
[i
]);
789 for (; i
< CX2341X_MBOX_MAX_DATA
; i
++)
790 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 4 + i
, 0);
792 flag
|= 3; /* tell 'em we're done writing */
793 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
795 /* wait for firmware to handle the API command */
796 timeout
= jiffies
+ msecs_to_jiffies(10);
798 mc417_memory_read(dev
, dev
->cx23417_mailbox
, &flag
);
801 if (time_after(jiffies
, timeout
)) {
802 dprintk(3, "ERROR: API Mailbox timeout\n");
808 /* read output values */
809 for (i
= 0; i
< out
; i
++) {
810 mc417_memory_read(dev
, dev
->cx23417_mailbox
+ 4 + i
, data
+ i
);
811 dprintk(3, "API Output %d = %d\n", i
, data
[i
]);
814 mc417_memory_read(dev
, dev
->cx23417_mailbox
+ 2, &retval
);
815 dprintk(3, "API result = %d\n", retval
);
818 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
823 /* We don't need to call the API often, so using just one
824 * mailbox will probably suffice
826 static int cx231xx_api_cmd(struct cx231xx
*dev
,
832 u32 data
[CX2341X_MBOX_MAX_DATA
];
836 dprintk(3, "%s() cmds = 0x%08x\n", __func__
, command
);
838 va_start(vargs
, outputcnt
);
839 for (i
= 0; i
< inputcnt
; i
++)
840 data
[i
] = va_arg(vargs
, int);
842 err
= cx231xx_mbox_func(dev
, command
, inputcnt
, outputcnt
, data
);
843 for (i
= 0; i
< outputcnt
; i
++) {
844 int *vptr
= va_arg(vargs
, int *);
852 static int cx231xx_find_mailbox(struct cx231xx
*dev
)
855 0x12345678, 0x34567812, 0x56781234, 0x78123456
857 int signaturecnt
= 0;
862 dprintk(2, "%s()\n", __func__
);
864 for (i
= 0; i
< 0x100; i
++) {/*CX231xx_FIRM_IMAGE_SIZE*/
865 ret
= mc417_memory_read(dev
, i
, &value
);
868 if (value
== signature
[signaturecnt
])
872 if (4 == signaturecnt
) {
873 dprintk(1, "Mailbox signature found at 0x%x\n", i
+1);
877 dprintk(3, "Mailbox signature values not found!\n");
880 void mciWriteMemoryToGPIO(struct cx231xx
*dev
, u32 address
, u32 value
,
887 temp
= 0x82|MCI_MEMORY_DATA_BYTE0
|((value
&0x000000FF)<<8);
891 temp
= temp
|((0x05)<<10);
895 /*write data byte 1;*/
896 temp
= 0x82|MCI_MEMORY_DATA_BYTE1
|(value
&0x0000FF00);
900 temp
= temp
|((0x05)<<10);
904 /*write data byte 2;*/
905 temp
= 0x82|MCI_MEMORY_DATA_BYTE2
|((value
&0x00FF0000)>>8);
909 temp
= temp
|((0x05)<<10);
913 /*write data byte 3;*/
914 temp
= 0x82|MCI_MEMORY_DATA_BYTE3
|((value
&0xFF000000)>>16);
918 temp
= temp
|((0x05)<<10);
922 /* write address byte 2;*/
923 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE2
| MCI_MODE_MEMORY_WRITE
|
924 ((address
& 0x003F0000)>>8);
928 temp
= temp
|((0x05)<<10);
932 /* write address byte 1;*/
933 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE1
| (address
& 0xFF00);
937 temp
= temp
|((0x05)<<10);
941 /* write address byte 0;*/
942 temp
= 0x82|MCI_MEMORY_ADDRESS_BYTE0
|((address
& 0x00FF)<<8);
946 temp
= temp
|((0x05)<<10);
950 for (i
= 0; i
< 6; i
++) {
951 *p_fw_image
= 0xFFFFFFFF;
958 static int cx231xx_load_firmware(struct cx231xx
*dev
)
960 static const unsigned char magic
[8] = {
961 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
963 const struct firmware
*firmware
;
967 /*u32 checksum = 0;*/
969 u32 transfer_size
= 0;
972 /*u32 current_fw[800];*/
973 u32
*p_current_fw
, *p_fw
;
976 u16 _buffer_size
= 4096;
979 p_current_fw
= (u32
*)vmalloc(1884180*4);
981 if (p_current_fw
== 0) {
982 dprintk(2, "FAIL!!!\n");
986 p_buffer
= (u8
*)vmalloc(4096);
988 dprintk(2, "FAIL!!!\n");
992 dprintk(2, "%s()\n", __func__
);
994 /* Save GPIO settings before reset of APU */
995 retval
|= mc417_memory_read(dev
, 0x9020, &gpio_output
);
996 retval
|= mc417_memory_read(dev
, 0x900C, &value
);
998 retval
= mc417_register_write(dev
,
999 IVTV_REG_VPU
, 0xFFFFFFED);
1000 retval
|= mc417_register_write(dev
,
1001 IVTV_REG_HW_BLOCKS
, IVTV_CMD_HW_BLOCKS_RST
);
1002 retval
|= mc417_register_write(dev
,
1003 IVTV_REG_ENC_SDRAM_REFRESH
, 0x80000800);
1004 retval
|= mc417_register_write(dev
,
1005 IVTV_REG_ENC_SDRAM_PRECHARGE
, 0x1A);
1006 retval
|= mc417_register_write(dev
,
1010 printk(KERN_ERR
"%s: Error with mc417_register_write\n",
1015 retval
= request_firmware(&firmware
, CX231xx_FIRM_IMAGE_NAME
,
1020 "ERROR: Hotplug firmware request failed (%s).\n",
1021 CX231xx_FIRM_IMAGE_NAME
);
1022 printk(KERN_ERR
"Please fix your hotplug setup, the board will "
1023 "not work without firmware loaded!\n");
1027 if (firmware
->size
!= CX231xx_FIRM_IMAGE_SIZE
) {
1028 printk(KERN_ERR
"ERROR: Firmware size mismatch "
1029 "(have %zd, expected %d)\n",
1030 firmware
->size
, CX231xx_FIRM_IMAGE_SIZE
);
1031 release_firmware(firmware
);
1035 if (0 != memcmp(firmware
->data
, magic
, 8)) {
1037 "ERROR: Firmware magic mismatch, wrong file?\n");
1038 release_firmware(firmware
);
1044 /* transfer to the chip */
1045 dprintk(2, "Loading firmware to GPIO...\n");
1046 p_fw_data
= (u32
*)firmware
->data
;
1047 dprintk(2, "firmware->size=%d\n", firmware
->size
);
1048 for (transfer_size
= 0; transfer_size
< firmware
->size
;
1049 transfer_size
+= 4) {
1050 fw_data
= *p_fw_data
;
1052 mciWriteMemoryToGPIO(dev
, address
, fw_data
, p_current_fw
);
1053 address
= address
+ 1;
1058 /*download the firmware by ep5-out*/
1060 for (frame
= 0; frame
< (int)(CX231xx_FIRM_IMAGE_SIZE
*20/_buffer_size
);
1062 for (i
= 0; i
< _buffer_size
; i
++) {
1064 (u8
)(*(p_fw
+(frame
*128*8+(i
++/4))) & 0x000000FF);
1066 (u8
)((*(p_fw
+(frame
*128*8+(i
++/4))) & 0x0000FF00)>>8);
1068 (u8
)((*(p_fw
+(frame
*128*8+(i
++/4))) & 0x00FF0000)>>16);
1070 (u8
)((*(p_fw
+(frame
*128*8+(i
/4))) & 0xFF000000)>>24);
1072 cx231xx_ep5_bulkout(dev
, p_buffer
, _buffer_size
);
1075 p_current_fw
= p_fw
;
1076 vfree(p_current_fw
);
1077 p_current_fw
= NULL
;
1079 release_firmware(firmware
);
1080 dprintk(1, "Firmware upload successful.\n");
1082 retval
|= mc417_register_write(dev
, IVTV_REG_HW_BLOCKS
,
1083 IVTV_CMD_HW_BLOCKS_RST
);
1085 printk(KERN_ERR
"%s: Error with mc417_register_write\n",
1089 /* F/W power up disturbs the GPIOs, restore state */
1090 retval
|= mc417_register_write(dev
, 0x9020, gpio_output
);
1091 retval
|= mc417_register_write(dev
, 0x900C, value
);
1093 retval
|= mc417_register_read(dev
, IVTV_REG_VPU
, &value
);
1094 retval
|= mc417_register_write(dev
, IVTV_REG_VPU
, value
& 0xFFFFFFE8);
1097 printk(KERN_ERR
"%s: Error with mc417_register_write\n",
1104 void cx231xx_417_check_encoder(struct cx231xx
*dev
)
1110 cx231xx_api_cmd(dev
, CX2341X_ENC_GET_SEQ_END
, 0, 2, &status
, &seq
);
1111 dprintk(1, "%s() status = %d, seq = %d\n", __func__
, status
, seq
);
1114 static void cx231xx_codec_settings(struct cx231xx
*dev
)
1116 dprintk(1, "%s()\n", __func__
);
1118 /* assign frame size */
1119 cx231xx_api_cmd(dev
, CX2341X_ENC_SET_FRAME_SIZE
, 2, 0,
1120 dev
->ts1
.height
, dev
->ts1
.width
);
1122 dev
->mpeg_params
.width
= dev
->ts1
.width
;
1123 dev
->mpeg_params
.height
= dev
->ts1
.height
;
1125 cx2341x_update(dev
, cx231xx_mbox_func
, NULL
, &dev
->mpeg_params
);
1127 cx231xx_api_cmd(dev
, CX2341X_ENC_MISC
, 2, 0, 3, 1);
1128 cx231xx_api_cmd(dev
, CX2341X_ENC_MISC
, 2, 0, 4, 1);
1131 static int cx231xx_initialize_codec(struct cx231xx
*dev
)
1138 dprintk(1, "%s()\n", __func__
);
1139 cx231xx_disable656(dev
);
1140 retval
= cx231xx_api_cmd(dev
, CX2341X_ENC_PING_FW
, 0, 0); /* ping */
1142 dprintk(2, "%s() PING OK\n", __func__
);
1143 retval
= cx231xx_load_firmware(dev
);
1145 printk(KERN_ERR
"%s() f/w load failed\n", __func__
);
1148 retval
= cx231xx_find_mailbox(dev
);
1150 printk(KERN_ERR
"%s() mailbox < 0, error\n",
1154 dev
->cx23417_mailbox
= retval
;
1155 retval
= cx231xx_api_cmd(dev
, CX2341X_ENC_PING_FW
, 0, 0);
1158 "ERROR: cx23417 firmware ping failed!\n");
1161 retval
= cx231xx_api_cmd(dev
, CX2341X_ENC_GET_VERSION
, 0, 1,
1164 printk(KERN_ERR
"ERROR: cx23417 firmware get encoder :"
1165 "version failed!\n");
1168 dprintk(1, "cx23417 firmware version is 0x%08x\n", version
);
1172 for (i
= 0; i
< 1; i
++) {
1173 retval
= mc417_register_read(dev
, 0x20f8, &val
);
1174 dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1180 cx231xx_enable656(dev
);
1181 /* stop mpeg capture */
1182 cx231xx_api_cmd(dev
, CX2341X_ENC_STOP_CAPTURE
,
1185 cx231xx_codec_settings(dev
);
1188 /* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1189 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1190 cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1191 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1194 /* Setup to capture VBI */
1195 data
[0] = 0x0001BD00;
1196 data
[1] = 1; /* frames per interrupt */
1197 data
[2] = 4; /* total bufs */
1198 data
[3] = 0x91559155; /* start codes */
1199 data
[4] = 0x206080C0; /* stop codes */
1200 data
[5] = 6; /* lines */
1201 data
[6] = 64; /* BPL */
1203 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1204 data[2], data[3], data[4], data[5], data[6]);
1206 for (i = 2; i <= 24; i++) {
1209 valid = ((i >= 19) && (i <= 21));
1210 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1212 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1213 i | 0x80000000, valid, 0, 0, 0);
1216 /* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1219 /* initialize the video input */
1220 retval
= cx231xx_api_cmd(dev
, CX2341X_ENC_INITIALIZE_INPUT
, 0, 0);
1225 /* Enable VIP style pixel invalidation so we work with scaled mode */
1226 mc417_memory_write(dev
, 2120, 0x00000080);
1228 /* start capturing to the host interface */
1229 retval
= cx231xx_api_cmd(dev
, CX2341X_ENC_START_CAPTURE
, 2, 0,
1230 CX231xx_MPEG_CAPTURE
, CX231xx_RAW_BITS_NONE
);
1235 for (i
= 0; i
< 1; i
++) {
1236 mc417_register_read(dev
, 0x20f8, &val
);
1237 dprintk(3, "***VIM Capture Lines =%d ***\n", val
);
1243 /* ------------------------------------------------------------------ */
1245 static int bb_buf_setup(struct videobuf_queue
*q
,
1246 unsigned int *count
, unsigned int *size
)
1248 struct cx231xx_fh
*fh
= q
->priv_data
;
1250 fh
->dev
->ts1
.ts_packet_size
= mpeglinesize
;
1251 fh
->dev
->ts1
.ts_packet_count
= mpeglines
;
1253 *size
= fh
->dev
->ts1
.ts_packet_size
* fh
->dev
->ts1
.ts_packet_count
;
1258 static void free_buffer(struct videobuf_queue
*vq
, struct cx231xx_buffer
*buf
)
1260 struct cx231xx_fh
*fh
= vq
->priv_data
;
1261 struct cx231xx
*dev
= fh
->dev
;
1262 unsigned long flags
= 0;
1267 spin_lock_irqsave(&dev
->video_mode
.slock
, flags
);
1269 if (dev
->video_mode
.isoc_ctl
.buf
== buf
)
1270 dev
->video_mode
.isoc_ctl
.buf
= NULL
;
1272 if (dev
->video_mode
.bulk_ctl
.buf
== buf
)
1273 dev
->video_mode
.bulk_ctl
.buf
= NULL
;
1275 spin_unlock_irqrestore(&dev
->video_mode
.slock
, flags
);
1276 videobuf_waiton(vq
, &buf
->vb
, 0, 0);
1277 videobuf_vmalloc_free(&buf
->vb
);
1278 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
1281 void buffer_copy(struct cx231xx
*dev
, char *data
, int len
, struct urb
*urb
,
1282 struct cx231xx_dmaqueue
*dma_q
)
1285 struct cx231xx_buffer
*buf
;
1289 if (dma_q
->mpeg_buffer_done
== 0) {
1290 if (list_empty(&dma_q
->active
))
1293 buf
= list_entry(dma_q
->active
.next
,
1294 struct cx231xx_buffer
, vb
.queue
);
1295 dev
->video_mode
.isoc_ctl
.buf
= buf
;
1296 dma_q
->mpeg_buffer_done
= 1;
1299 buf
= dev
->video_mode
.isoc_ctl
.buf
;
1300 vbuf
= videobuf_to_vmalloc(&buf
->vb
);
1302 if ((dma_q
->mpeg_buffer_completed
+len
) <
1303 mpeglines
*mpeglinesize
) {
1304 if (dma_q
->add_ps_package_head
==
1305 CX231XX_NEED_ADD_PS_PACKAGE_HEAD
) {
1306 memcpy(vbuf
+dma_q
->mpeg_buffer_completed
,
1308 dma_q
->mpeg_buffer_completed
=
1309 dma_q
->mpeg_buffer_completed
+ 3;
1310 dma_q
->add_ps_package_head
=
1311 CX231XX_NONEED_PS_PACKAGE_HEAD
;
1313 memcpy(vbuf
+dma_q
->mpeg_buffer_completed
, data
, len
);
1314 dma_q
->mpeg_buffer_completed
=
1315 dma_q
->mpeg_buffer_completed
+ len
;
1317 dma_q
->mpeg_buffer_done
= 0;
1320 mpeglines
*mpeglinesize
- dma_q
->mpeg_buffer_completed
;
1321 memcpy(vbuf
+dma_q
->mpeg_buffer_completed
,
1324 buf
->vb
.state
= VIDEOBUF_DONE
;
1325 buf
->vb
.field_count
++;
1326 do_gettimeofday(&buf
->vb
.ts
);
1327 list_del(&buf
->vb
.queue
);
1328 wake_up(&buf
->vb
.done
);
1329 dma_q
->mpeg_buffer_completed
= 0;
1331 if (len
- tail_data
> 0) {
1332 p_data
= data
+ tail_data
;
1333 dma_q
->left_data_count
= len
- tail_data
;
1334 memcpy(dma_q
->p_left_data
,
1335 p_data
, len
- tail_data
);
1343 void buffer_filled(char *data
, int len
, struct urb
*urb
,
1344 struct cx231xx_dmaqueue
*dma_q
)
1347 struct cx231xx_buffer
*buf
;
1349 if (list_empty(&dma_q
->active
))
1353 buf
= list_entry(dma_q
->active
.next
,
1354 struct cx231xx_buffer
, vb
.queue
);
1358 vbuf
= videobuf_to_vmalloc(&buf
->vb
);
1359 memcpy(vbuf
, data
, len
);
1360 buf
->vb
.state
= VIDEOBUF_DONE
;
1361 buf
->vb
.field_count
++;
1362 do_gettimeofday(&buf
->vb
.ts
);
1363 list_del(&buf
->vb
.queue
);
1364 wake_up(&buf
->vb
.done
);
1368 static inline int cx231xx_isoc_copy(struct cx231xx
*dev
, struct urb
*urb
)
1370 struct cx231xx_dmaqueue
*dma_q
= urb
->context
;
1371 unsigned char *p_buffer
;
1372 u32 buffer_size
= 0;
1375 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1376 if (dma_q
->left_data_count
> 0) {
1377 buffer_copy(dev
, dma_q
->p_left_data
,
1378 dma_q
->left_data_count
, urb
, dma_q
);
1379 dma_q
->mpeg_buffer_completed
= dma_q
->left_data_count
;
1380 dma_q
->left_data_count
= 0;
1383 p_buffer
= urb
->transfer_buffer
+
1384 urb
->iso_frame_desc
[i
].offset
;
1385 buffer_size
= urb
->iso_frame_desc
[i
].actual_length
;
1387 if (buffer_size
> 0)
1388 buffer_copy(dev
, p_buffer
, buffer_size
, urb
, dma_q
);
1393 static inline int cx231xx_bulk_copy(struct cx231xx
*dev
, struct urb
*urb
)
1397 /*struct cx231xx_buffer *buf;*/
1398 struct cx231xx_dmaqueue
*dma_q
= urb
->context
;
1399 unsigned char *p_buffer
, *buffer
;
1400 u32 buffer_size
= 0;
1402 p_buffer
= urb
->transfer_buffer
;
1403 buffer_size
= urb
->actual_length
;
1405 buffer
= kmalloc(buffer_size
, GFP_ATOMIC
);
1407 memcpy(buffer
, dma_q
->ps_head
, 3);
1408 memcpy(buffer
+3, p_buffer
, buffer_size
-3);
1409 memcpy(dma_q
->ps_head
, p_buffer
+buffer_size
-3, 3);
1412 buffer_filled(p_buffer
, buffer_size
, urb
, dma_q
);
1418 static int bb_buf_prepare(struct videobuf_queue
*q
,
1419 struct videobuf_buffer
*vb
, enum v4l2_field field
)
1421 struct cx231xx_fh
*fh
= q
->priv_data
;
1422 struct cx231xx_buffer
*buf
=
1423 container_of(vb
, struct cx231xx_buffer
, vb
);
1424 struct cx231xx
*dev
= fh
->dev
;
1425 int rc
= 0, urb_init
= 0;
1426 int size
= fh
->dev
->ts1
.ts_packet_size
* fh
->dev
->ts1
.ts_packet_count
;
1428 dma_qq
= &dev
->video_mode
.vidq
;
1430 if (0 != buf
->vb
.baddr
&& buf
->vb
.bsize
< size
)
1432 buf
->vb
.width
= fh
->dev
->ts1
.ts_packet_size
;
1433 buf
->vb
.height
= fh
->dev
->ts1
.ts_packet_count
;
1434 buf
->vb
.size
= size
;
1435 buf
->vb
.field
= field
;
1437 if (VIDEOBUF_NEEDS_INIT
== buf
->vb
.state
) {
1438 rc
= videobuf_iolock(q
, &buf
->vb
, NULL
);
1444 if (!dev
->video_mode
.isoc_ctl
.num_bufs
)
1447 if (!dev
->video_mode
.bulk_ctl
.num_bufs
)
1450 /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1451 urb_init, dev->video_mode.max_pkt_size);*/
1455 rc
= cx231xx_set_mode(dev
, CX231XX_DIGITAL_MODE
);
1456 rc
= cx231xx_unmute_audio(dev
);
1458 cx231xx_set_alt_setting(dev
, INDEX_TS1
, 4);
1459 rc
= cx231xx_init_isoc(dev
, mpeglines
,
1461 dev
->ts1_mode
.max_pkt_size
,
1464 cx231xx_set_alt_setting(dev
, INDEX_TS1
, 0);
1465 rc
= cx231xx_init_bulk(dev
, mpeglines
,
1467 dev
->ts1_mode
.max_pkt_size
,
1474 buf
->vb
.state
= VIDEOBUF_PREPARED
;
1478 free_buffer(q
, buf
);
1482 static void bb_buf_queue(struct videobuf_queue
*q
,
1483 struct videobuf_buffer
*vb
)
1485 struct cx231xx_fh
*fh
= q
->priv_data
;
1487 struct cx231xx_buffer
*buf
=
1488 container_of(vb
, struct cx231xx_buffer
, vb
);
1489 struct cx231xx
*dev
= fh
->dev
;
1490 struct cx231xx_dmaqueue
*vidq
= &dev
->video_mode
.vidq
;
1492 buf
->vb
.state
= VIDEOBUF_QUEUED
;
1493 list_add_tail(&buf
->vb
.queue
, &vidq
->active
);
1497 static void bb_buf_release(struct videobuf_queue
*q
,
1498 struct videobuf_buffer
*vb
)
1500 struct cx231xx_buffer
*buf
=
1501 container_of(vb
, struct cx231xx_buffer
, vb
);
1502 /*struct cx231xx_fh *fh = q->priv_data;*/
1503 /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1505 free_buffer(q
, buf
);
1508 static struct videobuf_queue_ops cx231xx_qops
= {
1509 .buf_setup
= bb_buf_setup
,
1510 .buf_prepare
= bb_buf_prepare
,
1511 .buf_queue
= bb_buf_queue
,
1512 .buf_release
= bb_buf_release
,
1515 /* ------------------------------------------------------------------ */
1517 static const u32
*ctrl_classes
[] = {
1522 static int cx231xx_queryctrl(struct cx231xx
*dev
,
1523 struct v4l2_queryctrl
*qctrl
)
1525 qctrl
->id
= v4l2_ctrl_next(ctrl_classes
, qctrl
->id
);
1529 /* MPEG V4L2 controls */
1530 if (cx2341x_ctrl_query(&dev
->mpeg_params
, qctrl
))
1531 qctrl
->flags
|= V4L2_CTRL_FLAG_DISABLED
;
1536 static int cx231xx_querymenu(struct cx231xx
*dev
,
1537 struct v4l2_querymenu
*qmenu
)
1539 struct v4l2_queryctrl qctrl
;
1541 qctrl
.id
= qmenu
->id
;
1542 cx231xx_queryctrl(dev
, &qctrl
);
1543 return v4l2_ctrl_query_menu(qmenu
, &qctrl
,
1544 cx2341x_ctrl_get_menu(&dev
->mpeg_params
, qmenu
->id
));
1547 static int vidioc_g_std(struct file
*file
, void *fh0
, v4l2_std_id
*norm
)
1549 struct cx231xx_fh
*fh
= file
->private_data
;
1550 struct cx231xx
*dev
= fh
->dev
;
1552 *norm
= dev
->encodernorm
.id
;
1555 static int vidioc_s_std(struct file
*file
, void *priv
, v4l2_std_id
*id
)
1557 struct cx231xx_fh
*fh
= file
->private_data
;
1558 struct cx231xx
*dev
= fh
->dev
;
1561 for (i
= 0; i
< ARRAY_SIZE(cx231xx_tvnorms
); i
++)
1562 if (*id
& cx231xx_tvnorms
[i
].id
)
1564 if (i
== ARRAY_SIZE(cx231xx_tvnorms
))
1566 dev
->encodernorm
= cx231xx_tvnorms
[i
];
1568 if (dev
->encodernorm
.id
& 0xb000) {
1569 dprintk(3, "encodernorm set to NTSC\n");
1570 dev
->norm
= V4L2_STD_NTSC
;
1571 dev
->ts1
.height
= 480;
1572 dev
->mpeg_params
.is_50hz
= 0;
1574 dprintk(3, "encodernorm set to PAL\n");
1575 dev
->norm
= V4L2_STD_PAL_B
;
1576 dev
->ts1
.height
= 576;
1577 dev
->mpeg_params
.is_50hz
= 1;
1579 call_all(dev
, core
, s_std
, dev
->norm
);
1580 /* do mode control overrides */
1581 cx231xx_do_mode_ctrl_overrides(dev
);
1583 dprintk(3, "exit vidioc_s_std() i=0x%x\n", i
);
1586 static int vidioc_g_audio(struct file
*file
, void *fh
,
1587 struct v4l2_audio
*a
)
1589 struct v4l2_audio
*vin
= a
;
1594 strncpy(vin
->name
, "VideoGrabber Audio", 14);
1595 vin
->capability
= V4L2_AUDCAP_STEREO
;
1598 static int vidioc_enumaudio(struct file
*file
, void *fh
,
1599 struct v4l2_audio
*a
)
1601 struct v4l2_audio
*vin
= a
;
1607 strncpy(vin
->name
, "VideoGrabber Audio", 14);
1608 vin
->capability
= V4L2_AUDCAP_STEREO
;
1613 static const char *iname
[] = {
1614 [CX231XX_VMUX_COMPOSITE1
] = "Composite1",
1615 [CX231XX_VMUX_SVIDEO
] = "S-Video",
1616 [CX231XX_VMUX_TELEVISION
] = "Television",
1617 [CX231XX_VMUX_CABLE
] = "Cable TV",
1618 [CX231XX_VMUX_DVB
] = "DVB",
1619 [CX231XX_VMUX_DEBUG
] = "for debug only",
1621 static int vidioc_enum_input(struct file
*file
, void *priv
,
1622 struct v4l2_input
*i
)
1624 struct cx231xx_fh
*fh
= file
->private_data
;
1625 struct cx231xx
*dev
= fh
->dev
;
1626 struct cx231xx_input
*input
;
1628 dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i
->index
);
1634 input
= &cx231xx_boards
[dev
->model
].input
[i
->index
];
1636 if (input
->type
== 0)
1640 * strcpy(i->name, input->name); */
1643 strcpy(i
->name
, iname
[INPUT(n
)->type
]);
1645 if (input
->type
== CX231XX_VMUX_TELEVISION
||
1646 input
->type
== CX231XX_VMUX_CABLE
)
1647 i
->type
= V4L2_INPUT_TYPE_TUNER
;
1649 i
->type
= V4L2_INPUT_TYPE_CAMERA
;
1655 static int vidioc_g_input(struct file
*file
, void *priv
, unsigned int *i
)
1661 static int vidioc_s_input(struct file
*file
, void *priv
, unsigned int i
)
1663 struct cx231xx_fh
*fh
= file
->private_data
;
1664 struct cx231xx
*dev
= fh
->dev
;
1666 dprintk(3, "enter vidioc_s_input() i=%d\n", i
);
1668 mutex_lock(&dev
->lock
);
1672 mutex_unlock(&dev
->lock
);
1677 dprintk(3, "exit vidioc_s_input()\n");
1681 static int vidioc_g_tuner(struct file
*file
, void *priv
,
1682 struct v4l2_tuner
*t
)
1687 static int vidioc_s_tuner(struct file
*file
, void *priv
,
1688 struct v4l2_tuner
*t
)
1693 static int vidioc_g_frequency(struct file
*file
, void *priv
,
1694 struct v4l2_frequency
*f
)
1699 static int vidioc_s_frequency(struct file
*file
, void *priv
,
1700 struct v4l2_frequency
*f
)
1707 static int vidioc_s_ctrl(struct file
*file
, void *priv
,
1708 struct v4l2_control
*ctl
)
1710 struct cx231xx_fh
*fh
= file
->private_data
;
1711 struct cx231xx
*dev
= fh
->dev
;
1712 dprintk(3, "enter vidioc_s_ctrl()\n");
1713 /* Update the A/V core */
1714 call_all(dev
, core
, s_ctrl
, ctl
);
1715 dprintk(3, "exit vidioc_s_ctrl()\n");
1718 static struct v4l2_capability pvr_capability
= {
1719 .driver
= "cx231xx",
1720 .card
= "VideoGrabber",
1723 .capabilities
= (V4L2_CAP_VIDEO_CAPTURE
|
1724 V4L2_CAP_TUNER
| V4L2_CAP_AUDIO
| V4L2_CAP_RADIO
|
1725 V4L2_CAP_STREAMING
| V4L2_CAP_READWRITE
),
1726 .reserved
= {0, 0, 0, 0}
1728 static int vidioc_querycap(struct file
*file
, void *priv
,
1729 struct v4l2_capability
*cap
)
1734 memcpy(cap
, &pvr_capability
, sizeof(struct v4l2_capability
));
1738 static int vidioc_enum_fmt_vid_cap(struct file
*file
, void *priv
,
1739 struct v4l2_fmtdesc
*f
)
1745 strlcpy(f
->description
, "MPEG", sizeof(f
->description
));
1746 f
->pixelformat
= V4L2_PIX_FMT_MPEG
;
1751 static int vidioc_g_fmt_vid_cap(struct file
*file
, void *priv
,
1752 struct v4l2_format
*f
)
1754 struct cx231xx_fh
*fh
= file
->private_data
;
1755 struct cx231xx
*dev
= fh
->dev
;
1756 dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1757 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_MPEG
;
1758 f
->fmt
.pix
.bytesperline
= 0;
1759 f
->fmt
.pix
.sizeimage
=
1760 dev
->ts1
.ts_packet_size
* dev
->ts1
.ts_packet_count
;
1761 f
->fmt
.pix
.colorspace
= 0;
1762 f
->fmt
.pix
.width
= dev
->ts1
.width
;
1763 f
->fmt
.pix
.height
= dev
->ts1
.height
;
1764 f
->fmt
.pix
.field
= fh
->vidq
.field
;
1765 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1766 dev
->ts1
.width
, dev
->ts1
.height
, fh
->vidq
.field
);
1767 dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1771 static int vidioc_try_fmt_vid_cap(struct file
*file
, void *priv
,
1772 struct v4l2_format
*f
)
1774 struct cx231xx_fh
*fh
= file
->private_data
;
1775 struct cx231xx
*dev
= fh
->dev
;
1776 dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1777 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_MPEG
;
1778 f
->fmt
.pix
.bytesperline
= 0;
1779 f
->fmt
.pix
.sizeimage
=
1780 dev
->ts1
.ts_packet_size
* dev
->ts1
.ts_packet_count
;
1781 f
->fmt
.pix
.colorspace
= 0;
1782 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1783 dev
->ts1
.width
, dev
->ts1
.height
, fh
->vidq
.field
);
1784 dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1788 static int vidioc_s_fmt_vid_cap(struct file
*file
, void *priv
,
1789 struct v4l2_format
*f
)
1795 static int vidioc_reqbufs(struct file
*file
, void *priv
,
1796 struct v4l2_requestbuffers
*p
)
1798 struct cx231xx_fh
*fh
= file
->private_data
;
1800 return videobuf_reqbufs(&fh
->vidq
, p
);
1803 static int vidioc_querybuf(struct file
*file
, void *priv
,
1804 struct v4l2_buffer
*p
)
1806 struct cx231xx_fh
*fh
= file
->private_data
;
1808 return videobuf_querybuf(&fh
->vidq
, p
);
1811 static int vidioc_qbuf(struct file
*file
, void *priv
,
1812 struct v4l2_buffer
*p
)
1814 struct cx231xx_fh
*fh
= file
->private_data
;
1816 return videobuf_qbuf(&fh
->vidq
, p
);
1819 static int vidioc_dqbuf(struct file
*file
, void *priv
, struct v4l2_buffer
*b
)
1821 struct cx231xx_fh
*fh
= priv
;
1823 return videobuf_dqbuf(&fh
->vidq
, b
, file
->f_flags
& O_NONBLOCK
);
1827 static int vidioc_streamon(struct file
*file
, void *priv
,
1828 enum v4l2_buf_type i
)
1830 struct cx231xx_fh
*fh
= file
->private_data
;
1832 struct cx231xx
*dev
= fh
->dev
;
1834 dprintk(3, "enter vidioc_streamon()\n");
1835 cx231xx_set_alt_setting(dev
, INDEX_TS1
, 0);
1836 rc
= cx231xx_set_mode(dev
, CX231XX_DIGITAL_MODE
);
1838 rc
= cx231xx_init_isoc(dev
, CX231XX_NUM_PACKETS
,
1840 dev
->video_mode
.max_pkt_size
,
1843 rc
= cx231xx_init_bulk(dev
, 320,
1845 dev
->ts1_mode
.max_pkt_size
,
1848 dprintk(3, "exit vidioc_streamon()\n");
1849 return videobuf_streamon(&fh
->vidq
);
1852 static int vidioc_streamoff(struct file
*file
, void *priv
, enum v4l2_buf_type i
)
1854 struct cx231xx_fh
*fh
= file
->private_data
;
1856 return videobuf_streamoff(&fh
->vidq
);
1859 static int vidioc_g_ext_ctrls(struct file
*file
, void *priv
,
1860 struct v4l2_ext_controls
*f
)
1862 struct cx231xx_fh
*fh
= priv
;
1863 struct cx231xx
*dev
= fh
->dev
;
1864 dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1865 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1867 dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1868 return cx2341x_ext_ctrls(&dev
->mpeg_params
, 0, f
, VIDIOC_G_EXT_CTRLS
);
1871 static int vidioc_s_ext_ctrls(struct file
*file
, void *priv
,
1872 struct v4l2_ext_controls
*f
)
1874 struct cx231xx_fh
*fh
= priv
;
1875 struct cx231xx
*dev
= fh
->dev
;
1876 struct cx2341x_mpeg_params p
;
1878 dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1879 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1882 p
= dev
->mpeg_params
;
1883 err
= cx2341x_ext_ctrls(&p
, 0, f
, VIDIOC_TRY_EXT_CTRLS
);
1885 err
= cx2341x_update(dev
, cx231xx_mbox_func
,
1886 &dev
->mpeg_params
, &p
);
1887 dev
->mpeg_params
= p
;
1896 static int vidioc_try_ext_ctrls(struct file
*file
, void *priv
,
1897 struct v4l2_ext_controls
*f
)
1899 struct cx231xx_fh
*fh
= priv
;
1900 struct cx231xx
*dev
= fh
->dev
;
1901 struct cx2341x_mpeg_params p
;
1903 dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1904 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1907 p
= dev
->mpeg_params
;
1908 err
= cx2341x_ext_ctrls(&p
, 0, f
, VIDIOC_TRY_EXT_CTRLS
);
1909 dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err
);
1913 static int vidioc_log_status(struct file
*file
, void *priv
)
1915 struct cx231xx_fh
*fh
= priv
;
1916 struct cx231xx
*dev
= fh
->dev
;
1919 snprintf(name
, sizeof(name
), "%s/2", dev
->name
);
1921 "%s/2: ============ START LOG STATUS ============\n",
1923 call_all(dev
, core
, log_status
);
1924 cx2341x_log_status(&dev
->mpeg_params
, name
);
1926 "%s/2: ============= END LOG STATUS =============\n",
1931 static int vidioc_querymenu(struct file
*file
, void *priv
,
1932 struct v4l2_querymenu
*a
)
1934 struct cx231xx_fh
*fh
= priv
;
1935 struct cx231xx
*dev
= fh
->dev
;
1936 dprintk(3, "enter vidioc_querymenu()\n");
1937 dprintk(3, "exit vidioc_querymenu()\n");
1938 return cx231xx_querymenu(dev
, a
);
1941 static int vidioc_queryctrl(struct file
*file
, void *priv
,
1942 struct v4l2_queryctrl
*c
)
1944 struct cx231xx_fh
*fh
= priv
;
1945 struct cx231xx
*dev
= fh
->dev
;
1946 dprintk(3, "enter vidioc_queryctrl()\n");
1947 dprintk(3, "exit vidioc_queryctrl()\n");
1948 return cx231xx_queryctrl(dev
, c
);
1951 static int mpeg_open(struct file
*file
)
1953 int minor
= video_devdata(file
)->minor
;
1954 struct cx231xx
*h
, *dev
= NULL
;
1955 /*struct list_head *list;*/
1956 struct cx231xx_fh
*fh
;
1959 dprintk(2, "%s()\n", __func__
);
1961 list_for_each_entry(h
, &cx231xx_devlist
, devlist
) {
1962 if (h
->v4l_device
->minor
== minor
)
1970 mutex_lock(&dev
->lock
);
1972 /* allocate + initialize per filehandle data */
1973 fh
= kzalloc(sizeof(*fh
), GFP_KERNEL
);
1975 mutex_unlock(&dev
->lock
);
1979 file
->private_data
= fh
;
1983 videobuf_queue_vmalloc_init(&fh
->vidq
, &cx231xx_qops
,
1984 NULL
, &dev
->video_mode
.slock
,
1985 V4L2_BUF_TYPE_VIDEO_CAPTURE
, V4L2_FIELD_INTERLACED
,
1986 sizeof(struct cx231xx_buffer
), fh
, NULL
);
1988 videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1989 &dev->udev->dev, &dev->ts1.slock,
1990 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1991 V4L2_FIELD_INTERLACED,
1992 sizeof(struct cx231xx_buffer),
1997 cx231xx_set_alt_setting(dev
, INDEX_VANC
, 1);
1998 cx231xx_set_gpio_value(dev
, 2, 0);
2000 cx231xx_initialize_codec(dev
);
2002 mutex_unlock(&dev
->lock
);
2003 cx231xx_start_TS1(dev
);
2008 static int mpeg_release(struct file
*file
)
2010 struct cx231xx_fh
*fh
= file
->private_data
;
2011 struct cx231xx
*dev
= fh
->dev
;
2013 dprintk(3, "mpeg_release()! dev=0x%x\n", dev
);
2016 dprintk(3, "abort!!!\n");
2020 mutex_lock(&dev
->lock
);
2022 cx231xx_stop_TS1(dev
);
2024 /* do this before setting alternate! */
2026 cx231xx_uninit_isoc(dev
);
2028 cx231xx_uninit_bulk(dev
);
2029 cx231xx_set_mode(dev
, CX231XX_SUSPEND
);
2031 cx231xx_api_cmd(fh
->dev
, CX2341X_ENC_STOP_CAPTURE
, 3, 0,
2032 CX231xx_END_NOW
, CX231xx_MPEG_CAPTURE
,
2033 CX231xx_RAW_BITS_NONE
);
2035 /* FIXME: Review this crap */
2036 /* Shut device down on last close */
2037 if (atomic_cmpxchg(&fh
->v4l_reading
, 1, 0) == 1) {
2038 if (atomic_dec_return(&dev
->v4l_reader_count
) == 0) {
2039 /* stop mpeg capture */
2042 cx231xx_417_check_encoder(dev
);
2047 if (fh
->vidq
.streaming
)
2048 videobuf_streamoff(&fh
->vidq
);
2049 if (fh
->vidq
.reading
)
2050 videobuf_read_stop(&fh
->vidq
);
2052 videobuf_mmap_free(&fh
->vidq
);
2053 file
->private_data
= NULL
;
2055 mutex_unlock(&dev
->lock
);
2059 static ssize_t
mpeg_read(struct file
*file
, char __user
*data
,
2060 size_t count
, loff_t
*ppos
)
2062 struct cx231xx_fh
*fh
= file
->private_data
;
2063 struct cx231xx
*dev
= fh
->dev
;
2066 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2067 /* Start mpeg encoder on first read. */
2068 if (atomic_cmpxchg(&fh
->v4l_reading
, 0, 1) == 0) {
2069 if (atomic_inc_return(&dev
->v4l_reader_count
) == 1) {
2070 if (cx231xx_initialize_codec(dev
) < 0)
2075 return videobuf_read_stream(&fh
->vidq
, data
, count
, ppos
, 0,
2076 file
->f_flags
& O_NONBLOCK
);
2079 static unsigned int mpeg_poll(struct file
*file
,
2080 struct poll_table_struct
*wait
)
2082 struct cx231xx_fh
*fh
= file
->private_data
;
2083 /*struct cx231xx *dev = fh->dev;*/
2085 /*dprintk(2, "%s\n", __func__);*/
2087 return videobuf_poll_stream(file
, &fh
->vidq
, wait
);
2090 static int mpeg_mmap(struct file
*file
, struct vm_area_struct
*vma
)
2092 struct cx231xx_fh
*fh
= file
->private_data
;
2093 struct cx231xx
*dev
= fh
->dev
;
2095 dprintk(2, "%s()\n", __func__
);
2097 return videobuf_mmap_mapper(&fh
->vidq
, vma
);
2100 static struct v4l2_file_operations mpeg_fops
= {
2101 .owner
= THIS_MODULE
,
2103 .release
= mpeg_release
,
2107 .ioctl
= video_ioctl2
,
2110 static const struct v4l2_ioctl_ops mpeg_ioctl_ops
= {
2111 .vidioc_s_std
= vidioc_s_std
,
2112 .vidioc_g_std
= vidioc_g_std
,
2113 .vidioc_enum_input
= vidioc_enum_input
,
2114 .vidioc_enumaudio
= vidioc_enumaudio
,
2115 .vidioc_g_audio
= vidioc_g_audio
,
2116 .vidioc_g_input
= vidioc_g_input
,
2117 .vidioc_s_input
= vidioc_s_input
,
2118 .vidioc_g_tuner
= vidioc_g_tuner
,
2119 .vidioc_s_tuner
= vidioc_s_tuner
,
2120 .vidioc_g_frequency
= vidioc_g_frequency
,
2121 .vidioc_s_frequency
= vidioc_s_frequency
,
2122 .vidioc_s_ctrl
= vidioc_s_ctrl
,
2123 .vidioc_querycap
= vidioc_querycap
,
2124 .vidioc_enum_fmt_vid_cap
= vidioc_enum_fmt_vid_cap
,
2125 .vidioc_g_fmt_vid_cap
= vidioc_g_fmt_vid_cap
,
2126 .vidioc_try_fmt_vid_cap
= vidioc_try_fmt_vid_cap
,
2127 .vidioc_s_fmt_vid_cap
= vidioc_s_fmt_vid_cap
,
2128 .vidioc_reqbufs
= vidioc_reqbufs
,
2129 .vidioc_querybuf
= vidioc_querybuf
,
2130 .vidioc_qbuf
= vidioc_qbuf
,
2131 .vidioc_dqbuf
= vidioc_dqbuf
,
2132 .vidioc_streamon
= vidioc_streamon
,
2133 .vidioc_streamoff
= vidioc_streamoff
,
2134 .vidioc_g_ext_ctrls
= vidioc_g_ext_ctrls
,
2135 .vidioc_s_ext_ctrls
= vidioc_s_ext_ctrls
,
2136 .vidioc_try_ext_ctrls
= vidioc_try_ext_ctrls
,
2137 .vidioc_log_status
= vidioc_log_status
,
2138 .vidioc_querymenu
= vidioc_querymenu
,
2139 .vidioc_queryctrl
= vidioc_queryctrl
,
2140 /* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/
2141 #ifdef CONFIG_VIDEO_ADV_DEBUG
2142 /* .vidioc_g_register = cx231xx_g_register,*/
2143 /* .vidioc_s_register = cx231xx_s_register,*/
2147 static struct video_device cx231xx_mpeg_template
= {
2150 .ioctl_ops
= &mpeg_ioctl_ops
,
2152 .tvnorms
= CX231xx_NORMS
,
2153 .current_norm
= V4L2_STD_NTSC_M
,
2156 void cx231xx_417_unregister(struct cx231xx
*dev
)
2158 dprintk(1, "%s()\n", __func__
);
2159 dprintk(3, "%s()\n", __func__
);
2161 if (dev
->v4l_device
) {
2162 if (-1 != dev
->v4l_device
->minor
)
2163 video_unregister_device(dev
->v4l_device
);
2165 video_device_release(dev
->v4l_device
);
2166 dev
->v4l_device
= NULL
;
2170 static struct video_device
*cx231xx_video_dev_alloc(
2171 struct cx231xx
*dev
,
2172 struct usb_device
*usbdev
,
2173 struct video_device
*template,
2176 struct video_device
*vfd
;
2178 dprintk(1, "%s()\n", __func__
);
2179 vfd
= video_device_alloc();
2184 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s %s (%s)", dev
->name
,
2185 type
, cx231xx_boards
[dev
->model
].name
);
2187 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
2188 vfd
->release
= video_device_release
;
2194 int cx231xx_417_register(struct cx231xx
*dev
)
2196 /* FIXME: Port1 hardcoded here */
2198 struct cx231xx_tsport
*tsport
= &dev
->ts1
;
2200 dprintk(1, "%s()\n", __func__
);
2202 /* Set default TV standard */
2203 dev
->encodernorm
= cx231xx_tvnorms
[0];
2205 if (dev
->encodernorm
.id
& V4L2_STD_525_60
)
2206 tsport
->height
= 480;
2208 tsport
->height
= 576;
2210 tsport
->width
= 720;
2211 cx2341x_fill_defaults(&dev
->mpeg_params
);
2212 dev
->norm
= V4L2_STD_NTSC
;
2214 dev
->mpeg_params
.port
= CX2341X_PORT_SERIAL
;
2216 /* Allocate and initialize V4L video device */
2217 dev
->v4l_device
= cx231xx_video_dev_alloc(dev
,
2218 dev
->udev
, &cx231xx_mpeg_template
, "mpeg");
2219 err
= video_register_device(dev
->v4l_device
,
2220 VFL_TYPE_GRABBER
, -1);
2222 dprintk(3, "%s: can't register mpeg device\n", dev
->name
);
2226 dprintk(3, "%s: registered device video%d [mpeg]\n",
2227 dev
->name
, dev
->v4l_device
->num
);