arch/arm/mach-mx5/board-mx51_babbage.c

   1 /*
   2  * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/i2c.h>
  16 #include <linux/gpio.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/fsl_devices.h>
  20 #include <linux/fec.h>
  21
  22 #include <mach/common.h>
  23 #include <mach/hardware.h>
  24 #include <mach/iomux-mx51.h>
  25 #include <mach/mxc_ehci.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/setup.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/time.h>
  32
  33 #include "devices-imx51.h"
  34 #include "devices.h"
  35 #include "cpu_op-mx51.h"
  36
  37 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
  38 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
  39 #define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
  40 #define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
  41
  42 /* USB_CTRL_1 */
  43 #define MX51_USB_CTRL_1_OFFSET                  0x10
  44 #define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
  45
  46 #define MX51_USB_PLLDIV_12_MHZ          0x00
  47 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  48 #define MX51_USB_PLL_DIV_24_MHZ 0x02
  49
  50 static struct pad_desc mx51babbage_pads[] = {
  51         /* UART1 */
  52         MX51_PAD_UART1_RXD__UART1_RXD,
  53         MX51_PAD_UART1_TXD__UART1_TXD,
  54         MX51_PAD_UART1_RTS__UART1_RTS,
  55         MX51_PAD_UART1_CTS__UART1_CTS,
  56
  57         /* UART2 */
  58         MX51_PAD_UART2_RXD__UART2_RXD,
  59         MX51_PAD_UART2_TXD__UART2_TXD,
  60
  61         /* UART3 */
  62         MX51_PAD_EIM_D25__UART3_RXD,
  63         MX51_PAD_EIM_D26__UART3_TXD,
  64         MX51_PAD_EIM_D27__UART3_RTS,
  65         MX51_PAD_EIM_D24__UART3_CTS,
  66
  67         /* I2C1 */
  68         MX51_PAD_EIM_D16__I2C1_SDA,
  69         MX51_PAD_EIM_D19__I2C1_SCL,
  70
  71         /* I2C2 */
  72         MX51_PAD_KEY_COL4__I2C2_SCL,
  73         MX51_PAD_KEY_COL5__I2C2_SDA,
  74
  75         /* HSI2C */
  76         MX51_PAD_I2C1_CLK__HSI2C_CLK,
  77         MX51_PAD_I2C1_DAT__HSI2C_DAT,
  78
  79         /* USB HOST1 */
  80         MX51_PAD_USBH1_CLK__USBH1_CLK,
  81         MX51_PAD_USBH1_DIR__USBH1_DIR,
  82         MX51_PAD_USBH1_NXT__USBH1_NXT,
  83         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  84         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  85         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  86         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  87         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  88         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  89         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  90         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  91
  92         /* USB HUB reset line*/
  93         MX51_PAD_GPIO_1_7__GPIO_1_7,
  94
  95         /* FEC */
  96         MX51_PAD_EIM_EB2__FEC_MDIO,
  97         MX51_PAD_EIM_EB3__FEC_RDAT1,
  98         MX51_PAD_EIM_CS2__FEC_RDAT2,
  99         MX51_PAD_EIM_CS3__FEC_RDAT3,
 100         MX51_PAD_EIM_CS4__FEC_RX_ER,
 101         MX51_PAD_EIM_CS5__FEC_CRS,
 102         MX51_PAD_NANDF_RB2__FEC_COL,
 103         MX51_PAD_NANDF_RB3__FEC_RXCLK,
 104         MX51_PAD_NANDF_RB6__FEC_RDAT0,
 105         MX51_PAD_NANDF_RB7__FEC_TDAT0,
 106         MX51_PAD_NANDF_CS2__FEC_TX_ER,
 107         MX51_PAD_NANDF_CS3__FEC_MDC,
 108         MX51_PAD_NANDF_CS4__FEC_TDAT1,
 109         MX51_PAD_NANDF_CS5__FEC_TDAT2,
 110         MX51_PAD_NANDF_CS6__FEC_TDAT3,
 111         MX51_PAD_NANDF_CS7__FEC_TX_EN,
 112         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 113
 114         /* FEC PHY reset line */
 115         MX51_PAD_EIM_A20__GPIO_2_14,
 116
 117         /* SD 1 */
 118         MX51_PAD_SD1_CMD__SD1_CMD,
 119         MX51_PAD_SD1_CLK__SD1_CLK,
 120         MX51_PAD_SD1_DATA0__SD1_DATA0,
 121         MX51_PAD_SD1_DATA1__SD1_DATA1,
 122         MX51_PAD_SD1_DATA2__SD1_DATA2,
 123         MX51_PAD_SD1_DATA3__SD1_DATA3,
 124
 125         /* SD 2 */
 126         MX51_PAD_SD2_CMD__SD2_CMD,
 127         MX51_PAD_SD2_CLK__SD2_CLK,
 128         MX51_PAD_SD2_DATA0__SD2_DATA0,
 129         MX51_PAD_SD2_DATA1__SD2_DATA1,
 130         MX51_PAD_SD2_DATA2__SD2_DATA2,
 131         MX51_PAD_SD2_DATA3__SD2_DATA3,
 132 };
 133
 134 /* Serial ports */
 135 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 136 static const struct imxuart_platform_data uart_pdata __initconst = {
 137         .flags = IMXUART_HAVE_RTSCTS,
 138 };
 139
 140 static inline void mxc_init_imx_uart(void)
 141 {
 142         imx51_add_imx_uart(0, &uart_pdata);
 143         imx51_add_imx_uart(1, &uart_pdata);
 144         imx51_add_imx_uart(2, &uart_pdata);
 145 }
 146 #else /* !SERIAL_IMX */
 147 static inline void mxc_init_imx_uart(void)
 148 {
 149 }
 150 #endif /* SERIAL_IMX */
 151
 152 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
 153         .bitrate = 100000,
 154 };
 155
 156 static struct imxi2c_platform_data babbage_hsi2c_data = {
 157         .bitrate = 400000,
 158 };
 159
 160 static int gpio_usbh1_active(void)
 161 {
 162         struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
 163         struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
 164         int ret;
 165
 166         /* Set USBH1_STP to GPIO and toggle it */
 167         mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
 168         ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
 169
 170         if (ret) {
 171                 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
 172                 return ret;
 173         }
 174         gpio_direction_output(BABBAGE_USBH1_STP, 0);
 175         gpio_set_value(BABBAGE_USBH1_STP, 1);
 176         msleep(100);
 177         gpio_free(BABBAGE_USBH1_STP);
 178
 179         /* De-assert USB PHY RESETB */
 180         mxc_iomux_v3_setup_pad(&phyreset_gpio);
 181         ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
 182
 183         if (ret) {
 184                 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
 185                 return ret;
 186         }
 187         gpio_direction_output(BABBAGE_PHY_RESET, 1);
 188         return 0;
 189 }
 190
 191 static inline void babbage_usbhub_reset(void)
 192 {
 193         int ret;
 194
 195         /* Bring USB hub out of reset */
 196         ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
 197         if (ret) {
 198                 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
 199                 return;
 200         }
 201         gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
 202
 203         /* USB HUB RESET - De-assert USB HUB RESET_N */
 204         msleep(1);
 205         gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
 206         msleep(1);
 207         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 208 }
 209
 210 static inline void babbage_fec_reset(void)
 211 {
 212         int ret;
 213
 214         /* reset FEC PHY */
 215         ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
 216         if (ret) {
 217                 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
 218                 return;
 219         }
 220         gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
 221         gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
 222         msleep(1);
 223         gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
 224 }
 225
 226 /* This function is board specific as the bit mask for the plldiv will also
 227 be different for other Freescale SoCs, thus a common bitmask is not
 228 possible and cannot get place in /plat-mxc/ehci.c.*/
 229 static int initialize_otg_port(struct platform_device *pdev)
 230 {
 231         u32 v;
 232         void __iomem *usb_base;
 233         void __iomem *usbother_base;
 234
 235         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 236         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 237
 238         /* Set the PHY clock to 19.2MHz */
 239         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 240         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 241         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 242         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 243         iounmap(usb_base);
 244         return 0;
 245 }
 246
 247 static int initialize_usbh1_port(struct platform_device *pdev)
 248 {
 249         u32 v;
 250         void __iomem *usb_base;
 251         void __iomem *usbother_base;
 252
 253         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 254         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 255
 256         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 257         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 258         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 259         iounmap(usb_base);
 260         return 0;
 261 }
 262
 263 static struct mxc_usbh_platform_data dr_utmi_config = {
 264         .init           = initialize_otg_port,
 265         .portsc = MXC_EHCI_UTMI_16BIT,
 266         .flags  = MXC_EHCI_INTERNAL_PHY,
 267 };
 268
 269 static struct fsl_usb2_platform_data usb_pdata = {
 270         .operating_mode = FSL_USB2_DR_DEVICE,
 271         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 272 };
 273
 274 static struct mxc_usbh_platform_data usbh1_config = {
 275         .init           = initialize_usbh1_port,
 276         .portsc = MXC_EHCI_MODE_ULPI,
 277         .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 278 };
 279
 280 static int otg_mode_host;
 281
 282 static int __init babbage_otg_mode(char *options)
 283 {
 284         if (!strcmp(options, "host"))
 285                 otg_mode_host = 1;
 286         else if (!strcmp(options, "device"))
 287                 otg_mode_host = 0;
 288         else
 289                 pr_info("otg_mode neither \"host\" nor \"device\". "
 290                         "Defaulting to device\n");
 291         return 0;
 292 }
 293 __setup("otg_mode=", babbage_otg_mode);
 294
 295 /*
 296  * Board specific initialization.
 297  */
 298 static void __init mxc_board_init(void)
 299 {
 300         struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
 301
 302 #if defined(CONFIG_CPU_FREQ_IMX)
 303         get_cpu_op = mx51_get_cpu_op;
 304 #endif
 305         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
 306                                         ARRAY_SIZE(mx51babbage_pads));
 307         mxc_init_imx_uart();
 308         babbage_fec_reset();
 309         imx51_add_fec(NULL);
 310
 311         imx51_add_imx_i2c(0, &babbage_i2c_data);
 312         imx51_add_imx_i2c(1, &babbage_i2c_data);
 313         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
 314
 315         if (otg_mode_host)
 316                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 317         else {
 318                 initialize_otg_port(NULL);
 319                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 320         }
 321
 322         gpio_usbh1_active();
 323         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 324         /* setback USBH1_STP to be function */
 325         mxc_iomux_v3_setup_pad(&usbh1stp);
 326         babbage_usbhub_reset();
 327
 328         imx51_add_esdhc(0, NULL);
 329         imx51_add_esdhc(1, NULL);
 330 }
 331
 332 static void __init mx51_babbage_timer_init(void)
 333 {
 334         mx51_clocks_init(32768, 24000000, 22579200, 0);
 335 }
 336
 337 static struct sys_timer mxc_timer = {
 338         .init   = mx51_babbage_timer_init,
 339 };
 340
 341 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
 342         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
 343         .phys_io = MX51_AIPS1_BASE_ADDR,
 344         .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 345         .boot_params = MX51_PHYS_OFFSET + 0x100,
 346         .map_io = mx51_map_io,
 347         .init_irq = mx51_init_irq,
 348         .init_machine = mxc_board_init,
 349         .timer = &mxc_timer,
 350 MACHINE_END